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x86, xsave: context switch support using xsave/xrstor
[linux-2.6/mini2440.git] / include / asm-x86 / processor.h
blob77b7af6b573bfa3f08afa13de9e53f6fd07cf1f7
1 #ifndef ASM_X86__PROCESSOR_H
2 #define ASM_X86__PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
18 #include <asm/page.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23
24 #include <linux/personality.h>
25 #include <linux/cpumask.h>
26 #include <linux/cache.h>
27 #include <linux/threads.h>
28 #include <linux/init.h>
29
30 /*
31 * Default implementation of macro that returns current
32 * instruction pointer ("program counter").
33 */
34 static inline void *current_text_addr(void)
35 {
36 void *pc;
37
38 asm volatile("mov $1f, %0; 1:":"=r" (pc));
39
40 return pc;
41 }
42
43 #ifdef CONFIG_X86_VSMP
44 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
45 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
46 #else
47 # define ARCH_MIN_TASKALIGN 16
48 # define ARCH_MIN_MMSTRUCT_ALIGN 0
49 #endif
50
51 /*
52 * CPU type and hardware bug flags. Kept separately for each CPU.
53 * Members of this structure are referenced in head.S, so think twice
54 * before touching them. [mj]
55 */
56
57 struct cpuinfo_x86 {
58 __u8 x86; /* CPU family */
59 __u8 x86_vendor; /* CPU vendor */
60 __u8 x86_model;
61 __u8 x86_mask;
62 #ifdef CONFIG_X86_32
63 char wp_works_ok; /* It doesn't on 386's */
64
65 /* Problems on some 486Dx4's and old 386's: */
66 char hlt_works_ok;
67 char hard_math;
68 char rfu;
69 char fdiv_bug;
70 char f00f_bug;
71 char coma_bug;
72 char pad0;
73 #else
74 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
75 int x86_tlbsize;
76 __u8 x86_virt_bits;
77 __u8 x86_phys_bits;
78 /* CPUID returned core id bits: */
79 __u8 x86_coreid_bits;
80 /* Max extended CPUID function supported: */
81 __u32 extended_cpuid_level;
82 #endif
83 /* Maximum supported CPUID level, -1=no CPUID: */
84 int cpuid_level;
85 __u32 x86_capability[NCAPINTS];
86 char x86_vendor_id[16];
87 char x86_model_id[64];
88 /* in KB - valid for CPUS which support this call: */
89 int x86_cache_size;
90 int x86_cache_alignment; /* In bytes */
91 int x86_power;
92 unsigned long loops_per_jiffy;
93 #ifdef CONFIG_SMP
94 /* cpus sharing the last level cache: */
95 cpumask_t llc_shared_map;
96 #endif
97 /* cpuid returned max cores value: */
98 u16 x86_max_cores;
99 u16 apicid;
100 u16 initial_apicid;
101 u16 x86_clflush_size;
102 #ifdef CONFIG_SMP
103 /* number of cores as seen by the OS: */
104 u16 booted_cores;
105 /* Physical processor id: */
106 u16 phys_proc_id;
107 /* Core id: */
108 u16 cpu_core_id;
109 /* Index into per_cpu list: */
110 u16 cpu_index;
111 #endif
112 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
113
114 #define X86_VENDOR_INTEL 0
115 #define X86_VENDOR_CYRIX 1
116 #define X86_VENDOR_AMD 2
117 #define X86_VENDOR_UMC 3
118 #define X86_VENDOR_CENTAUR 5
119 #define X86_VENDOR_TRANSMETA 7
120 #define X86_VENDOR_NSC 8
121 #define X86_VENDOR_NUM 9
122
123 #define X86_VENDOR_UNKNOWN 0xff
124
125 /*
126 * capabilities of CPUs
127 */
128 extern struct cpuinfo_x86 boot_cpu_data;
129 extern struct cpuinfo_x86 new_cpu_data;
130
131 extern struct tss_struct doublefault_tss;
132 extern __u32 cleared_cpu_caps[NCAPINTS];
133
134 #ifdef CONFIG_SMP
135 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
136 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
137 #define current_cpu_data __get_cpu_var(cpu_info)
138 #else
139 #define cpu_data(cpu) boot_cpu_data
140 #define current_cpu_data boot_cpu_data
141 #endif
142
143 static inline int hlt_works(int cpu)
144 {
145 #ifdef CONFIG_X86_32
146 return cpu_data(cpu).hlt_works_ok;
147 #else
148 return 1;
149 #endif
150 }
151
152 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
153
154 extern void cpu_detect(struct cpuinfo_x86 *c);
155
156 extern void early_cpu_init(void);
157 extern void identify_boot_cpu(void);
158 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
159 extern void print_cpu_info(struct cpuinfo_x86 *);
160 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
161 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
162 extern unsigned short num_cache_leaves;
163
164 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
165 extern void detect_ht(struct cpuinfo_x86 *c);
166 #else
167 static inline void detect_ht(struct cpuinfo_x86 *c) {}
168 #endif
169
170 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
171 unsigned int *ecx, unsigned int *edx)
172 {
173 /* ecx is often an input as well as an output. */
174 asm("cpuid"
175 : "=a" (*eax),
176 "=b" (*ebx),
177 "=c" (*ecx),
178 "=d" (*edx)
179 : "0" (*eax), "2" (*ecx));
180 }
181
182 static inline void load_cr3(pgd_t *pgdir)
183 {
184 write_cr3(__pa(pgdir));
185 }
186
187 #ifdef CONFIG_X86_32
188 /* This is the TSS defined by the hardware. */
189 struct x86_hw_tss {
190 unsigned short back_link, __blh;
191 unsigned long sp0;
192 unsigned short ss0, __ss0h;
193 unsigned long sp1;
194 /* ss1 caches MSR_IA32_SYSENTER_CS: */
195 unsigned short ss1, __ss1h;
196 unsigned long sp2;
197 unsigned short ss2, __ss2h;
198 unsigned long __cr3;
199 unsigned long ip;
200 unsigned long flags;
201 unsigned long ax;
202 unsigned long cx;
203 unsigned long dx;
204 unsigned long bx;
205 unsigned long sp;
206 unsigned long bp;
207 unsigned long si;
208 unsigned long di;
209 unsigned short es, __esh;
210 unsigned short cs, __csh;
211 unsigned short ss, __ssh;
212 unsigned short ds, __dsh;
213 unsigned short fs, __fsh;
214 unsigned short gs, __gsh;
215 unsigned short ldt, __ldth;
216 unsigned short trace;
217 unsigned short io_bitmap_base;
218
219 } __attribute__((packed));
220 #else
221 struct x86_hw_tss {
222 u32 reserved1;
223 u64 sp0;
224 u64 sp1;
225 u64 sp2;
226 u64 reserved2;
227 u64 ist[7];
228 u32 reserved3;
229 u32 reserved4;
230 u16 reserved5;
231 u16 io_bitmap_base;
232
233 } __attribute__((packed)) ____cacheline_aligned;
234 #endif
235
236 /*
237 * IO-bitmap sizes:
238 */
239 #define IO_BITMAP_BITS 65536
240 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
241 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
242 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
243 #define INVALID_IO_BITMAP_OFFSET 0x8000
244 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
245
246 struct tss_struct {
247 /*
248 * The hardware state:
249 */
250 struct x86_hw_tss x86_tss;
251
252 /*
253 * The extra 1 is there because the CPU will access an
254 * additional byte beyond the end of the IO permission
255 * bitmap. The extra byte must be all 1 bits, and must
256 * be within the limit.
257 */
258 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
259 /*
260 * Cache the current maximum and the last task that used the bitmap:
261 */
262 unsigned long io_bitmap_max;
263 struct thread_struct *io_bitmap_owner;
264
265 /*
266 * .. and then another 0x100 bytes for the emergency kernel stack:
267 */
268 unsigned long stack[64];
269
270 } ____cacheline_aligned;
271
272 DECLARE_PER_CPU(struct tss_struct, init_tss);
273
274 /*
275 * Save the original ist values for checking stack pointers during debugging
276 */
277 struct orig_ist {
278 unsigned long ist[7];
279 };
280
281 #define MXCSR_DEFAULT 0x1f80
282
283 struct i387_fsave_struct {
284 u32 cwd; /* FPU Control Word */
285 u32 swd; /* FPU Status Word */
286 u32 twd; /* FPU Tag Word */
287 u32 fip; /* FPU IP Offset */
288 u32 fcs; /* FPU IP Selector */
289 u32 foo; /* FPU Operand Pointer Offset */
290 u32 fos; /* FPU Operand Pointer Selector */
291
292 /* 8*10 bytes for each FP-reg = 80 bytes: */
293 u32 st_space[20];
294
295 /* Software status information [not touched by FSAVE ]: */
296 u32 status;
297 };
298
299 struct i387_fxsave_struct {
300 u16 cwd; /* Control Word */
301 u16 swd; /* Status Word */
302 u16 twd; /* Tag Word */
303 u16 fop; /* Last Instruction Opcode */
304 union {
305 struct {
306 u64 rip; /* Instruction Pointer */
307 u64 rdp; /* Data Pointer */
308 };
309 struct {
310 u32 fip; /* FPU IP Offset */
311 u32 fcs; /* FPU IP Selector */
312 u32 foo; /* FPU Operand Offset */
313 u32 fos; /* FPU Operand Selector */
314 };
315 };
316 u32 mxcsr; /* MXCSR Register State */
317 u32 mxcsr_mask; /* MXCSR Mask */
318
319 /* 8*16 bytes for each FP-reg = 128 bytes: */
320 u32 st_space[32];
321
322 /* 16*16 bytes for each XMM-reg = 256 bytes: */
323 u32 xmm_space[64];
324
325 u32 padding[24];
326
327 } __attribute__((aligned(16)));
328
329 struct i387_soft_struct {
330 u32 cwd;
331 u32 swd;
332 u32 twd;
333 u32 fip;
334 u32 fcs;
335 u32 foo;
336 u32 fos;
337 /* 8*10 bytes for each FP-reg = 80 bytes: */
338 u32 st_space[20];
339 u8 ftop;
340 u8 changed;
341 u8 lookahead;
342 u8 no_update;
343 u8 rm;
344 u8 alimit;
345 struct info *info;
346 u32 entry_eip;
347 };
348
349 struct xsave_hdr_struct {
350 u64 xstate_bv;
351 u64 reserved1[2];
352 u64 reserved2[5];
353 } __attribute__((packed));
354
355 struct xsave_struct {
356 struct i387_fxsave_struct i387;
357 struct xsave_hdr_struct xsave_hdr;
358 /* new processor state extensions will go here */
359 } __attribute__ ((packed, aligned (64)));
360
361 union thread_xstate {
362 struct i387_fsave_struct fsave;
363 struct i387_fxsave_struct fxsave;
364 struct i387_soft_struct soft;
365 struct xsave_struct xsave;
366 };
367
368 #ifdef CONFIG_X86_64
369 DECLARE_PER_CPU(struct orig_ist, orig_ist);
370 #endif
371
372 extern void print_cpu_info(struct cpuinfo_x86 *);
373 extern unsigned int xstate_size;
374 extern void free_thread_xstate(struct task_struct *);
375 extern struct kmem_cache *task_xstate_cachep;
376 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
377 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
378 extern unsigned short num_cache_leaves;
379
380 struct thread_struct {
381 /* Cached TLS descriptors: */
382 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
383 unsigned long sp0;
384 unsigned long sp;
385 #ifdef CONFIG_X86_32
386 unsigned long sysenter_cs;
387 #else
388 unsigned long usersp; /* Copy from PDA */
389 unsigned short es;
390 unsigned short ds;
391 unsigned short fsindex;
392 unsigned short gsindex;
393 #endif
394 unsigned long ip;
395 unsigned long fs;
396 unsigned long gs;
397 /* Hardware debugging registers: */
398 unsigned long debugreg0;
399 unsigned long debugreg1;
400 unsigned long debugreg2;
401 unsigned long debugreg3;
402 unsigned long debugreg6;
403 unsigned long debugreg7;
404 /* Fault info: */
405 unsigned long cr2;
406 unsigned long trap_no;
407 unsigned long error_code;
408 /* floating point and extended processor state */
409 union thread_xstate *xstate;
410 #ifdef CONFIG_X86_32
411 /* Virtual 86 mode info */
412 struct vm86_struct __user *vm86_info;
413 unsigned long screen_bitmap;
414 unsigned long v86flags;
415 unsigned long v86mask;
416 unsigned long saved_sp0;
417 unsigned int saved_fs;
418 unsigned int saved_gs;
419 #endif
420 /* IO permissions: */
421 unsigned long *io_bitmap_ptr;
422 unsigned long iopl;
423 /* Max allowed port in the bitmap, in bytes: */
424 unsigned io_bitmap_max;
425 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
426 unsigned long debugctlmsr;
427 /* Debug Store - if not 0 points to a DS Save Area configuration;
428 * goes into MSR_IA32_DS_AREA */
429 unsigned long ds_area_msr;
430 };
431
432 static inline unsigned long native_get_debugreg(int regno)
433 {
434 unsigned long val = 0; /* Damn you, gcc! */
435
436 switch (regno) {
437 case 0:
438 asm("mov %%db0, %0" :"=r" (val));
439 break;
440 case 1:
441 asm("mov %%db1, %0" :"=r" (val));
442 break;
443 case 2:
444 asm("mov %%db2, %0" :"=r" (val));
445 break;
446 case 3:
447 asm("mov %%db3, %0" :"=r" (val));
448 break;
449 case 6:
450 asm("mov %%db6, %0" :"=r" (val));
451 break;
452 case 7:
453 asm("mov %%db7, %0" :"=r" (val));
454 break;
455 default:
456 BUG();
457 }
458 return val;
459 }
460
461 static inline void native_set_debugreg(int regno, unsigned long value)
462 {
463 switch (regno) {
464 case 0:
465 asm("mov %0, %%db0" ::"r" (value));
466 break;
467 case 1:
468 asm("mov %0, %%db1" ::"r" (value));
469 break;
470 case 2:
471 asm("mov %0, %%db2" ::"r" (value));
472 break;
473 case 3:
474 asm("mov %0, %%db3" ::"r" (value));
475 break;
476 case 6:
477 asm("mov %0, %%db6" ::"r" (value));
478 break;
479 case 7:
480 asm("mov %0, %%db7" ::"r" (value));
481 break;
482 default:
483 BUG();
484 }
485 }
486
487 /*
488 * Set IOPL bits in EFLAGS from given mask
489 */
490 static inline void native_set_iopl_mask(unsigned mask)
491 {
492 #ifdef CONFIG_X86_32
493 unsigned int reg;
494
495 asm volatile ("pushfl;"
496 "popl %0;"
497 "andl %1, %0;"
498 "orl %2, %0;"
499 "pushl %0;"
500 "popfl"
501 : "=&r" (reg)
502 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
503 #endif
504 }
505
506 static inline void
507 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
508 {
509 tss->x86_tss.sp0 = thread->sp0;
510 #ifdef CONFIG_X86_32
511 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
512 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
513 tss->x86_tss.ss1 = thread->sysenter_cs;
514 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
515 }
516 #endif
517 }
518
519 static inline void native_swapgs(void)
520 {
521 #ifdef CONFIG_X86_64
522 asm volatile("swapgs" ::: "memory");
523 #endif
524 }
525
526 #ifdef CONFIG_PARAVIRT
527 #include <asm/paravirt.h>
528 #else
529 #define __cpuid native_cpuid
530 #define paravirt_enabled() 0
531
532 /*
533 * These special macros can be used to get or set a debugging register
534 */
535 #define get_debugreg(var, register) \
536 (var) = native_get_debugreg(register)
537 #define set_debugreg(value, register) \
538 native_set_debugreg(register, value)
539
540 static inline void load_sp0(struct tss_struct *tss,
541 struct thread_struct *thread)
542 {
543 native_load_sp0(tss, thread);
544 }
545
546 #define set_iopl_mask native_set_iopl_mask
547 #endif /* CONFIG_PARAVIRT */
548
549 /*
550 * Save the cr4 feature set we're using (ie
551 * Pentium 4MB enable and PPro Global page
552 * enable), so that any CPU's that boot up
553 * after us can get the correct flags.
554 */
555 extern unsigned long mmu_cr4_features;
556
557 static inline void set_in_cr4(unsigned long mask)
558 {
559 unsigned cr4;
560
561 mmu_cr4_features |= mask;
562 cr4 = read_cr4();
563 cr4 |= mask;
564 write_cr4(cr4);
565 }
566
567 static inline void clear_in_cr4(unsigned long mask)
568 {
569 unsigned cr4;
570
571 mmu_cr4_features &= ~mask;
572 cr4 = read_cr4();
573 cr4 &= ~mask;
574 write_cr4(cr4);
575 }
576
577 struct microcode_header {
578 unsigned int hdrver;
579 unsigned int rev;
580 unsigned int date;
581 unsigned int sig;
582 unsigned int cksum;
583 unsigned int ldrver;
584 unsigned int pf;
585 unsigned int datasize;
586 unsigned int totalsize;
587 unsigned int reserved[3];
588 };
589
590 struct microcode {
591 struct microcode_header hdr;
592 unsigned int bits[0];
593 };
594
595 typedef struct microcode microcode_t;
596 typedef struct microcode_header microcode_header_t;
597
598 /* microcode format is extended from prescott processors */
599 struct extended_signature {
600 unsigned int sig;
601 unsigned int pf;
602 unsigned int cksum;
603 };
604
605 struct extended_sigtable {
606 unsigned int count;
607 unsigned int cksum;
608 unsigned int reserved[3];
609 struct extended_signature sigs[0];
610 };
611
612 typedef struct {
613 unsigned long seg;
614 } mm_segment_t;
615
616
617 /*
618 * create a kernel thread without removing it from tasklists
619 */
620 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
621
622 /* Free all resources held by a thread. */
623 extern void release_thread(struct task_struct *);
624
625 /* Prepare to copy thread state - unlazy all lazy state */
626 extern void prepare_to_copy(struct task_struct *tsk);
627
628 unsigned long get_wchan(struct task_struct *p);
629
630 /*
631 * Generic CPUID function
632 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
633 * resulting in stale register contents being returned.
634 */
635 static inline void cpuid(unsigned int op,
636 unsigned int *eax, unsigned int *ebx,
637 unsigned int *ecx, unsigned int *edx)
638 {
639 *eax = op;
640 *ecx = 0;
641 __cpuid(eax, ebx, ecx, edx);
642 }
643
644 /* Some CPUID calls want 'count' to be placed in ecx */
645 static inline void cpuid_count(unsigned int op, int count,
646 unsigned int *eax, unsigned int *ebx,
647 unsigned int *ecx, unsigned int *edx)
648 {
649 *eax = op;
650 *ecx = count;
651 __cpuid(eax, ebx, ecx, edx);
652 }
653
654 /*
655 * CPUID functions returning a single datum
656 */
657 static inline unsigned int cpuid_eax(unsigned int op)
658 {
659 unsigned int eax, ebx, ecx, edx;
660
661 cpuid(op, &eax, &ebx, &ecx, &edx);
662
663 return eax;
664 }
665
666 static inline unsigned int cpuid_ebx(unsigned int op)
667 {
668 unsigned int eax, ebx, ecx, edx;
669
670 cpuid(op, &eax, &ebx, &ecx, &edx);
671
672 return ebx;
673 }
674
675 static inline unsigned int cpuid_ecx(unsigned int op)
676 {
677 unsigned int eax, ebx, ecx, edx;
678
679 cpuid(op, &eax, &ebx, &ecx, &edx);
680
681 return ecx;
682 }
683
684 static inline unsigned int cpuid_edx(unsigned int op)
685 {
686 unsigned int eax, ebx, ecx, edx;
687
688 cpuid(op, &eax, &ebx, &ecx, &edx);
689
690 return edx;
691 }
692
693 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
694 static inline void rep_nop(void)
695 {
696 asm volatile("rep; nop" ::: "memory");
697 }
698
699 static inline void cpu_relax(void)
700 {
701 rep_nop();
702 }
703
704 /* Stop speculative execution: */
705 static inline void sync_core(void)
706 {
707 int tmp;
708
709 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
710 : "ebx", "ecx", "edx", "memory");
711 }
712
713 static inline void __monitor(const void *eax, unsigned long ecx,
714 unsigned long edx)
715 {
716 /* "monitor %eax, %ecx, %edx;" */
717 asm volatile(".byte 0x0f, 0x01, 0xc8;"
718 :: "a" (eax), "c" (ecx), "d"(edx));
719 }
720
721 static inline void __mwait(unsigned long eax, unsigned long ecx)
722 {
723 /* "mwait %eax, %ecx;" */
724 asm volatile(".byte 0x0f, 0x01, 0xc9;"
725 :: "a" (eax), "c" (ecx));
726 }
727
728 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
729 {
730 trace_hardirqs_on();
731 /* "mwait %eax, %ecx;" */
732 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
733 :: "a" (eax), "c" (ecx));
734 }
735
736 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
737
738 extern void select_idle_routine(const struct cpuinfo_x86 *c);
739
740 extern unsigned long boot_option_idle_override;
741 extern unsigned long idle_halt;
742 extern unsigned long idle_nomwait;
743
744 extern void enable_sep_cpu(void);
745 extern int sysenter_setup(void);
746
747 /* Defined in head.S */
748 extern struct desc_ptr early_gdt_descr;
749
750 extern void cpu_set_gdt(int);
751 extern void switch_to_new_gdt(void);
752 extern void cpu_init(void);
753 extern void init_gdt(int cpu);
754
755 static inline void update_debugctlmsr(unsigned long debugctlmsr)
756 {
757 #ifndef CONFIG_X86_DEBUGCTLMSR
758 if (boot_cpu_data.x86 < 6)
759 return;
760 #endif
761 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
762 }
763
764 /*
765 * from system description table in BIOS. Mostly for MCA use, but
766 * others may find it useful:
767 */
768 extern unsigned int machine_id;
769 extern unsigned int machine_submodel_id;
770 extern unsigned int BIOS_revision;
771
772 /* Boot loader type from the setup header: */
773 extern int bootloader_type;
774
775 extern char ignore_fpu_irq;
776
777 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
778 #define ARCH_HAS_PREFETCHW
779 #define ARCH_HAS_SPINLOCK_PREFETCH
780
781 #ifdef CONFIG_X86_32
782 # define BASE_PREFETCH ASM_NOP4
783 # define ARCH_HAS_PREFETCH
784 #else
785 # define BASE_PREFETCH "prefetcht0 (%1)"
786 #endif
787
788 /*
789 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
790 *
791 * It's not worth to care about 3dnow prefetches for the K6
792 * because they are microcoded there and very slow.
793 */
794 static inline void prefetch(const void *x)
795 {
796 alternative_input(BASE_PREFETCH,
797 "prefetchnta (%1)",
798 X86_FEATURE_XMM,
799 "r" (x));
800 }
801
802 /*
803 * 3dnow prefetch to get an exclusive cache line.
804 * Useful for spinlocks to avoid one state transition in the
805 * cache coherency protocol:
806 */
807 static inline void prefetchw(const void *x)
808 {
809 alternative_input(BASE_PREFETCH,
810 "prefetchw (%1)",
811 X86_FEATURE_3DNOW,
812 "r" (x));
813 }
814
815 static inline void spin_lock_prefetch(const void *x)
816 {
817 prefetchw(x);
818 }
819
820 #ifdef CONFIG_X86_32
821 /*
822 * User space process size: 3GB (default).
823 */
824 #define TASK_SIZE PAGE_OFFSET
825 #define STACK_TOP TASK_SIZE
826 #define STACK_TOP_MAX STACK_TOP
827
828 #define INIT_THREAD { \
829 .sp0 = sizeof(init_stack) + (long)&init_stack, \
830 .vm86_info = NULL, \
831 .sysenter_cs = __KERNEL_CS, \
832 .io_bitmap_ptr = NULL, \
833 .fs = __KERNEL_PERCPU, \
834 }
835
836 /*
837 * Note that the .io_bitmap member must be extra-big. This is because
838 * the CPU will access an additional byte beyond the end of the IO
839 * permission bitmap. The extra byte must be all 1 bits, and must
840 * be within the limit.
841 */
842 #define INIT_TSS { \
843 .x86_tss = { \
844 .sp0 = sizeof(init_stack) + (long)&init_stack, \
845 .ss0 = __KERNEL_DS, \
846 .ss1 = __KERNEL_CS, \
847 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
848 }, \
849 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
850 }
851
852 extern unsigned long thread_saved_pc(struct task_struct *tsk);
853
854 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
855 #define KSTK_TOP(info) \
856 ({ \
857 unsigned long *__ptr = (unsigned long *)(info); \
858 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
859 })
860
861 /*
862 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
863 * This is necessary to guarantee that the entire "struct pt_regs"
864 * is accessable even if the CPU haven't stored the SS/ESP registers
865 * on the stack (interrupt gate does not save these registers
866 * when switching to the same priv ring).
867 * Therefore beware: accessing the ss/esp fields of the
868 * "struct pt_regs" is possible, but they may contain the
869 * completely wrong values.
870 */
871 #define task_pt_regs(task) \
872 ({ \
873 struct pt_regs *__regs__; \
874 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
875 __regs__ - 1; \
876 })
877
878 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
879
880 #else
881 /*
882 * User space process size. 47bits minus one guard page.
883 */
884 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
885
886 /* This decides where the kernel will search for a free chunk of vm
887 * space during mmap's.
888 */
889 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
890 0xc0000000 : 0xFFFFe000)
891
892 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
893 IA32_PAGE_OFFSET : TASK_SIZE64)
894 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
895 IA32_PAGE_OFFSET : TASK_SIZE64)
896
897 #define STACK_TOP TASK_SIZE
898 #define STACK_TOP_MAX TASK_SIZE64
899
900 #define INIT_THREAD { \
901 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
902 }
903
904 #define INIT_TSS { \
905 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
906 }
907
908 /*
909 * Return saved PC of a blocked thread.
910 * What is this good for? it will be always the scheduler or ret_from_fork.
911 */
912 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
913
914 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
915 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
916 #endif /* CONFIG_X86_64 */
917
918 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
919 unsigned long new_sp);
920
921 /*
922 * This decides where the kernel will search for a free chunk of vm
923 * space during mmap's.
924 */
925 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
926
927 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
928
929 /* Get/set a process' ability to use the timestamp counter instruction */
930 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
931 #define SET_TSC_CTL(val) set_tsc_mode((val))
932
933 extern int get_tsc_mode(unsigned long adr);
934 extern int set_tsc_mode(unsigned int val);
935
936 #endif /* ASM_X86__PROCESSOR_H */
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