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gianfar: Fix soft lockup with multi-interrupt TSECs
[linux-2.6/mini2440.git] / drivers / net / gianfar.c
blobea530673236ef8e6f46f6ab05c87ba47e1096f02
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "gianfar_mii.h"
97
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
135 int amount_pull);
136 static void gfar_vlan_rx_register(struct net_device *netdev,
137 struct vlan_group *grp);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143
144 extern const struct ethtool_ops gfar_ethtool_ops;
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private *priv)
152 {
153 return priv->vlgrp || priv->rx_csum_enable;
154 }
155
156 static int gfar_of_init(struct net_device *dev)
157 {
158 struct device_node *phy, *mdio;
159 const unsigned int *id;
160 const char *model;
161 const char *ctype;
162 const void *mac_addr;
163 const phandle *ph;
164 u64 addr, size;
165 int err = 0;
166 struct gfar_private *priv = netdev_priv(dev);
167 struct device_node *np = priv->node;
168 char bus_name[MII_BUS_ID_SIZE];
169
170 if (!np || !of_device_is_available(np))
171 return -ENODEV;
172
173 /* get a pointer to the register memory */
174 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
175 priv->regs = ioremap(addr, size);
176
177 if (priv->regs == NULL)
178 return -ENOMEM;
179
180 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
181
182 model = of_get_property(np, "model", NULL);
183
184 /* If we aren't the FEC we have multiple interrupts */
185 if (model && strcasecmp(model, "FEC")) {
186 priv->interruptReceive = irq_of_parse_and_map(np, 1);
187
188 priv->interruptError = irq_of_parse_and_map(np, 2);
189
190 if (priv->interruptTransmit < 0 ||
191 priv->interruptReceive < 0 ||
192 priv->interruptError < 0) {
193 err = -EINVAL;
194 goto err_out;
195 }
196 }
197
198 mac_addr = of_get_mac_address(np);
199 if (mac_addr)
200 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
201
202 if (model && !strcasecmp(model, "TSEC"))
203 priv->device_flags =
204 FSL_GIANFAR_DEV_HAS_GIGABIT |
205 FSL_GIANFAR_DEV_HAS_COALESCE |
206 FSL_GIANFAR_DEV_HAS_RMON |
207 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
208 if (model && !strcasecmp(model, "eTSEC"))
209 priv->device_flags =
210 FSL_GIANFAR_DEV_HAS_GIGABIT |
211 FSL_GIANFAR_DEV_HAS_COALESCE |
212 FSL_GIANFAR_DEV_HAS_RMON |
213 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
214 FSL_GIANFAR_DEV_HAS_PADDING |
215 FSL_GIANFAR_DEV_HAS_CSUM |
216 FSL_GIANFAR_DEV_HAS_VLAN |
217 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
218 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
219
220 ctype = of_get_property(np, "phy-connection-type", NULL);
221
222 /* We only care about rgmii-id. The rest are autodetected */
223 if (ctype && !strcmp(ctype, "rgmii-id"))
224 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
225 else
226 priv->interface = PHY_INTERFACE_MODE_MII;
227
228 if (of_get_property(np, "fsl,magic-packet", NULL))
229 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
230
231 ph = of_get_property(np, "phy-handle", NULL);
232 if (ph == NULL) {
233 u32 *fixed_link;
234
235 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
236 if (!fixed_link) {
237 err = -ENODEV;
238 goto err_out;
239 }
240
241 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
242 PHY_ID_FMT, "0", fixed_link[0]);
243 } else {
244 phy = of_find_node_by_phandle(*ph);
245
246 if (phy == NULL) {
247 err = -ENODEV;
248 goto err_out;
249 }
250
251 mdio = of_get_parent(phy);
252
253 id = of_get_property(phy, "reg", NULL);
254
255 of_node_put(phy);
256 of_node_put(mdio);
257
258 gfar_mdio_bus_name(bus_name, mdio);
259 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
260 bus_name, *id);
261 }
262
263 /* Find the TBI PHY. If it's not there, we don't support SGMII */
264 ph = of_get_property(np, "tbi-handle", NULL);
265 if (ph) {
266 struct device_node *tbi = of_find_node_by_phandle(*ph);
267 struct of_device *ofdev;
268 struct mii_bus *bus;
269
270 if (!tbi)
271 return 0;
272
273 mdio = of_get_parent(tbi);
274 if (!mdio)
275 return 0;
276
277 ofdev = of_find_device_by_node(mdio);
278
279 of_node_put(mdio);
280
281 id = of_get_property(tbi, "reg", NULL);
282 if (!id)
283 return 0;
284
285 of_node_put(tbi);
286
287 bus = dev_get_drvdata(&ofdev->dev);
288
289 priv->tbiphy = bus->phy_map[*id];
290 }
291
292 return 0;
293
294 err_out:
295 iounmap(priv->regs);
296 return err;
297 }
298
299 /* Ioctl MII Interface */
300 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
301 {
302 struct gfar_private *priv = netdev_priv(dev);
303
304 if (!netif_running(dev))
305 return -EINVAL;
306
307 if (!priv->phydev)
308 return -ENODEV;
309
310 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
311 }
312
313 /* Set up the ethernet device structure, private data,
314 * and anything else we need before we start */
315 static int gfar_probe(struct of_device *ofdev,
316 const struct of_device_id *match)
317 {
318 u32 tempval;
319 struct net_device *dev = NULL;
320 struct gfar_private *priv = NULL;
321 DECLARE_MAC_BUF(mac);
322 int err = 0;
323 int len_devname;
324
325 /* Create an ethernet device instance */
326 dev = alloc_etherdev(sizeof (*priv));
327
328 if (NULL == dev)
329 return -ENOMEM;
330
331 priv = netdev_priv(dev);
332 priv->dev = dev;
333 priv->node = ofdev->node;
334
335 err = gfar_of_init(dev);
336
337 if (err)
338 goto regs_fail;
339
340 spin_lock_init(&priv->txlock);
341 spin_lock_init(&priv->rxlock);
342 spin_lock_init(&priv->bflock);
343 INIT_WORK(&priv->reset_task, gfar_reset_task);
344
345 dev_set_drvdata(&ofdev->dev, priv);
346
347 /* Stop the DMA engine now, in case it was running before */
348 /* (The firmware could have used it, and left it running). */
349 gfar_halt(dev);
350
351 /* Reset MAC layer */
352 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
353
354 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
355 gfar_write(&priv->regs->maccfg1, tempval);
356
357 /* Initialize MACCFG2. */
358 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
359
360 /* Initialize ECNTRL */
361 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
362
363 /* Set the dev->base_addr to the gfar reg region */
364 dev->base_addr = (unsigned long) (priv->regs);
365
366 SET_NETDEV_DEV(dev, &ofdev->dev);
367
368 /* Fill in the dev structure */
369 dev->open = gfar_enet_open;
370 dev->hard_start_xmit = gfar_start_xmit;
371 dev->tx_timeout = gfar_timeout;
372 dev->watchdog_timeo = TX_TIMEOUT;
373 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
374 #ifdef CONFIG_NET_POLL_CONTROLLER
375 dev->poll_controller = gfar_netpoll;
376 #endif
377 dev->stop = gfar_close;
378 dev->change_mtu = gfar_change_mtu;
379 dev->mtu = 1500;
380 dev->set_multicast_list = gfar_set_multi;
381
382 dev->ethtool_ops = &gfar_ethtool_ops;
383 dev->do_ioctl = gfar_ioctl;
384
385 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
386 priv->rx_csum_enable = 1;
387 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
388 } else
389 priv->rx_csum_enable = 0;
390
391 priv->vlgrp = NULL;
392
393 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
394 dev->vlan_rx_register = gfar_vlan_rx_register;
395
396 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
397 }
398
399 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
400 priv->extended_hash = 1;
401 priv->hash_width = 9;
402
403 priv->hash_regs[0] = &priv->regs->igaddr0;
404 priv->hash_regs[1] = &priv->regs->igaddr1;
405 priv->hash_regs[2] = &priv->regs->igaddr2;
406 priv->hash_regs[3] = &priv->regs->igaddr3;
407 priv->hash_regs[4] = &priv->regs->igaddr4;
408 priv->hash_regs[5] = &priv->regs->igaddr5;
409 priv->hash_regs[6] = &priv->regs->igaddr6;
410 priv->hash_regs[7] = &priv->regs->igaddr7;
411 priv->hash_regs[8] = &priv->regs->gaddr0;
412 priv->hash_regs[9] = &priv->regs->gaddr1;
413 priv->hash_regs[10] = &priv->regs->gaddr2;
414 priv->hash_regs[11] = &priv->regs->gaddr3;
415 priv->hash_regs[12] = &priv->regs->gaddr4;
416 priv->hash_regs[13] = &priv->regs->gaddr5;
417 priv->hash_regs[14] = &priv->regs->gaddr6;
418 priv->hash_regs[15] = &priv->regs->gaddr7;
419
420 } else {
421 priv->extended_hash = 0;
422 priv->hash_width = 8;
423
424 priv->hash_regs[0] = &priv->regs->gaddr0;
425 priv->hash_regs[1] = &priv->regs->gaddr1;
426 priv->hash_regs[2] = &priv->regs->gaddr2;
427 priv->hash_regs[3] = &priv->regs->gaddr3;
428 priv->hash_regs[4] = &priv->regs->gaddr4;
429 priv->hash_regs[5] = &priv->regs->gaddr5;
430 priv->hash_regs[6] = &priv->regs->gaddr6;
431 priv->hash_regs[7] = &priv->regs->gaddr7;
432 }
433
434 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
435 priv->padding = DEFAULT_PADDING;
436 else
437 priv->padding = 0;
438
439 if (dev->features & NETIF_F_IP_CSUM)
440 dev->hard_header_len += GMAC_FCB_LEN;
441
442 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
443 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
444 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
445 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
446
447 priv->txcoalescing = DEFAULT_TX_COALESCE;
448 priv->txic = DEFAULT_TXIC;
449 priv->rxcoalescing = DEFAULT_RX_COALESCE;
450 priv->rxic = DEFAULT_RXIC;
451
452 /* Enable most messages by default */
453 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
454
455 /* Carrier starts down, phylib will bring it up */
456 netif_carrier_off(dev);
457
458 err = register_netdev(dev);
459
460 if (err) {
461 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
462 dev->name);
463 goto register_fail;
464 }
465
466 /* fill out IRQ number and name fields */
467 len_devname = strlen(dev->name);
468 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
469 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
470 strncpy(&priv->int_name_tx[len_devname],
471 "_tx", sizeof("_tx") + 1);
472
473 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
474 strncpy(&priv->int_name_rx[len_devname],
475 "_rx", sizeof("_rx") + 1);
476
477 strncpy(&priv->int_name_er[0], dev->name, len_devname);
478 strncpy(&priv->int_name_er[len_devname],
479 "_er", sizeof("_er") + 1);
480 } else
481 priv->int_name_tx[len_devname] = '\0';
482
483 /* Create all the sysfs files */
484 gfar_init_sysfs(dev);
485
486 /* Print out the device info */
487 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
488
489 /* Even more device info helps when determining which kernel */
490 /* provided which set of benchmarks. */
491 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
492 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
493 dev->name, priv->rx_ring_size, priv->tx_ring_size);
494
495 return 0;
496
497 register_fail:
498 iounmap(priv->regs);
499 regs_fail:
500 free_netdev(dev);
501 return err;
502 }
503
504 static int gfar_remove(struct of_device *ofdev)
505 {
506 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
507
508 dev_set_drvdata(&ofdev->dev, NULL);
509
510 iounmap(priv->regs);
511 free_netdev(priv->dev);
512
513 return 0;
514 }
515
516 #ifdef CONFIG_PM
517 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
518 {
519 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
520 struct net_device *dev = priv->dev;
521 unsigned long flags;
522 u32 tempval;
523
524 int magic_packet = priv->wol_en &&
525 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
526
527 netif_device_detach(dev);
528
529 if (netif_running(dev)) {
530 spin_lock_irqsave(&priv->txlock, flags);
531 spin_lock(&priv->rxlock);
532
533 gfar_halt_nodisable(dev);
534
535 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
536 tempval = gfar_read(&priv->regs->maccfg1);
537
538 tempval &= ~MACCFG1_TX_EN;
539
540 if (!magic_packet)
541 tempval &= ~MACCFG1_RX_EN;
542
543 gfar_write(&priv->regs->maccfg1, tempval);
544
545 spin_unlock(&priv->rxlock);
546 spin_unlock_irqrestore(&priv->txlock, flags);
547
548 napi_disable(&priv->napi);
549
550 if (magic_packet) {
551 /* Enable interrupt on Magic Packet */
552 gfar_write(&priv->regs->imask, IMASK_MAG);
553
554 /* Enable Magic Packet mode */
555 tempval = gfar_read(&priv->regs->maccfg2);
556 tempval |= MACCFG2_MPEN;
557 gfar_write(&priv->regs->maccfg2, tempval);
558 } else {
559 phy_stop(priv->phydev);
560 }
561 }
562
563 return 0;
564 }
565
566 static int gfar_resume(struct of_device *ofdev)
567 {
568 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
569 struct net_device *dev = priv->dev;
570 unsigned long flags;
571 u32 tempval;
572 int magic_packet = priv->wol_en &&
573 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
574
575 if (!netif_running(dev)) {
576 netif_device_attach(dev);
577 return 0;
578 }
579
580 if (!magic_packet && priv->phydev)
581 phy_start(priv->phydev);
582
583 /* Disable Magic Packet mode, in case something
584 * else woke us up.
585 */
586
587 spin_lock_irqsave(&priv->txlock, flags);
588 spin_lock(&priv->rxlock);
589
590 tempval = gfar_read(&priv->regs->maccfg2);
591 tempval &= ~MACCFG2_MPEN;
592 gfar_write(&priv->regs->maccfg2, tempval);
593
594 gfar_start(dev);
595
596 spin_unlock(&priv->rxlock);
597 spin_unlock_irqrestore(&priv->txlock, flags);
598
599 netif_device_attach(dev);
600
601 napi_enable(&priv->napi);
602
603 return 0;
604 }
605 #else
606 #define gfar_suspend NULL
607 #define gfar_resume NULL
608 #endif
609
610 /* Reads the controller's registers to determine what interface
611 * connects it to the PHY.
612 */
613 static phy_interface_t gfar_get_interface(struct net_device *dev)
614 {
615 struct gfar_private *priv = netdev_priv(dev);
616 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
617
618 if (ecntrl & ECNTRL_SGMII_MODE)
619 return PHY_INTERFACE_MODE_SGMII;
620
621 if (ecntrl & ECNTRL_TBI_MODE) {
622 if (ecntrl & ECNTRL_REDUCED_MODE)
623 return PHY_INTERFACE_MODE_RTBI;
624 else
625 return PHY_INTERFACE_MODE_TBI;
626 }
627
628 if (ecntrl & ECNTRL_REDUCED_MODE) {
629 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
630 return PHY_INTERFACE_MODE_RMII;
631 else {
632 phy_interface_t interface = priv->interface;
633
634 /*
635 * This isn't autodetected right now, so it must
636 * be set by the device tree or platform code.
637 */
638 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
639 return PHY_INTERFACE_MODE_RGMII_ID;
640
641 return PHY_INTERFACE_MODE_RGMII;
642 }
643 }
644
645 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
646 return PHY_INTERFACE_MODE_GMII;
647
648 return PHY_INTERFACE_MODE_MII;
649 }
650
651
652 /* Initializes driver's PHY state, and attaches to the PHY.
653 * Returns 0 on success.
654 */
655 static int init_phy(struct net_device *dev)
656 {
657 struct gfar_private *priv = netdev_priv(dev);
658 uint gigabit_support =
659 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
660 SUPPORTED_1000baseT_Full : 0;
661 struct phy_device *phydev;
662 phy_interface_t interface;
663
664 priv->oldlink = 0;
665 priv->oldspeed = 0;
666 priv->oldduplex = -1;
667
668 interface = gfar_get_interface(dev);
669
670 phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
671
672 if (interface == PHY_INTERFACE_MODE_SGMII)
673 gfar_configure_serdes(dev);
674
675 if (IS_ERR(phydev)) {
676 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
677 return PTR_ERR(phydev);
678 }
679
680 /* Remove any features not supported by the controller */
681 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
682 phydev->advertising = phydev->supported;
683
684 priv->phydev = phydev;
685
686 return 0;
687 }
688
689 /*
690 * Initialize TBI PHY interface for communicating with the
691 * SERDES lynx PHY on the chip. We communicate with this PHY
692 * through the MDIO bus on each controller, treating it as a
693 * "normal" PHY at the address found in the TBIPA register. We assume
694 * that the TBIPA register is valid. Either the MDIO bus code will set
695 * it to a value that doesn't conflict with other PHYs on the bus, or the
696 * value doesn't matter, as there are no other PHYs on the bus.
697 */
698 static void gfar_configure_serdes(struct net_device *dev)
699 {
700 struct gfar_private *priv = netdev_priv(dev);
701
702 if (!priv->tbiphy) {
703 printk(KERN_WARNING "SGMII mode requires that the device "
704 "tree specify a tbi-handle\n");
705 return;
706 }
707
708 /*
709 * If the link is already up, we must already be ok, and don't need to
710 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
711 * everything for us? Resetting it takes the link down and requires
712 * several seconds for it to come back.
713 */
714 if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
715 return;
716
717 /* Single clk mode, mii mode off(for serdes communication) */
718 phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
719
720 phy_write(priv->tbiphy, MII_ADVERTISE,
721 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
722 ADVERTISE_1000XPSE_ASYM);
723
724 phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
725 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
726 }
727
728 static void init_registers(struct net_device *dev)
729 {
730 struct gfar_private *priv = netdev_priv(dev);
731
732 /* Clear IEVENT */
733 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
734
735 /* Initialize IMASK */
736 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
737
738 /* Init hash registers to zero */
739 gfar_write(&priv->regs->igaddr0, 0);
740 gfar_write(&priv->regs->igaddr1, 0);
741 gfar_write(&priv->regs->igaddr2, 0);
742 gfar_write(&priv->regs->igaddr3, 0);
743 gfar_write(&priv->regs->igaddr4, 0);
744 gfar_write(&priv->regs->igaddr5, 0);
745 gfar_write(&priv->regs->igaddr6, 0);
746 gfar_write(&priv->regs->igaddr7, 0);
747
748 gfar_write(&priv->regs->gaddr0, 0);
749 gfar_write(&priv->regs->gaddr1, 0);
750 gfar_write(&priv->regs->gaddr2, 0);
751 gfar_write(&priv->regs->gaddr3, 0);
752 gfar_write(&priv->regs->gaddr4, 0);
753 gfar_write(&priv->regs->gaddr5, 0);
754 gfar_write(&priv->regs->gaddr6, 0);
755 gfar_write(&priv->regs->gaddr7, 0);
756
757 /* Zero out the rmon mib registers if it has them */
758 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
759 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
760
761 /* Mask off the CAM interrupts */
762 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
763 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
764 }
765
766 /* Initialize the max receive buffer length */
767 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
768
769 /* Initialize the Minimum Frame Length Register */
770 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
771 }
772
773
774 /* Halt the receive and transmit queues */
775 static void gfar_halt_nodisable(struct net_device *dev)
776 {
777 struct gfar_private *priv = netdev_priv(dev);
778 struct gfar __iomem *regs = priv->regs;
779 u32 tempval;
780
781 /* Mask all interrupts */
782 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
783
784 /* Clear all interrupts */
785 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
786
787 /* Stop the DMA, and wait for it to stop */
788 tempval = gfar_read(&priv->regs->dmactrl);
789 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
790 != (DMACTRL_GRS | DMACTRL_GTS)) {
791 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
792 gfar_write(&priv->regs->dmactrl, tempval);
793
794 while (!(gfar_read(&priv->regs->ievent) &
795 (IEVENT_GRSC | IEVENT_GTSC)))
796 cpu_relax();
797 }
798 }
799
800 /* Halt the receive and transmit queues */
801 void gfar_halt(struct net_device *dev)
802 {
803 struct gfar_private *priv = netdev_priv(dev);
804 struct gfar __iomem *regs = priv->regs;
805 u32 tempval;
806
807 gfar_halt_nodisable(dev);
808
809 /* Disable Rx and Tx */
810 tempval = gfar_read(&regs->maccfg1);
811 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
812 gfar_write(&regs->maccfg1, tempval);
813 }
814
815 void stop_gfar(struct net_device *dev)
816 {
817 struct gfar_private *priv = netdev_priv(dev);
818 struct gfar __iomem *regs = priv->regs;
819 unsigned long flags;
820
821 phy_stop(priv->phydev);
822
823 /* Lock it down */
824 spin_lock_irqsave(&priv->txlock, flags);
825 spin_lock(&priv->rxlock);
826
827 gfar_halt(dev);
828
829 spin_unlock(&priv->rxlock);
830 spin_unlock_irqrestore(&priv->txlock, flags);
831
832 /* Free the IRQs */
833 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
834 free_irq(priv->interruptError, dev);
835 free_irq(priv->interruptTransmit, dev);
836 free_irq(priv->interruptReceive, dev);
837 } else {
838 free_irq(priv->interruptTransmit, dev);
839 }
840
841 free_skb_resources(priv);
842
843 dma_free_coherent(&dev->dev,
844 sizeof(struct txbd8)*priv->tx_ring_size
845 + sizeof(struct rxbd8)*priv->rx_ring_size,
846 priv->tx_bd_base,
847 gfar_read(&regs->tbase0));
848 }
849
850 /* If there are any tx skbs or rx skbs still around, free them.
851 * Then free tx_skbuff and rx_skbuff */
852 static void free_skb_resources(struct gfar_private *priv)
853 {
854 struct rxbd8 *rxbdp;
855 struct txbd8 *txbdp;
856 int i, j;
857
858 /* Go through all the buffer descriptors and free their data buffers */
859 txbdp = priv->tx_bd_base;
860
861 for (i = 0; i < priv->tx_ring_size; i++) {
862 if (!priv->tx_skbuff[i])
863 continue;
864
865 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
866 txbdp->length, DMA_TO_DEVICE);
867 txbdp->lstatus = 0;
868 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
869 txbdp++;
870 dma_unmap_page(&priv->dev->dev, txbdp->bufPtr,
871 txbdp->length, DMA_TO_DEVICE);
872 }
873 txbdp++;
874 dev_kfree_skb_any(priv->tx_skbuff[i]);
875 priv->tx_skbuff[i] = NULL;
876 }
877
878 kfree(priv->tx_skbuff);
879
880 rxbdp = priv->rx_bd_base;
881
882 /* rx_skbuff is not guaranteed to be allocated, so only
883 * free it and its contents if it is allocated */
884 if(priv->rx_skbuff != NULL) {
885 for (i = 0; i < priv->rx_ring_size; i++) {
886 if (priv->rx_skbuff[i]) {
887 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
888 priv->rx_buffer_size,
889 DMA_FROM_DEVICE);
890
891 dev_kfree_skb_any(priv->rx_skbuff[i]);
892 priv->rx_skbuff[i] = NULL;
893 }
894
895 rxbdp->lstatus = 0;
896 rxbdp->bufPtr = 0;
897
898 rxbdp++;
899 }
900
901 kfree(priv->rx_skbuff);
902 }
903 }
904
905 void gfar_start(struct net_device *dev)
906 {
907 struct gfar_private *priv = netdev_priv(dev);
908 struct gfar __iomem *regs = priv->regs;
909 u32 tempval;
910
911 /* Enable Rx and Tx in MACCFG1 */
912 tempval = gfar_read(&regs->maccfg1);
913 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
914 gfar_write(&regs->maccfg1, tempval);
915
916 /* Initialize DMACTRL to have WWR and WOP */
917 tempval = gfar_read(&priv->regs->dmactrl);
918 tempval |= DMACTRL_INIT_SETTINGS;
919 gfar_write(&priv->regs->dmactrl, tempval);
920
921 /* Make sure we aren't stopped */
922 tempval = gfar_read(&priv->regs->dmactrl);
923 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
924 gfar_write(&priv->regs->dmactrl, tempval);
925
926 /* Clear THLT/RHLT, so that the DMA starts polling now */
927 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
928 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
929
930 /* Unmask the interrupts we look for */
931 gfar_write(&regs->imask, IMASK_DEFAULT);
932
933 dev->trans_start = jiffies;
934 }
935
936 /* Bring the controller up and running */
937 int startup_gfar(struct net_device *dev)
938 {
939 struct txbd8 *txbdp;
940 struct rxbd8 *rxbdp;
941 dma_addr_t addr = 0;
942 unsigned long vaddr;
943 int i;
944 struct gfar_private *priv = netdev_priv(dev);
945 struct gfar __iomem *regs = priv->regs;
946 int err = 0;
947 u32 rctrl = 0;
948 u32 attrs = 0;
949
950 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
951
952 /* Allocate memory for the buffer descriptors */
953 vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
954 sizeof (struct txbd8) * priv->tx_ring_size +
955 sizeof (struct rxbd8) * priv->rx_ring_size,
956 &addr, GFP_KERNEL);
957
958 if (vaddr == 0) {
959 if (netif_msg_ifup(priv))
960 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
961 dev->name);
962 return -ENOMEM;
963 }
964
965 priv->tx_bd_base = (struct txbd8 *) vaddr;
966
967 /* enet DMA only understands physical addresses */
968 gfar_write(&regs->tbase0, addr);
969
970 /* Start the rx descriptor ring where the tx ring leaves off */
971 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
972 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
973 priv->rx_bd_base = (struct rxbd8 *) vaddr;
974 gfar_write(&regs->rbase0, addr);
975
976 /* Setup the skbuff rings */
977 priv->tx_skbuff =
978 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
979 priv->tx_ring_size, GFP_KERNEL);
980
981 if (NULL == priv->tx_skbuff) {
982 if (netif_msg_ifup(priv))
983 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
984 dev->name);
985 err = -ENOMEM;
986 goto tx_skb_fail;
987 }
988
989 for (i = 0; i < priv->tx_ring_size; i++)
990 priv->tx_skbuff[i] = NULL;
991
992 priv->rx_skbuff =
993 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
994 priv->rx_ring_size, GFP_KERNEL);
995
996 if (NULL == priv->rx_skbuff) {
997 if (netif_msg_ifup(priv))
998 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
999 dev->name);
1000 err = -ENOMEM;
1001 goto rx_skb_fail;
1002 }
1003
1004 for (i = 0; i < priv->rx_ring_size; i++)
1005 priv->rx_skbuff[i] = NULL;
1006
1007 /* Initialize some variables in our dev structure */
1008 priv->num_txbdfree = priv->tx_ring_size;
1009 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1010 priv->cur_rx = priv->rx_bd_base;
1011 priv->skb_curtx = priv->skb_dirtytx = 0;
1012 priv->skb_currx = 0;
1013
1014 /* Initialize Transmit Descriptor Ring */
1015 txbdp = priv->tx_bd_base;
1016 for (i = 0; i < priv->tx_ring_size; i++) {
1017 txbdp->lstatus = 0;
1018 txbdp->bufPtr = 0;
1019 txbdp++;
1020 }
1021
1022 /* Set the last descriptor in the ring to indicate wrap */
1023 txbdp--;
1024 txbdp->status |= TXBD_WRAP;
1025
1026 rxbdp = priv->rx_bd_base;
1027 for (i = 0; i < priv->rx_ring_size; i++) {
1028 struct sk_buff *skb;
1029
1030 skb = gfar_new_skb(dev);
1031
1032 if (!skb) {
1033 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1034 dev->name);
1035
1036 goto err_rxalloc_fail;
1037 }
1038
1039 priv->rx_skbuff[i] = skb;
1040
1041 gfar_new_rxbdp(dev, rxbdp, skb);
1042
1043 rxbdp++;
1044 }
1045
1046 /* Set the last descriptor in the ring to wrap */
1047 rxbdp--;
1048 rxbdp->status |= RXBD_WRAP;
1049
1050 /* If the device has multiple interrupts, register for
1051 * them. Otherwise, only register for the one */
1052 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1053 /* Install our interrupt handlers for Error,
1054 * Transmit, and Receive */
1055 if (request_irq(priv->interruptError, gfar_error,
1056 0, priv->int_name_er, dev) < 0) {
1057 if (netif_msg_intr(priv))
1058 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1059 dev->name, priv->interruptError);
1060
1061 err = -1;
1062 goto err_irq_fail;
1063 }
1064
1065 if (request_irq(priv->interruptTransmit, gfar_transmit,
1066 0, priv->int_name_tx, dev) < 0) {
1067 if (netif_msg_intr(priv))
1068 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1069 dev->name, priv->interruptTransmit);
1070
1071 err = -1;
1072
1073 goto tx_irq_fail;
1074 }
1075
1076 if (request_irq(priv->interruptReceive, gfar_receive,
1077 0, priv->int_name_rx, dev) < 0) {
1078 if (netif_msg_intr(priv))
1079 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1080 dev->name, priv->interruptReceive);
1081
1082 err = -1;
1083 goto rx_irq_fail;
1084 }
1085 } else {
1086 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1087 0, priv->int_name_tx, dev) < 0) {
1088 if (netif_msg_intr(priv))
1089 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1090 dev->name, priv->interruptTransmit);
1091
1092 err = -1;
1093 goto err_irq_fail;
1094 }
1095 }
1096
1097 phy_start(priv->phydev);
1098
1099 /* Configure the coalescing support */
1100 gfar_write(&regs->txic, 0);
1101 if (priv->txcoalescing)
1102 gfar_write(&regs->txic, priv->txic);
1103
1104 gfar_write(&regs->rxic, 0);
1105 if (priv->rxcoalescing)
1106 gfar_write(&regs->rxic, priv->rxic);
1107
1108 if (priv->rx_csum_enable)
1109 rctrl |= RCTRL_CHECKSUMMING;
1110
1111 if (priv->extended_hash) {
1112 rctrl |= RCTRL_EXTHASH;
1113
1114 gfar_clear_exact_match(dev);
1115 rctrl |= RCTRL_EMEN;
1116 }
1117
1118 if (priv->padding) {
1119 rctrl &= ~RCTRL_PAL_MASK;
1120 rctrl |= RCTRL_PADDING(priv->padding);
1121 }
1122
1123 /* Init rctrl based on our settings */
1124 gfar_write(&priv->regs->rctrl, rctrl);
1125
1126 if (dev->features & NETIF_F_IP_CSUM)
1127 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1128
1129 /* Set the extraction length and index */
1130 attrs = ATTRELI_EL(priv->rx_stash_size) |
1131 ATTRELI_EI(priv->rx_stash_index);
1132
1133 gfar_write(&priv->regs->attreli, attrs);
1134
1135 /* Start with defaults, and add stashing or locking
1136 * depending on the approprate variables */
1137 attrs = ATTR_INIT_SETTINGS;
1138
1139 if (priv->bd_stash_en)
1140 attrs |= ATTR_BDSTASH;
1141
1142 if (priv->rx_stash_size != 0)
1143 attrs |= ATTR_BUFSTASH;
1144
1145 gfar_write(&priv->regs->attr, attrs);
1146
1147 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1148 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1149 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1150
1151 /* Start the controller */
1152 gfar_start(dev);
1153
1154 return 0;
1155
1156 rx_irq_fail:
1157 free_irq(priv->interruptTransmit, dev);
1158 tx_irq_fail:
1159 free_irq(priv->interruptError, dev);
1160 err_irq_fail:
1161 err_rxalloc_fail:
1162 rx_skb_fail:
1163 free_skb_resources(priv);
1164 tx_skb_fail:
1165 dma_free_coherent(&dev->dev,
1166 sizeof(struct txbd8)*priv->tx_ring_size
1167 + sizeof(struct rxbd8)*priv->rx_ring_size,
1168 priv->tx_bd_base,
1169 gfar_read(&regs->tbase0));
1170
1171 return err;
1172 }
1173
1174 /* Called when something needs to use the ethernet device */
1175 /* Returns 0 for success. */
1176 static int gfar_enet_open(struct net_device *dev)
1177 {
1178 struct gfar_private *priv = netdev_priv(dev);
1179 int err;
1180
1181 napi_enable(&priv->napi);
1182
1183 /* Initialize a bunch of registers */
1184 init_registers(dev);
1185
1186 gfar_set_mac_address(dev);
1187
1188 err = init_phy(dev);
1189
1190 if(err) {
1191 napi_disable(&priv->napi);
1192 return err;
1193 }
1194
1195 err = startup_gfar(dev);
1196 if (err) {
1197 napi_disable(&priv->napi);
1198 return err;
1199 }
1200
1201 netif_start_queue(dev);
1202
1203 return err;
1204 }
1205
1206 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1207 {
1208 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1209
1210 cacheable_memzero(fcb, GMAC_FCB_LEN);
1211
1212 return fcb;
1213 }
1214
1215 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1216 {
1217 u8 flags = 0;
1218
1219 /* If we're here, it's a IP packet with a TCP or UDP
1220 * payload. We set it to checksum, using a pseudo-header
1221 * we provide
1222 */
1223 flags = TXFCB_DEFAULT;
1224
1225 /* Tell the controller what the protocol is */
1226 /* And provide the already calculated phcs */
1227 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1228 flags |= TXFCB_UDP;
1229 fcb->phcs = udp_hdr(skb)->check;
1230 } else
1231 fcb->phcs = tcp_hdr(skb)->check;
1232
1233 /* l3os is the distance between the start of the
1234 * frame (skb->data) and the start of the IP hdr.
1235 * l4os is the distance between the start of the
1236 * l3 hdr and the l4 hdr */
1237 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1238 fcb->l4os = skb_network_header_len(skb);
1239
1240 fcb->flags = flags;
1241 }
1242
1243 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1244 {
1245 fcb->flags |= TXFCB_VLN;
1246 fcb->vlctl = vlan_tx_tag_get(skb);
1247 }
1248
1249 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1250 struct txbd8 *base, int ring_size)
1251 {
1252 struct txbd8 *new_bd = bdp + stride;
1253
1254 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1255 }
1256
1257 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1258 int ring_size)
1259 {
1260 return skip_txbd(bdp, 1, base, ring_size);
1261 }
1262
1263 /* This is called by the kernel when a frame is ready for transmission. */
1264 /* It is pointed to by the dev->hard_start_xmit function pointer */
1265 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1266 {
1267 struct gfar_private *priv = netdev_priv(dev);
1268 struct txfcb *fcb = NULL;
1269 struct txbd8 *txbdp, *txbdp_start, *base;
1270 u32 lstatus;
1271 int i;
1272 u32 bufaddr;
1273 unsigned long flags;
1274 unsigned int nr_frags, length;
1275
1276 base = priv->tx_bd_base;
1277
1278 /* total number of fragments in the SKB */
1279 nr_frags = skb_shinfo(skb)->nr_frags;
1280
1281 spin_lock_irqsave(&priv->txlock, flags);
1282
1283 /* check if there is space to queue this packet */
1284 if (nr_frags > priv->num_txbdfree) {
1285 /* no space, stop the queue */
1286 netif_stop_queue(dev);
1287 dev->stats.tx_fifo_errors++;
1288 spin_unlock_irqrestore(&priv->txlock, flags);
1289 return NETDEV_TX_BUSY;
1290 }
1291
1292 /* Update transmit stats */
1293 dev->stats.tx_bytes += skb->len;
1294
1295 txbdp = txbdp_start = priv->cur_tx;
1296
1297 if (nr_frags == 0) {
1298 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1299 } else {
1300 /* Place the fragment addresses and lengths into the TxBDs */
1301 for (i = 0; i < nr_frags; i++) {
1302 /* Point at the next BD, wrapping as needed */
1303 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1304
1305 length = skb_shinfo(skb)->frags[i].size;
1306
1307 lstatus = txbdp->lstatus | length |
1308 BD_LFLAG(TXBD_READY);
1309
1310 /* Handle the last BD specially */
1311 if (i == nr_frags - 1)
1312 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1313
1314 bufaddr = dma_map_page(&dev->dev,
1315 skb_shinfo(skb)->frags[i].page,
1316 skb_shinfo(skb)->frags[i].page_offset,
1317 length,
1318 DMA_TO_DEVICE);
1319
1320 /* set the TxBD length and buffer pointer */
1321 txbdp->bufPtr = bufaddr;
1322 txbdp->lstatus = lstatus;
1323 }
1324
1325 lstatus = txbdp_start->lstatus;
1326 }
1327
1328 /* Set up checksumming */
1329 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1330 fcb = gfar_add_fcb(skb);
1331 lstatus |= BD_LFLAG(TXBD_TOE);
1332 gfar_tx_checksum(skb, fcb);
1333 }
1334
1335 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1336 if (unlikely(NULL == fcb)) {
1337 fcb = gfar_add_fcb(skb);
1338 lstatus |= BD_LFLAG(TXBD_TOE);
1339 }
1340
1341 gfar_tx_vlan(skb, fcb);
1342 }
1343
1344 /* setup the TxBD length and buffer pointer for the first BD */
1345 priv->tx_skbuff[priv->skb_curtx] = skb;
1346 txbdp_start->bufPtr = dma_map_single(&dev->dev, skb->data,
1347 skb_headlen(skb), DMA_TO_DEVICE);
1348
1349 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1350
1351 /*
1352 * The powerpc-specific eieio() is used, as wmb() has too strong
1353 * semantics (it requires synchronization between cacheable and
1354 * uncacheable mappings, which eieio doesn't provide and which we
1355 * don't need), thus requiring a more expensive sync instruction. At
1356 * some point, the set of architecture-independent barrier functions
1357 * should be expanded to include weaker barriers.
1358 */
1359 eieio();
1360
1361 txbdp_start->lstatus = lstatus;
1362
1363 /* Update the current skb pointer to the next entry we will use
1364 * (wrapping if necessary) */
1365 priv->skb_curtx = (priv->skb_curtx + 1) &
1366 TX_RING_MOD_MASK(priv->tx_ring_size);
1367
1368 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1369
1370 /* reduce TxBD free count */
1371 priv->num_txbdfree -= (nr_frags + 1);
1372
1373 dev->trans_start = jiffies;
1374
1375 /* If the next BD still needs to be cleaned up, then the bds
1376 are full. We need to tell the kernel to stop sending us stuff. */
1377 if (!priv->num_txbdfree) {
1378 netif_stop_queue(dev);
1379
1380 dev->stats.tx_fifo_errors++;
1381 }
1382
1383 /* Tell the DMA to go go go */
1384 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1385
1386 /* Unlock priv */
1387 spin_unlock_irqrestore(&priv->txlock, flags);
1388
1389 return 0;
1390 }
1391
1392 /* Stops the kernel queue, and halts the controller */
1393 static int gfar_close(struct net_device *dev)
1394 {
1395 struct gfar_private *priv = netdev_priv(dev);
1396
1397 napi_disable(&priv->napi);
1398
1399 cancel_work_sync(&priv->reset_task);
1400 stop_gfar(dev);
1401
1402 /* Disconnect from the PHY */
1403 phy_disconnect(priv->phydev);
1404 priv->phydev = NULL;
1405
1406 netif_stop_queue(dev);
1407
1408 return 0;
1409 }
1410
1411 /* Changes the mac address if the controller is not running. */
1412 static int gfar_set_mac_address(struct net_device *dev)
1413 {
1414 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1415
1416 return 0;
1417 }
1418
1419
1420 /* Enables and disables VLAN insertion/extraction */
1421 static void gfar_vlan_rx_register(struct net_device *dev,
1422 struct vlan_group *grp)
1423 {
1424 struct gfar_private *priv = netdev_priv(dev);
1425 unsigned long flags;
1426 struct vlan_group *old_grp;
1427 u32 tempval;
1428
1429 spin_lock_irqsave(&priv->rxlock, flags);
1430
1431 old_grp = priv->vlgrp;
1432
1433 if (old_grp == grp)
1434 return;
1435
1436 if (grp) {
1437 /* Enable VLAN tag insertion */
1438 tempval = gfar_read(&priv->regs->tctrl);
1439 tempval |= TCTRL_VLINS;
1440
1441 gfar_write(&priv->regs->tctrl, tempval);
1442
1443 /* Enable VLAN tag extraction */
1444 tempval = gfar_read(&priv->regs->rctrl);
1445 tempval |= RCTRL_VLEX;
1446 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1447 gfar_write(&priv->regs->rctrl, tempval);
1448 } else {
1449 /* Disable VLAN tag insertion */
1450 tempval = gfar_read(&priv->regs->tctrl);
1451 tempval &= ~TCTRL_VLINS;
1452 gfar_write(&priv->regs->tctrl, tempval);
1453
1454 /* Disable VLAN tag extraction */
1455 tempval = gfar_read(&priv->regs->rctrl);
1456 tempval &= ~RCTRL_VLEX;
1457 /* If parse is no longer required, then disable parser */
1458 if (tempval & RCTRL_REQ_PARSER)
1459 tempval |= RCTRL_PRSDEP_INIT;
1460 else
1461 tempval &= ~RCTRL_PRSDEP_INIT;
1462 gfar_write(&priv->regs->rctrl, tempval);
1463 }
1464
1465 gfar_change_mtu(dev, dev->mtu);
1466
1467 spin_unlock_irqrestore(&priv->rxlock, flags);
1468 }
1469
1470 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1471 {
1472 int tempsize, tempval;
1473 struct gfar_private *priv = netdev_priv(dev);
1474 int oldsize = priv->rx_buffer_size;
1475 int frame_size = new_mtu + ETH_HLEN;
1476
1477 if (priv->vlgrp)
1478 frame_size += VLAN_HLEN;
1479
1480 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1481 if (netif_msg_drv(priv))
1482 printk(KERN_ERR "%s: Invalid MTU setting\n",
1483 dev->name);
1484 return -EINVAL;
1485 }
1486
1487 if (gfar_uses_fcb(priv))
1488 frame_size += GMAC_FCB_LEN;
1489
1490 frame_size += priv->padding;
1491
1492 tempsize =
1493 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1494 INCREMENTAL_BUFFER_SIZE;
1495
1496 /* Only stop and start the controller if it isn't already
1497 * stopped, and we changed something */
1498 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1499 stop_gfar(dev);
1500
1501 priv->rx_buffer_size = tempsize;
1502
1503 dev->mtu = new_mtu;
1504
1505 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1506 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1507
1508 /* If the mtu is larger than the max size for standard
1509 * ethernet frames (ie, a jumbo frame), then set maccfg2
1510 * to allow huge frames, and to check the length */
1511 tempval = gfar_read(&priv->regs->maccfg2);
1512
1513 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1514 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1515 else
1516 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1517
1518 gfar_write(&priv->regs->maccfg2, tempval);
1519
1520 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1521 startup_gfar(dev);
1522
1523 return 0;
1524 }
1525
1526 /* gfar_reset_task gets scheduled when a packet has not been
1527 * transmitted after a set amount of time.
1528 * For now, assume that clearing out all the structures, and
1529 * starting over will fix the problem.
1530 */
1531 static void gfar_reset_task(struct work_struct *work)
1532 {
1533 struct gfar_private *priv = container_of(work, struct gfar_private,
1534 reset_task);
1535 struct net_device *dev = priv->dev;
1536
1537 if (dev->flags & IFF_UP) {
1538 stop_gfar(dev);
1539 startup_gfar(dev);
1540 }
1541
1542 netif_tx_schedule_all(dev);
1543 }
1544
1545 static void gfar_timeout(struct net_device *dev)
1546 {
1547 struct gfar_private *priv = netdev_priv(dev);
1548
1549 dev->stats.tx_errors++;
1550 schedule_work(&priv->reset_task);
1551 }
1552
1553 /* Interrupt Handler for Transmit complete */
1554 static int gfar_clean_tx_ring(struct net_device *dev)
1555 {
1556 struct gfar_private *priv = netdev_priv(dev);
1557 struct txbd8 *bdp;
1558 struct txbd8 *lbdp = NULL;
1559 struct txbd8 *base = priv->tx_bd_base;
1560 struct sk_buff *skb;
1561 int skb_dirtytx;
1562 int tx_ring_size = priv->tx_ring_size;
1563 int frags = 0;
1564 int i;
1565 int howmany = 0;
1566 u32 lstatus;
1567
1568 bdp = priv->dirty_tx;
1569 skb_dirtytx = priv->skb_dirtytx;
1570
1571 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1572 frags = skb_shinfo(skb)->nr_frags;
1573 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1574
1575 lstatus = lbdp->lstatus;
1576
1577 /* Only clean completed frames */
1578 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1579 (lstatus & BD_LENGTH_MASK))
1580 break;
1581
1582 dma_unmap_single(&dev->dev,
1583 bdp->bufPtr,
1584 bdp->length,
1585 DMA_TO_DEVICE);
1586
1587 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1588 bdp = next_txbd(bdp, base, tx_ring_size);
1589
1590 for (i = 0; i < frags; i++) {
1591 dma_unmap_page(&dev->dev,
1592 bdp->bufPtr,
1593 bdp->length,
1594 DMA_TO_DEVICE);
1595 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1596 bdp = next_txbd(bdp, base, tx_ring_size);
1597 }
1598
1599 dev_kfree_skb_any(skb);
1600 priv->tx_skbuff[skb_dirtytx] = NULL;
1601
1602 skb_dirtytx = (skb_dirtytx + 1) &
1603 TX_RING_MOD_MASK(tx_ring_size);
1604
1605 howmany++;
1606 priv->num_txbdfree += frags + 1;
1607 }
1608
1609 /* If we freed a buffer, we can restart transmission, if necessary */
1610 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1611 netif_wake_queue(dev);
1612
1613 /* Update dirty indicators */
1614 priv->skb_dirtytx = skb_dirtytx;
1615 priv->dirty_tx = bdp;
1616
1617 dev->stats.tx_packets += howmany;
1618
1619 return howmany;
1620 }
1621
1622 static void gfar_schedule_cleanup(struct net_device *dev)
1623 {
1624 struct gfar_private *priv = netdev_priv(dev);
1625 unsigned long flags;
1626
1627 spin_lock_irqsave(&priv->txlock, flags);
1628 spin_lock(&priv->rxlock);
1629
1630 if (netif_rx_schedule_prep(&priv->napi)) {
1631 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1632 __netif_rx_schedule(&priv->napi);
1633 }
1634
1635 spin_unlock(&priv->rxlock);
1636 spin_unlock_irqrestore(&priv->txlock, flags);
1637 }
1638
1639 /* Interrupt Handler for Transmit complete */
1640 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1641 {
1642 gfar_schedule_cleanup((struct net_device *)dev_id);
1643 return IRQ_HANDLED;
1644 }
1645
1646 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1647 struct sk_buff *skb)
1648 {
1649 struct gfar_private *priv = netdev_priv(dev);
1650 u32 lstatus;
1651
1652 bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1653 priv->rx_buffer_size, DMA_FROM_DEVICE);
1654
1655 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1656
1657 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1658 lstatus |= BD_LFLAG(RXBD_WRAP);
1659
1660 eieio();
1661
1662 bdp->lstatus = lstatus;
1663 }
1664
1665
1666 struct sk_buff * gfar_new_skb(struct net_device *dev)
1667 {
1668 unsigned int alignamount;
1669 struct gfar_private *priv = netdev_priv(dev);
1670 struct sk_buff *skb = NULL;
1671
1672 /* We have to allocate the skb, so keep trying till we succeed */
1673 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1674
1675 if (!skb)
1676 return NULL;
1677
1678 alignamount = RXBUF_ALIGNMENT -
1679 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1680
1681 /* We need the data buffer to be aligned properly. We will reserve
1682 * as many bytes as needed to align the data properly
1683 */
1684 skb_reserve(skb, alignamount);
1685
1686 return skb;
1687 }
1688
1689 static inline void count_errors(unsigned short status, struct net_device *dev)
1690 {
1691 struct gfar_private *priv = netdev_priv(dev);
1692 struct net_device_stats *stats = &dev->stats;
1693 struct gfar_extra_stats *estats = &priv->extra_stats;
1694
1695 /* If the packet was truncated, none of the other errors
1696 * matter */
1697 if (status & RXBD_TRUNCATED) {
1698 stats->rx_length_errors++;
1699
1700 estats->rx_trunc++;
1701
1702 return;
1703 }
1704 /* Count the errors, if there were any */
1705 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1706 stats->rx_length_errors++;
1707
1708 if (status & RXBD_LARGE)
1709 estats->rx_large++;
1710 else
1711 estats->rx_short++;
1712 }
1713 if (status & RXBD_NONOCTET) {
1714 stats->rx_frame_errors++;
1715 estats->rx_nonoctet++;
1716 }
1717 if (status & RXBD_CRCERR) {
1718 estats->rx_crcerr++;
1719 stats->rx_crc_errors++;
1720 }
1721 if (status & RXBD_OVERRUN) {
1722 estats->rx_overrun++;
1723 stats->rx_crc_errors++;
1724 }
1725 }
1726
1727 irqreturn_t gfar_receive(int irq, void *dev_id)
1728 {
1729 gfar_schedule_cleanup((struct net_device *)dev_id);
1730 return IRQ_HANDLED;
1731 }
1732
1733 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1734 {
1735 /* If valid headers were found, and valid sums
1736 * were verified, then we tell the kernel that no
1737 * checksumming is necessary. Otherwise, it is */
1738 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1739 skb->ip_summed = CHECKSUM_UNNECESSARY;
1740 else
1741 skb->ip_summed = CHECKSUM_NONE;
1742 }
1743
1744
1745 /* gfar_process_frame() -- handle one incoming packet if skb
1746 * isn't NULL. */
1747 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1748 int amount_pull)
1749 {
1750 struct gfar_private *priv = netdev_priv(dev);
1751 struct rxfcb *fcb = NULL;
1752
1753 int ret;
1754
1755 /* fcb is at the beginning if exists */
1756 fcb = (struct rxfcb *)skb->data;
1757
1758 /* Remove the FCB from the skb */
1759 /* Remove the padded bytes, if there are any */
1760 if (amount_pull)
1761 skb_pull(skb, amount_pull);
1762
1763 if (priv->rx_csum_enable)
1764 gfar_rx_checksum(skb, fcb);
1765
1766 /* Tell the skb what kind of packet this is */
1767 skb->protocol = eth_type_trans(skb, dev);
1768
1769 /* Send the packet up the stack */
1770 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1771 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1772 else
1773 ret = netif_receive_skb(skb);
1774
1775 if (NET_RX_DROP == ret)
1776 priv->extra_stats.kernel_dropped++;
1777
1778 return 0;
1779 }
1780
1781 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1782 * until the budget/quota has been reached. Returns the number
1783 * of frames handled
1784 */
1785 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1786 {
1787 struct rxbd8 *bdp, *base;
1788 struct sk_buff *skb;
1789 int pkt_len;
1790 int amount_pull;
1791 int howmany = 0;
1792 struct gfar_private *priv = netdev_priv(dev);
1793
1794 /* Get the first full descriptor */
1795 bdp = priv->cur_rx;
1796 base = priv->rx_bd_base;
1797
1798 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1799 priv->padding;
1800
1801 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1802 struct sk_buff *newskb;
1803 rmb();
1804
1805 /* Add another skb for the future */
1806 newskb = gfar_new_skb(dev);
1807
1808 skb = priv->rx_skbuff[priv->skb_currx];
1809
1810 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1811 priv->rx_buffer_size, DMA_FROM_DEVICE);
1812
1813 /* We drop the frame if we failed to allocate a new buffer */
1814 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1815 bdp->status & RXBD_ERR)) {
1816 count_errors(bdp->status, dev);
1817
1818 if (unlikely(!newskb))
1819 newskb = skb;
1820 else if (skb)
1821 dev_kfree_skb_any(skb);
1822 } else {
1823 /* Increment the number of packets */
1824 dev->stats.rx_packets++;
1825 howmany++;
1826
1827 if (likely(skb)) {
1828 pkt_len = bdp->length - ETH_FCS_LEN;
1829 /* Remove the FCS from the packet length */
1830 skb_put(skb, pkt_len);
1831 dev->stats.rx_bytes += pkt_len;
1832
1833 gfar_process_frame(dev, skb, amount_pull);
1834
1835 } else {
1836 if (netif_msg_rx_err(priv))
1837 printk(KERN_WARNING
1838 "%s: Missing skb!\n", dev->name);
1839 dev->stats.rx_dropped++;
1840 priv->extra_stats.rx_skbmissing++;
1841 }
1842
1843 }
1844
1845 priv->rx_skbuff[priv->skb_currx] = newskb;
1846
1847 /* Setup the new bdp */
1848 gfar_new_rxbdp(dev, bdp, newskb);
1849
1850 /* Update to the next pointer */
1851 bdp = next_bd(bdp, base, priv->rx_ring_size);
1852
1853 /* update to point at the next skb */
1854 priv->skb_currx =
1855 (priv->skb_currx + 1) &
1856 RX_RING_MOD_MASK(priv->rx_ring_size);
1857 }
1858
1859 /* Update the current rxbd pointer to be the next one */
1860 priv->cur_rx = bdp;
1861
1862 return howmany;
1863 }
1864
1865 static int gfar_poll(struct napi_struct *napi, int budget)
1866 {
1867 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1868 struct net_device *dev = priv->dev;
1869 int tx_cleaned = 0;
1870 int rx_cleaned = 0;
1871 unsigned long flags;
1872
1873 /* Clear IEVENT, so interrupts aren't called again
1874 * because of the packets that have already arrived */
1875 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1876
1877 /* If we fail to get the lock, don't bother with the TX BDs */
1878 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1879 tx_cleaned = gfar_clean_tx_ring(dev);
1880 spin_unlock_irqrestore(&priv->txlock, flags);
1881 }
1882
1883 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1884
1885 if (tx_cleaned)
1886 return budget;
1887
1888 if (rx_cleaned < budget) {
1889 netif_rx_complete(napi);
1890
1891 /* Clear the halt bit in RSTAT */
1892 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1893
1894 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1895
1896 /* If we are coalescing interrupts, update the timer */
1897 /* Otherwise, clear it */
1898 if (likely(priv->rxcoalescing)) {
1899 gfar_write(&priv->regs->rxic, 0);
1900 gfar_write(&priv->regs->rxic, priv->rxic);
1901 }
1902 if (likely(priv->txcoalescing)) {
1903 gfar_write(&priv->regs->txic, 0);
1904 gfar_write(&priv->regs->txic, priv->txic);
1905 }
1906 }
1907
1908 return rx_cleaned;
1909 }
1910
1911 #ifdef CONFIG_NET_POLL_CONTROLLER
1912 /*
1913 * Polling 'interrupt' - used by things like netconsole to send skbs
1914 * without having to re-enable interrupts. It's not called while
1915 * the interrupt routine is executing.
1916 */
1917 static void gfar_netpoll(struct net_device *dev)
1918 {
1919 struct gfar_private *priv = netdev_priv(dev);
1920
1921 /* If the device has multiple interrupts, run tx/rx */
1922 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1923 disable_irq(priv->interruptTransmit);
1924 disable_irq(priv->interruptReceive);
1925 disable_irq(priv->interruptError);
1926 gfar_interrupt(priv->interruptTransmit, dev);
1927 enable_irq(priv->interruptError);
1928 enable_irq(priv->interruptReceive);
1929 enable_irq(priv->interruptTransmit);
1930 } else {
1931 disable_irq(priv->interruptTransmit);
1932 gfar_interrupt(priv->interruptTransmit, dev);
1933 enable_irq(priv->interruptTransmit);
1934 }
1935 }
1936 #endif
1937
1938 /* The interrupt handler for devices with one interrupt */
1939 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1940 {
1941 struct net_device *dev = dev_id;
1942 struct gfar_private *priv = netdev_priv(dev);
1943
1944 /* Save ievent for future reference */
1945 u32 events = gfar_read(&priv->regs->ievent);
1946
1947 /* Check for reception */
1948 if (events & IEVENT_RX_MASK)
1949 gfar_receive(irq, dev_id);
1950
1951 /* Check for transmit completion */
1952 if (events & IEVENT_TX_MASK)
1953 gfar_transmit(irq, dev_id);
1954
1955 /* Check for errors */
1956 if (events & IEVENT_ERR_MASK)
1957 gfar_error(irq, dev_id);
1958
1959 return IRQ_HANDLED;
1960 }
1961
1962 /* Called every time the controller might need to be made
1963 * aware of new link state. The PHY code conveys this
1964 * information through variables in the phydev structure, and this
1965 * function converts those variables into the appropriate
1966 * register values, and can bring down the device if needed.
1967 */
1968 static void adjust_link(struct net_device *dev)
1969 {
1970 struct gfar_private *priv = netdev_priv(dev);
1971 struct gfar __iomem *regs = priv->regs;
1972 unsigned long flags;
1973 struct phy_device *phydev = priv->phydev;
1974 int new_state = 0;
1975
1976 spin_lock_irqsave(&priv->txlock, flags);
1977 if (phydev->link) {
1978 u32 tempval = gfar_read(&regs->maccfg2);
1979 u32 ecntrl = gfar_read(&regs->ecntrl);
1980
1981 /* Now we make sure that we can be in full duplex mode.
1982 * If not, we operate in half-duplex mode. */
1983 if (phydev->duplex != priv->oldduplex) {
1984 new_state = 1;
1985 if (!(phydev->duplex))
1986 tempval &= ~(MACCFG2_FULL_DUPLEX);
1987 else
1988 tempval |= MACCFG2_FULL_DUPLEX;
1989
1990 priv->oldduplex = phydev->duplex;
1991 }
1992
1993 if (phydev->speed != priv->oldspeed) {
1994 new_state = 1;
1995 switch (phydev->speed) {
1996 case 1000:
1997 tempval =
1998 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1999
2000 ecntrl &= ~(ECNTRL_R100);
2001 break;
2002 case 100:
2003 case 10:
2004 tempval =
2005 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2006
2007 /* Reduced mode distinguishes
2008 * between 10 and 100 */
2009 if (phydev->speed == SPEED_100)
2010 ecntrl |= ECNTRL_R100;
2011 else
2012 ecntrl &= ~(ECNTRL_R100);
2013 break;
2014 default:
2015 if (netif_msg_link(priv))
2016 printk(KERN_WARNING
2017 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2018 dev->name, phydev->speed);
2019 break;
2020 }
2021
2022 priv->oldspeed = phydev->speed;
2023 }
2024
2025 gfar_write(&regs->maccfg2, tempval);
2026 gfar_write(&regs->ecntrl, ecntrl);
2027
2028 if (!priv->oldlink) {
2029 new_state = 1;
2030 priv->oldlink = 1;
2031 }
2032 } else if (priv->oldlink) {
2033 new_state = 1;
2034 priv->oldlink = 0;
2035 priv->oldspeed = 0;
2036 priv->oldduplex = -1;
2037 }
2038
2039 if (new_state && netif_msg_link(priv))
2040 phy_print_status(phydev);
2041
2042 spin_unlock_irqrestore(&priv->txlock, flags);
2043 }
2044
2045 /* Update the hash table based on the current list of multicast
2046 * addresses we subscribe to. Also, change the promiscuity of
2047 * the device based on the flags (this function is called
2048 * whenever dev->flags is changed */
2049 static void gfar_set_multi(struct net_device *dev)
2050 {
2051 struct dev_mc_list *mc_ptr;
2052 struct gfar_private *priv = netdev_priv(dev);
2053 struct gfar __iomem *regs = priv->regs;
2054 u32 tempval;
2055
2056 if(dev->flags & IFF_PROMISC) {
2057 /* Set RCTRL to PROM */
2058 tempval = gfar_read(&regs->rctrl);
2059 tempval |= RCTRL_PROM;
2060 gfar_write(&regs->rctrl, tempval);
2061 } else {
2062 /* Set RCTRL to not PROM */
2063 tempval = gfar_read(&regs->rctrl);
2064 tempval &= ~(RCTRL_PROM);
2065 gfar_write(&regs->rctrl, tempval);
2066 }
2067
2068 if(dev->flags & IFF_ALLMULTI) {
2069 /* Set the hash to rx all multicast frames */
2070 gfar_write(&regs->igaddr0, 0xffffffff);
2071 gfar_write(&regs->igaddr1, 0xffffffff);
2072 gfar_write(&regs->igaddr2, 0xffffffff);
2073 gfar_write(&regs->igaddr3, 0xffffffff);
2074 gfar_write(&regs->igaddr4, 0xffffffff);
2075 gfar_write(&regs->igaddr5, 0xffffffff);
2076 gfar_write(&regs->igaddr6, 0xffffffff);
2077 gfar_write(&regs->igaddr7, 0xffffffff);
2078 gfar_write(&regs->gaddr0, 0xffffffff);
2079 gfar_write(&regs->gaddr1, 0xffffffff);
2080 gfar_write(&regs->gaddr2, 0xffffffff);
2081 gfar_write(&regs->gaddr3, 0xffffffff);
2082 gfar_write(&regs->gaddr4, 0xffffffff);
2083 gfar_write(&regs->gaddr5, 0xffffffff);
2084 gfar_write(&regs->gaddr6, 0xffffffff);
2085 gfar_write(&regs->gaddr7, 0xffffffff);
2086 } else {
2087 int em_num;
2088 int idx;
2089
2090 /* zero out the hash */
2091 gfar_write(&regs->igaddr0, 0x0);
2092 gfar_write(&regs->igaddr1, 0x0);
2093 gfar_write(&regs->igaddr2, 0x0);
2094 gfar_write(&regs->igaddr3, 0x0);
2095 gfar_write(&regs->igaddr4, 0x0);
2096 gfar_write(&regs->igaddr5, 0x0);
2097 gfar_write(&regs->igaddr6, 0x0);
2098 gfar_write(&regs->igaddr7, 0x0);
2099 gfar_write(&regs->gaddr0, 0x0);
2100 gfar_write(&regs->gaddr1, 0x0);
2101 gfar_write(&regs->gaddr2, 0x0);
2102 gfar_write(&regs->gaddr3, 0x0);
2103 gfar_write(&regs->gaddr4, 0x0);
2104 gfar_write(&regs->gaddr5, 0x0);
2105 gfar_write(&regs->gaddr6, 0x0);
2106 gfar_write(&regs->gaddr7, 0x0);
2107
2108 /* If we have extended hash tables, we need to
2109 * clear the exact match registers to prepare for
2110 * setting them */
2111 if (priv->extended_hash) {
2112 em_num = GFAR_EM_NUM + 1;
2113 gfar_clear_exact_match(dev);
2114 idx = 1;
2115 } else {
2116 idx = 0;
2117 em_num = 0;
2118 }
2119
2120 if(dev->mc_count == 0)
2121 return;
2122
2123 /* Parse the list, and set the appropriate bits */
2124 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2125 if (idx < em_num) {
2126 gfar_set_mac_for_addr(dev, idx,
2127 mc_ptr->dmi_addr);
2128 idx++;
2129 } else
2130 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2131 }
2132 }
2133
2134 return;
2135 }
2136
2137
2138 /* Clears each of the exact match registers to zero, so they
2139 * don't interfere with normal reception */
2140 static void gfar_clear_exact_match(struct net_device *dev)
2141 {
2142 int idx;
2143 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2144
2145 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2146 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2147 }
2148
2149 /* Set the appropriate hash bit for the given addr */
2150 /* The algorithm works like so:
2151 * 1) Take the Destination Address (ie the multicast address), and
2152 * do a CRC on it (little endian), and reverse the bits of the
2153 * result.
2154 * 2) Use the 8 most significant bits as a hash into a 256-entry
2155 * table. The table is controlled through 8 32-bit registers:
2156 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2157 * gaddr7. This means that the 3 most significant bits in the
2158 * hash index which gaddr register to use, and the 5 other bits
2159 * indicate which bit (assuming an IBM numbering scheme, which
2160 * for PowerPC (tm) is usually the case) in the register holds
2161 * the entry. */
2162 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2163 {
2164 u32 tempval;
2165 struct gfar_private *priv = netdev_priv(dev);
2166 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2167 int width = priv->hash_width;
2168 u8 whichbit = (result >> (32 - width)) & 0x1f;
2169 u8 whichreg = result >> (32 - width + 5);
2170 u32 value = (1 << (31-whichbit));
2171
2172 tempval = gfar_read(priv->hash_regs[whichreg]);
2173 tempval |= value;
2174 gfar_write(priv->hash_regs[whichreg], tempval);
2175
2176 return;
2177 }
2178
2179
2180 /* There are multiple MAC Address register pairs on some controllers
2181 * This function sets the numth pair to a given address
2182 */
2183 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2184 {
2185 struct gfar_private *priv = netdev_priv(dev);
2186 int idx;
2187 char tmpbuf[MAC_ADDR_LEN];
2188 u32 tempval;
2189 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2190
2191 macptr += num*2;
2192
2193 /* Now copy it into the mac registers backwards, cuz */
2194 /* little endian is silly */
2195 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2196 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2197
2198 gfar_write(macptr, *((u32 *) (tmpbuf)));
2199
2200 tempval = *((u32 *) (tmpbuf + 4));
2201
2202 gfar_write(macptr+1, tempval);
2203 }
2204
2205 /* GFAR error interrupt handler */
2206 static irqreturn_t gfar_error(int irq, void *dev_id)
2207 {
2208 struct net_device *dev = dev_id;
2209 struct gfar_private *priv = netdev_priv(dev);
2210
2211 /* Save ievent for future reference */
2212 u32 events = gfar_read(&priv->regs->ievent);
2213
2214 /* Clear IEVENT */
2215 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2216
2217 /* Magic Packet is not an error. */
2218 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2219 (events & IEVENT_MAG))
2220 events &= ~IEVENT_MAG;
2221
2222 /* Hmm... */
2223 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2224 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2225 dev->name, events, gfar_read(&priv->regs->imask));
2226
2227 /* Update the error counters */
2228 if (events & IEVENT_TXE) {
2229 dev->stats.tx_errors++;
2230
2231 if (events & IEVENT_LC)
2232 dev->stats.tx_window_errors++;
2233 if (events & IEVENT_CRL)
2234 dev->stats.tx_aborted_errors++;
2235 if (events & IEVENT_XFUN) {
2236 if (netif_msg_tx_err(priv))
2237 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2238 "packet dropped.\n", dev->name);
2239 dev->stats.tx_dropped++;
2240 priv->extra_stats.tx_underrun++;
2241
2242 /* Reactivate the Tx Queues */
2243 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2244 }
2245 if (netif_msg_tx_err(priv))
2246 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2247 }
2248 if (events & IEVENT_BSY) {
2249 dev->stats.rx_errors++;
2250 priv->extra_stats.rx_bsy++;
2251
2252 gfar_receive(irq, dev_id);
2253
2254 if (netif_msg_rx_err(priv))
2255 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2256 dev->name, gfar_read(&priv->regs->rstat));
2257 }
2258 if (events & IEVENT_BABR) {
2259 dev->stats.rx_errors++;
2260 priv->extra_stats.rx_babr++;
2261
2262 if (netif_msg_rx_err(priv))
2263 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2264 }
2265 if (events & IEVENT_EBERR) {
2266 priv->extra_stats.eberr++;
2267 if (netif_msg_rx_err(priv))
2268 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2269 }
2270 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2271 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2272
2273 if (events & IEVENT_BABT) {
2274 priv->extra_stats.tx_babt++;
2275 if (netif_msg_tx_err(priv))
2276 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2277 }
2278 return IRQ_HANDLED;
2279 }
2280
2281 /* work with hotplug and coldplug */
2282 MODULE_ALIAS("platform:fsl-gianfar");
2283
2284 static struct of_device_id gfar_match[] =
2285 {
2286 {
2287 .type = "network",
2288 .compatible = "gianfar",
2289 },
2290 {},
2291 };
2292
2293 /* Structure for a device driver */
2294 static struct of_platform_driver gfar_driver = {
2295 .name = "fsl-gianfar",
2296 .match_table = gfar_match,
2297
2298 .probe = gfar_probe,
2299 .remove = gfar_remove,
2300 .suspend = gfar_suspend,
2301 .resume = gfar_resume,
2302 };
2303
2304 static int __init gfar_init(void)
2305 {
2306 int err = gfar_mdio_init();
2307
2308 if (err)
2309 return err;
2310
2311 err = of_register_platform_driver(&gfar_driver);
2312
2313 if (err)
2314 gfar_mdio_exit();
2315
2316 return err;
2317 }
2318
2319 static void __exit gfar_exit(void)
2320 {
2321 of_unregister_platform_driver(&gfar_driver);
2322 gfar_mdio_exit();
2323 }
2324
2325 module_init(gfar_init);
2326 module_exit(gfar_exit);
2327
Support for the Chinese Samsung S3C2440 based development boards