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ALSA: wss-lib: remove "pops" before each played sound
[linux-2.6/mini2440.git] / sound / isa / wss / wss_lib.c
blobf0c0be5bb684d0f15a2c192854cbc14d1ef745c1
1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
4 *
5 * Bugs:
6 * - sometimes record brokes playback with WSS portion of
7 * Yamaha OPL3-SA3 chip
8 * - CS4231 (GUS MAX) - still trouble with occasional noises
9 * - broken initialization?
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/slab.h>
32 #include <linux/ioport.h>
33 #include <sound/core.h>
34 #include <sound/wss.h>
35 #include <sound/pcm_params.h>
36 #include <sound/tlv.h>
37
38 #include <asm/io.h>
39 #include <asm/dma.h>
40 #include <asm/irq.h>
41
42 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
43 MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
44 MODULE_LICENSE("GPL");
45
46 #if 0
47 #define SNDRV_DEBUG_MCE
48 #endif
49
50 /*
51 * Some variables
52 */
53
54 static unsigned char freq_bits[14] = {
55 /* 5510 */ 0x00 | CS4231_XTAL2,
56 /* 6620 */ 0x0E | CS4231_XTAL2,
57 /* 8000 */ 0x00 | CS4231_XTAL1,
58 /* 9600 */ 0x0E | CS4231_XTAL1,
59 /* 11025 */ 0x02 | CS4231_XTAL2,
60 /* 16000 */ 0x02 | CS4231_XTAL1,
61 /* 18900 */ 0x04 | CS4231_XTAL2,
62 /* 22050 */ 0x06 | CS4231_XTAL2,
63 /* 27042 */ 0x04 | CS4231_XTAL1,
64 /* 32000 */ 0x06 | CS4231_XTAL1,
65 /* 33075 */ 0x0C | CS4231_XTAL2,
66 /* 37800 */ 0x08 | CS4231_XTAL2,
67 /* 44100 */ 0x0A | CS4231_XTAL2,
68 /* 48000 */ 0x0C | CS4231_XTAL1
69 };
70
71 static unsigned int rates[14] = {
72 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
73 27042, 32000, 33075, 37800, 44100, 48000
74 };
75
76 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
77 .count = ARRAY_SIZE(rates),
78 .list = rates,
79 .mask = 0,
80 };
81
82 static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
83 {
84 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
85 &hw_constraints_rates);
86 }
87
88 static unsigned char snd_wss_original_image[32] =
89 {
90 0x00, /* 00/00 - lic */
91 0x00, /* 01/01 - ric */
92 0x9f, /* 02/02 - la1ic */
93 0x9f, /* 03/03 - ra1ic */
94 0x9f, /* 04/04 - la2ic */
95 0x9f, /* 05/05 - ra2ic */
96 0xbf, /* 06/06 - loc */
97 0xbf, /* 07/07 - roc */
98 0x20, /* 08/08 - pdfr */
99 CS4231_AUTOCALIB, /* 09/09 - ic */
100 0x00, /* 0a/10 - pc */
101 0x00, /* 0b/11 - ti */
102 CS4231_MODE2, /* 0c/12 - mi */
103 0xfc, /* 0d/13 - lbc */
104 0x00, /* 0e/14 - pbru */
105 0x00, /* 0f/15 - pbrl */
106 0x80, /* 10/16 - afei */
107 0x01, /* 11/17 - afeii */
108 0x9f, /* 12/18 - llic */
109 0x9f, /* 13/19 - rlic */
110 0x00, /* 14/20 - tlb */
111 0x00, /* 15/21 - thb */
112 0x00, /* 16/22 - la3mic/reserved */
113 0x00, /* 17/23 - ra3mic/reserved */
114 0x00, /* 18/24 - afs */
115 0x00, /* 19/25 - lamoc/version */
116 0xcf, /* 1a/26 - mioc */
117 0x00, /* 1b/27 - ramoc/reserved */
118 0x20, /* 1c/28 - cdfr */
119 0x00, /* 1d/29 - res4 */
120 0x00, /* 1e/30 - cbru */
121 0x00, /* 1f/31 - cbrl */
122 };
123
124 static unsigned char snd_opti93x_original_image[32] =
125 {
126 0x00, /* 00/00 - l_mixout_outctrl */
127 0x00, /* 01/01 - r_mixout_outctrl */
128 0x88, /* 02/02 - l_cd_inctrl */
129 0x88, /* 03/03 - r_cd_inctrl */
130 0x88, /* 04/04 - l_a1/fm_inctrl */
131 0x88, /* 05/05 - r_a1/fm_inctrl */
132 0x80, /* 06/06 - l_dac_inctrl */
133 0x80, /* 07/07 - r_dac_inctrl */
134 0x00, /* 08/08 - ply_dataform_reg */
135 0x00, /* 09/09 - if_conf */
136 0x00, /* 0a/10 - pin_ctrl */
137 0x00, /* 0b/11 - err_init_reg */
138 0x0a, /* 0c/12 - id_reg */
139 0x00, /* 0d/13 - reserved */
140 0x00, /* 0e/14 - ply_upcount_reg */
141 0x00, /* 0f/15 - ply_lowcount_reg */
142 0x88, /* 10/16 - reserved/l_a1_inctrl */
143 0x88, /* 11/17 - reserved/r_a1_inctrl */
144 0x88, /* 12/18 - l_line_inctrl */
145 0x88, /* 13/19 - r_line_inctrl */
146 0x88, /* 14/20 - l_mic_inctrl */
147 0x88, /* 15/21 - r_mic_inctrl */
148 0x80, /* 16/22 - l_out_outctrl */
149 0x80, /* 17/23 - r_out_outctrl */
150 0x00, /* 18/24 - reserved */
151 0x00, /* 19/25 - reserved */
152 0x00, /* 1a/26 - reserved */
153 0x00, /* 1b/27 - reserved */
154 0x00, /* 1c/28 - cap_dataform_reg */
155 0x00, /* 1d/29 - reserved */
156 0x00, /* 1e/30 - cap_upcount_reg */
157 0x00 /* 1f/31 - cap_lowcount_reg */
158 };
159
160 /*
161 * Basic I/O functions
162 */
163
164 static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
165 {
166 outb(val, chip->port + offset);
167 }
168
169 static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
170 {
171 return inb(chip->port + offset);
172 }
173
174 static void snd_wss_wait(struct snd_wss *chip)
175 {
176 int timeout;
177
178 for (timeout = 250;
179 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
180 timeout--)
181 udelay(100);
182 }
183
184 static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
185 unsigned char value)
186 {
187 int timeout;
188
189 for (timeout = 250;
190 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
191 timeout--)
192 udelay(10);
193 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
194 wss_outb(chip, CS4231P(REG), value);
195 mb();
196 }
197
198 void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
199 {
200 snd_wss_wait(chip);
201 #ifdef CONFIG_SND_DEBUG
202 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
203 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
204 #endif
205 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
206 wss_outb(chip, CS4231P(REG), value);
207 chip->image[reg] = value;
208 mb();
209 snd_printdd("codec out - reg 0x%x = 0x%x\n",
210 chip->mce_bit | reg, value);
211 }
212 EXPORT_SYMBOL(snd_wss_out);
213
214 unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
215 {
216 snd_wss_wait(chip);
217 #ifdef CONFIG_SND_DEBUG
218 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
219 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
220 #endif
221 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
222 mb();
223 return wss_inb(chip, CS4231P(REG));
224 }
225 EXPORT_SYMBOL(snd_wss_in);
226
227 void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
228 unsigned char val)
229 {
230 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
231 wss_outb(chip, CS4231P(REG),
232 reg | (chip->image[CS4236_EXT_REG] & 0x01));
233 wss_outb(chip, CS4231P(REG), val);
234 chip->eimage[CS4236_REG(reg)] = val;
235 #if 0
236 printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
237 #endif
238 }
239 EXPORT_SYMBOL(snd_cs4236_ext_out);
240
241 unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
242 {
243 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
244 wss_outb(chip, CS4231P(REG),
245 reg | (chip->image[CS4236_EXT_REG] & 0x01));
246 #if 1
247 return wss_inb(chip, CS4231P(REG));
248 #else
249 {
250 unsigned char res;
251 res = wss_inb(chip, CS4231P(REG));
252 printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
253 return res;
254 }
255 #endif
256 }
257 EXPORT_SYMBOL(snd_cs4236_ext_in);
258
259 #if 0
260
261 static void snd_wss_debug(struct snd_wss *chip)
262 {
263 printk(KERN_DEBUG
264 "CS4231 REGS: INDEX = 0x%02x "
265 " STATUS = 0x%02x\n",
266 wss_inb(chip, CS4231P(REGSEL)),
267 wss_inb(chip, CS4231P(STATUS)));
268 printk(KERN_DEBUG
269 " 0x00: left input = 0x%02x "
270 " 0x10: alt 1 (CFIG 2) = 0x%02x\n",
271 snd_wss_in(chip, 0x00),
272 snd_wss_in(chip, 0x10));
273 printk(KERN_DEBUG
274 " 0x01: right input = 0x%02x "
275 " 0x11: alt 2 (CFIG 3) = 0x%02x\n",
276 snd_wss_in(chip, 0x01),
277 snd_wss_in(chip, 0x11));
278 printk(KERN_DEBUG
279 " 0x02: GF1 left input = 0x%02x "
280 " 0x12: left line in = 0x%02x\n",
281 snd_wss_in(chip, 0x02),
282 snd_wss_in(chip, 0x12));
283 printk(KERN_DEBUG
284 " 0x03: GF1 right input = 0x%02x "
285 " 0x13: right line in = 0x%02x\n",
286 snd_wss_in(chip, 0x03),
287 snd_wss_in(chip, 0x13));
288 printk(KERN_DEBUG
289 " 0x04: CD left input = 0x%02x "
290 " 0x14: timer low = 0x%02x\n",
291 snd_wss_in(chip, 0x04),
292 snd_wss_in(chip, 0x14));
293 printk(KERN_DEBUG
294 " 0x05: CD right input = 0x%02x "
295 " 0x15: timer high = 0x%02x\n",
296 snd_wss_in(chip, 0x05),
297 snd_wss_in(chip, 0x15));
298 printk(KERN_DEBUG
299 " 0x06: left output = 0x%02x "
300 " 0x16: left MIC (PnP) = 0x%02x\n",
301 snd_wss_in(chip, 0x06),
302 snd_wss_in(chip, 0x16));
303 printk(KERN_DEBUG
304 " 0x07: right output = 0x%02x "
305 " 0x17: right MIC (PnP) = 0x%02x\n",
306 snd_wss_in(chip, 0x07),
307 snd_wss_in(chip, 0x17));
308 printk(KERN_DEBUG
309 " 0x08: playback format = 0x%02x "
310 " 0x18: IRQ status = 0x%02x\n",
311 snd_wss_in(chip, 0x08),
312 snd_wss_in(chip, 0x18));
313 printk(KERN_DEBUG
314 " 0x09: iface (CFIG 1) = 0x%02x "
315 " 0x19: left line out = 0x%02x\n",
316 snd_wss_in(chip, 0x09),
317 snd_wss_in(chip, 0x19));
318 printk(KERN_DEBUG
319 " 0x0a: pin control = 0x%02x "
320 " 0x1a: mono control = 0x%02x\n",
321 snd_wss_in(chip, 0x0a),
322 snd_wss_in(chip, 0x1a));
323 printk(KERN_DEBUG
324 " 0x0b: init & status = 0x%02x "
325 " 0x1b: right line out = 0x%02x\n",
326 snd_wss_in(chip, 0x0b),
327 snd_wss_in(chip, 0x1b));
328 printk(KERN_DEBUG
329 " 0x0c: revision & mode = 0x%02x "
330 " 0x1c: record format = 0x%02x\n",
331 snd_wss_in(chip, 0x0c),
332 snd_wss_in(chip, 0x1c));
333 printk(KERN_DEBUG
334 " 0x0d: loopback = 0x%02x "
335 " 0x1d: var freq (PnP) = 0x%02x\n",
336 snd_wss_in(chip, 0x0d),
337 snd_wss_in(chip, 0x1d));
338 printk(KERN_DEBUG
339 " 0x0e: ply upr count = 0x%02x "
340 " 0x1e: ply lwr count = 0x%02x\n",
341 snd_wss_in(chip, 0x0e),
342 snd_wss_in(chip, 0x1e));
343 printk(KERN_DEBUG
344 " 0x0f: rec upr count = 0x%02x "
345 " 0x1f: rec lwr count = 0x%02x\n",
346 snd_wss_in(chip, 0x0f),
347 snd_wss_in(chip, 0x1f));
348 }
349
350 #endif
351
352 /*
353 * CS4231 detection / MCE routines
354 */
355
356 static void snd_wss_busy_wait(struct snd_wss *chip)
357 {
358 int timeout;
359
360 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
361 for (timeout = 5; timeout > 0; timeout--)
362 wss_inb(chip, CS4231P(REGSEL));
363 /* end of cleanup sequence */
364 for (timeout = 25000;
365 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
366 timeout--)
367 udelay(10);
368 }
369
370 void snd_wss_mce_up(struct snd_wss *chip)
371 {
372 unsigned long flags;
373 int timeout;
374
375 snd_wss_wait(chip);
376 #ifdef CONFIG_SND_DEBUG
377 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
378 snd_printk("mce_up - auto calibration time out (0)\n");
379 #endif
380 spin_lock_irqsave(&chip->reg_lock, flags);
381 chip->mce_bit |= CS4231_MCE;
382 timeout = wss_inb(chip, CS4231P(REGSEL));
383 if (timeout == 0x80)
384 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
385 if (!(timeout & CS4231_MCE))
386 wss_outb(chip, CS4231P(REGSEL),
387 chip->mce_bit | (timeout & 0x1f));
388 spin_unlock_irqrestore(&chip->reg_lock, flags);
389 }
390 EXPORT_SYMBOL(snd_wss_mce_up);
391
392 void snd_wss_mce_down(struct snd_wss *chip)
393 {
394 unsigned long flags;
395 unsigned long end_time;
396 int timeout;
397 int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
398
399 snd_wss_busy_wait(chip);
400
401 #ifdef CONFIG_SND_DEBUG
402 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
403 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
404 #endif
405 spin_lock_irqsave(&chip->reg_lock, flags);
406 chip->mce_bit &= ~CS4231_MCE;
407 timeout = wss_inb(chip, CS4231P(REGSEL));
408 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
409 spin_unlock_irqrestore(&chip->reg_lock, flags);
410 if (timeout == 0x80)
411 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
412 if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
413 return;
414
415 /*
416 * Wait for (possible -- during init auto-calibration may not be set)
417 * calibration process to start. Needs upto 5 sample periods on AD1848
418 * which at the slowest possible rate of 5.5125 kHz means 907 us.
419 */
420 msleep(1);
421
422 snd_printdd("(1) jiffies = %lu\n", jiffies);
423
424 /* check condition up to 250 ms */
425 end_time = jiffies + msecs_to_jiffies(250);
426 while (snd_wss_in(chip, CS4231_TEST_INIT) &
427 CS4231_CALIB_IN_PROGRESS) {
428
429 if (time_after(jiffies, end_time)) {
430 snd_printk(KERN_ERR "mce_down - "
431 "auto calibration time out (2)\n");
432 return;
433 }
434 msleep(1);
435 }
436
437 snd_printdd("(2) jiffies = %lu\n", jiffies);
438
439 /* check condition up to 100 ms */
440 end_time = jiffies + msecs_to_jiffies(100);
441 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
442 if (time_after(jiffies, end_time)) {
443 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
444 return;
445 }
446 msleep(1);
447 }
448
449 snd_printdd("(3) jiffies = %lu\n", jiffies);
450 snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
451 }
452 EXPORT_SYMBOL(snd_wss_mce_down);
453
454 static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
455 {
456 switch (format & 0xe0) {
457 case CS4231_LINEAR_16:
458 case CS4231_LINEAR_16_BIG:
459 size >>= 1;
460 break;
461 case CS4231_ADPCM_16:
462 return size >> 2;
463 }
464 if (format & CS4231_STEREO)
465 size >>= 1;
466 return size;
467 }
468
469 static int snd_wss_trigger(struct snd_pcm_substream *substream,
470 int cmd)
471 {
472 struct snd_wss *chip = snd_pcm_substream_chip(substream);
473 int result = 0;
474 unsigned int what;
475 struct snd_pcm_substream *s;
476 int do_start;
477
478 switch (cmd) {
479 case SNDRV_PCM_TRIGGER_START:
480 case SNDRV_PCM_TRIGGER_RESUME:
481 do_start = 1; break;
482 case SNDRV_PCM_TRIGGER_STOP:
483 case SNDRV_PCM_TRIGGER_SUSPEND:
484 do_start = 0; break;
485 default:
486 return -EINVAL;
487 }
488
489 what = 0;
490 snd_pcm_group_for_each_entry(s, substream) {
491 if (s == chip->playback_substream) {
492 what |= CS4231_PLAYBACK_ENABLE;
493 snd_pcm_trigger_done(s, substream);
494 } else if (s == chip->capture_substream) {
495 what |= CS4231_RECORD_ENABLE;
496 snd_pcm_trigger_done(s, substream);
497 }
498 }
499 spin_lock(&chip->reg_lock);
500 if (do_start) {
501 chip->image[CS4231_IFACE_CTRL] |= what;
502 if (chip->trigger)
503 chip->trigger(chip, what, 1);
504 } else {
505 chip->image[CS4231_IFACE_CTRL] &= ~what;
506 if (chip->trigger)
507 chip->trigger(chip, what, 0);
508 }
509 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
510 spin_unlock(&chip->reg_lock);
511 #if 0
512 snd_wss_debug(chip);
513 #endif
514 return result;
515 }
516
517 /*
518 * CODEC I/O
519 */
520
521 static unsigned char snd_wss_get_rate(unsigned int rate)
522 {
523 int i;
524
525 for (i = 0; i < ARRAY_SIZE(rates); i++)
526 if (rate == rates[i])
527 return freq_bits[i];
528 // snd_BUG();
529 return freq_bits[ARRAY_SIZE(rates) - 1];
530 }
531
532 static unsigned char snd_wss_get_format(struct snd_wss *chip,
533 int format,
534 int channels)
535 {
536 unsigned char rformat;
537
538 rformat = CS4231_LINEAR_8;
539 switch (format) {
540 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
541 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
542 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
543 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
544 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
545 }
546 if (channels > 1)
547 rformat |= CS4231_STEREO;
548 #if 0
549 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
550 #endif
551 return rformat;
552 }
553
554 static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
555 {
556 unsigned long flags;
557
558 mute = mute ? 0x80 : 0;
559 spin_lock_irqsave(&chip->reg_lock, flags);
560 if (chip->calibrate_mute == mute) {
561 spin_unlock_irqrestore(&chip->reg_lock, flags);
562 return;
563 }
564 if (!mute) {
565 snd_wss_dout(chip, CS4231_LEFT_INPUT,
566 chip->image[CS4231_LEFT_INPUT]);
567 snd_wss_dout(chip, CS4231_RIGHT_INPUT,
568 chip->image[CS4231_RIGHT_INPUT]);
569 snd_wss_dout(chip, CS4231_LOOPBACK,
570 chip->image[CS4231_LOOPBACK]);
571 } else {
572 snd_wss_dout(chip, CS4231_LEFT_INPUT,
573 0);
574 snd_wss_dout(chip, CS4231_RIGHT_INPUT,
575 0);
576 snd_wss_dout(chip, CS4231_LOOPBACK,
577 0xfd);
578 }
579
580 snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
581 mute | chip->image[CS4231_AUX1_LEFT_INPUT]);
582 snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
583 mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);
584 snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
585 mute | chip->image[CS4231_AUX2_LEFT_INPUT]);
586 snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
587 mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);
588 snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
589 mute | chip->image[CS4231_LEFT_OUTPUT]);
590 snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
591 mute | chip->image[CS4231_RIGHT_OUTPUT]);
592 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
593 snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
594 mute | chip->image[CS4231_LEFT_LINE_IN]);
595 snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
596 mute | chip->image[CS4231_RIGHT_LINE_IN]);
597 snd_wss_dout(chip, CS4231_MONO_CTRL,
598 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
599 }
600 if (chip->hardware == WSS_HW_INTERWAVE) {
601 snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
602 mute | chip->image[CS4231_LEFT_MIC_INPUT]);
603 snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
604 mute | chip->image[CS4231_RIGHT_MIC_INPUT]);
605 snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
606 mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);
607 snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
608 mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);
609 }
610 chip->calibrate_mute = mute;
611 spin_unlock_irqrestore(&chip->reg_lock, flags);
612 }
613
614 static void snd_wss_playback_format(struct snd_wss *chip,
615 struct snd_pcm_hw_params *params,
616 unsigned char pdfr)
617 {
618 unsigned long flags;
619 int full_calib = 1;
620
621 mutex_lock(&chip->mce_mutex);
622 if (chip->hardware == WSS_HW_CS4231A ||
623 (chip->hardware & WSS_HW_CS4232_MASK)) {
624 spin_lock_irqsave(&chip->reg_lock, flags);
625 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
626 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
627 chip->image[CS4231_ALT_FEATURE_1] | 0x10);
628 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
629 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
630 chip->image[CS4231_PLAYBK_FORMAT]);
631 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
632 chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
633 udelay(100); /* Fixes audible clicks at least on GUS MAX */
634 full_calib = 0;
635 }
636 spin_unlock_irqrestore(&chip->reg_lock, flags);
637 } else if (chip->hardware == WSS_HW_AD1845) {
638 unsigned rate = params_rate(params);
639
640 /*
641 * Program the AD1845 correctly for the playback stream.
642 * Note that we do NOT need to toggle the MCE bit because
643 * the PLAYBACK_ENABLE bit of the Interface Configuration
644 * register is set.
645 *
646 * NOTE: We seem to need to write to the MSB before the LSB
647 * to get the correct sample frequency.
648 */
649 spin_lock_irqsave(&chip->reg_lock, flags);
650 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, (pdfr & 0xf0));
651 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
652 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
653 full_calib = 0;
654 spin_unlock_irqrestore(&chip->reg_lock, flags);
655 }
656 if (full_calib) {
657 snd_wss_mce_up(chip);
658 spin_lock_irqsave(&chip->reg_lock, flags);
659 if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
660 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
661 pdfr = (pdfr & 0xf0) |
662 (chip->image[CS4231_REC_FORMAT] & 0x0f);
663 } else {
664 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
665 }
666 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
667 spin_unlock_irqrestore(&chip->reg_lock, flags);
668 if (chip->hardware == WSS_HW_OPL3SA2)
669 udelay(100); /* this seems to help */
670 snd_wss_mce_down(chip);
671 }
672 mutex_unlock(&chip->mce_mutex);
673 }
674
675 static void snd_wss_capture_format(struct snd_wss *chip,
676 struct snd_pcm_hw_params *params,
677 unsigned char cdfr)
678 {
679 unsigned long flags;
680 int full_calib = 1;
681
682 mutex_lock(&chip->mce_mutex);
683 if (chip->hardware == WSS_HW_CS4231A ||
684 (chip->hardware & WSS_HW_CS4232_MASK)) {
685 spin_lock_irqsave(&chip->reg_lock, flags);
686 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
687 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
688 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
689 chip->image[CS4231_ALT_FEATURE_1] | 0x20);
690 snd_wss_out(chip, CS4231_REC_FORMAT,
691 chip->image[CS4231_REC_FORMAT] = cdfr);
692 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
693 chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
694 full_calib = 0;
695 }
696 spin_unlock_irqrestore(&chip->reg_lock, flags);
697 } else if (chip->hardware == WSS_HW_AD1845) {
698 unsigned rate = params_rate(params);
699
700 /*
701 * Program the AD1845 correctly for the capture stream.
702 * Note that we do NOT need to toggle the MCE bit because
703 * the PLAYBACK_ENABLE bit of the Interface Configuration
704 * register is set.
705 *
706 * NOTE: We seem to need to write to the MSB before the LSB
707 * to get the correct sample frequency.
708 */
709 spin_lock_irqsave(&chip->reg_lock, flags);
710 snd_wss_out(chip, CS4231_REC_FORMAT, (cdfr & 0xf0));
711 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
712 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
713 full_calib = 0;
714 spin_unlock_irqrestore(&chip->reg_lock, flags);
715 }
716 if (full_calib) {
717 snd_wss_mce_up(chip);
718 spin_lock_irqsave(&chip->reg_lock, flags);
719 if (chip->hardware != WSS_HW_INTERWAVE &&
720 !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
721 if (chip->single_dma)
722 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
723 else
724 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
725 (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
726 (cdfr & 0x0f));
727 spin_unlock_irqrestore(&chip->reg_lock, flags);
728 snd_wss_mce_down(chip);
729 snd_wss_mce_up(chip);
730 spin_lock_irqsave(&chip->reg_lock, flags);
731 }
732 if (chip->hardware & WSS_HW_AD1848_MASK)
733 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
734 else
735 snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
736 spin_unlock_irqrestore(&chip->reg_lock, flags);
737 snd_wss_mce_down(chip);
738 }
739 mutex_unlock(&chip->mce_mutex);
740 }
741
742 /*
743 * Timer interface
744 */
745
746 static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
747 {
748 struct snd_wss *chip = snd_timer_chip(timer);
749 if (chip->hardware & WSS_HW_CS4236B_MASK)
750 return 14467;
751 else
752 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
753 }
754
755 static int snd_wss_timer_start(struct snd_timer *timer)
756 {
757 unsigned long flags;
758 unsigned int ticks;
759 struct snd_wss *chip = snd_timer_chip(timer);
760 spin_lock_irqsave(&chip->reg_lock, flags);
761 ticks = timer->sticks;
762 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
763 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
764 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
765 chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
766 snd_wss_out(chip, CS4231_TIMER_HIGH,
767 chip->image[CS4231_TIMER_HIGH]);
768 chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
769 snd_wss_out(chip, CS4231_TIMER_LOW,
770 chip->image[CS4231_TIMER_LOW]);
771 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
772 chip->image[CS4231_ALT_FEATURE_1] |
773 CS4231_TIMER_ENABLE);
774 }
775 spin_unlock_irqrestore(&chip->reg_lock, flags);
776 return 0;
777 }
778
779 static int snd_wss_timer_stop(struct snd_timer *timer)
780 {
781 unsigned long flags;
782 struct snd_wss *chip = snd_timer_chip(timer);
783 spin_lock_irqsave(&chip->reg_lock, flags);
784 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
785 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
786 chip->image[CS4231_ALT_FEATURE_1]);
787 spin_unlock_irqrestore(&chip->reg_lock, flags);
788 return 0;
789 }
790
791 static void snd_wss_init(struct snd_wss *chip)
792 {
793 unsigned long flags;
794
795 snd_wss_calibrate_mute(chip, 1);
796 snd_wss_mce_down(chip);
797
798 #ifdef SNDRV_DEBUG_MCE
799 snd_printk("init: (1)\n");
800 #endif
801 snd_wss_mce_up(chip);
802 spin_lock_irqsave(&chip->reg_lock, flags);
803 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
804 CS4231_PLAYBACK_PIO |
805 CS4231_RECORD_ENABLE |
806 CS4231_RECORD_PIO |
807 CS4231_CALIB_MODE);
808 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
809 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
810 spin_unlock_irqrestore(&chip->reg_lock, flags);
811 snd_wss_mce_down(chip);
812
813 #ifdef SNDRV_DEBUG_MCE
814 snd_printk("init: (2)\n");
815 #endif
816
817 snd_wss_mce_up(chip);
818 spin_lock_irqsave(&chip->reg_lock, flags);
819 chip->image[CS4231_IFACE_CTRL] &= ~CS4231_AUTOCALIB;
820 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
821 snd_wss_out(chip,
822 CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
823 spin_unlock_irqrestore(&chip->reg_lock, flags);
824 snd_wss_mce_down(chip);
825
826 #ifdef SNDRV_DEBUG_MCE
827 snd_printk("init: (3) - afei = 0x%x\n",
828 chip->image[CS4231_ALT_FEATURE_1]);
829 #endif
830
831 spin_lock_irqsave(&chip->reg_lock, flags);
832 snd_wss_out(chip, CS4231_ALT_FEATURE_2,
833 chip->image[CS4231_ALT_FEATURE_2]);
834 spin_unlock_irqrestore(&chip->reg_lock, flags);
835
836 snd_wss_mce_up(chip);
837 spin_lock_irqsave(&chip->reg_lock, flags);
838 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
839 chip->image[CS4231_PLAYBK_FORMAT]);
840 spin_unlock_irqrestore(&chip->reg_lock, flags);
841 snd_wss_mce_down(chip);
842
843 #ifdef SNDRV_DEBUG_MCE
844 snd_printk("init: (4)\n");
845 #endif
846
847 snd_wss_mce_up(chip);
848 spin_lock_irqsave(&chip->reg_lock, flags);
849 if (!(chip->hardware & WSS_HW_AD1848_MASK))
850 snd_wss_out(chip, CS4231_REC_FORMAT,
851 chip->image[CS4231_REC_FORMAT]);
852 spin_unlock_irqrestore(&chip->reg_lock, flags);
853 snd_wss_mce_down(chip);
854 snd_wss_calibrate_mute(chip, 0);
855
856 #ifdef SNDRV_DEBUG_MCE
857 snd_printk("init: (5)\n");
858 #endif
859 }
860
861 static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
862 {
863 unsigned long flags;
864
865 mutex_lock(&chip->open_mutex);
866 if ((chip->mode & mode) ||
867 ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
868 mutex_unlock(&chip->open_mutex);
869 return -EAGAIN;
870 }
871 if (chip->mode & WSS_MODE_OPEN) {
872 chip->mode |= mode;
873 mutex_unlock(&chip->open_mutex);
874 return 0;
875 }
876 /* ok. now enable and ack CODEC IRQ */
877 spin_lock_irqsave(&chip->reg_lock, flags);
878 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
879 snd_wss_out(chip, CS4231_IRQ_STATUS,
880 CS4231_PLAYBACK_IRQ |
881 CS4231_RECORD_IRQ |
882 CS4231_TIMER_IRQ);
883 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
884 }
885 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
886 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
887 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
888 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
889 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
890 snd_wss_out(chip, CS4231_IRQ_STATUS,
891 CS4231_PLAYBACK_IRQ |
892 CS4231_RECORD_IRQ |
893 CS4231_TIMER_IRQ);
894 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
895 }
896 spin_unlock_irqrestore(&chip->reg_lock, flags);
897
898 chip->mode = mode;
899 mutex_unlock(&chip->open_mutex);
900 return 0;
901 }
902
903 static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
904 {
905 unsigned long flags;
906
907 mutex_lock(&chip->open_mutex);
908 chip->mode &= ~mode;
909 if (chip->mode & WSS_MODE_OPEN) {
910 mutex_unlock(&chip->open_mutex);
911 return;
912 }
913 /* disable IRQ */
914 spin_lock_irqsave(&chip->reg_lock, flags);
915 if (!(chip->hardware & WSS_HW_AD1848_MASK))
916 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
917 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
918 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
919 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
920 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
921
922 /* now disable record & playback */
923
924 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
925 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
926 spin_unlock_irqrestore(&chip->reg_lock, flags);
927 snd_wss_mce_up(chip);
928 spin_lock_irqsave(&chip->reg_lock, flags);
929 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
930 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
931 snd_wss_out(chip, CS4231_IFACE_CTRL,
932 chip->image[CS4231_IFACE_CTRL]);
933 spin_unlock_irqrestore(&chip->reg_lock, flags);
934 snd_wss_mce_down(chip);
935 spin_lock_irqsave(&chip->reg_lock, flags);
936 }
937
938 /* clear IRQ again */
939 if (!(chip->hardware & WSS_HW_AD1848_MASK))
940 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
941 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
942 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
943 spin_unlock_irqrestore(&chip->reg_lock, flags);
944
945 chip->mode = 0;
946 mutex_unlock(&chip->open_mutex);
947 }
948
949 /*
950 * timer open/close
951 */
952
953 static int snd_wss_timer_open(struct snd_timer *timer)
954 {
955 struct snd_wss *chip = snd_timer_chip(timer);
956 snd_wss_open(chip, WSS_MODE_TIMER);
957 return 0;
958 }
959
960 static int snd_wss_timer_close(struct snd_timer *timer)
961 {
962 struct snd_wss *chip = snd_timer_chip(timer);
963 snd_wss_close(chip, WSS_MODE_TIMER);
964 return 0;
965 }
966
967 static struct snd_timer_hardware snd_wss_timer_table =
968 {
969 .flags = SNDRV_TIMER_HW_AUTO,
970 .resolution = 9945,
971 .ticks = 65535,
972 .open = snd_wss_timer_open,
973 .close = snd_wss_timer_close,
974 .c_resolution = snd_wss_timer_resolution,
975 .start = snd_wss_timer_start,
976 .stop = snd_wss_timer_stop,
977 };
978
979 /*
980 * ok.. exported functions..
981 */
982
983 static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
984 struct snd_pcm_hw_params *hw_params)
985 {
986 struct snd_wss *chip = snd_pcm_substream_chip(substream);
987 unsigned char new_pdfr;
988 int err;
989
990 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
991 return err;
992 new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
993 params_channels(hw_params)) |
994 snd_wss_get_rate(params_rate(hw_params));
995 chip->set_playback_format(chip, hw_params, new_pdfr);
996 return 0;
997 }
998
999 static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
1000 {
1001 return snd_pcm_lib_free_pages(substream);
1002 }
1003
1004 static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
1005 {
1006 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1007 struct snd_pcm_runtime *runtime = substream->runtime;
1008 unsigned long flags;
1009 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1010 unsigned int count = snd_pcm_lib_period_bytes(substream);
1011
1012 spin_lock_irqsave(&chip->reg_lock, flags);
1013 chip->p_dma_size = size;
1014 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
1015 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
1016 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
1017 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1018 snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
1019 spin_unlock_irqrestore(&chip->reg_lock, flags);
1020 #if 0
1021 snd_wss_debug(chip);
1022 #endif
1023 return 0;
1024 }
1025
1026 static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
1027 struct snd_pcm_hw_params *hw_params)
1028 {
1029 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1030 unsigned char new_cdfr;
1031 int err;
1032
1033 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1034 return err;
1035 new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
1036 params_channels(hw_params)) |
1037 snd_wss_get_rate(params_rate(hw_params));
1038 chip->set_capture_format(chip, hw_params, new_cdfr);
1039 return 0;
1040 }
1041
1042 static int snd_wss_capture_hw_free(struct snd_pcm_substream *substream)
1043 {
1044 return snd_pcm_lib_free_pages(substream);
1045 }
1046
1047 static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
1048 {
1049 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1050 struct snd_pcm_runtime *runtime = substream->runtime;
1051 unsigned long flags;
1052 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1053 unsigned int count = snd_pcm_lib_period_bytes(substream);
1054
1055 spin_lock_irqsave(&chip->reg_lock, flags);
1056 chip->c_dma_size = size;
1057 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
1058 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
1059 if (chip->hardware & WSS_HW_AD1848_MASK)
1060 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
1061 count);
1062 else
1063 count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
1064 count);
1065 count--;
1066 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1067 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1068 snd_wss_out(chip, CS4231_PLY_UPR_CNT,
1069 (unsigned char) (count >> 8));
1070 } else {
1071 snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
1072 snd_wss_out(chip, CS4231_REC_UPR_CNT,
1073 (unsigned char) (count >> 8));
1074 }
1075 spin_unlock_irqrestore(&chip->reg_lock, flags);
1076 return 0;
1077 }
1078
1079 void snd_wss_overrange(struct snd_wss *chip)
1080 {
1081 unsigned long flags;
1082 unsigned char res;
1083
1084 spin_lock_irqsave(&chip->reg_lock, flags);
1085 res = snd_wss_in(chip, CS4231_TEST_INIT);
1086 spin_unlock_irqrestore(&chip->reg_lock, flags);
1087 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1088 chip->capture_substream->runtime->overrange++;
1089 }
1090 EXPORT_SYMBOL(snd_wss_overrange);
1091
1092 irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
1093 {
1094 struct snd_wss *chip = dev_id;
1095 unsigned char status;
1096
1097 if (chip->hardware & WSS_HW_AD1848_MASK)
1098 /* pretend it was the only possible irq for AD1848 */
1099 status = CS4231_PLAYBACK_IRQ;
1100 else
1101 status = snd_wss_in(chip, CS4231_IRQ_STATUS);
1102 if (status & CS4231_TIMER_IRQ) {
1103 if (chip->timer)
1104 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1105 }
1106 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1107 if (status & CS4231_PLAYBACK_IRQ) {
1108 if (chip->mode & WSS_MODE_PLAY) {
1109 if (chip->playback_substream)
1110 snd_pcm_period_elapsed(chip->playback_substream);
1111 }
1112 if (chip->mode & WSS_MODE_RECORD) {
1113 if (chip->capture_substream) {
1114 snd_wss_overrange(chip);
1115 snd_pcm_period_elapsed(chip->capture_substream);
1116 }
1117 }
1118 }
1119 } else {
1120 if (status & CS4231_PLAYBACK_IRQ) {
1121 if (chip->playback_substream)
1122 snd_pcm_period_elapsed(chip->playback_substream);
1123 }
1124 if (status & CS4231_RECORD_IRQ) {
1125 if (chip->capture_substream) {
1126 snd_wss_overrange(chip);
1127 snd_pcm_period_elapsed(chip->capture_substream);
1128 }
1129 }
1130 }
1131
1132 spin_lock(&chip->reg_lock);
1133 status = ~CS4231_ALL_IRQS | ~status;
1134 if (chip->hardware & WSS_HW_AD1848_MASK)
1135 wss_outb(chip, CS4231P(STATUS), 0);
1136 else
1137 snd_wss_out(chip, CS4231_IRQ_STATUS, status);
1138 spin_unlock(&chip->reg_lock);
1139 return IRQ_HANDLED;
1140 }
1141 EXPORT_SYMBOL(snd_wss_interrupt);
1142
1143 static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
1144 {
1145 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1146 size_t ptr;
1147
1148 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1149 return 0;
1150 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
1151 return bytes_to_frames(substream->runtime, ptr);
1152 }
1153
1154 static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
1155 {
1156 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1157 size_t ptr;
1158
1159 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1160 return 0;
1161 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
1162 return bytes_to_frames(substream->runtime, ptr);
1163 }
1164
1165 /*
1166
1167 */
1168
1169 static int snd_ad1848_probe(struct snd_wss *chip)
1170 {
1171 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1172 unsigned long flags;
1173 unsigned char r;
1174 unsigned short hardware = 0;
1175 int err = 0;
1176 int i;
1177
1178 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
1179 if (time_after(jiffies, timeout))
1180 return -ENODEV;
1181 cond_resched();
1182 }
1183 spin_lock_irqsave(&chip->reg_lock, flags);
1184
1185 /* set CS423x MODE 1 */
1186 snd_wss_dout(chip, CS4231_MISC_INFO, 0);
1187
1188 snd_wss_dout(chip, CS4231_RIGHT_INPUT, 0x45); /* 0x55 & ~0x10 */
1189 r = snd_wss_in(chip, CS4231_RIGHT_INPUT);
1190 if (r != 0x45) {
1191 /* RMGE always high on AD1847 */
1192 if ((r & ~CS4231_ENABLE_MIC_GAIN) != 0x45) {
1193 err = -ENODEV;
1194 goto out;
1195 }
1196 hardware = WSS_HW_AD1847;
1197 } else {
1198 snd_wss_dout(chip, CS4231_LEFT_INPUT, 0xaa);
1199 r = snd_wss_in(chip, CS4231_LEFT_INPUT);
1200 /* L/RMGE always low on AT2320 */
1201 if ((r | CS4231_ENABLE_MIC_GAIN) != 0xaa) {
1202 err = -ENODEV;
1203 goto out;
1204 }
1205 }
1206
1207 /* clear pending IRQ */
1208 wss_inb(chip, CS4231P(STATUS));
1209 wss_outb(chip, CS4231P(STATUS), 0);
1210 mb();
1211
1212 if ((chip->hardware & WSS_HW_TYPE_MASK) != WSS_HW_DETECT)
1213 goto out;
1214
1215 if (hardware) {
1216 chip->hardware = hardware;
1217 goto out;
1218 }
1219
1220 r = snd_wss_in(chip, CS4231_MISC_INFO);
1221
1222 /* set CS423x MODE 2 */
1223 snd_wss_dout(chip, CS4231_MISC_INFO, CS4231_MODE2);
1224 for (i = 0; i < 16; i++) {
1225 if (snd_wss_in(chip, i) != snd_wss_in(chip, 16 + i)) {
1226 /* we have more than 16 registers: check ID */
1227 if ((r & 0xf) != 0xa)
1228 goto out_mode;
1229 /*
1230 * on CMI8330, CS4231_VERSION is volume control and
1231 * can be set to 0
1232 */
1233 snd_wss_dout(chip, CS4231_VERSION, 0);
1234 r = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1235 if (!r)
1236 chip->hardware = WSS_HW_CMI8330;
1237 goto out_mode;
1238 }
1239 }
1240 if (r & 0x80)
1241 chip->hardware = WSS_HW_CS4248;
1242 else
1243 chip->hardware = WSS_HW_AD1848;
1244 out_mode:
1245 snd_wss_dout(chip, CS4231_MISC_INFO, 0);
1246 out:
1247 spin_unlock_irqrestore(&chip->reg_lock, flags);
1248 return err;
1249 }
1250
1251 static int snd_wss_probe(struct snd_wss *chip)
1252 {
1253 unsigned long flags;
1254 int i, id, rev, regnum;
1255 unsigned char *ptr;
1256 unsigned int hw;
1257
1258 id = snd_ad1848_probe(chip);
1259 if (id < 0)
1260 return id;
1261
1262 hw = chip->hardware;
1263 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1264 for (i = 0; i < 50; i++) {
1265 mb();
1266 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
1267 msleep(2);
1268 else {
1269 spin_lock_irqsave(&chip->reg_lock, flags);
1270 snd_wss_out(chip, CS4231_MISC_INFO,
1271 CS4231_MODE2);
1272 id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
1273 spin_unlock_irqrestore(&chip->reg_lock, flags);
1274 if (id == 0x0a)
1275 break; /* this is valid value */
1276 }
1277 }
1278 snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
1279 if (id != 0x0a)
1280 return -ENODEV; /* no valid device found */
1281
1282 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1283 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
1284 if (rev == 0x80) {
1285 unsigned char tmp = snd_wss_in(chip, 23);
1286 snd_wss_out(chip, 23, ~tmp);
1287 if (snd_wss_in(chip, 23) != tmp)
1288 chip->hardware = WSS_HW_AD1845;
1289 else
1290 chip->hardware = WSS_HW_CS4231;
1291 } else if (rev == 0xa0) {
1292 chip->hardware = WSS_HW_CS4231A;
1293 } else if (rev == 0xa2) {
1294 chip->hardware = WSS_HW_CS4232;
1295 } else if (rev == 0xb2) {
1296 chip->hardware = WSS_HW_CS4232A;
1297 } else if (rev == 0x83) {
1298 chip->hardware = WSS_HW_CS4236;
1299 } else if (rev == 0x03) {
1300 chip->hardware = WSS_HW_CS4236B;
1301 } else {
1302 snd_printk("unknown CS chip with version 0x%x\n", rev);
1303 return -ENODEV; /* unknown CS4231 chip? */
1304 }
1305 }
1306 spin_lock_irqsave(&chip->reg_lock, flags);
1307 wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
1308 wss_outb(chip, CS4231P(STATUS), 0);
1309 mb();
1310 spin_unlock_irqrestore(&chip->reg_lock, flags);
1311
1312 if (!(chip->hardware & WSS_HW_AD1848_MASK))
1313 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1314 switch (chip->hardware) {
1315 case WSS_HW_INTERWAVE:
1316 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
1317 break;
1318 case WSS_HW_CS4235:
1319 case WSS_HW_CS4236B:
1320 case WSS_HW_CS4237B:
1321 case WSS_HW_CS4238B:
1322 case WSS_HW_CS4239:
1323 if (hw == WSS_HW_DETECT3)
1324 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
1325 else
1326 chip->hardware = WSS_HW_CS4236;
1327 break;
1328 }
1329
1330 chip->image[CS4231_IFACE_CTRL] =
1331 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
1332 (chip->single_dma ? CS4231_SINGLE_DMA : 0);
1333 if (chip->hardware != WSS_HW_OPTI93X) {
1334 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1335 chip->image[CS4231_ALT_FEATURE_2] =
1336 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
1337 }
1338 /* enable fine grained frequency selection */
1339 if (chip->hardware == WSS_HW_AD1845)
1340 chip->image[AD1845_PWR_DOWN] = 8;
1341
1342 ptr = (unsigned char *) &chip->image;
1343 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
1344 snd_wss_mce_down(chip);
1345 spin_lock_irqsave(&chip->reg_lock, flags);
1346 for (i = 0; i < regnum; i++) /* ok.. fill all registers */
1347 snd_wss_out(chip, i, *ptr++);
1348 spin_unlock_irqrestore(&chip->reg_lock, flags);
1349 snd_wss_mce_up(chip);
1350 snd_wss_mce_down(chip);
1351
1352 mdelay(2);
1353
1354 /* ok.. try check hardware version for CS4236+ chips */
1355 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1356 if (chip->hardware == WSS_HW_CS4236B) {
1357 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
1358 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
1359 id = snd_cs4236_ext_in(chip, CS4236_VERSION);
1360 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
1361 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
1362 if ((id & 0x1f) == 0x1d) { /* CS4235 */
1363 chip->hardware = WSS_HW_CS4235;
1364 switch (id >> 5) {
1365 case 4:
1366 case 5:
1367 case 6:
1368 break;
1369 default:
1370 snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
1371 }
1372 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
1373 switch (id >> 5) {
1374 case 4:
1375 case 5:
1376 case 6:
1377 case 7:
1378 chip->hardware = WSS_HW_CS4236B;
1379 break;
1380 default:
1381 snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
1382 }
1383 } else if ((id & 0x1f) == 0x08) { /* CS4237B */
1384 chip->hardware = WSS_HW_CS4237B;
1385 switch (id >> 5) {
1386 case 4:
1387 case 5:
1388 case 6:
1389 case 7:
1390 break;
1391 default:
1392 snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
1393 }
1394 } else if ((id & 0x1f) == 0x09) { /* CS4238B */
1395 chip->hardware = WSS_HW_CS4238B;
1396 switch (id >> 5) {
1397 case 5:
1398 case 6:
1399 case 7:
1400 break;
1401 default:
1402 snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
1403 }
1404 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
1405 chip->hardware = WSS_HW_CS4239;
1406 switch (id >> 5) {
1407 case 4:
1408 case 5:
1409 case 6:
1410 break;
1411 default:
1412 snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
1413 }
1414 } else {
1415 snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
1416 }
1417 }
1418 }
1419 return 0; /* all things are ok.. */
1420 }
1421
1422 /*
1423
1424 */
1425
1426 static struct snd_pcm_hardware snd_wss_playback =
1427 {
1428 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1429 SNDRV_PCM_INFO_MMAP_VALID |
1430 SNDRV_PCM_INFO_RESUME |
1431 SNDRV_PCM_INFO_SYNC_START),
1432 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1433 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1434 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1435 .rate_min = 5510,
1436 .rate_max = 48000,
1437 .channels_min = 1,
1438 .channels_max = 2,
1439 .buffer_bytes_max = (128*1024),
1440 .period_bytes_min = 64,
1441 .period_bytes_max = (128*1024),
1442 .periods_min = 1,
1443 .periods_max = 1024,
1444 .fifo_size = 0,
1445 };
1446
1447 static struct snd_pcm_hardware snd_wss_capture =
1448 {
1449 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1450 SNDRV_PCM_INFO_MMAP_VALID |
1451 SNDRV_PCM_INFO_RESUME |
1452 SNDRV_PCM_INFO_SYNC_START),
1453 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1454 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1455 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1456 .rate_min = 5510,
1457 .rate_max = 48000,
1458 .channels_min = 1,
1459 .channels_max = 2,
1460 .buffer_bytes_max = (128*1024),
1461 .period_bytes_min = 64,
1462 .period_bytes_max = (128*1024),
1463 .periods_min = 1,
1464 .periods_max = 1024,
1465 .fifo_size = 0,
1466 };
1467
1468 /*
1469
1470 */
1471
1472 static int snd_wss_playback_open(struct snd_pcm_substream *substream)
1473 {
1474 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1475 struct snd_pcm_runtime *runtime = substream->runtime;
1476 int err;
1477
1478 runtime->hw = snd_wss_playback;
1479
1480 /* hardware limitation of older chipsets */
1481 if (chip->hardware & WSS_HW_AD1848_MASK)
1482 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1483 SNDRV_PCM_FMTBIT_S16_BE);
1484
1485 /* hardware bug in InterWave chipset */
1486 if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
1487 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
1488
1489 /* hardware limitation of cheap chips */
1490 if (chip->hardware == WSS_HW_CS4235 ||
1491 chip->hardware == WSS_HW_CS4239)
1492 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1493
1494 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
1495 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
1496
1497 if (chip->claim_dma) {
1498 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
1499 return err;
1500 }
1501
1502 err = snd_wss_open(chip, WSS_MODE_PLAY);
1503 if (err < 0) {
1504 if (chip->release_dma)
1505 chip->release_dma(chip, chip->dma_private_data, chip->dma1);
1506 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1507 return err;
1508 }
1509 chip->playback_substream = substream;
1510 snd_pcm_set_sync(substream);
1511 chip->rate_constraint(runtime);
1512 return 0;
1513 }
1514
1515 static int snd_wss_capture_open(struct snd_pcm_substream *substream)
1516 {
1517 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1518 struct snd_pcm_runtime *runtime = substream->runtime;
1519 int err;
1520
1521 runtime->hw = snd_wss_capture;
1522
1523 /* hardware limitation of older chipsets */
1524 if (chip->hardware & WSS_HW_AD1848_MASK)
1525 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1526 SNDRV_PCM_FMTBIT_S16_BE);
1527
1528 /* hardware limitation of cheap chips */
1529 if (chip->hardware == WSS_HW_CS4235 ||
1530 chip->hardware == WSS_HW_CS4239 ||
1531 chip->hardware == WSS_HW_OPTI93X)
1532 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |
1533 SNDRV_PCM_FMTBIT_S16_LE;
1534
1535 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
1536 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
1537
1538 if (chip->claim_dma) {
1539 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
1540 return err;
1541 }
1542
1543 err = snd_wss_open(chip, WSS_MODE_RECORD);
1544 if (err < 0) {
1545 if (chip->release_dma)
1546 chip->release_dma(chip, chip->dma_private_data, chip->dma2);
1547 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1548 return err;
1549 }
1550 chip->capture_substream = substream;
1551 snd_pcm_set_sync(substream);
1552 chip->rate_constraint(runtime);
1553 return 0;
1554 }
1555
1556 static int snd_wss_playback_close(struct snd_pcm_substream *substream)
1557 {
1558 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1559
1560 chip->playback_substream = NULL;
1561 snd_wss_close(chip, WSS_MODE_PLAY);
1562 return 0;
1563 }
1564
1565 static int snd_wss_capture_close(struct snd_pcm_substream *substream)
1566 {
1567 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1568
1569 chip->capture_substream = NULL;
1570 snd_wss_close(chip, WSS_MODE_RECORD);
1571 return 0;
1572 }
1573
1574 static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
1575 {
1576 int tmp;
1577
1578 if (!chip->thinkpad_flag)
1579 return;
1580
1581 outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
1582 tmp = inb(AD1848_THINKPAD_CTL_PORT2);
1583
1584 if (on)
1585 /* turn it on */
1586 tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
1587 else
1588 /* turn it off */
1589 tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
1590
1591 outb(tmp, AD1848_THINKPAD_CTL_PORT2);
1592 }
1593
1594 #ifdef CONFIG_PM
1595
1596 /* lowlevel suspend callback for CS4231 */
1597 static void snd_wss_suspend(struct snd_wss *chip)
1598 {
1599 int reg;
1600 unsigned long flags;
1601
1602 snd_pcm_suspend_all(chip->pcm);
1603 spin_lock_irqsave(&chip->reg_lock, flags);
1604 for (reg = 0; reg < 32; reg++)
1605 chip->image[reg] = snd_wss_in(chip, reg);
1606 spin_unlock_irqrestore(&chip->reg_lock, flags);
1607 if (chip->thinkpad_flag)
1608 snd_wss_thinkpad_twiddle(chip, 0);
1609 }
1610
1611 /* lowlevel resume callback for CS4231 */
1612 static void snd_wss_resume(struct snd_wss *chip)
1613 {
1614 int reg;
1615 unsigned long flags;
1616 /* int timeout; */
1617
1618 if (chip->thinkpad_flag)
1619 snd_wss_thinkpad_twiddle(chip, 1);
1620 snd_wss_mce_up(chip);
1621 spin_lock_irqsave(&chip->reg_lock, flags);
1622 for (reg = 0; reg < 32; reg++) {
1623 switch (reg) {
1624 case CS4231_VERSION:
1625 break;
1626 default:
1627 snd_wss_out(chip, reg, chip->image[reg]);
1628 break;
1629 }
1630 }
1631 spin_unlock_irqrestore(&chip->reg_lock, flags);
1632 #if 1
1633 snd_wss_mce_down(chip);
1634 #else
1635 /* The following is a workaround to avoid freeze after resume on TP600E.
1636 This is the first half of copy of snd_wss_mce_down(), but doesn't
1637 include rescheduling. -- iwai
1638 */
1639 snd_wss_busy_wait(chip);
1640 spin_lock_irqsave(&chip->reg_lock, flags);
1641 chip->mce_bit &= ~CS4231_MCE;
1642 timeout = wss_inb(chip, CS4231P(REGSEL));
1643 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
1644 spin_unlock_irqrestore(&chip->reg_lock, flags);
1645 if (timeout == 0x80)
1646 snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
1647 if ((timeout & CS4231_MCE) == 0 ||
1648 !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
1649 return;
1650 }
1651 snd_wss_busy_wait(chip);
1652 #endif
1653 }
1654 #endif /* CONFIG_PM */
1655
1656 static int snd_wss_free(struct snd_wss *chip)
1657 {
1658 release_and_free_resource(chip->res_port);
1659 release_and_free_resource(chip->res_cport);
1660 if (chip->irq >= 0) {
1661 disable_irq(chip->irq);
1662 if (!(chip->hwshare & WSS_HWSHARE_IRQ))
1663 free_irq(chip->irq, (void *) chip);
1664 }
1665 if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
1666 snd_dma_disable(chip->dma1);
1667 free_dma(chip->dma1);
1668 }
1669 if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
1670 chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
1671 snd_dma_disable(chip->dma2);
1672 free_dma(chip->dma2);
1673 }
1674 if (chip->timer)
1675 snd_device_free(chip->card, chip->timer);
1676 kfree(chip);
1677 return 0;
1678 }
1679
1680 static int snd_wss_dev_free(struct snd_device *device)
1681 {
1682 struct snd_wss *chip = device->device_data;
1683 return snd_wss_free(chip);
1684 }
1685
1686 const char *snd_wss_chip_id(struct snd_wss *chip)
1687 {
1688 switch (chip->hardware) {
1689 case WSS_HW_CS4231:
1690 return "CS4231";
1691 case WSS_HW_CS4231A:
1692 return "CS4231A";
1693 case WSS_HW_CS4232:
1694 return "CS4232";
1695 case WSS_HW_CS4232A:
1696 return "CS4232A";
1697 case WSS_HW_CS4235:
1698 return "CS4235";
1699 case WSS_HW_CS4236:
1700 return "CS4236";
1701 case WSS_HW_CS4236B:
1702 return "CS4236B";
1703 case WSS_HW_CS4237B:
1704 return "CS4237B";
1705 case WSS_HW_CS4238B:
1706 return "CS4238B";
1707 case WSS_HW_CS4239:
1708 return "CS4239";
1709 case WSS_HW_INTERWAVE:
1710 return "AMD InterWave";
1711 case WSS_HW_OPL3SA2:
1712 return chip->card->shortname;
1713 case WSS_HW_AD1845:
1714 return "AD1845";
1715 case WSS_HW_OPTI93X:
1716 return "OPTi 93x";
1717 case WSS_HW_AD1847:
1718 return "AD1847";
1719 case WSS_HW_AD1848:
1720 return "AD1848";
1721 case WSS_HW_CS4248:
1722 return "CS4248";
1723 case WSS_HW_CMI8330:
1724 return "CMI8330/C3D";
1725 default:
1726 return "???";
1727 }
1728 }
1729 EXPORT_SYMBOL(snd_wss_chip_id);
1730
1731 static int snd_wss_new(struct snd_card *card,
1732 unsigned short hardware,
1733 unsigned short hwshare,
1734 struct snd_wss **rchip)
1735 {
1736 struct snd_wss *chip;
1737
1738 *rchip = NULL;
1739 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1740 if (chip == NULL)
1741 return -ENOMEM;
1742 chip->hardware = hardware;
1743 chip->hwshare = hwshare;
1744
1745 spin_lock_init(&chip->reg_lock);
1746 mutex_init(&chip->mce_mutex);
1747 mutex_init(&chip->open_mutex);
1748 chip->card = card;
1749 chip->rate_constraint = snd_wss_xrate;
1750 chip->set_playback_format = snd_wss_playback_format;
1751 chip->set_capture_format = snd_wss_capture_format;
1752 if (chip->hardware == WSS_HW_OPTI93X)
1753 memcpy(&chip->image, &snd_opti93x_original_image,
1754 sizeof(snd_opti93x_original_image));
1755 else
1756 memcpy(&chip->image, &snd_wss_original_image,
1757 sizeof(snd_wss_original_image));
1758 if (chip->hardware & WSS_HW_AD1848_MASK) {
1759 chip->image[CS4231_PIN_CTRL] = 0;
1760 chip->image[CS4231_TEST_INIT] = 0;
1761 }
1762
1763 *rchip = chip;
1764 return 0;
1765 }
1766
1767 int snd_wss_create(struct snd_card *card,
1768 unsigned long port,
1769 unsigned long cport,
1770 int irq, int dma1, int dma2,
1771 unsigned short hardware,
1772 unsigned short hwshare,
1773 struct snd_wss **rchip)
1774 {
1775 static struct snd_device_ops ops = {
1776 .dev_free = snd_wss_dev_free,
1777 };
1778 struct snd_wss *chip;
1779 int err;
1780
1781 err = snd_wss_new(card, hardware, hwshare, &chip);
1782 if (err < 0)
1783 return err;
1784
1785 chip->irq = -1;
1786 chip->dma1 = -1;
1787 chip->dma2 = -1;
1788
1789 chip->res_port = request_region(port, 4, "WSS");
1790 if (!chip->res_port) {
1791 snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
1792 snd_wss_free(chip);
1793 return -EBUSY;
1794 }
1795 chip->port = port;
1796 if ((long)cport >= 0) {
1797 chip->res_cport = request_region(cport, 8, "CS4232 Control");
1798 if (!chip->res_cport) {
1799 snd_printk(KERN_ERR
1800 "wss: can't grab control port 0x%lx\n", cport);
1801 snd_wss_free(chip);
1802 return -ENODEV;
1803 }
1804 }
1805 chip->cport = cport;
1806 if (!(hwshare & WSS_HWSHARE_IRQ))
1807 if (request_irq(irq, snd_wss_interrupt, IRQF_DISABLED,
1808 "WSS", (void *) chip)) {
1809 snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
1810 snd_wss_free(chip);
1811 return -EBUSY;
1812 }
1813 chip->irq = irq;
1814 if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
1815 snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
1816 snd_wss_free(chip);
1817 return -EBUSY;
1818 }
1819 chip->dma1 = dma1;
1820 if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 &&
1821 dma2 >= 0 && request_dma(dma2, "WSS - 2")) {
1822 snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2);
1823 snd_wss_free(chip);
1824 return -EBUSY;
1825 }
1826 if (dma1 == dma2 || dma2 < 0) {
1827 chip->single_dma = 1;
1828 chip->dma2 = chip->dma1;
1829 } else
1830 chip->dma2 = dma2;
1831
1832 if (hardware == WSS_HW_THINKPAD) {
1833 chip->thinkpad_flag = 1;
1834 chip->hardware = WSS_HW_DETECT; /* reset */
1835 snd_wss_thinkpad_twiddle(chip, 1);
1836 }
1837
1838 /* global setup */
1839 if (snd_wss_probe(chip) < 0) {
1840 snd_wss_free(chip);
1841 return -ENODEV;
1842 }
1843 snd_wss_init(chip);
1844
1845 #if 0
1846 if (chip->hardware & WSS_HW_CS4232_MASK) {
1847 if (chip->res_cport == NULL)
1848 snd_printk("CS4232 control port features are not accessible\n");
1849 }
1850 #endif
1851
1852 /* Register device */
1853 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1854 if (err < 0) {
1855 snd_wss_free(chip);
1856 return err;
1857 }
1858
1859 #ifdef CONFIG_PM
1860 /* Power Management */
1861 chip->suspend = snd_wss_suspend;
1862 chip->resume = snd_wss_resume;
1863 #endif
1864
1865 *rchip = chip;
1866 return 0;
1867 }
1868 EXPORT_SYMBOL(snd_wss_create);
1869
1870 static struct snd_pcm_ops snd_wss_playback_ops = {
1871 .open = snd_wss_playback_open,
1872 .close = snd_wss_playback_close,
1873 .ioctl = snd_pcm_lib_ioctl,
1874 .hw_params = snd_wss_playback_hw_params,
1875 .hw_free = snd_wss_playback_hw_free,
1876 .prepare = snd_wss_playback_prepare,
1877 .trigger = snd_wss_trigger,
1878 .pointer = snd_wss_playback_pointer,
1879 };
1880
1881 static struct snd_pcm_ops snd_wss_capture_ops = {
1882 .open = snd_wss_capture_open,
1883 .close = snd_wss_capture_close,
1884 .ioctl = snd_pcm_lib_ioctl,
1885 .hw_params = snd_wss_capture_hw_params,
1886 .hw_free = snd_wss_capture_hw_free,
1887 .prepare = snd_wss_capture_prepare,
1888 .trigger = snd_wss_trigger,
1889 .pointer = snd_wss_capture_pointer,
1890 };
1891
1892 int snd_wss_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm)
1893 {
1894 struct snd_pcm *pcm;
1895 int err;
1896
1897 err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);
1898 if (err < 0)
1899 return err;
1900
1901 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);
1902 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);
1903
1904 /* global setup */
1905 pcm->private_data = chip;
1906 pcm->info_flags = 0;
1907 if (chip->single_dma)
1908 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
1909 if (chip->hardware != WSS_HW_INTERWAVE)
1910 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
1911 strcpy(pcm->name, snd_wss_chip_id(chip));
1912
1913 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1914 snd_dma_isa_data(),
1915 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
1916
1917 chip->pcm = pcm;
1918 if (rpcm)
1919 *rpcm = pcm;
1920 return 0;
1921 }
1922 EXPORT_SYMBOL(snd_wss_pcm);
1923
1924 static void snd_wss_timer_free(struct snd_timer *timer)
1925 {
1926 struct snd_wss *chip = timer->private_data;
1927 chip->timer = NULL;
1928 }
1929
1930 int snd_wss_timer(struct snd_wss *chip, int device, struct snd_timer **rtimer)
1931 {
1932 struct snd_timer *timer;
1933 struct snd_timer_id tid;
1934 int err;
1935
1936 /* Timer initialization */
1937 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1938 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1939 tid.card = chip->card->number;
1940 tid.device = device;
1941 tid.subdevice = 0;
1942 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1943 return err;
1944 strcpy(timer->name, snd_wss_chip_id(chip));
1945 timer->private_data = chip;
1946 timer->private_free = snd_wss_timer_free;
1947 timer->hw = snd_wss_timer_table;
1948 chip->timer = timer;
1949 if (rtimer)
1950 *rtimer = timer;
1951 return 0;
1952 }
1953 EXPORT_SYMBOL(snd_wss_timer);
1954
1955 /*
1956 * MIXER part
1957 */
1958
1959 static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,
1960 struct snd_ctl_elem_info *uinfo)
1961 {
1962 static char *texts[4] = {
1963 "Line", "Aux", "Mic", "Mix"
1964 };
1965 static char *opl3sa_texts[4] = {
1966 "Line", "CD", "Mic", "Mix"
1967 };
1968 static char *gusmax_texts[4] = {
1969 "Line", "Synth", "Mic", "Mix"
1970 };
1971 char **ptexts = texts;
1972 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1973
1974 if (snd_BUG_ON(!chip->card))
1975 return -EINVAL;
1976 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1977 uinfo->count = 2;
1978 uinfo->value.enumerated.items = 4;
1979 if (uinfo->value.enumerated.item > 3)
1980 uinfo->value.enumerated.item = 3;
1981 if (!strcmp(chip->card->driver, "GUS MAX"))
1982 ptexts = gusmax_texts;
1983 switch (chip->hardware) {
1984 case WSS_HW_INTERWAVE:
1985 ptexts = gusmax_texts;
1986 break;
1987 case WSS_HW_OPL3SA2:
1988 ptexts = opl3sa_texts;
1989 break;
1990 }
1991 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
1992 return 0;
1993 }
1994
1995 static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,
1996 struct snd_ctl_elem_value *ucontrol)
1997 {
1998 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1999 unsigned long flags;
2000
2001 spin_lock_irqsave(&chip->reg_lock, flags);
2002 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
2003 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
2004 spin_unlock_irqrestore(&chip->reg_lock, flags);
2005 return 0;
2006 }
2007
2008 static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,
2009 struct snd_ctl_elem_value *ucontrol)
2010 {
2011 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2012 unsigned long flags;
2013 unsigned short left, right;
2014 int change;
2015
2016 if (ucontrol->value.enumerated.item[0] > 3 ||
2017 ucontrol->value.enumerated.item[1] > 3)
2018 return -EINVAL;
2019 left = ucontrol->value.enumerated.item[0] << 6;
2020 right = ucontrol->value.enumerated.item[1] << 6;
2021 spin_lock_irqsave(&chip->reg_lock, flags);
2022 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
2023 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
2024 change = left != chip->image[CS4231_LEFT_INPUT] ||
2025 right != chip->image[CS4231_RIGHT_INPUT];
2026 snd_wss_out(chip, CS4231_LEFT_INPUT, left);
2027 snd_wss_out(chip, CS4231_RIGHT_INPUT, right);
2028 spin_unlock_irqrestore(&chip->reg_lock, flags);
2029 return change;
2030 }
2031
2032 int snd_wss_info_single(struct snd_kcontrol *kcontrol,
2033 struct snd_ctl_elem_info *uinfo)
2034 {
2035 int mask = (kcontrol->private_value >> 16) & 0xff;
2036
2037 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2038 uinfo->count = 1;
2039 uinfo->value.integer.min = 0;
2040 uinfo->value.integer.max = mask;
2041 return 0;
2042 }
2043 EXPORT_SYMBOL(snd_wss_info_single);
2044
2045 int snd_wss_get_single(struct snd_kcontrol *kcontrol,
2046 struct snd_ctl_elem_value *ucontrol)
2047 {
2048 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2049 unsigned long flags;
2050 int reg = kcontrol->private_value & 0xff;
2051 int shift = (kcontrol->private_value >> 8) & 0xff;
2052 int mask = (kcontrol->private_value >> 16) & 0xff;
2053 int invert = (kcontrol->private_value >> 24) & 0xff;
2054
2055 spin_lock_irqsave(&chip->reg_lock, flags);
2056 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
2057 spin_unlock_irqrestore(&chip->reg_lock, flags);
2058 if (invert)
2059 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2060 return 0;
2061 }
2062 EXPORT_SYMBOL(snd_wss_get_single);
2063
2064 int snd_wss_put_single(struct snd_kcontrol *kcontrol,
2065 struct snd_ctl_elem_value *ucontrol)
2066 {
2067 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2068 unsigned long flags;
2069 int reg = kcontrol->private_value & 0xff;
2070 int shift = (kcontrol->private_value >> 8) & 0xff;
2071 int mask = (kcontrol->private_value >> 16) & 0xff;
2072 int invert = (kcontrol->private_value >> 24) & 0xff;
2073 int change;
2074 unsigned short val;
2075
2076 val = (ucontrol->value.integer.value[0] & mask);
2077 if (invert)
2078 val = mask - val;
2079 val <<= shift;
2080 spin_lock_irqsave(&chip->reg_lock, flags);
2081 val = (chip->image[reg] & ~(mask << shift)) | val;
2082 change = val != chip->image[reg];
2083 snd_wss_out(chip, reg, val);
2084 spin_unlock_irqrestore(&chip->reg_lock, flags);
2085 return change;
2086 }
2087 EXPORT_SYMBOL(snd_wss_put_single);
2088
2089 int snd_wss_info_double(struct snd_kcontrol *kcontrol,
2090 struct snd_ctl_elem_info *uinfo)
2091 {
2092 int mask = (kcontrol->private_value >> 24) & 0xff;
2093
2094 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2095 uinfo->count = 2;
2096 uinfo->value.integer.min = 0;
2097 uinfo->value.integer.max = mask;
2098 return 0;
2099 }
2100 EXPORT_SYMBOL(snd_wss_info_double);
2101
2102 int snd_wss_get_double(struct snd_kcontrol *kcontrol,
2103 struct snd_ctl_elem_value *ucontrol)
2104 {
2105 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2106 unsigned long flags;
2107 int left_reg = kcontrol->private_value & 0xff;
2108 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2109 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2110 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2111 int mask = (kcontrol->private_value >> 24) & 0xff;
2112 int invert = (kcontrol->private_value >> 22) & 1;
2113
2114 spin_lock_irqsave(&chip->reg_lock, flags);
2115 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
2116 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
2117 spin_unlock_irqrestore(&chip->reg_lock, flags);
2118 if (invert) {
2119 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2120 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
2121 }
2122 return 0;
2123 }
2124 EXPORT_SYMBOL(snd_wss_get_double);
2125
2126 int snd_wss_put_double(struct snd_kcontrol *kcontrol,
2127 struct snd_ctl_elem_value *ucontrol)
2128 {
2129 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2130 unsigned long flags;
2131 int left_reg = kcontrol->private_value & 0xff;
2132 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2133 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2134 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2135 int mask = (kcontrol->private_value >> 24) & 0xff;
2136 int invert = (kcontrol->private_value >> 22) & 1;
2137 int change;
2138 unsigned short val1, val2;
2139
2140 val1 = ucontrol->value.integer.value[0] & mask;
2141 val2 = ucontrol->value.integer.value[1] & mask;
2142 if (invert) {
2143 val1 = mask - val1;
2144 val2 = mask - val2;
2145 }
2146 val1 <<= shift_left;
2147 val2 <<= shift_right;
2148 spin_lock_irqsave(&chip->reg_lock, flags);
2149 if (left_reg != right_reg) {
2150 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
2151 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
2152 change = val1 != chip->image[left_reg] ||
2153 val2 != chip->image[right_reg];
2154 snd_wss_out(chip, left_reg, val1);
2155 snd_wss_out(chip, right_reg, val2);
2156 } else {
2157 mask = (mask << shift_left) | (mask << shift_right);
2158 val1 = (chip->image[left_reg] & ~mask) | val1 | val2;
2159 change = val1 != chip->image[left_reg];
2160 snd_wss_out(chip, left_reg, val1);
2161 }
2162 spin_unlock_irqrestore(&chip->reg_lock, flags);
2163 return change;
2164 }
2165 EXPORT_SYMBOL(snd_wss_put_double);
2166
2167 static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
2168 static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
2169 static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
2170
2171 static struct snd_kcontrol_new snd_ad1848_controls[] = {
2172 WSS_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT,
2173 7, 7, 1, 1),
2174 WSS_DOUBLE_TLV("PCM Playback Volume", 0,
2175 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
2176 db_scale_6bit),
2177 WSS_DOUBLE("Aux Playback Switch", 0,
2178 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2179 WSS_DOUBLE_TLV("Aux Playback Volume", 0,
2180 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
2181 db_scale_5bit_12db_max),
2182 WSS_DOUBLE("Aux Playback Switch", 1,
2183 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2184 WSS_DOUBLE_TLV("Aux Playback Volume", 1,
2185 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
2186 db_scale_5bit_12db_max),
2187 WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
2188 0, 0, 15, 0, db_scale_rec_gain),
2189 {
2190 .name = "Capture Source",
2191 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2192 .info = snd_wss_info_mux,
2193 .get = snd_wss_get_mux,
2194 .put = snd_wss_put_mux,
2195 },
2196 WSS_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
2197 WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 1, 63, 0,
2198 db_scale_6bit),
2199 };
2200
2201 static struct snd_kcontrol_new snd_wss_controls[] = {
2202 WSS_DOUBLE("PCM Playback Switch", 0,
2203 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2204 WSS_DOUBLE("PCM Playback Volume", 0,
2205 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
2206 WSS_DOUBLE("Line Playback Switch", 0,
2207 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2208 WSS_DOUBLE("Line Playback Volume", 0,
2209 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
2210 WSS_DOUBLE("Aux Playback Switch", 0,
2211 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2212 WSS_DOUBLE("Aux Playback Volume", 0,
2213 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
2214 WSS_DOUBLE("Aux Playback Switch", 1,
2215 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2216 WSS_DOUBLE("Aux Playback Volume", 1,
2217 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
2218 WSS_SINGLE("Mono Playback Switch", 0,
2219 CS4231_MONO_CTRL, 7, 1, 1),
2220 WSS_SINGLE("Mono Playback Volume", 0,
2221 CS4231_MONO_CTRL, 0, 15, 1),
2222 WSS_SINGLE("Mono Output Playback Switch", 0,
2223 CS4231_MONO_CTRL, 6, 1, 1),
2224 WSS_SINGLE("Mono Output Playback Bypass", 0,
2225 CS4231_MONO_CTRL, 5, 1, 0),
2226 WSS_DOUBLE("Capture Volume", 0,
2227 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2228 {
2229 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2230 .name = "Capture Source",
2231 .info = snd_wss_info_mux,
2232 .get = snd_wss_get_mux,
2233 .put = snd_wss_put_mux,
2234 },
2235 WSS_DOUBLE("Mic Boost", 0,
2236 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2237 WSS_SINGLE("Loopback Capture Switch", 0,
2238 CS4231_LOOPBACK, 0, 1, 0),
2239 WSS_SINGLE("Loopback Capture Volume", 0,
2240 CS4231_LOOPBACK, 2, 63, 1)
2241 };
2242
2243 static struct snd_kcontrol_new snd_opti93x_controls[] = {
2244 WSS_DOUBLE("Master Playback Switch", 0,
2245 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
2246 WSS_DOUBLE("Master Playback Volume", 0,
2247 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
2248 WSS_DOUBLE("PCM Playback Switch", 0,
2249 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2250 WSS_DOUBLE("PCM Playback Volume", 0,
2251 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
2252 WSS_DOUBLE("FM Playback Switch", 0,
2253 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2254 WSS_DOUBLE("FM Playback Volume", 0,
2255 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
2256 WSS_DOUBLE("Line Playback Switch", 0,
2257 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2258 WSS_DOUBLE("Line Playback Volume", 0,
2259 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
2260 WSS_DOUBLE("Mic Playback Switch", 0,
2261 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
2262 WSS_DOUBLE("Mic Playback Volume", 0,
2263 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
2264 WSS_DOUBLE("Mic Boost", 0,
2265 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2266 WSS_DOUBLE("CD Playback Switch", 0,
2267 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2268 WSS_DOUBLE("CD Playback Volume", 0,
2269 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
2270 WSS_DOUBLE("Aux Playback Switch", 0,
2271 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
2272 WSS_DOUBLE("Aux Playback Volume", 0,
2273 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
2274 WSS_DOUBLE("Capture Volume", 0,
2275 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2276 {
2277 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2278 .name = "Capture Source",
2279 .info = snd_wss_info_mux,
2280 .get = snd_wss_get_mux,
2281 .put = snd_wss_put_mux,
2282 }
2283 };
2284
2285 int snd_wss_mixer(struct snd_wss *chip)
2286 {
2287 struct snd_card *card;
2288 unsigned int idx;
2289 int err;
2290
2291 if (snd_BUG_ON(!chip || !chip->pcm))
2292 return -EINVAL;
2293
2294 card = chip->card;
2295
2296 strcpy(card->mixername, chip->pcm->name);
2297
2298 if (chip->hardware == WSS_HW_OPTI93X)
2299 for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
2300 err = snd_ctl_add(card,
2301 snd_ctl_new1(&snd_opti93x_controls[idx],
2302 chip));
2303 if (err < 0)
2304 return err;
2305 }
2306 else if (chip->hardware & WSS_HW_AD1848_MASK)
2307 for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++) {
2308 err = snd_ctl_add(card,
2309 snd_ctl_new1(&snd_ad1848_controls[idx],
2310 chip));
2311 if (err < 0)
2312 return err;
2313 }
2314 else
2315 for (idx = 0; idx < ARRAY_SIZE(snd_wss_controls); idx++) {
2316 err = snd_ctl_add(card,
2317 snd_ctl_new1(&snd_wss_controls[idx],
2318 chip));
2319 if (err < 0)
2320 return err;
2321 }
2322 return 0;
2323 }
2324 EXPORT_SYMBOL(snd_wss_mixer);
2325
2326 const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)
2327 {
2328 return direction == SNDRV_PCM_STREAM_PLAYBACK ?
2329 &snd_wss_playback_ops : &snd_wss_capture_ops;
2330 }
2331 EXPORT_SYMBOL(snd_wss_get_pcm_ops);
2332
2333 /*
2334 * INIT part
2335 */
2336
2337 static int __init alsa_wss_init(void)
2338 {
2339 return 0;
2340 }
2341
2342 static void __exit alsa_wss_exit(void)
2343 {
2344 }
2345
2346 module_init(alsa_wss_init);
2347 module_exit(alsa_wss_exit);
Support for the Chinese Samsung S3C2440 based development boards