1 #include "amd64_edac.h"
4 static struct edac_pci_ctl_info
*amd64_ctl_pci
;
6 static int report_gart_errors
;
7 module_param(report_gart_errors
, int, 0644);
10 * Set by command line parameter. If BIOS has enabled the ECC, this override is
11 * cleared to prevent re-enabling the hardware by this driver.
13 static int ecc_enable_override
;
14 module_param(ecc_enable_override
, int, 0644);
16 static struct msr
*msrs
;
18 /* Lookup table for all possible MC control instances */
20 static struct mem_ctl_info
*mci_lookup
[EDAC_MAX_NUMNODES
];
21 static struct amd64_pvt
*pvt_lookup
[EDAC_MAX_NUMNODES
];
24 * See F2x80 for K8 and F2x[1,0]80 for Fam10 and later. The table below is only
25 * for DDR2 DRAM mapping.
27 u32 revf_quad_ddr2_shift
[] = {
28 0, /* 0000b NULL DIMM (128mb) */
47 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
48 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
51 *FIXME: Produce a better mapping/linearisation.
54 struct scrubrate scrubrates
[] = {
55 { 0x01, 1600000000UL},
77 { 0x00, 0UL}, /* scrubbing off */
81 * Memory scrubber control interface. For K8, memory scrubbing is handled by
82 * hardware and can involve L2 cache, dcache as well as the main memory. With
83 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
86 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
87 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
88 * bytes/sec for the setting.
90 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
91 * other archs, we might not have access to the caches directly.
95 * scan the scrub rate mapping table for a close or matching bandwidth value to
96 * issue. If requested is too big, then use last maximum value found.
98 static int amd64_search_set_scrub_rate(struct pci_dev
*ctl
, u32 new_bw
,
105 * map the configured rate (new_bw) to a value specific to the AMD64
106 * memory controller and apply to register. Search for the first
107 * bandwidth entry that is greater or equal than the setting requested
108 * and program that. If at last entry, turn off DRAM scrubbing.
110 for (i
= 0; i
< ARRAY_SIZE(scrubrates
); i
++) {
112 * skip scrub rates which aren't recommended
113 * (see F10 BKDG, F3x58)
115 if (scrubrates
[i
].scrubval
< min_scrubrate
)
118 if (scrubrates
[i
].bandwidth
<= new_bw
)
122 * if no suitable bandwidth found, turn off DRAM scrubbing
123 * entirely by falling back to the last element in the
128 scrubval
= scrubrates
[i
].scrubval
;
130 edac_printk(KERN_DEBUG
, EDAC_MC
,
131 "Setting scrub rate bandwidth: %u\n",
132 scrubrates
[i
].bandwidth
);
134 edac_printk(KERN_DEBUG
, EDAC_MC
, "Turning scrubbing off.\n");
136 pci_write_bits32(ctl
, K8_SCRCTRL
, scrubval
, 0x001F);
141 static int amd64_set_scrub_rate(struct mem_ctl_info
*mci
, u32
*bandwidth
)
143 struct amd64_pvt
*pvt
= mci
->pvt_info
;
144 u32 min_scrubrate
= 0x0;
146 switch (boot_cpu_data
.x86
) {
148 min_scrubrate
= K8_MIN_SCRUB_RATE_BITS
;
151 min_scrubrate
= F10_MIN_SCRUB_RATE_BITS
;
154 min_scrubrate
= F11_MIN_SCRUB_RATE_BITS
;
158 amd64_printk(KERN_ERR
, "Unsupported family!\n");
161 return amd64_search_set_scrub_rate(pvt
->misc_f3_ctl
, *bandwidth
,
165 static int amd64_get_scrub_rate(struct mem_ctl_info
*mci
, u32
*bw
)
167 struct amd64_pvt
*pvt
= mci
->pvt_info
;
169 int status
= -1, i
, ret
= 0;
171 ret
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_SCRCTRL
, &scrubval
);
173 debugf0("Reading K8_SCRCTRL failed\n");
175 scrubval
= scrubval
& 0x001F;
177 edac_printk(KERN_DEBUG
, EDAC_MC
,
178 "pci-read, sdram scrub control value: %d \n", scrubval
);
180 for (i
= 0; ARRAY_SIZE(scrubrates
); i
++) {
181 if (scrubrates
[i
].scrubval
== scrubval
) {
182 *bw
= scrubrates
[i
].bandwidth
;
191 /* Map from a CSROW entry to the mask entry that operates on it */
192 static inline u32
amd64_map_to_dcs_mask(struct amd64_pvt
*pvt
, int csrow
)
194 if (boot_cpu_data
.x86
== 0xf && pvt
->ext_model
< OPTERON_CPU_REV_F
)
200 /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
201 static u32
amd64_get_dct_base(struct amd64_pvt
*pvt
, int dct
, int csrow
)
204 return pvt
->dcsb0
[csrow
];
206 return pvt
->dcsb1
[csrow
];
210 * Return the 'mask' address the i'th CS entry. This function is needed because
211 * there number of DCSM registers on Rev E and prior vs Rev F and later is
214 static u32
amd64_get_dct_mask(struct amd64_pvt
*pvt
, int dct
, int csrow
)
217 return pvt
->dcsm0
[amd64_map_to_dcs_mask(pvt
, csrow
)];
219 return pvt
->dcsm1
[amd64_map_to_dcs_mask(pvt
, csrow
)];
224 * In *base and *limit, pass back the full 40-bit base and limit physical
225 * addresses for the node given by node_id. This information is obtained from
226 * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The
227 * base and limit addresses are of type SysAddr, as defined at the start of
228 * section 3.4.4 (p. 70). They are the lowest and highest physical addresses
229 * in the address range they represent.
231 static void amd64_get_base_and_limit(struct amd64_pvt
*pvt
, int node_id
,
232 u64
*base
, u64
*limit
)
234 *base
= pvt
->dram_base
[node_id
];
235 *limit
= pvt
->dram_limit
[node_id
];
239 * Return 1 if the SysAddr given by sys_addr matches the base/limit associated
242 static int amd64_base_limit_match(struct amd64_pvt
*pvt
,
243 u64 sys_addr
, int node_id
)
245 u64 base
, limit
, addr
;
247 amd64_get_base_and_limit(pvt
, node_id
, &base
, &limit
);
249 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
250 * all ones if the most significant implemented address bit is 1.
251 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
252 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
253 * Application Programming.
255 addr
= sys_addr
& 0x000000ffffffffffull
;
257 return (addr
>= base
) && (addr
<= limit
);
261 * Attempt to map a SysAddr to a node. On success, return a pointer to the
262 * mem_ctl_info structure for the node that the SysAddr maps to.
264 * On failure, return NULL.
266 static struct mem_ctl_info
*find_mc_by_sys_addr(struct mem_ctl_info
*mci
,
269 struct amd64_pvt
*pvt
;
274 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
275 * 3.4.4.2) registers to map the SysAddr to a node ID.
280 * The value of this field should be the same for all DRAM Base
281 * registers. Therefore we arbitrarily choose to read it from the
282 * register for node 0.
284 intlv_en
= pvt
->dram_IntlvEn
[0];
287 for (node_id
= 0; node_id
< DRAM_REG_COUNT
; node_id
++) {
288 if (amd64_base_limit_match(pvt
, sys_addr
, node_id
))
294 if (unlikely((intlv_en
!= 0x01) &&
295 (intlv_en
!= 0x03) &&
296 (intlv_en
!= 0x07))) {
297 amd64_printk(KERN_WARNING
, "junk value of 0x%x extracted from "
298 "IntlvEn field of DRAM Base Register for node 0: "
299 "this probably indicates a BIOS bug.\n", intlv_en
);
303 bits
= (((u32
) sys_addr
) >> 12) & intlv_en
;
305 for (node_id
= 0; ; ) {
306 if ((pvt
->dram_IntlvSel
[node_id
] & intlv_en
) == bits
)
307 break; /* intlv_sel field matches */
309 if (++node_id
>= DRAM_REG_COUNT
)
313 /* sanity test for sys_addr */
314 if (unlikely(!amd64_base_limit_match(pvt
, sys_addr
, node_id
))) {
315 amd64_printk(KERN_WARNING
,
316 "%s(): sys_addr 0x%llx falls outside base/limit "
317 "address range for node %d with node interleaving "
319 __func__
, sys_addr
, node_id
);
324 return edac_mc_find(node_id
);
327 debugf2("sys_addr 0x%lx doesn't match any node\n",
328 (unsigned long)sys_addr
);
334 * Extract the DRAM CS base address from selected csrow register.
336 static u64
base_from_dct_base(struct amd64_pvt
*pvt
, int csrow
)
338 return ((u64
) (amd64_get_dct_base(pvt
, 0, csrow
) & pvt
->dcsb_base
)) <<
343 * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way.
345 static u64
mask_from_dct_mask(struct amd64_pvt
*pvt
, int csrow
)
347 u64 dcsm_bits
, other_bits
;
350 /* Extract bits from DRAM CS Mask. */
351 dcsm_bits
= amd64_get_dct_mask(pvt
, 0, csrow
) & pvt
->dcsm_mask
;
353 other_bits
= pvt
->dcsm_mask
;
354 other_bits
= ~(other_bits
<< pvt
->dcs_shift
);
357 * The extracted bits from DCSM belong in the spaces represented by
358 * the cleared bits in other_bits.
360 mask
= (dcsm_bits
<< pvt
->dcs_shift
) | other_bits
;
366 * @input_addr is an InputAddr associated with the node given by mci. Return the
367 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
369 static int input_addr_to_csrow(struct mem_ctl_info
*mci
, u64 input_addr
)
371 struct amd64_pvt
*pvt
;
378 * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS
379 * base/mask register pair, test the condition shown near the start of
380 * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
382 for (csrow
= 0; csrow
< pvt
->cs_count
; csrow
++) {
384 /* This DRAM chip select is disabled on this node */
385 if ((pvt
->dcsb0
[csrow
] & K8_DCSB_CS_ENABLE
) == 0)
388 base
= base_from_dct_base(pvt
, csrow
);
389 mask
= ~mask_from_dct_mask(pvt
, csrow
);
391 if ((input_addr
& mask
) == (base
& mask
)) {
392 debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",
393 (unsigned long)input_addr
, csrow
,
400 debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",
401 (unsigned long)input_addr
, pvt
->mc_node_id
);
407 * Return the base value defined by the DRAM Base register for the node
408 * represented by mci. This function returns the full 40-bit value despite the
409 * fact that the register only stores bits 39-24 of the value. See section
410 * 3.4.4.1 (BKDG #26094, K8, revA-E)
412 static inline u64
get_dram_base(struct mem_ctl_info
*mci
)
414 struct amd64_pvt
*pvt
= mci
->pvt_info
;
416 return pvt
->dram_base
[pvt
->mc_node_id
];
420 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
421 * for the node represented by mci. Info is passed back in *hole_base,
422 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
423 * info is invalid. Info may be invalid for either of the following reasons:
425 * - The revision of the node is not E or greater. In this case, the DRAM Hole
426 * Address Register does not exist.
428 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
429 * indicating that its contents are not valid.
431 * The values passed back in *hole_base, *hole_offset, and *hole_size are
432 * complete 32-bit values despite the fact that the bitfields in the DHAR
433 * only represent bits 31-24 of the base and offset values.
435 int amd64_get_dram_hole_info(struct mem_ctl_info
*mci
, u64
*hole_base
,
436 u64
*hole_offset
, u64
*hole_size
)
438 struct amd64_pvt
*pvt
= mci
->pvt_info
;
441 /* only revE and later have the DRAM Hole Address Register */
442 if (boot_cpu_data
.x86
== 0xf && pvt
->ext_model
< OPTERON_CPU_REV_E
) {
443 debugf1(" revision %d for node %d does not support DHAR\n",
444 pvt
->ext_model
, pvt
->mc_node_id
);
448 /* only valid for Fam10h */
449 if (boot_cpu_data
.x86
== 0x10 &&
450 (pvt
->dhar
& F10_DRAM_MEM_HOIST_VALID
) == 0) {
451 debugf1(" Dram Memory Hoisting is DISABLED on this system\n");
455 if ((pvt
->dhar
& DHAR_VALID
) == 0) {
456 debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n",
461 /* This node has Memory Hoisting */
463 /* +------------------+--------------------+--------------------+-----
464 * | memory | DRAM hole | relocated |
465 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
467 * | | | [0x100000000, |
468 * | | | (0x100000000+ |
469 * | | | (0xffffffff-x))] |
470 * +------------------+--------------------+--------------------+-----
472 * Above is a diagram of physical memory showing the DRAM hole and the
473 * relocated addresses from the DRAM hole. As shown, the DRAM hole
474 * starts at address x (the base address) and extends through address
475 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
476 * addresses in the hole so that they start at 0x100000000.
479 base
= dhar_base(pvt
->dhar
);
482 *hole_size
= (0x1ull
<< 32) - base
;
484 if (boot_cpu_data
.x86
> 0xf)
485 *hole_offset
= f10_dhar_offset(pvt
->dhar
);
487 *hole_offset
= k8_dhar_offset(pvt
->dhar
);
489 debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
490 pvt
->mc_node_id
, (unsigned long)*hole_base
,
491 (unsigned long)*hole_offset
, (unsigned long)*hole_size
);
495 EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info
);
498 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
499 * assumed that sys_addr maps to the node given by mci.
501 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
502 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
503 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
504 * then it is also involved in translating a SysAddr to a DramAddr. Sections
505 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
506 * These parts of the documentation are unclear. I interpret them as follows:
508 * When node n receives a SysAddr, it processes the SysAddr as follows:
510 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
511 * Limit registers for node n. If the SysAddr is not within the range
512 * specified by the base and limit values, then node n ignores the Sysaddr
513 * (since it does not map to node n). Otherwise continue to step 2 below.
515 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
516 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
517 * the range of relocated addresses (starting at 0x100000000) from the DRAM
518 * hole. If not, skip to step 3 below. Else get the value of the
519 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
520 * offset defined by this value from the SysAddr.
522 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
523 * Base register for node n. To obtain the DramAddr, subtract the base
524 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
526 static u64
sys_addr_to_dram_addr(struct mem_ctl_info
*mci
, u64 sys_addr
)
528 u64 dram_base
, hole_base
, hole_offset
, hole_size
, dram_addr
;
531 dram_base
= get_dram_base(mci
);
533 ret
= amd64_get_dram_hole_info(mci
, &hole_base
, &hole_offset
,
536 if ((sys_addr
>= (1ull << 32)) &&
537 (sys_addr
< ((1ull << 32) + hole_size
))) {
538 /* use DHAR to translate SysAddr to DramAddr */
539 dram_addr
= sys_addr
- hole_offset
;
541 debugf2("using DHAR to translate SysAddr 0x%lx to "
543 (unsigned long)sys_addr
,
544 (unsigned long)dram_addr
);
551 * Translate the SysAddr to a DramAddr as shown near the start of
552 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
553 * only deals with 40-bit values. Therefore we discard bits 63-40 of
554 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
555 * discard are all 1s. Otherwise the bits we discard are all 0s. See
556 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
557 * Programmer's Manual Volume 1 Application Programming.
559 dram_addr
= (sys_addr
& 0xffffffffffull
) - dram_base
;
561 debugf2("using DRAM Base register to translate SysAddr 0x%lx to "
562 "DramAddr 0x%lx\n", (unsigned long)sys_addr
,
563 (unsigned long)dram_addr
);
568 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
569 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
570 * for node interleaving.
572 static int num_node_interleave_bits(unsigned intlv_en
)
574 static const int intlv_shift_table
[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
577 BUG_ON(intlv_en
> 7);
578 n
= intlv_shift_table
[intlv_en
];
582 /* Translate the DramAddr given by @dram_addr to an InputAddr. */
583 static u64
dram_addr_to_input_addr(struct mem_ctl_info
*mci
, u64 dram_addr
)
585 struct amd64_pvt
*pvt
;
592 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
593 * concerning translating a DramAddr to an InputAddr.
595 intlv_shift
= num_node_interleave_bits(pvt
->dram_IntlvEn
[0]);
596 input_addr
= ((dram_addr
>> intlv_shift
) & 0xffffff000ull
) +
599 debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
600 intlv_shift
, (unsigned long)dram_addr
,
601 (unsigned long)input_addr
);
607 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
608 * assumed that @sys_addr maps to the node given by mci.
610 static u64
sys_addr_to_input_addr(struct mem_ctl_info
*mci
, u64 sys_addr
)
615 dram_addr_to_input_addr(mci
, sys_addr_to_dram_addr(mci
, sys_addr
));
617 debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
618 (unsigned long)sys_addr
, (unsigned long)input_addr
);
625 * @input_addr is an InputAddr associated with the node represented by mci.
626 * Translate @input_addr to a DramAddr and return the result.
628 static u64
input_addr_to_dram_addr(struct mem_ctl_info
*mci
, u64 input_addr
)
630 struct amd64_pvt
*pvt
;
631 int node_id
, intlv_shift
;
636 * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
637 * shows how to translate a DramAddr to an InputAddr. Here we reverse
638 * this procedure. When translating from a DramAddr to an InputAddr, the
639 * bits used for node interleaving are discarded. Here we recover these
640 * bits from the IntlvSel field of the DRAM Limit register (section
641 * 3.4.4.2) for the node that input_addr is associated with.
644 node_id
= pvt
->mc_node_id
;
645 BUG_ON((node_id
< 0) || (node_id
> 7));
647 intlv_shift
= num_node_interleave_bits(pvt
->dram_IntlvEn
[0]);
649 if (intlv_shift
== 0) {
650 debugf1(" InputAddr 0x%lx translates to DramAddr of "
651 "same value\n", (unsigned long)input_addr
);
656 bits
= ((input_addr
& 0xffffff000ull
) << intlv_shift
) +
657 (input_addr
& 0xfff);
659 intlv_sel
= pvt
->dram_IntlvSel
[node_id
] & ((1 << intlv_shift
) - 1);
660 dram_addr
= bits
+ (intlv_sel
<< 12);
662 debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx "
663 "(%d node interleave bits)\n", (unsigned long)input_addr
,
664 (unsigned long)dram_addr
, intlv_shift
);
670 * @dram_addr is a DramAddr that maps to the node represented by mci. Convert
671 * @dram_addr to a SysAddr.
673 static u64
dram_addr_to_sys_addr(struct mem_ctl_info
*mci
, u64 dram_addr
)
675 struct amd64_pvt
*pvt
= mci
->pvt_info
;
676 u64 hole_base
, hole_offset
, hole_size
, base
, limit
, sys_addr
;
679 ret
= amd64_get_dram_hole_info(mci
, &hole_base
, &hole_offset
,
682 if ((dram_addr
>= hole_base
) &&
683 (dram_addr
< (hole_base
+ hole_size
))) {
684 sys_addr
= dram_addr
+ hole_offset
;
686 debugf1("using DHAR to translate DramAddr 0x%lx to "
687 "SysAddr 0x%lx\n", (unsigned long)dram_addr
,
688 (unsigned long)sys_addr
);
694 amd64_get_base_and_limit(pvt
, pvt
->mc_node_id
, &base
, &limit
);
695 sys_addr
= dram_addr
+ base
;
698 * The sys_addr we have computed up to this point is a 40-bit value
699 * because the k8 deals with 40-bit values. However, the value we are
700 * supposed to return is a full 64-bit physical address. The AMD
701 * x86-64 architecture specifies that the most significant implemented
702 * address bit through bit 63 of a physical address must be either all
703 * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a
704 * 64-bit value below. See section 3.4.2 of AMD publication 24592:
705 * AMD x86-64 Architecture Programmer's Manual Volume 1 Application
708 sys_addr
|= ~((sys_addr
& (1ull << 39)) - 1);
710 debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
711 pvt
->mc_node_id
, (unsigned long)dram_addr
,
712 (unsigned long)sys_addr
);
718 * @input_addr is an InputAddr associated with the node given by mci. Translate
719 * @input_addr to a SysAddr.
721 static inline u64
input_addr_to_sys_addr(struct mem_ctl_info
*mci
,
724 return dram_addr_to_sys_addr(mci
,
725 input_addr_to_dram_addr(mci
, input_addr
));
729 * Find the minimum and maximum InputAddr values that map to the given @csrow.
730 * Pass back these values in *input_addr_min and *input_addr_max.
732 static void find_csrow_limits(struct mem_ctl_info
*mci
, int csrow
,
733 u64
*input_addr_min
, u64
*input_addr_max
)
735 struct amd64_pvt
*pvt
;
739 BUG_ON((csrow
< 0) || (csrow
>= pvt
->cs_count
));
741 base
= base_from_dct_base(pvt
, csrow
);
742 mask
= mask_from_dct_mask(pvt
, csrow
);
744 *input_addr_min
= base
& ~mask
;
745 *input_addr_max
= base
| mask
| pvt
->dcs_mask_notused
;
749 * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB
750 * Address High (section 3.6.4.6) register values and return the result. Address
751 * is located in the info structure (nbeah and nbeal), the encoding is device
754 static u64
extract_error_address(struct mem_ctl_info
*mci
,
755 struct err_regs
*info
)
757 struct amd64_pvt
*pvt
= mci
->pvt_info
;
759 return pvt
->ops
->get_error_address(mci
, info
);
763 /* Map the Error address to a PAGE and PAGE OFFSET. */
764 static inline void error_address_to_page_and_offset(u64 error_address
,
765 u32
*page
, u32
*offset
)
767 *page
= (u32
) (error_address
>> PAGE_SHIFT
);
768 *offset
= ((u32
) error_address
) & ~PAGE_MASK
;
772 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
773 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
774 * of a node that detected an ECC memory error. mci represents the node that
775 * the error address maps to (possibly different from the node that detected
776 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
779 static int sys_addr_to_csrow(struct mem_ctl_info
*mci
, u64 sys_addr
)
783 csrow
= input_addr_to_csrow(mci
, sys_addr_to_input_addr(mci
, sys_addr
));
786 amd64_mc_printk(mci
, KERN_ERR
,
787 "Failed to translate InputAddr to csrow for "
788 "address 0x%lx\n", (unsigned long)sys_addr
);
792 static int get_channel_from_ecc_syndrome(unsigned short syndrome
);
794 static void amd64_cpu_display_info(struct amd64_pvt
*pvt
)
796 if (boot_cpu_data
.x86
== 0x11)
797 edac_printk(KERN_DEBUG
, EDAC_MC
, "F11h CPU detected\n");
798 else if (boot_cpu_data
.x86
== 0x10)
799 edac_printk(KERN_DEBUG
, EDAC_MC
, "F10h CPU detected\n");
800 else if (boot_cpu_data
.x86
== 0xf)
801 edac_printk(KERN_DEBUG
, EDAC_MC
, "%s detected\n",
802 (pvt
->ext_model
>= OPTERON_CPU_REV_F
) ?
803 "Rev F or later" : "Rev E or earlier");
805 /* we'll hardly ever ever get here */
806 edac_printk(KERN_ERR
, EDAC_MC
, "Unknown cpu!\n");
810 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
813 static enum edac_type
amd64_determine_edac_cap(struct amd64_pvt
*pvt
)
816 enum dev_type edac_cap
= EDAC_FLAG_NONE
;
818 bit
= (boot_cpu_data
.x86
> 0xf || pvt
->ext_model
>= OPTERON_CPU_REV_F
)
822 if (pvt
->dclr0
& BIT(bit
))
823 edac_cap
= EDAC_FLAG_SECDED
;
829 static void f10_debug_display_dimm_sizes(int ctrl
, struct amd64_pvt
*pvt
,
832 /* Display and decode various NB registers for debug purposes. */
833 static void amd64_dump_misc_regs(struct amd64_pvt
*pvt
)
837 debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n",
839 (pvt
->nbcap
& K8_NBCAP_DCT_DUAL
) ? "True" : "False",
840 (pvt
->nbcap
& K8_NBCAP_DUAL_NODE
) ? "True" : "False",
841 (pvt
->nbcap
& K8_NBCAP_8_NODE
) ? "True" : "False");
842 debugf1(" ECC Capable=%s ChipKill Capable=%s\n",
843 (pvt
->nbcap
& K8_NBCAP_SECDED
) ? "True" : "False",
844 (pvt
->nbcap
& K8_NBCAP_CHIPKILL
) ? "True" : "False");
845 debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n",
847 (pvt
->dclr0
& BIT(19)) ? "Enabled" : "Disabled",
848 (pvt
->dclr0
& BIT(8)) ? "Enabled" : "Disabled",
849 (pvt
->dclr0
& BIT(11)) ? "128b" : "64b");
850 debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n",
851 (pvt
->dclr0
& BIT(12)) ? "Y" : "N",
852 (pvt
->dclr0
& BIT(13)) ? "Y" : "N",
853 (pvt
->dclr0
& BIT(14)) ? "Y" : "N",
854 (pvt
->dclr0
& BIT(15)) ? "Y" : "N",
855 (pvt
->dclr0
& BIT(16)) ? "UN-Buffered" : "Buffered");
858 debugf1(" online-spare: 0x%8.08x\n", pvt
->online_spare
);
860 if (boot_cpu_data
.x86
== 0xf) {
861 debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
862 pvt
->dhar
, dhar_base(pvt
->dhar
),
863 k8_dhar_offset(pvt
->dhar
));
864 debugf1(" DramHoleValid=%s\n",
865 (pvt
->dhar
& DHAR_VALID
) ? "True" : "False");
867 debugf1(" dbam-dkt: 0x%8.08x\n", pvt
->dbam0
);
869 /* everything below this point is Fam10h and above */
873 debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
874 pvt
->dhar
, dhar_base(pvt
->dhar
),
875 f10_dhar_offset(pvt
->dhar
));
876 debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n",
877 (pvt
->dhar
& F10_DRAM_MEM_HOIST_VALID
) ?
879 (pvt
->dhar
& DHAR_VALID
) ?
883 /* Only if NOT ganged does dcl1 have valid info */
884 if (!dct_ganging_enabled(pvt
)) {
885 debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s "
886 "Width=%s\n", pvt
->dclr1
,
887 (pvt
->dclr1
& BIT(19)) ? "Enabled" : "Disabled",
888 (pvt
->dclr1
& BIT(8)) ? "Enabled" : "Disabled",
889 (pvt
->dclr1
& BIT(11)) ? "128b" : "64b");
890 debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s "
892 (pvt
->dclr1
& BIT(12)) ? "Y" : "N",
893 (pvt
->dclr1
& BIT(13)) ? "Y" : "N",
894 (pvt
->dclr1
& BIT(14)) ? "Y" : "N",
895 (pvt
->dclr1
& BIT(15)) ? "Y" : "N",
896 (pvt
->dclr1
& BIT(16)) ? "UN-Buffered" : "Buffered");
900 * Determine if ganged and then dump memory sizes for first controller,
901 * and if NOT ganged dump info for 2nd controller.
903 ganged
= dct_ganging_enabled(pvt
);
905 f10_debug_display_dimm_sizes(0, pvt
, ganged
);
908 f10_debug_display_dimm_sizes(1, pvt
, ganged
);
911 /* Read in both of DBAM registers */
912 static void amd64_read_dbam_reg(struct amd64_pvt
*pvt
)
918 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
, &pvt
->dbam0
);
922 if (boot_cpu_data
.x86
>= 0x10) {
924 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
, &pvt
->dbam1
);
933 debugf0("Error reading F2x%03x.\n", reg
);
937 * NOTE: CPU Revision Dependent code: Rev E and Rev F
939 * Set the DCSB and DCSM mask values depending on the CPU revision value. Also
940 * set the shift factor for the DCSB and DCSM values.
942 * ->dcs_mask_notused, RevE:
944 * To find the max InputAddr for the csrow, start with the base address and set
945 * all bits that are "don't care" bits in the test at the start of section
948 * The "don't care" bits are all set bits in the mask and all bits in the gaps
949 * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS
950 * represents bits [24:20] and [12:0], which are all bits in the above-mentioned
953 * ->dcs_mask_notused, RevF and later:
955 * To find the max InputAddr for the csrow, start with the base address and set
956 * all bits that are "don't care" bits in the test at the start of NPT section
959 * The "don't care" bits are all set bits in the mask and all bits in the gaps
960 * between bit ranges [36:27] and [21:13].
962 * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0],
963 * which are all bits in the above-mentioned gaps.
965 static void amd64_set_dct_base_and_mask(struct amd64_pvt
*pvt
)
968 if (boot_cpu_data
.x86
== 0xf && pvt
->ext_model
< OPTERON_CPU_REV_F
) {
969 pvt
->dcsb_base
= REV_E_DCSB_BASE_BITS
;
970 pvt
->dcsm_mask
= REV_E_DCSM_MASK_BITS
;
971 pvt
->dcs_mask_notused
= REV_E_DCS_NOTUSED_BITS
;
972 pvt
->dcs_shift
= REV_E_DCS_SHIFT
;
976 pvt
->dcsb_base
= REV_F_F1Xh_DCSB_BASE_BITS
;
977 pvt
->dcsm_mask
= REV_F_F1Xh_DCSM_MASK_BITS
;
978 pvt
->dcs_mask_notused
= REV_F_F1Xh_DCS_NOTUSED_BITS
;
979 pvt
->dcs_shift
= REV_F_F1Xh_DCS_SHIFT
;
981 if (boot_cpu_data
.x86
== 0x11) {
992 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers
994 static void amd64_read_dct_base_mask(struct amd64_pvt
*pvt
)
996 int cs
, reg
, err
= 0;
998 amd64_set_dct_base_and_mask(pvt
);
1000 for (cs
= 0; cs
< pvt
->cs_count
; cs
++) {
1001 reg
= K8_DCSB0
+ (cs
* 4);
1002 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
1005 debugf0("Reading K8_DCSB0[%d] failed\n", cs
);
1007 debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n",
1008 cs
, pvt
->dcsb0
[cs
], reg
);
1010 /* If DCT are NOT ganged, then read in DCT1's base */
1011 if (boot_cpu_data
.x86
>= 0x10 && !dct_ganging_enabled(pvt
)) {
1012 reg
= F10_DCSB1
+ (cs
* 4);
1013 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
1016 debugf0("Reading F10_DCSB1[%d] failed\n", cs
);
1018 debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n",
1019 cs
, pvt
->dcsb1
[cs
], reg
);
1025 for (cs
= 0; cs
< pvt
->num_dcsm
; cs
++) {
1026 reg
= K8_DCSM0
+ (cs
* 4);
1027 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
1030 debugf0("Reading K8_DCSM0 failed\n");
1032 debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n",
1033 cs
, pvt
->dcsm0
[cs
], reg
);
1035 /* If DCT are NOT ganged, then read in DCT1's mask */
1036 if (boot_cpu_data
.x86
>= 0x10 && !dct_ganging_enabled(pvt
)) {
1037 reg
= F10_DCSM1
+ (cs
* 4);
1038 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, reg
,
1041 debugf0("Reading F10_DCSM1[%d] failed\n", cs
);
1043 debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n",
1044 cs
, pvt
->dcsm1
[cs
], reg
);
1050 static enum mem_type
amd64_determine_memory_type(struct amd64_pvt
*pvt
)
1054 if (boot_cpu_data
.x86
>= 0x10 || pvt
->ext_model
>= OPTERON_CPU_REV_F
) {
1055 /* Rev F and later */
1056 type
= (pvt
->dclr0
& BIT(16)) ? MEM_DDR2
: MEM_RDDR2
;
1058 /* Rev E and earlier */
1059 type
= (pvt
->dclr0
& BIT(18)) ? MEM_DDR
: MEM_RDDR
;
1062 debugf1(" Memory type is: %s\n",
1063 (type
== MEM_DDR2
) ? "MEM_DDR2" :
1064 (type
== MEM_RDDR2
) ? "MEM_RDDR2" :
1065 (type
== MEM_DDR
) ? "MEM_DDR" : "MEM_RDDR");
1071 * Read the DRAM Configuration Low register. It differs between CG, D & E revs
1072 * and the later RevF memory controllers (DDR vs DDR2)
1075 * number of memory channels in operation
1077 * contents of the DCL0_LOW register
1079 static int k8_early_channel_count(struct amd64_pvt
*pvt
)
1083 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
1087 if ((boot_cpu_data
.x86_model
>> 4) >= OPTERON_CPU_REV_F
) {
1088 /* RevF (NPT) and later */
1089 flag
= pvt
->dclr0
& F10_WIDTH_128
;
1091 /* RevE and earlier */
1092 flag
= pvt
->dclr0
& REVE_WIDTH_128
;
1098 return (flag
) ? 2 : 1;
1101 /* extract the ERROR ADDRESS for the K8 CPUs */
1102 static u64
k8_get_error_address(struct mem_ctl_info
*mci
,
1103 struct err_regs
*info
)
1105 return (((u64
) (info
->nbeah
& 0xff)) << 32) +
1106 (info
->nbeal
& ~0x03);
1110 * Read the Base and Limit registers for K8 based Memory controllers; extract
1111 * fields from the 'raw' reg into separate data fields
1113 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN
1115 static void k8_read_dram_base_limit(struct amd64_pvt
*pvt
, int dram
)
1118 u32 off
= dram
<< 3; /* 8 bytes between DRAM entries */
1121 err
= pci_read_config_dword(pvt
->addr_f1_ctl
,
1122 K8_DRAM_BASE_LOW
+ off
, &low
);
1124 debugf0("Reading K8_DRAM_BASE_LOW failed\n");
1126 /* Extract parts into separate data entries */
1127 pvt
->dram_base
[dram
] = ((u64
) low
& 0xFFFF0000) << 8;
1128 pvt
->dram_IntlvEn
[dram
] = (low
>> 8) & 0x7;
1129 pvt
->dram_rw_en
[dram
] = (low
& 0x3);
1131 err
= pci_read_config_dword(pvt
->addr_f1_ctl
,
1132 K8_DRAM_LIMIT_LOW
+ off
, &low
);
1134 debugf0("Reading K8_DRAM_LIMIT_LOW failed\n");
1137 * Extract parts into separate data entries. Limit is the HIGHEST memory
1138 * location of the region, so lower 24 bits need to be all ones
1140 pvt
->dram_limit
[dram
] = (((u64
) low
& 0xFFFF0000) << 8) | 0x00FFFFFF;
1141 pvt
->dram_IntlvSel
[dram
] = (low
>> 8) & 0x7;
1142 pvt
->dram_DstNode
[dram
] = (low
& 0x7);
1145 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info
*mci
,
1146 struct err_regs
*info
,
1149 struct mem_ctl_info
*src_mci
;
1150 unsigned short syndrome
;
1154 /* Extract the syndrome parts and form a 16-bit syndrome */
1155 syndrome
= HIGH_SYNDROME(info
->nbsl
) << 8;
1156 syndrome
|= LOW_SYNDROME(info
->nbsh
);
1158 /* CHIPKILL enabled */
1159 if (info
->nbcfg
& K8_NBCFG_CHIPKILL
) {
1160 channel
= get_channel_from_ecc_syndrome(syndrome
);
1163 * Syndrome didn't map, so we don't know which of the
1164 * 2 DIMMs is in error. So we need to ID 'both' of them
1167 amd64_mc_printk(mci
, KERN_WARNING
,
1168 "unknown syndrome 0x%x - possible error "
1169 "reporting race\n", syndrome
);
1170 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1175 * non-chipkill ecc mode
1177 * The k8 documentation is unclear about how to determine the
1178 * channel number when using non-chipkill memory. This method
1179 * was obtained from email communication with someone at AMD.
1180 * (Wish the email was placed in this comment - norsk)
1182 channel
= ((SystemAddress
& BIT(3)) != 0);
1186 * Find out which node the error address belongs to. This may be
1187 * different from the node that detected the error.
1189 src_mci
= find_mc_by_sys_addr(mci
, SystemAddress
);
1191 amd64_mc_printk(mci
, KERN_ERR
,
1192 "failed to map error address 0x%lx to a node\n",
1193 (unsigned long)SystemAddress
);
1194 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1198 /* Now map the SystemAddress to a CSROW */
1199 csrow
= sys_addr_to_csrow(src_mci
, SystemAddress
);
1201 edac_mc_handle_ce_no_info(src_mci
, EDAC_MOD_STR
);
1203 error_address_to_page_and_offset(SystemAddress
, &page
, &offset
);
1205 edac_mc_handle_ce(src_mci
, page
, offset
, syndrome
, csrow
,
1206 channel
, EDAC_MOD_STR
);
1211 * determrine the number of PAGES in for this DIMM's size based on its DRAM
1214 * First step is to calc the number of bits to shift a value of 1 left to
1215 * indicate show many pages. Start with the DBAM value as the starting bits,
1216 * then proceed to adjust those shift bits, based on CPU rev and the table.
1217 * See BKDG on the DBAM
1219 static int k8_dbam_map_to_pages(struct amd64_pvt
*pvt
, int dram_map
)
1223 if (pvt
->ext_model
>= OPTERON_CPU_REV_F
) {
1224 nr_pages
= 1 << (revf_quad_ddr2_shift
[dram_map
] - PAGE_SHIFT
);
1227 * RevE and less section; this line is tricky. It collapses the
1228 * table used by RevD and later to one that matches revisions CG
1231 dram_map
-= (pvt
->ext_model
>= OPTERON_CPU_REV_D
) ?
1232 (dram_map
> 8 ? 4 : (dram_map
> 5 ?
1233 3 : (dram_map
> 2 ? 1 : 0))) : 0;
1235 /* 25 shift is 32MiB minimum DIMM size in RevE and prior */
1236 nr_pages
= 1 << (dram_map
+ 25 - PAGE_SHIFT
);
1243 * Get the number of DCT channels in use.
1246 * number of Memory Channels in operation
1248 * contents of the DCL0_LOW register
1250 static int f10_early_channel_count(struct amd64_pvt
*pvt
)
1252 int dbams
[] = { DBAM0
, DBAM1
};
1253 int err
= 0, channels
= 0;
1257 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
1261 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_1
, &pvt
->dclr1
);
1265 /* If we are in 128 bit mode, then we are using 2 channels */
1266 if (pvt
->dclr0
& F10_WIDTH_128
) {
1267 debugf0("Data WIDTH is 128 bits - 2 channels\n");
1273 * Need to check if in UN-ganged mode: In such, there are 2 channels,
1274 * but they are NOT in 128 bit mode and thus the above 'dcl0' status bit
1277 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1278 * their CSEnable bit on. If so, then SINGLE DIMM case.
1280 debugf0("Data WIDTH is NOT 128 bits - need more decoding\n");
1283 * Check DRAM Bank Address Mapping values for each DIMM to see if there
1284 * is more than just one DIMM present in unganged mode. Need to check
1285 * both controllers since DIMMs can be placed in either one.
1287 for (i
= 0; i
< ARRAY_SIZE(dbams
); i
++) {
1288 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, dbams
[i
], &dbam
);
1292 for (j
= 0; j
< 4; j
++) {
1293 if (DBAM_DIMM(j
, dbam
) > 0) {
1300 debugf0("MCT channel count: %d\n", channels
);
1309 static int f10_dbam_map_to_pages(struct amd64_pvt
*pvt
, int dram_map
)
1311 return 1 << (revf_quad_ddr2_shift
[dram_map
] - PAGE_SHIFT
);
1314 /* Enable extended configuration access via 0xCF8 feature */
1315 static void amd64_setup(struct amd64_pvt
*pvt
)
1319 pci_read_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, ®
);
1321 pvt
->flags
.cf8_extcfg
= !!(reg
& F10_NB_CFG_LOW_ENABLE_EXT_CFG
);
1322 reg
|= F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1323 pci_write_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, reg
);
1326 /* Restore the extended configuration access via 0xCF8 feature */
1327 static void amd64_teardown(struct amd64_pvt
*pvt
)
1331 pci_read_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, ®
);
1333 reg
&= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1334 if (pvt
->flags
.cf8_extcfg
)
1335 reg
|= F10_NB_CFG_LOW_ENABLE_EXT_CFG
;
1336 pci_write_config_dword(pvt
->misc_f3_ctl
, F10_NB_CFG_HIGH
, reg
);
1339 static u64
f10_get_error_address(struct mem_ctl_info
*mci
,
1340 struct err_regs
*info
)
1342 return (((u64
) (info
->nbeah
& 0xffff)) << 32) +
1343 (info
->nbeal
& ~0x01);
1347 * Read the Base and Limit registers for F10 based Memory controllers. Extract
1348 * fields from the 'raw' reg into separate data fields.
1350 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN.
1352 static void f10_read_dram_base_limit(struct amd64_pvt
*pvt
, int dram
)
1354 u32 high_offset
, low_offset
, high_base
, low_base
, high_limit
, low_limit
;
1356 low_offset
= K8_DRAM_BASE_LOW
+ (dram
<< 3);
1357 high_offset
= F10_DRAM_BASE_HIGH
+ (dram
<< 3);
1359 /* read the 'raw' DRAM BASE Address register */
1360 pci_read_config_dword(pvt
->addr_f1_ctl
, low_offset
, &low_base
);
1362 /* Read from the ECS data register */
1363 pci_read_config_dword(pvt
->addr_f1_ctl
, high_offset
, &high_base
);
1365 /* Extract parts into separate data entries */
1366 pvt
->dram_rw_en
[dram
] = (low_base
& 0x3);
1368 if (pvt
->dram_rw_en
[dram
] == 0)
1371 pvt
->dram_IntlvEn
[dram
] = (low_base
>> 8) & 0x7;
1373 pvt
->dram_base
[dram
] = (((u64
)high_base
& 0x000000FF) << 40) |
1374 (((u64
)low_base
& 0xFFFF0000) << 8);
1376 low_offset
= K8_DRAM_LIMIT_LOW
+ (dram
<< 3);
1377 high_offset
= F10_DRAM_LIMIT_HIGH
+ (dram
<< 3);
1379 /* read the 'raw' LIMIT registers */
1380 pci_read_config_dword(pvt
->addr_f1_ctl
, low_offset
, &low_limit
);
1382 /* Read from the ECS data register for the HIGH portion */
1383 pci_read_config_dword(pvt
->addr_f1_ctl
, high_offset
, &high_limit
);
1385 debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n",
1386 high_base
, low_base
, high_limit
, low_limit
);
1388 pvt
->dram_DstNode
[dram
] = (low_limit
& 0x7);
1389 pvt
->dram_IntlvSel
[dram
] = (low_limit
>> 8) & 0x7;
1392 * Extract address values and form a LIMIT address. Limit is the HIGHEST
1393 * memory location of the region, so low 24 bits need to be all ones.
1395 pvt
->dram_limit
[dram
] = (((u64
)high_limit
& 0x000000FF) << 40) |
1396 (((u64
) low_limit
& 0xFFFF0000) << 8) |
1400 static void f10_read_dram_ctl_register(struct amd64_pvt
*pvt
)
1404 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCTL_SEL_LOW
,
1405 &pvt
->dram_ctl_select_low
);
1407 debugf0("Reading F10_DCTL_SEL_LOW failed\n");
1409 debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n",
1410 pvt
->dram_ctl_select_low
, dct_sel_baseaddr(pvt
));
1412 debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-"
1413 "sel-hi-range=%s\n",
1414 (dct_ganging_enabled(pvt
) ? "GANGED" : "NOT GANGED"),
1415 (dct_dram_enabled(pvt
) ? "Enabled" : "Disabled"),
1416 (dct_high_range_enabled(pvt
) ? "Enabled" : "Disabled"));
1418 debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n",
1419 (dct_data_intlv_enabled(pvt
) ? "Enabled" : "Disabled"),
1420 (dct_memory_cleared(pvt
) ? "True " : "False "),
1421 dct_sel_interleave_addr(pvt
));
1424 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCTL_SEL_HIGH
,
1425 &pvt
->dram_ctl_select_high
);
1427 debugf0("Reading F10_DCTL_SEL_HIGH failed\n");
1431 * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1432 * Interleaving Modes.
1434 static u32
f10_determine_channel(struct amd64_pvt
*pvt
, u64 sys_addr
,
1435 int hi_range_sel
, u32 intlv_en
)
1437 u32 cs
, temp
, dct_sel_high
= (pvt
->dram_ctl_select_low
>> 1) & 1;
1439 if (dct_ganging_enabled(pvt
))
1441 else if (hi_range_sel
)
1443 else if (dct_interleave_enabled(pvt
)) {
1445 * see F2x110[DctSelIntLvAddr] - channel interleave mode
1447 if (dct_sel_interleave_addr(pvt
) == 0)
1448 cs
= sys_addr
>> 6 & 1;
1449 else if ((dct_sel_interleave_addr(pvt
) >> 1) & 1) {
1450 temp
= hweight_long((u32
) ((sys_addr
>> 16) & 0x1F)) % 2;
1452 if (dct_sel_interleave_addr(pvt
) & 1)
1453 cs
= (sys_addr
>> 9 & 1) ^ temp
;
1455 cs
= (sys_addr
>> 6 & 1) ^ temp
;
1456 } else if (intlv_en
& 4)
1457 cs
= sys_addr
>> 15 & 1;
1458 else if (intlv_en
& 2)
1459 cs
= sys_addr
>> 14 & 1;
1460 else if (intlv_en
& 1)
1461 cs
= sys_addr
>> 13 & 1;
1463 cs
= sys_addr
>> 12 & 1;
1464 } else if (dct_high_range_enabled(pvt
) && !dct_ganging_enabled(pvt
))
1465 cs
= ~dct_sel_high
& 1;
1472 static inline u32
f10_map_intlv_en_to_shift(u32 intlv_en
)
1476 else if (intlv_en
== 3)
1478 else if (intlv_en
== 7)
1484 /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */
1485 static inline u64
f10_get_base_addr_offset(u64 sys_addr
, int hi_range_sel
,
1486 u32 dct_sel_base_addr
,
1487 u64 dct_sel_base_off
,
1488 u32 hole_valid
, u32 hole_off
,
1494 if (!(dct_sel_base_addr
& 0xFFFFF800) &&
1495 hole_valid
&& (sys_addr
>= 0x100000000ULL
))
1496 chan_off
= hole_off
<< 16;
1498 chan_off
= dct_sel_base_off
;
1500 if (hole_valid
&& (sys_addr
>= 0x100000000ULL
))
1501 chan_off
= hole_off
<< 16;
1503 chan_off
= dram_base
& 0xFFFFF8000000ULL
;
1506 return (sys_addr
& 0x0000FFFFFFFFFFC0ULL
) -
1507 (chan_off
& 0x0000FFFFFF800000ULL
);
1510 /* Hack for the time being - Can we get this from BIOS?? */
1511 #define CH0SPARE_RANK 0
1512 #define CH1SPARE_RANK 1
1515 * checks if the csrow passed in is marked as SPARED, if so returns the new
1518 static inline int f10_process_possible_spare(int csrow
,
1519 u32 cs
, struct amd64_pvt
*pvt
)
1524 /* Depending on channel, isolate respective SPARING info */
1526 swap_done
= F10_ONLINE_SPARE_SWAPDONE1(pvt
->online_spare
);
1527 bad_dram_cs
= F10_ONLINE_SPARE_BADDRAM_CS1(pvt
->online_spare
);
1528 if (swap_done
&& (csrow
== bad_dram_cs
))
1529 csrow
= CH1SPARE_RANK
;
1531 swap_done
= F10_ONLINE_SPARE_SWAPDONE0(pvt
->online_spare
);
1532 bad_dram_cs
= F10_ONLINE_SPARE_BADDRAM_CS0(pvt
->online_spare
);
1533 if (swap_done
&& (csrow
== bad_dram_cs
))
1534 csrow
= CH0SPARE_RANK
;
1540 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
1541 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
1544 * -EINVAL: NOT FOUND
1545 * 0..csrow = Chip-Select Row
1547 static int f10_lookup_addr_in_dct(u32 in_addr
, u32 nid
, u32 cs
)
1549 struct mem_ctl_info
*mci
;
1550 struct amd64_pvt
*pvt
;
1551 u32 cs_base
, cs_mask
;
1552 int cs_found
= -EINVAL
;
1555 mci
= mci_lookup
[nid
];
1559 pvt
= mci
->pvt_info
;
1561 debugf1("InputAddr=0x%x channelselect=%d\n", in_addr
, cs
);
1563 for (csrow
= 0; csrow
< pvt
->cs_count
; csrow
++) {
1565 cs_base
= amd64_get_dct_base(pvt
, cs
, csrow
);
1566 if (!(cs_base
& K8_DCSB_CS_ENABLE
))
1570 * We have an ENABLED CSROW, Isolate just the MASK bits of the
1571 * target: [28:19] and [13:5], which map to [36:27] and [21:13]
1572 * of the actual address.
1574 cs_base
&= REV_F_F1Xh_DCSB_BASE_BITS
;
1577 * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and
1578 * [4:0] to become ON. Then mask off bits [28:0] ([36:8])
1580 cs_mask
= amd64_get_dct_mask(pvt
, cs
, csrow
);
1582 debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n",
1583 csrow
, cs_base
, cs_mask
);
1585 cs_mask
= (cs_mask
| 0x0007C01F) & 0x1FFFFFFF;
1587 debugf1(" Final CSMask=0x%x\n", cs_mask
);
1588 debugf1(" (InputAddr & ~CSMask)=0x%x "
1589 "(CSBase & ~CSMask)=0x%x\n",
1590 (in_addr
& ~cs_mask
), (cs_base
& ~cs_mask
));
1592 if ((in_addr
& ~cs_mask
) == (cs_base
& ~cs_mask
)) {
1593 cs_found
= f10_process_possible_spare(csrow
, cs
, pvt
);
1595 debugf1(" MATCH csrow=%d\n", cs_found
);
1602 /* For a given @dram_range, check if @sys_addr falls within it. */
1603 static int f10_match_to_this_node(struct amd64_pvt
*pvt
, int dram_range
,
1604 u64 sys_addr
, int *nid
, int *chan_sel
)
1606 int node_id
, cs_found
= -EINVAL
, high_range
= 0;
1607 u32 intlv_en
, intlv_sel
, intlv_shift
, hole_off
;
1608 u32 hole_valid
, tmp
, dct_sel_base
, channel
;
1609 u64 dram_base
, chan_addr
, dct_sel_base_off
;
1611 dram_base
= pvt
->dram_base
[dram_range
];
1612 intlv_en
= pvt
->dram_IntlvEn
[dram_range
];
1614 node_id
= pvt
->dram_DstNode
[dram_range
];
1615 intlv_sel
= pvt
->dram_IntlvSel
[dram_range
];
1617 debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
1618 dram_range
, dram_base
, sys_addr
, pvt
->dram_limit
[dram_range
]);
1621 * This assumes that one node's DHAR is the same as all the other
1624 hole_off
= (pvt
->dhar
& 0x0000FF80);
1625 hole_valid
= (pvt
->dhar
& 0x1);
1626 dct_sel_base_off
= (pvt
->dram_ctl_select_high
& 0xFFFFFC00) << 16;
1628 debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n",
1629 hole_off
, hole_valid
, intlv_sel
);
1632 (intlv_sel
!= ((sys_addr
>> 12) & intlv_en
)))
1635 dct_sel_base
= dct_sel_baseaddr(pvt
);
1638 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
1639 * select between DCT0 and DCT1.
1641 if (dct_high_range_enabled(pvt
) &&
1642 !dct_ganging_enabled(pvt
) &&
1643 ((sys_addr
>> 27) >= (dct_sel_base
>> 11)))
1646 channel
= f10_determine_channel(pvt
, sys_addr
, high_range
, intlv_en
);
1648 chan_addr
= f10_get_base_addr_offset(sys_addr
, high_range
, dct_sel_base
,
1649 dct_sel_base_off
, hole_valid
,
1650 hole_off
, dram_base
);
1652 intlv_shift
= f10_map_intlv_en_to_shift(intlv_en
);
1654 /* remove Node ID (in case of memory interleaving) */
1655 tmp
= chan_addr
& 0xFC0;
1657 chan_addr
= ((chan_addr
>> intlv_shift
) & 0xFFFFFFFFF000ULL
) | tmp
;
1659 /* remove channel interleave and hash */
1660 if (dct_interleave_enabled(pvt
) &&
1661 !dct_high_range_enabled(pvt
) &&
1662 !dct_ganging_enabled(pvt
)) {
1663 if (dct_sel_interleave_addr(pvt
) != 1)
1664 chan_addr
= (chan_addr
>> 1) & 0xFFFFFFFFFFFFFFC0ULL
;
1666 tmp
= chan_addr
& 0xFC0;
1667 chan_addr
= ((chan_addr
& 0xFFFFFFFFFFFFC000ULL
) >> 1)
1672 debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n",
1673 chan_addr
, (u32
)(chan_addr
>> 8));
1675 cs_found
= f10_lookup_addr_in_dct(chan_addr
>> 8, node_id
, channel
);
1677 if (cs_found
>= 0) {
1679 *chan_sel
= channel
;
1684 static int f10_translate_sysaddr_to_cs(struct amd64_pvt
*pvt
, u64 sys_addr
,
1685 int *node
, int *chan_sel
)
1687 int dram_range
, cs_found
= -EINVAL
;
1688 u64 dram_base
, dram_limit
;
1690 for (dram_range
= 0; dram_range
< DRAM_REG_COUNT
; dram_range
++) {
1692 if (!pvt
->dram_rw_en
[dram_range
])
1695 dram_base
= pvt
->dram_base
[dram_range
];
1696 dram_limit
= pvt
->dram_limit
[dram_range
];
1698 if ((dram_base
<= sys_addr
) && (sys_addr
<= dram_limit
)) {
1700 cs_found
= f10_match_to_this_node(pvt
, dram_range
,
1711 * This the F10h reference code from AMD to map a @sys_addr to NodeID,
1714 * The @sys_addr is usually an error address received from the hardware.
1716 static void f10_map_sysaddr_to_csrow(struct mem_ctl_info
*mci
,
1717 struct err_regs
*info
,
1720 struct amd64_pvt
*pvt
= mci
->pvt_info
;
1722 unsigned short syndrome
;
1723 int nid
, csrow
, chan
= 0;
1725 csrow
= f10_translate_sysaddr_to_cs(pvt
, sys_addr
, &nid
, &chan
);
1728 error_address_to_page_and_offset(sys_addr
, &page
, &offset
);
1730 syndrome
= HIGH_SYNDROME(info
->nbsl
) << 8;
1731 syndrome
|= LOW_SYNDROME(info
->nbsh
);
1734 * Is CHIPKILL on? If so, then we can attempt to use the
1735 * syndrome to isolate which channel the error was on.
1737 if (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
)
1738 chan
= get_channel_from_ecc_syndrome(syndrome
);
1741 edac_mc_handle_ce(mci
, page
, offset
, syndrome
,
1742 csrow
, chan
, EDAC_MOD_STR
);
1745 * Channel unknown, report all channels on this
1748 for (chan
= 0; chan
< mci
->csrows
[csrow
].nr_channels
;
1750 edac_mc_handle_ce(mci
, page
, offset
,
1758 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
1763 * Input (@index) is the DBAM DIMM value (1 of 4) used as an index into a shift
1764 * table (revf_quad_ddr2_shift) which starts at 128MB DIMM size. Index of 0
1765 * indicates an empty DIMM slot, as reported by Hardware on empty slots.
1767 * Normalize to 128MB by subracting 27 bit shift.
1769 static int map_dbam_to_csrow_size(int index
)
1773 if (index
> 0 && index
<= DBAM_MAX_VALUE
)
1774 mega_bytes
= ((128 << (revf_quad_ddr2_shift
[index
]-27)));
1780 * debug routine to display the memory sizes of a DIMM (ganged or not) and it
1783 static void f10_debug_display_dimm_sizes(int ctrl
, struct amd64_pvt
*pvt
,
1786 int dimm
, size0
, size1
;
1790 debugf1(" dbam%d: 0x%8.08x CSROW is %s\n", ctrl
,
1791 ctrl
? pvt
->dbam1
: pvt
->dbam0
,
1792 ganged
? "GANGED - dbam1 not used" : "NON-GANGED");
1794 dbam
= ctrl
? pvt
->dbam1
: pvt
->dbam0
;
1795 dcsb
= ctrl
? pvt
->dcsb1
: pvt
->dcsb0
;
1797 /* Dump memory sizes for DIMM and its CSROWs */
1798 for (dimm
= 0; dimm
< 4; dimm
++) {
1801 if (dcsb
[dimm
*2] & K8_DCSB_CS_ENABLE
)
1802 size0
= map_dbam_to_csrow_size(DBAM_DIMM(dimm
, dbam
));
1805 if (dcsb
[dimm
*2 + 1] & K8_DCSB_CS_ENABLE
)
1806 size1
= map_dbam_to_csrow_size(DBAM_DIMM(dimm
, dbam
));
1808 debugf1(" CTRL-%d DIMM-%d=%5dMB CSROW-%d=%5dMB "
1821 * Very early hardware probe on pci_probe thread to determine if this module
1822 * supports the hardware.
1828 static int f10_probe_valid_hardware(struct amd64_pvt
*pvt
)
1833 * If we are on a DDR3 machine, we don't know yet if
1834 * we support that properly at this time
1836 if ((pvt
->dchr0
& F10_DCHR_Ddr3Mode
) ||
1837 (pvt
->dchr1
& F10_DCHR_Ddr3Mode
)) {
1839 amd64_printk(KERN_WARNING
,
1840 "%s() This machine is running with DDR3 memory. "
1841 "This is not currently supported. "
1842 "DCHR0=0x%x DCHR1=0x%x\n",
1843 __func__
, pvt
->dchr0
, pvt
->dchr1
);
1845 amd64_printk(KERN_WARNING
,
1846 " Contact '%s' module MAINTAINER to help add"
1857 * There currently are 3 types type of MC devices for AMD Athlon/Opterons
1858 * (as per PCI DEVICE_IDs):
1860 * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI
1861 * DEVICE ID, even though there is differences between the different Revisions
1864 * Family F10h and F11h.
1867 static struct amd64_family_type amd64_family_types
[] = {
1870 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP
,
1871 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_K8_NB_MISC
,
1873 .early_channel_count
= k8_early_channel_count
,
1874 .get_error_address
= k8_get_error_address
,
1875 .read_dram_base_limit
= k8_read_dram_base_limit
,
1876 .map_sysaddr_to_csrow
= k8_map_sysaddr_to_csrow
,
1877 .dbam_map_to_pages
= k8_dbam_map_to_pages
,
1881 .ctl_name
= "Family 10h",
1882 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_10H_NB_MAP
,
1883 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_10H_NB_MISC
,
1885 .probe_valid_hardware
= f10_probe_valid_hardware
,
1886 .early_channel_count
= f10_early_channel_count
,
1887 .get_error_address
= f10_get_error_address
,
1888 .read_dram_base_limit
= f10_read_dram_base_limit
,
1889 .read_dram_ctl_register
= f10_read_dram_ctl_register
,
1890 .map_sysaddr_to_csrow
= f10_map_sysaddr_to_csrow
,
1891 .dbam_map_to_pages
= f10_dbam_map_to_pages
,
1895 .ctl_name
= "Family 11h",
1896 .addr_f1_ctl
= PCI_DEVICE_ID_AMD_11H_NB_MAP
,
1897 .misc_f3_ctl
= PCI_DEVICE_ID_AMD_11H_NB_MISC
,
1899 .probe_valid_hardware
= f10_probe_valid_hardware
,
1900 .early_channel_count
= f10_early_channel_count
,
1901 .get_error_address
= f10_get_error_address
,
1902 .read_dram_base_limit
= f10_read_dram_base_limit
,
1903 .read_dram_ctl_register
= f10_read_dram_ctl_register
,
1904 .map_sysaddr_to_csrow
= f10_map_sysaddr_to_csrow
,
1905 .dbam_map_to_pages
= f10_dbam_map_to_pages
,
1910 static struct pci_dev
*pci_get_related_function(unsigned int vendor
,
1911 unsigned int device
,
1912 struct pci_dev
*related
)
1914 struct pci_dev
*dev
= NULL
;
1916 dev
= pci_get_device(vendor
, device
, dev
);
1918 if ((dev
->bus
->number
== related
->bus
->number
) &&
1919 (PCI_SLOT(dev
->devfn
) == PCI_SLOT(related
->devfn
)))
1921 dev
= pci_get_device(vendor
, device
, dev
);
1928 * syndrome mapping table for ECC ChipKill devices
1930 * The comment in each row is the token (nibble) number that is in error.
1931 * The least significant nibble of the syndrome is the mask for the bits
1932 * that are in error (need to be toggled) for the particular nibble.
1934 * Each row contains 16 entries.
1935 * The first entry (0th) is the channel number for that row of syndromes.
1936 * The remaining 15 entries are the syndromes for the respective Error
1939 * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the
1941 * The 2nd index entry is 0x0010 that the second bit is damaged.
1942 * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits
1944 * Thus so on until index 15, 0x1111, whose entry has the syndrome
1945 * indicating that all 4 bits are damaged.
1947 * A search is performed on this table looking for a given syndrome.
1949 * See the AMD documentation for ECC syndromes. This ECC table is valid
1950 * across all the versions of the AMD64 processors.
1952 * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a
1953 * COLUMN index, then search all ROWS of that column, looking for a match
1954 * with the input syndrome. The ROW value will be the token number.
1956 * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this
1959 #define NUMBER_ECC_ROWS 36
1960 static const unsigned short ecc_chipkill_syndromes
[NUMBER_ECC_ROWS
][16] = {
1961 /* Channel 0 syndromes */
1962 {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57,
1963 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df },
1964 {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7,
1965 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f },
1966 {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
1967 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f },
1968 {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057,
1969 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df },
1970 {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097,
1971 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f },
1972 {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857,
1973 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf },
1974 {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467,
1975 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f },
1976 {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27,
1977 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff },
1978 {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177,
1979 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f },
1980 {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07,
1981 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f },
1982 {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07,
1983 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f },
1984 {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7,
1985 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f },
1986 {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87,
1987 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f },
1988 {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067,
1989 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f },
1990 {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77,
1991 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f },
1992 {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77,
1993 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f },
1995 /* Channel 1 syndromes */
1996 {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187,
1997 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f },
1998 {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627,
1999 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff },
2000 {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97,
2001 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f },
2002 {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97,
2003 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f },
2004 {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987,
2005 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f },
2006 {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677,
2007 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f },
2008 {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387,
2009 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f },
2010 {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17,
2011 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf },
2012 {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7,
2013 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f },
2014 {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397,
2015 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f },
2016 {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617,
2017 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf },
2018 {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527,
2019 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff },
2020 {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7,
2021 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef },
2022 {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7,
2023 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def },
2024 {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67,
2025 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f },
2026 {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377,
2027 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f },
2029 /* ECC bits are also in the set of tokens and they too can go bad
2030 * first 2 cover channel 0, while the second 2 cover channel 1
2032 {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807,
2033 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f },
2034 {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07,
2035 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f },
2036 {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97,
2037 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f },
2038 {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757,
2039 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df }
2043 * Given the syndrome argument, scan each of the channel tables for a syndrome
2044 * match. Depending on which table it is found, return the channel number.
2046 static int get_channel_from_ecc_syndrome(unsigned short syndrome
)
2051 /* Determine column to scan */
2052 column
= syndrome
& 0xF;
2054 /* Scan all rows, looking for syndrome, or end of table */
2055 for (row
= 0; row
< NUMBER_ECC_ROWS
; row
++) {
2056 if (ecc_chipkill_syndromes
[row
][column
] == syndrome
)
2057 return ecc_chipkill_syndromes
[row
][0];
2060 debugf0("syndrome(%x) not found\n", syndrome
);
2065 * Check for valid error in the NB Status High register. If so, proceed to read
2066 * NB Status Low, NB Address Low and NB Address High registers and store data
2067 * into error structure.
2070 * - 1: if hardware regs contains valid error info
2071 * - 0: if no valid error is indicated
2073 static int amd64_get_error_info_regs(struct mem_ctl_info
*mci
,
2074 struct err_regs
*regs
)
2076 struct amd64_pvt
*pvt
;
2077 struct pci_dev
*misc_f3_ctl
;
2080 pvt
= mci
->pvt_info
;
2081 misc_f3_ctl
= pvt
->misc_f3_ctl
;
2083 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBSH
, ®s
->nbsh
);
2087 if (!(regs
->nbsh
& K8_NBSH_VALID_BIT
))
2090 /* valid error, read remaining error information registers */
2091 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBSL
, ®s
->nbsl
);
2095 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBEAL
, ®s
->nbeal
);
2099 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBEAH
, ®s
->nbeah
);
2103 err
= pci_read_config_dword(misc_f3_ctl
, K8_NBCFG
, ®s
->nbcfg
);
2110 debugf0("Reading error info register failed\n");
2115 * This function is called to retrieve the error data from hardware and store it
2116 * in the info structure.
2119 * - 1: if a valid error is found
2120 * - 0: if no error is found
2122 static int amd64_get_error_info(struct mem_ctl_info
*mci
,
2123 struct err_regs
*info
)
2125 struct amd64_pvt
*pvt
;
2126 struct err_regs regs
;
2128 pvt
= mci
->pvt_info
;
2130 if (!amd64_get_error_info_regs(mci
, info
))
2134 * Here's the problem with the K8's EDAC reporting: There are four
2135 * registers which report pieces of error information. They are shared
2136 * between CEs and UEs. Furthermore, contrary to what is stated in the
2137 * BKDG, the overflow bit is never used! Every error always updates the
2138 * reporting registers.
2140 * Can you see the race condition? All four error reporting registers
2141 * must be read before a new error updates them! There is no way to read
2142 * all four registers atomically. The best than can be done is to detect
2143 * that a race has occured and then report the error without any kind of
2146 * What is still positive is that errors are still reported and thus
2147 * problems can still be detected - just not localized because the
2148 * syndrome and address are spread out across registers.
2150 * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev.
2151 * UEs and CEs should have separate register sets with proper overflow
2152 * bits that are used! At very least the problem can be fixed by
2153 * honoring the ErrValid bit in 'nbsh' and not updating registers - just
2154 * set the overflow bit - unless the current error is CE and the new
2155 * error is UE which would be the only situation for overwriting the
2161 /* Use info from the second read - most current */
2162 if (unlikely(!amd64_get_error_info_regs(mci
, info
)))
2165 /* clear the error bits in hardware */
2166 pci_write_bits32(pvt
->misc_f3_ctl
, K8_NBSH
, 0, K8_NBSH_VALID_BIT
);
2168 /* Check for the possible race condition */
2169 if ((regs
.nbsh
!= info
->nbsh
) ||
2170 (regs
.nbsl
!= info
->nbsl
) ||
2171 (regs
.nbeah
!= info
->nbeah
) ||
2172 (regs
.nbeal
!= info
->nbeal
)) {
2173 amd64_mc_printk(mci
, KERN_WARNING
,
2174 "hardware STATUS read access race condition "
2182 * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
2183 * ADDRESS and process.
2185 static void amd64_handle_ce(struct mem_ctl_info
*mci
,
2186 struct err_regs
*info
)
2188 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2191 /* Ensure that the Error Address is VALID */
2192 if ((info
->nbsh
& K8_NBSH_VALID_ERROR_ADDR
) == 0) {
2193 amd64_mc_printk(mci
, KERN_ERR
,
2194 "HW has no ERROR_ADDRESS available\n");
2195 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
);
2199 SystemAddress
= extract_error_address(mci
, info
);
2201 amd64_mc_printk(mci
, KERN_ERR
,
2202 "CE ERROR_ADDRESS= 0x%llx\n", SystemAddress
);
2204 pvt
->ops
->map_sysaddr_to_csrow(mci
, info
, SystemAddress
);
2207 /* Handle any Un-correctable Errors (UEs) */
2208 static void amd64_handle_ue(struct mem_ctl_info
*mci
,
2209 struct err_regs
*info
)
2214 struct mem_ctl_info
*log_mci
, *src_mci
= NULL
;
2218 if ((info
->nbsh
& K8_NBSH_VALID_ERROR_ADDR
) == 0) {
2219 amd64_mc_printk(mci
, KERN_CRIT
,
2220 "HW has no ERROR_ADDRESS available\n");
2221 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2225 SystemAddress
= extract_error_address(mci
, info
);
2228 * Find out which node the error address belongs to. This may be
2229 * different from the node that detected the error.
2231 src_mci
= find_mc_by_sys_addr(mci
, SystemAddress
);
2233 amd64_mc_printk(mci
, KERN_CRIT
,
2234 "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n",
2235 (unsigned long)SystemAddress
);
2236 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2242 csrow
= sys_addr_to_csrow(log_mci
, SystemAddress
);
2244 amd64_mc_printk(mci
, KERN_CRIT
,
2245 "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n",
2246 (unsigned long)SystemAddress
);
2247 edac_mc_handle_ue_no_info(log_mci
, EDAC_MOD_STR
);
2249 error_address_to_page_and_offset(SystemAddress
, &page
, &offset
);
2250 edac_mc_handle_ue(log_mci
, page
, offset
, csrow
, EDAC_MOD_STR
);
2254 static inline void __amd64_decode_bus_error(struct mem_ctl_info
*mci
,
2255 struct err_regs
*info
)
2257 u32 ec
= ERROR_CODE(info
->nbsl
);
2258 u32 xec
= EXT_ERROR_CODE(info
->nbsl
);
2259 int ecc_type
= (info
->nbsh
>> 13) & 0x3;
2261 /* Bail early out if this was an 'observed' error */
2262 if (PP(ec
) == K8_NBSL_PP_OBS
)
2265 /* Do only ECC errors */
2266 if (xec
&& xec
!= F10_NBSL_EXT_ERR_ECC
)
2270 amd64_handle_ce(mci
, info
);
2271 else if (ecc_type
== 1)
2272 amd64_handle_ue(mci
, info
);
2275 * If main error is CE then overflow must be CE. If main error is UE
2276 * then overflow is unknown. We'll call the overflow a CE - if
2277 * panic_on_ue is set then we're already panic'ed and won't arrive
2278 * here. Else, then apparently someone doesn't think that UE's are
2281 if (info
->nbsh
& K8_NBSH_OVERFLOW
)
2282 edac_mc_handle_ce_no_info(mci
, EDAC_MOD_STR
"Error Overflow");
2285 void amd64_decode_bus_error(int node_id
, struct err_regs
*regs
)
2287 struct mem_ctl_info
*mci
= mci_lookup
[node_id
];
2289 __amd64_decode_bus_error(mci
, regs
);
2292 * Check the UE bit of the NB status high register, if set generate some
2293 * logs. If NOT a GART error, then process the event as a NO-INFO event.
2294 * If it was a GART error, skip that process.
2296 * FIXME: this should go somewhere else, if at all.
2298 if (regs
->nbsh
& K8_NBSH_UC_ERR
&& !report_gart_errors
)
2299 edac_mc_handle_ue_no_info(mci
, "UE bit is set");
2304 * The main polling 'check' function, called FROM the edac core to perform the
2305 * error checking and if an error is encountered, error processing.
2307 static void amd64_check(struct mem_ctl_info
*mci
)
2309 struct err_regs regs
;
2311 if (amd64_get_error_info(mci
, ®s
)) {
2312 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2313 amd_decode_nb_mce(pvt
->mc_node_id
, ®s
, 1);
2319 * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer
2320 * 2) AMD Family index value
2323 * Upon return of 0, the following filled in:
2325 * struct pvt->addr_f1_ctl
2326 * struct pvt->misc_f3_ctl
2328 * Filled in with related device funcitions of 'dram_f2_ctl'
2329 * These devices are "reserved" via the pci_get_device()
2331 * Upon return of 1 (error status):
2335 static int amd64_reserve_mc_sibling_devices(struct amd64_pvt
*pvt
, int mc_idx
)
2337 const struct amd64_family_type
*amd64_dev
= &amd64_family_types
[mc_idx
];
2339 /* Reserve the ADDRESS MAP Device */
2340 pvt
->addr_f1_ctl
= pci_get_related_function(pvt
->dram_f2_ctl
->vendor
,
2341 amd64_dev
->addr_f1_ctl
,
2344 if (!pvt
->addr_f1_ctl
) {
2345 amd64_printk(KERN_ERR
, "error address map device not found: "
2346 "vendor %x device 0x%x (broken BIOS?)\n",
2347 PCI_VENDOR_ID_AMD
, amd64_dev
->addr_f1_ctl
);
2351 /* Reserve the MISC Device */
2352 pvt
->misc_f3_ctl
= pci_get_related_function(pvt
->dram_f2_ctl
->vendor
,
2353 amd64_dev
->misc_f3_ctl
,
2356 if (!pvt
->misc_f3_ctl
) {
2357 pci_dev_put(pvt
->addr_f1_ctl
);
2358 pvt
->addr_f1_ctl
= NULL
;
2360 amd64_printk(KERN_ERR
, "error miscellaneous device not found: "
2361 "vendor %x device 0x%x (broken BIOS?)\n",
2362 PCI_VENDOR_ID_AMD
, amd64_dev
->misc_f3_ctl
);
2366 debugf1(" Addr Map device PCI Bus ID:\t%s\n",
2367 pci_name(pvt
->addr_f1_ctl
));
2368 debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n",
2369 pci_name(pvt
->dram_f2_ctl
));
2370 debugf1(" Misc device PCI Bus ID:\t%s\n",
2371 pci_name(pvt
->misc_f3_ctl
));
2376 static void amd64_free_mc_sibling_devices(struct amd64_pvt
*pvt
)
2378 pci_dev_put(pvt
->addr_f1_ctl
);
2379 pci_dev_put(pvt
->misc_f3_ctl
);
2383 * Retrieve the hardware registers of the memory controller (this includes the
2384 * 'Address Map' and 'Misc' device regs)
2386 static void amd64_read_mc_registers(struct amd64_pvt
*pvt
)
2392 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2393 * those are Read-As-Zero
2395 rdmsrl(MSR_K8_TOP_MEM1
, msr_val
);
2396 pvt
->top_mem
= msr_val
>> 23;
2397 debugf0(" TOP_MEM=0x%08llx\n", pvt
->top_mem
);
2399 /* check first whether TOP_MEM2 is enabled */
2400 rdmsrl(MSR_K8_SYSCFG
, msr_val
);
2401 if (msr_val
& (1U << 21)) {
2402 rdmsrl(MSR_K8_TOP_MEM2
, msr_val
);
2403 pvt
->top_mem2
= msr_val
>> 23;
2404 debugf0(" TOP_MEM2=0x%08llx\n", pvt
->top_mem2
);
2406 debugf0(" TOP_MEM2 disabled.\n");
2408 amd64_cpu_display_info(pvt
);
2410 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCAP
, &pvt
->nbcap
);
2414 if (pvt
->ops
->read_dram_ctl_register
)
2415 pvt
->ops
->read_dram_ctl_register(pvt
);
2417 for (dram
= 0; dram
< DRAM_REG_COUNT
; dram
++) {
2419 * Call CPU specific READ function to get the DRAM Base and
2420 * Limit values from the DCT.
2422 pvt
->ops
->read_dram_base_limit(pvt
, dram
);
2425 * Only print out debug info on rows with both R and W Enabled.
2426 * Normal processing, compiler should optimize this whole 'if'
2427 * debug output block away.
2429 if (pvt
->dram_rw_en
[dram
] != 0) {
2430 debugf1(" DRAM_BASE[%d]: 0x%8.08x-%8.08x "
2431 "DRAM_LIMIT: 0x%8.08x-%8.08x\n",
2433 (u32
)(pvt
->dram_base
[dram
] >> 32),
2434 (u32
)(pvt
->dram_base
[dram
] & 0xFFFFFFFF),
2435 (u32
)(pvt
->dram_limit
[dram
] >> 32),
2436 (u32
)(pvt
->dram_limit
[dram
] & 0xFFFFFFFF));
2437 debugf1(" IntlvEn=%s %s %s "
2438 "IntlvSel=%d DstNode=%d\n",
2439 pvt
->dram_IntlvEn
[dram
] ?
2440 "Enabled" : "Disabled",
2441 (pvt
->dram_rw_en
[dram
] & 0x2) ? "W" : "!W",
2442 (pvt
->dram_rw_en
[dram
] & 0x1) ? "R" : "!R",
2443 pvt
->dram_IntlvSel
[dram
],
2444 pvt
->dram_DstNode
[dram
]);
2448 amd64_read_dct_base_mask(pvt
);
2450 err
= pci_read_config_dword(pvt
->addr_f1_ctl
, K8_DHAR
, &pvt
->dhar
);
2454 amd64_read_dbam_reg(pvt
);
2456 err
= pci_read_config_dword(pvt
->misc_f3_ctl
,
2457 F10_ONLINE_SPARE
, &pvt
->online_spare
);
2461 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_0
, &pvt
->dclr0
);
2465 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCHR_0
, &pvt
->dchr0
);
2469 if (!dct_ganging_enabled(pvt
)) {
2470 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCLR_1
,
2475 err
= pci_read_config_dword(pvt
->dram_f2_ctl
, F10_DCHR_1
,
2481 amd64_dump_misc_regs(pvt
);
2486 debugf0("Reading an MC register failed\n");
2491 * NOTE: CPU Revision Dependent code
2494 * @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1)
2495 * k8 private pointer to -->
2496 * DRAM Bank Address mapping register
2498 * DCL register where dual_channel_active is
2500 * The DBAM register consists of 4 sets of 4 bits each definitions:
2503 * 0-3 CSROWs 0 and 1
2504 * 4-7 CSROWs 2 and 3
2505 * 8-11 CSROWs 4 and 5
2506 * 12-15 CSROWs 6 and 7
2508 * Values range from: 0 to 15
2509 * The meaning of the values depends on CPU revision and dual-channel state,
2510 * see relevant BKDG more info.
2512 * The memory controller provides for total of only 8 CSROWs in its current
2513 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
2514 * single channel or two (2) DIMMs in dual channel mode.
2516 * The following code logic collapses the various tables for CSROW based on CPU
2520 * The number of PAGE_SIZE pages on the specified CSROW number it
2524 static u32
amd64_csrow_nr_pages(int csrow_nr
, struct amd64_pvt
*pvt
)
2526 u32 dram_map
, nr_pages
;
2529 * The math on this doesn't look right on the surface because x/2*4 can
2530 * be simplified to x*2 but this expression makes use of the fact that
2531 * it is integral math where 1/2=0. This intermediate value becomes the
2532 * number of bits to shift the DBAM register to extract the proper CSROW
2535 dram_map
= (pvt
->dbam0
>> ((csrow_nr
/ 2) * 4)) & 0xF;
2537 nr_pages
= pvt
->ops
->dbam_map_to_pages(pvt
, dram_map
);
2540 * If dual channel then double the memory size of single channel.
2541 * Channel count is 1 or 2
2543 nr_pages
<<= (pvt
->channel_count
- 1);
2545 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr
, dram_map
);
2546 debugf0(" nr_pages= %u channel-count = %d\n",
2547 nr_pages
, pvt
->channel_count
);
2553 * Initialize the array of csrow attribute instances, based on the values
2554 * from pci config hardware registers.
2556 static int amd64_init_csrows(struct mem_ctl_info
*mci
)
2558 struct csrow_info
*csrow
;
2559 struct amd64_pvt
*pvt
;
2560 u64 input_addr_min
, input_addr_max
, sys_addr
;
2561 int i
, err
= 0, empty
= 1;
2563 pvt
= mci
->pvt_info
;
2565 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &pvt
->nbcfg
);
2567 debugf0("Reading K8_NBCFG failed\n");
2569 debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt
->nbcfg
,
2570 (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2571 (pvt
->nbcfg
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled"
2574 for (i
= 0; i
< pvt
->cs_count
; i
++) {
2575 csrow
= &mci
->csrows
[i
];
2577 if ((pvt
->dcsb0
[i
] & K8_DCSB_CS_ENABLE
) == 0) {
2578 debugf1("----CSROW %d EMPTY for node %d\n", i
,
2583 debugf1("----CSROW %d VALID for MC node %d\n",
2584 i
, pvt
->mc_node_id
);
2587 csrow
->nr_pages
= amd64_csrow_nr_pages(i
, pvt
);
2588 find_csrow_limits(mci
, i
, &input_addr_min
, &input_addr_max
);
2589 sys_addr
= input_addr_to_sys_addr(mci
, input_addr_min
);
2590 csrow
->first_page
= (u32
) (sys_addr
>> PAGE_SHIFT
);
2591 sys_addr
= input_addr_to_sys_addr(mci
, input_addr_max
);
2592 csrow
->last_page
= (u32
) (sys_addr
>> PAGE_SHIFT
);
2593 csrow
->page_mask
= ~mask_from_dct_mask(pvt
, i
);
2594 /* 8 bytes of resolution */
2596 csrow
->mtype
= amd64_determine_memory_type(pvt
);
2598 debugf1(" for MC node %d csrow %d:\n", pvt
->mc_node_id
, i
);
2599 debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n",
2600 (unsigned long)input_addr_min
,
2601 (unsigned long)input_addr_max
);
2602 debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n",
2603 (unsigned long)sys_addr
, csrow
->page_mask
);
2604 debugf1(" nr_pages: %u first_page: 0x%lx "
2605 "last_page: 0x%lx\n",
2606 (unsigned)csrow
->nr_pages
,
2607 csrow
->first_page
, csrow
->last_page
);
2610 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
2612 if (pvt
->nbcfg
& K8_NBCFG_ECC_ENABLE
)
2614 (pvt
->nbcfg
& K8_NBCFG_CHIPKILL
) ?
2615 EDAC_S4ECD4ED
: EDAC_SECDED
;
2617 csrow
->edac_mode
= EDAC_NONE
;
2623 /* get all cores on this DCT */
2624 static void get_cpus_on_this_dct_cpumask(struct cpumask
*mask
, int nid
)
2628 for_each_online_cpu(cpu
)
2629 if (amd_get_nb_id(cpu
) == nid
)
2630 cpumask_set_cpu(cpu
, mask
);
2633 /* check MCG_CTL on all the cpus on this node */
2634 static bool amd64_nb_mce_bank_enabled_on_node(int nid
)
2640 if (!zalloc_cpumask_var(&mask
, GFP_KERNEL
)) {
2641 amd64_printk(KERN_WARNING
, "%s: error allocating mask\n",
2646 get_cpus_on_this_dct_cpumask(mask
, nid
);
2648 rdmsr_on_cpus(mask
, MSR_IA32_MCG_CTL
, msrs
);
2650 for_each_cpu(cpu
, mask
) {
2651 struct msr
*reg
= per_cpu_ptr(msrs
, cpu
);
2652 nbe
= reg
->l
& K8_MSR_MCGCTL_NBE
;
2654 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2656 (nbe
? "enabled" : "disabled"));
2664 free_cpumask_var(mask
);
2668 static int amd64_toggle_ecc_err_reporting(struct amd64_pvt
*pvt
, bool on
)
2670 cpumask_var_t cmask
;
2673 if (!zalloc_cpumask_var(&cmask
, GFP_KERNEL
)) {
2674 amd64_printk(KERN_WARNING
, "%s: error allocating mask\n",
2679 get_cpus_on_this_dct_cpumask(cmask
, pvt
->mc_node_id
);
2681 rdmsr_on_cpus(cmask
, MSR_IA32_MCG_CTL
, msrs
);
2683 for_each_cpu(cpu
, cmask
) {
2685 struct msr
*reg
= per_cpu_ptr(msrs
, cpu
);
2688 if (reg
->l
& K8_MSR_MCGCTL_NBE
)
2689 pvt
->flags
.ecc_report
= 1;
2691 reg
->l
|= K8_MSR_MCGCTL_NBE
;
2694 * Turn off ECC reporting only when it was off before
2696 if (!pvt
->flags
.ecc_report
)
2697 reg
->l
&= ~K8_MSR_MCGCTL_NBE
;
2700 wrmsr_on_cpus(cmask
, MSR_IA32_MCG_CTL
, msrs
);
2702 free_cpumask_var(cmask
);
2708 * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
2711 static void amd64_enable_ecc_error_reporting(struct mem_ctl_info
*mci
)
2713 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2715 u32 value
, mask
= K8_NBCTL_CECCEn
| K8_NBCTL_UECCEn
;
2717 if (!ecc_enable_override
)
2720 amd64_printk(KERN_WARNING
,
2721 "'ecc_enable_override' parameter is active, "
2722 "Enabling AMD ECC hardware now: CAUTION\n");
2724 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, &value
);
2726 debugf0("Reading K8_NBCTL failed\n");
2728 /* turn on UECCn and CECCEn bits */
2729 pvt
->old_nbctl
= value
& mask
;
2730 pvt
->nbctl_mcgctl_saved
= 1;
2733 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, value
);
2735 if (amd64_toggle_ecc_err_reporting(pvt
, ON
))
2736 amd64_printk(KERN_WARNING
, "Error enabling ECC reporting over "
2739 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2741 debugf0("Reading K8_NBCFG failed\n");
2743 debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value
,
2744 (value
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2745 (value
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled");
2747 if (!(value
& K8_NBCFG_ECC_ENABLE
)) {
2748 amd64_printk(KERN_WARNING
,
2749 "This node reports that DRAM ECC is "
2750 "currently Disabled; ENABLING now\n");
2752 /* Attempt to turn on DRAM ECC Enable */
2753 value
|= K8_NBCFG_ECC_ENABLE
;
2754 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, value
);
2756 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2758 debugf0("Reading K8_NBCFG failed\n");
2760 if (!(value
& K8_NBCFG_ECC_ENABLE
)) {
2761 amd64_printk(KERN_WARNING
,
2762 "Hardware rejects Enabling DRAM ECC checking\n"
2763 "Check memory DIMM configuration\n");
2765 amd64_printk(KERN_DEBUG
,
2766 "Hardware accepted DRAM ECC Enable\n");
2769 debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value
,
2770 (value
& K8_NBCFG_CHIPKILL
) ? "Enabled" : "Disabled",
2771 (value
& K8_NBCFG_ECC_ENABLE
) ? "Enabled" : "Disabled");
2773 pvt
->ctl_error_info
.nbcfg
= value
;
2776 static void amd64_restore_ecc_error_reporting(struct amd64_pvt
*pvt
)
2779 u32 value
, mask
= K8_NBCTL_CECCEn
| K8_NBCTL_UECCEn
;
2781 if (!pvt
->nbctl_mcgctl_saved
)
2784 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, &value
);
2786 debugf0("Reading K8_NBCTL failed\n");
2788 value
|= pvt
->old_nbctl
;
2790 /* restore the NB Enable MCGCTL bit */
2791 pci_write_config_dword(pvt
->misc_f3_ctl
, K8_NBCTL
, value
);
2793 if (amd64_toggle_ecc_err_reporting(pvt
, OFF
))
2794 amd64_printk(KERN_WARNING
, "Error restoring ECC reporting over "
2799 * EDAC requires that the BIOS have ECC enabled before taking over the
2800 * processing of ECC errors. This is because the BIOS can properly initialize
2801 * the memory system completely. A command line option allows to force-enable
2802 * hardware ECC later in amd64_enable_ecc_error_reporting().
2804 static const char *ecc_msg
=
2805 "ECC disabled in the BIOS or no ECC capability, module will not load.\n"
2806 " Either enable ECC checking or force module loading by setting "
2807 "'ecc_enable_override'.\n"
2808 " (Note that use of the override may cause unknown side effects.)\n";
2810 static int amd64_check_ecc_enabled(struct amd64_pvt
*pvt
)
2815 bool nb_mce_en
= false;
2817 err
= pci_read_config_dword(pvt
->misc_f3_ctl
, K8_NBCFG
, &value
);
2819 debugf0("Reading K8_NBCTL failed\n");
2821 ecc_enabled
= !!(value
& K8_NBCFG_ECC_ENABLE
);
2823 amd64_printk(KERN_NOTICE
, "This node reports that Memory ECC "
2824 "is currently disabled, set F3x%x[22] (%s).\n",
2825 K8_NBCFG
, pci_name(pvt
->misc_f3_ctl
));
2827 amd64_printk(KERN_INFO
, "ECC is enabled by BIOS.\n");
2829 nb_mce_en
= amd64_nb_mce_bank_enabled_on_node(pvt
->mc_node_id
);
2831 amd64_printk(KERN_NOTICE
, "NB MCE bank disabled, set MSR "
2832 "0x%08x[4] on node %d to enable.\n",
2833 MSR_IA32_MCG_CTL
, pvt
->mc_node_id
);
2835 if (!ecc_enabled
|| !nb_mce_en
) {
2836 if (!ecc_enable_override
) {
2837 amd64_printk(KERN_NOTICE
, "%s", ecc_msg
);
2840 ecc_enable_override
= 0;
2846 struct mcidev_sysfs_attribute sysfs_attrs
[ARRAY_SIZE(amd64_dbg_attrs
) +
2847 ARRAY_SIZE(amd64_inj_attrs
) +
2850 struct mcidev_sysfs_attribute terminator
= { .attr
= { .name
= NULL
} };
2852 static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info
*mci
)
2854 unsigned int i
= 0, j
= 0;
2856 for (; i
< ARRAY_SIZE(amd64_dbg_attrs
); i
++)
2857 sysfs_attrs
[i
] = amd64_dbg_attrs
[i
];
2859 for (j
= 0; j
< ARRAY_SIZE(amd64_inj_attrs
); j
++, i
++)
2860 sysfs_attrs
[i
] = amd64_inj_attrs
[j
];
2862 sysfs_attrs
[i
] = terminator
;
2864 mci
->mc_driver_sysfs_attributes
= sysfs_attrs
;
2867 static void amd64_setup_mci_misc_attributes(struct mem_ctl_info
*mci
)
2869 struct amd64_pvt
*pvt
= mci
->pvt_info
;
2871 mci
->mtype_cap
= MEM_FLAG_DDR2
| MEM_FLAG_RDDR2
;
2872 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
;
2874 if (pvt
->nbcap
& K8_NBCAP_SECDED
)
2875 mci
->edac_ctl_cap
|= EDAC_FLAG_SECDED
;
2877 if (pvt
->nbcap
& K8_NBCAP_CHIPKILL
)
2878 mci
->edac_ctl_cap
|= EDAC_FLAG_S4ECD4ED
;
2880 mci
->edac_cap
= amd64_determine_edac_cap(pvt
);
2881 mci
->mod_name
= EDAC_MOD_STR
;
2882 mci
->mod_ver
= EDAC_AMD64_VERSION
;
2883 mci
->ctl_name
= get_amd_family_name(pvt
->mc_type_index
);
2884 mci
->dev_name
= pci_name(pvt
->dram_f2_ctl
);
2885 mci
->ctl_page_to_phys
= NULL
;
2887 /* IMPORTANT: Set the polling 'check' function in this module */
2888 mci
->edac_check
= amd64_check
;
2890 /* memory scrubber interface */
2891 mci
->set_sdram_scrub_rate
= amd64_set_scrub_rate
;
2892 mci
->get_sdram_scrub_rate
= amd64_get_scrub_rate
;
2896 * Init stuff for this DRAM Controller device.
2898 * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration
2899 * Space feature MUST be enabled on ALL Processors prior to actually reading
2900 * from the ECS registers. Since the loading of the module can occur on any
2901 * 'core', and cores don't 'see' all the other processors ECS data when the
2902 * others are NOT enabled. Our solution is to first enable ECS access in this
2903 * routine on all processors, gather some data in a amd64_pvt structure and
2904 * later come back in a finish-setup function to perform that final
2905 * initialization. See also amd64_init_2nd_stage() for that.
2907 static int amd64_probe_one_instance(struct pci_dev
*dram_f2_ctl
,
2910 struct amd64_pvt
*pvt
= NULL
;
2914 pvt
= kzalloc(sizeof(struct amd64_pvt
), GFP_KERNEL
);
2918 pvt
->mc_node_id
= get_node_id(dram_f2_ctl
);
2920 pvt
->dram_f2_ctl
= dram_f2_ctl
;
2921 pvt
->ext_model
= boot_cpu_data
.x86_model
>> 4;
2922 pvt
->mc_type_index
= mc_type_index
;
2923 pvt
->ops
= family_ops(mc_type_index
);
2926 * We have the dram_f2_ctl device as an argument, now go reserve its
2927 * sibling devices from the PCI system.
2930 err
= amd64_reserve_mc_sibling_devices(pvt
, mc_type_index
);
2935 err
= amd64_check_ecc_enabled(pvt
);
2940 * Key operation here: setup of HW prior to performing ops on it. Some
2941 * setup is required to access ECS data. After this is performed, the
2942 * 'teardown' function must be called upon error and normal exit paths.
2944 if (boot_cpu_data
.x86
>= 0x10)
2948 * Save the pointer to the private data for use in 2nd initialization
2951 pvt_lookup
[pvt
->mc_node_id
] = pvt
;
2956 amd64_free_mc_sibling_devices(pvt
);
2966 * This is the finishing stage of the init code. Needs to be performed after all
2967 * MCs' hardware have been prepped for accessing extended config space.
2969 static int amd64_init_2nd_stage(struct amd64_pvt
*pvt
)
2971 int node_id
= pvt
->mc_node_id
;
2972 struct mem_ctl_info
*mci
;
2975 amd64_read_mc_registers(pvt
);
2978 if (pvt
->ops
->probe_valid_hardware
) {
2979 err
= pvt
->ops
->probe_valid_hardware(pvt
);
2985 * We need to determine how many memory channels there are. Then use
2986 * that information for calculating the size of the dynamic instance
2987 * tables in the 'mci' structure
2989 pvt
->channel_count
= pvt
->ops
->early_channel_count(pvt
);
2990 if (pvt
->channel_count
< 0)
2994 mci
= edac_mc_alloc(0, pvt
->cs_count
, pvt
->channel_count
, node_id
);
2998 mci
->pvt_info
= pvt
;
3000 mci
->dev
= &pvt
->dram_f2_ctl
->dev
;
3001 amd64_setup_mci_misc_attributes(mci
);
3003 if (amd64_init_csrows(mci
))
3004 mci
->edac_cap
= EDAC_FLAG_NONE
;
3006 amd64_enable_ecc_error_reporting(mci
);
3007 amd64_set_mc_sysfs_attributes(mci
);
3010 if (edac_mc_add_mc(mci
)) {
3011 debugf1("failed edac_mc_add_mc()\n");
3015 mci_lookup
[node_id
] = mci
;
3016 pvt_lookup
[node_id
] = NULL
;
3018 /* register stuff with EDAC MCE */
3019 if (report_gart_errors
)
3020 amd_report_gart_errors(true);
3022 amd_register_ecc_decoder(amd64_decode_bus_error
);
3030 debugf0("failure to init 2nd stage: ret=%d\n", ret
);
3032 amd64_restore_ecc_error_reporting(pvt
);
3034 if (boot_cpu_data
.x86
> 0xf)
3035 amd64_teardown(pvt
);
3037 amd64_free_mc_sibling_devices(pvt
);
3039 kfree(pvt_lookup
[pvt
->mc_node_id
]);
3040 pvt_lookup
[node_id
] = NULL
;
3046 static int __devinit
amd64_init_one_instance(struct pci_dev
*pdev
,
3047 const struct pci_device_id
*mc_type
)
3051 debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev
),
3052 get_amd_family_name(mc_type
->driver_data
));
3054 ret
= pci_enable_device(pdev
);
3058 ret
= amd64_probe_one_instance(pdev
, mc_type
->driver_data
);
3061 debugf0("ret=%d\n", ret
);
3066 static void __devexit
amd64_remove_one_instance(struct pci_dev
*pdev
)
3068 struct mem_ctl_info
*mci
;
3069 struct amd64_pvt
*pvt
;
3071 /* Remove from EDAC CORE tracking list */
3072 mci
= edac_mc_del_mc(&pdev
->dev
);
3076 pvt
= mci
->pvt_info
;
3078 amd64_restore_ecc_error_reporting(pvt
);
3080 if (boot_cpu_data
.x86
> 0xf)
3081 amd64_teardown(pvt
);
3083 amd64_free_mc_sibling_devices(pvt
);
3085 /* unregister from EDAC MCE */
3086 amd_report_gart_errors(false);
3087 amd_unregister_ecc_decoder(amd64_decode_bus_error
);
3089 /* Free the EDAC CORE resources */
3090 mci
->pvt_info
= NULL
;
3091 mci_lookup
[pvt
->mc_node_id
] = NULL
;
3098 * This table is part of the interface for loading drivers for PCI devices. The
3099 * PCI core identifies what devices are on a system during boot, and then
3100 * inquiry this table to see if this driver is for a given device found.
3102 static const struct pci_device_id amd64_pci_table
[] __devinitdata
= {
3104 .vendor
= PCI_VENDOR_ID_AMD
,
3105 .device
= PCI_DEVICE_ID_AMD_K8_NB_MEMCTL
,
3106 .subvendor
= PCI_ANY_ID
,
3107 .subdevice
= PCI_ANY_ID
,
3110 .driver_data
= K8_CPUS
3113 .vendor
= PCI_VENDOR_ID_AMD
,
3114 .device
= PCI_DEVICE_ID_AMD_10H_NB_DRAM
,
3115 .subvendor
= PCI_ANY_ID
,
3116 .subdevice
= PCI_ANY_ID
,
3119 .driver_data
= F10_CPUS
3122 .vendor
= PCI_VENDOR_ID_AMD
,
3123 .device
= PCI_DEVICE_ID_AMD_11H_NB_DRAM
,
3124 .subvendor
= PCI_ANY_ID
,
3125 .subdevice
= PCI_ANY_ID
,
3128 .driver_data
= F11_CPUS
3132 MODULE_DEVICE_TABLE(pci
, amd64_pci_table
);
3134 static struct pci_driver amd64_pci_driver
= {
3135 .name
= EDAC_MOD_STR
,
3136 .probe
= amd64_init_one_instance
,
3137 .remove
= __devexit_p(amd64_remove_one_instance
),
3138 .id_table
= amd64_pci_table
,
3141 static void amd64_setup_pci_device(void)
3143 struct mem_ctl_info
*mci
;
3144 struct amd64_pvt
*pvt
;
3149 mci
= mci_lookup
[0];
3152 pvt
= mci
->pvt_info
;
3154 edac_pci_create_generic_ctl(&pvt
->dram_f2_ctl
->dev
,
3157 if (!amd64_ctl_pci
) {
3158 pr_warning("%s(): Unable to create PCI control\n",
3161 pr_warning("%s(): PCI error report via EDAC not set\n",
3167 static int __init
amd64_edac_init(void)
3169 int nb
, err
= -ENODEV
;
3170 bool load_ok
= false;
3172 edac_printk(KERN_INFO
, EDAC_MOD_STR
, EDAC_AMD64_VERSION
"\n");
3176 if (cache_k8_northbridges() < 0)
3179 msrs
= msrs_alloc();
3183 err
= pci_register_driver(&amd64_pci_driver
);
3188 * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd
3189 * amd64_pvt structs. These will be used in the 2nd stage init function
3190 * to finish initialization of the MC instances.
3193 for (nb
= 0; nb
< num_k8_northbridges
; nb
++) {
3194 if (!pvt_lookup
[nb
])
3197 err
= amd64_init_2nd_stage(pvt_lookup
[nb
]);
3205 amd64_setup_pci_device();
3210 pci_unregister_driver(&amd64_pci_driver
);
3218 static void __exit
amd64_edac_exit(void)
3221 edac_pci_release_generic_ctl(amd64_ctl_pci
);
3223 pci_unregister_driver(&amd64_pci_driver
);
3229 module_init(amd64_edac_init
);
3230 module_exit(amd64_edac_exit
);
3232 MODULE_LICENSE("GPL");
3233 MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
3234 "Dave Peterson, Thayne Harbaugh");
3235 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
3236 EDAC_AMD64_VERSION
);
3238 module_param(edac_op_state
, int, 0444);
3239 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");