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cpuset: fix the problem that cpuset_mem_spread_node() returns an offline node
[linux-2.6/mini2440.git] / drivers / hwmon / dme1737.c
blob27d62574284fa14faefbaa754f53bdc0244bcbfc
1 /*
2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x and
3 * SCH5027 Super-I/O chips integrated hardware monitoring features.
4 * Copyright (c) 2007, 2008 Juerg Haefliger <juergh@gmail.com>
5 *
6 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
7 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
8 * if a SCH311x chip is found. Both types of chips have very similar hardware
9 * monitoring capabilities but differ in the way they can be accessed.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/slab.h>
29 #include <linux/jiffies.h>
30 #include <linux/i2c.h>
31 #include <linux/platform_device.h>
32 #include <linux/hwmon.h>
33 #include <linux/hwmon-sysfs.h>
34 #include <linux/hwmon-vid.h>
35 #include <linux/err.h>
36 #include <linux/mutex.h>
37 #include <linux/acpi.h>
38 #include <linux/io.h>
39
40 /* ISA device, if found */
41 static struct platform_device *pdev;
42
43 /* Module load parameters */
44 static int force_start;
45 module_param(force_start, bool, 0);
46 MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
47
48 static unsigned short force_id;
49 module_param(force_id, ushort, 0);
50 MODULE_PARM_DESC(force_id, "Override the detected device ID");
51
52 static int probe_all_addr;
53 module_param(probe_all_addr, bool, 0);
54 MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC "
55 "addresses");
56
57 /* Addresses to scan */
58 static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
59
60 /* Insmod parameters */
61 I2C_CLIENT_INSMOD_2(dme1737, sch5027);
62
63 /* ISA chip types */
64 enum isa_chips { sch311x = sch5027 + 1 };
65
66 /* ---------------------------------------------------------------------
67 * Registers
68 *
69 * The sensors are defined as follows:
70 *
71 * Voltages Temperatures
72 * -------- ------------
73 * in0 +5VTR (+5V stdby) temp1 Remote diode 1
74 * in1 Vccp (proc core) temp2 Internal temp
75 * in2 VCC (internal +3.3V) temp3 Remote diode 2
76 * in3 +5V
77 * in4 +12V
78 * in5 VTR (+3.3V stby)
79 * in6 Vbat
80 *
81 * --------------------------------------------------------------------- */
82
83 /* Voltages (in) numbered 0-6 (ix) */
84 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) \
85 : 0x94 + (ix))
86 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
87 : 0x91 + (ix) * 2)
88 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
89 : 0x92 + (ix) * 2)
90
91 /* Temperatures (temp) numbered 0-2 (ix) */
92 #define DME1737_REG_TEMP(ix) (0x25 + (ix))
93 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
94 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
95 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
96 : 0x1c + (ix))
97
98 /* Voltage and temperature LSBs
99 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
100 * IN_TEMP_LSB(0) = [in5, in6]
101 * IN_TEMP_LSB(1) = [temp3, temp1]
102 * IN_TEMP_LSB(2) = [in4, temp2]
103 * IN_TEMP_LSB(3) = [in3, in0]
104 * IN_TEMP_LSB(4) = [in2, in1] */
105 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
106 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0};
107 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4};
108 static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
109 static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
110
111 /* Fans numbered 0-5 (ix) */
112 #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
113 : 0xa1 + (ix) * 2)
114 #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
115 : 0xa5 + (ix) * 2)
116 #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
117 : 0xb2 + (ix))
118 #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
119
120 /* PWMs numbered 0-2, 4-5 (ix) */
121 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
122 : 0xa1 + (ix))
123 #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
124 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
125 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
126 : 0xa3 + (ix))
127 /* The layout of the ramp rate registers is different from the other pwm
128 * registers. The bits for the 3 PWMs are stored in 2 registers:
129 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
130 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */
131 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
132
133 /* Thermal zones 0-2 */
134 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
135 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
136 /* The layout of the hysteresis registers is different from the other zone
137 * registers. The bits for the 3 zones are stored in 2 registers:
138 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
139 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */
140 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
141
142 /* Alarm registers and bit mapping
143 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
144 * alarm value [0, ALARM3, ALARM2, ALARM1]. */
145 #define DME1737_REG_ALARM1 0x41
146 #define DME1737_REG_ALARM2 0x42
147 #define DME1737_REG_ALARM3 0x83
148 static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17};
149 static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
150 static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
151
152 /* Miscellaneous registers */
153 #define DME1737_REG_DEVICE 0x3d
154 #define DME1737_REG_COMPANY 0x3e
155 #define DME1737_REG_VERSTEP 0x3f
156 #define DME1737_REG_CONFIG 0x40
157 #define DME1737_REG_CONFIG2 0x7f
158 #define DME1737_REG_VID 0x43
159 #define DME1737_REG_TACH_PWM 0x81
160
161 /* ---------------------------------------------------------------------
162 * Misc defines
163 * --------------------------------------------------------------------- */
164
165 /* Chip identification */
166 #define DME1737_COMPANY_SMSC 0x5c
167 #define DME1737_VERSTEP 0x88
168 #define DME1737_VERSTEP_MASK 0xf8
169 #define SCH311X_DEVICE 0x8c
170 #define SCH5027_VERSTEP 0x69
171
172 /* Length of ISA address segment */
173 #define DME1737_EXTENT 2
174
175 /* ---------------------------------------------------------------------
176 * Data structures and manipulation thereof
177 * --------------------------------------------------------------------- */
178
179 struct dme1737_data {
180 struct i2c_client *client; /* for I2C devices only */
181 struct device *hwmon_dev;
182 const char *name;
183 unsigned int addr; /* for ISA devices only */
184
185 struct mutex update_lock;
186 int valid; /* !=0 if following fields are valid */
187 unsigned long last_update; /* in jiffies */
188 unsigned long last_vbat; /* in jiffies */
189 enum chips type;
190 const int *in_nominal; /* pointer to IN_NOMINAL array */
191
192 u8 vid;
193 u8 pwm_rr_en;
194 u8 has_pwm;
195 u8 has_fan;
196
197 /* Register values */
198 u16 in[7];
199 u8 in_min[7];
200 u8 in_max[7];
201 s16 temp[3];
202 s8 temp_min[3];
203 s8 temp_max[3];
204 s8 temp_offset[3];
205 u8 config;
206 u8 config2;
207 u8 vrm;
208 u16 fan[6];
209 u16 fan_min[6];
210 u8 fan_max[2];
211 u8 fan_opt[6];
212 u8 pwm[6];
213 u8 pwm_min[3];
214 u8 pwm_config[3];
215 u8 pwm_acz[3];
216 u8 pwm_freq[6];
217 u8 pwm_rr[2];
218 u8 zone_low[3];
219 u8 zone_abs[3];
220 u8 zone_hyst[2];
221 u32 alarms;
222 };
223
224 /* Nominal voltage values */
225 static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
226 3300};
227 static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
228 3300};
229 static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
230 3300};
231 #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
232 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
233 IN_NOMINAL_DME1737)
234
235 /* Voltage input
236 * Voltage inputs have 16 bits resolution, limit values have 8 bits
237 * resolution. */
238 static inline int IN_FROM_REG(int reg, int nominal, int res)
239 {
240 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
241 }
242
243 static inline int IN_TO_REG(int val, int nominal)
244 {
245 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255);
246 }
247
248 /* Temperature input
249 * The register values represent temperatures in 2's complement notation from
250 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
251 * values have 8 bits resolution. */
252 static inline int TEMP_FROM_REG(int reg, int res)
253 {
254 return (reg * 1000) >> (res - 8);
255 }
256
257 static inline int TEMP_TO_REG(int val)
258 {
259 return SENSORS_LIMIT((val < 0 ? val - 500 : val + 500) / 1000,
260 -128, 127);
261 }
262
263 /* Temperature range */
264 static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
265 10000, 13333, 16000, 20000, 26666, 32000,
266 40000, 53333, 80000};
267
268 static inline int TEMP_RANGE_FROM_REG(int reg)
269 {
270 return TEMP_RANGE[(reg >> 4) & 0x0f];
271 }
272
273 static int TEMP_RANGE_TO_REG(int val, int reg)
274 {
275 int i;
276
277 for (i = 15; i > 0; i--) {
278 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) {
279 break;
280 }
281 }
282
283 return (reg & 0x0f) | (i << 4);
284 }
285
286 /* Temperature hysteresis
287 * Register layout:
288 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
289 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] */
290 static inline int TEMP_HYST_FROM_REG(int reg, int ix)
291 {
292 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
293 }
294
295 static inline int TEMP_HYST_TO_REG(int val, int ix, int reg)
296 {
297 int hyst = SENSORS_LIMIT((val + 500) / 1000, 0, 15);
298
299 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
300 }
301
302 /* Fan input RPM */
303 static inline int FAN_FROM_REG(int reg, int tpc)
304 {
305 if (tpc) {
306 return tpc * reg;
307 } else {
308 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
309 }
310 }
311
312 static inline int FAN_TO_REG(int val, int tpc)
313 {
314 if (tpc) {
315 return SENSORS_LIMIT(val / tpc, 0, 0xffff);
316 } else {
317 return (val <= 0) ? 0xffff :
318 SENSORS_LIMIT(90000 * 60 / val, 0, 0xfffe);
319 }
320 }
321
322 /* Fan TPC (tach pulse count)
323 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
324 * is configured in legacy (non-tpc) mode */
325 static inline int FAN_TPC_FROM_REG(int reg)
326 {
327 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
328 }
329
330 /* Fan type
331 * The type of a fan is expressed in number of pulses-per-revolution that it
332 * emits */
333 static inline int FAN_TYPE_FROM_REG(int reg)
334 {
335 int edge = (reg >> 1) & 0x03;
336
337 return (edge > 0) ? 1 << (edge - 1) : 0;
338 }
339
340 static inline int FAN_TYPE_TO_REG(int val, int reg)
341 {
342 int edge = (val == 4) ? 3 : val;
343
344 return (reg & 0xf9) | (edge << 1);
345 }
346
347 /* Fan max RPM */
348 static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
349 0x11, 0x0f, 0x0e};
350
351 static int FAN_MAX_FROM_REG(int reg)
352 {
353 int i;
354
355 for (i = 10; i > 0; i--) {
356 if (reg == FAN_MAX[i]) {
357 break;
358 }
359 }
360
361 return 1000 + i * 500;
362 }
363
364 static int FAN_MAX_TO_REG(int val)
365 {
366 int i;
367
368 for (i = 10; i > 0; i--) {
369 if (val > (1000 + (i - 1) * 500)) {
370 break;
371 }
372 }
373
374 return FAN_MAX[i];
375 }
376
377 /* PWM enable
378 * Register to enable mapping:
379 * 000: 2 fan on zone 1 auto
380 * 001: 2 fan on zone 2 auto
381 * 010: 2 fan on zone 3 auto
382 * 011: 0 fan full on
383 * 100: -1 fan disabled
384 * 101: 2 fan on hottest of zones 2,3 auto
385 * 110: 2 fan on hottest of zones 1,2,3 auto
386 * 111: 1 fan in manual mode */
387 static inline int PWM_EN_FROM_REG(int reg)
388 {
389 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
390
391 return en[(reg >> 5) & 0x07];
392 }
393
394 static inline int PWM_EN_TO_REG(int val, int reg)
395 {
396 int en = (val == 1) ? 7 : 3;
397
398 return (reg & 0x1f) | ((en & 0x07) << 5);
399 }
400
401 /* PWM auto channels zone
402 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
403 * corresponding to zone x+1):
404 * 000: 001 fan on zone 1 auto
405 * 001: 010 fan on zone 2 auto
406 * 010: 100 fan on zone 3 auto
407 * 011: 000 fan full on
408 * 100: 000 fan disabled
409 * 101: 110 fan on hottest of zones 2,3 auto
410 * 110: 111 fan on hottest of zones 1,2,3 auto
411 * 111: 000 fan in manual mode */
412 static inline int PWM_ACZ_FROM_REG(int reg)
413 {
414 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
415
416 return acz[(reg >> 5) & 0x07];
417 }
418
419 static inline int PWM_ACZ_TO_REG(int val, int reg)
420 {
421 int acz = (val == 4) ? 2 : val - 1;
422
423 return (reg & 0x1f) | ((acz & 0x07) << 5);
424 }
425
426 /* PWM frequency */
427 static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
428 15000, 20000, 30000, 25000, 0, 0, 0, 0};
429
430 static inline int PWM_FREQ_FROM_REG(int reg)
431 {
432 return PWM_FREQ[reg & 0x0f];
433 }
434
435 static int PWM_FREQ_TO_REG(int val, int reg)
436 {
437 int i;
438
439 /* the first two cases are special - stupid chip design! */
440 if (val > 27500) {
441 i = 10;
442 } else if (val > 22500) {
443 i = 11;
444 } else {
445 for (i = 9; i > 0; i--) {
446 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) {
447 break;
448 }
449 }
450 }
451
452 return (reg & 0xf0) | i;
453 }
454
455 /* PWM ramp rate
456 * Register layout:
457 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
458 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */
459 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
460
461 static inline int PWM_RR_FROM_REG(int reg, int ix)
462 {
463 int rr = (ix == 1) ? reg >> 4 : reg;
464
465 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
466 }
467
468 static int PWM_RR_TO_REG(int val, int ix, int reg)
469 {
470 int i;
471
472 for (i = 0; i < 7; i++) {
473 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) {
474 break;
475 }
476 }
477
478 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
479 }
480
481 /* PWM ramp rate enable */
482 static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
483 {
484 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
485 }
486
487 static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg)
488 {
489 int en = (ix == 1) ? 0x80 : 0x08;
490
491 return val ? reg | en : reg & ~en;
492 }
493
494 /* PWM min/off
495 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
496 * the register layout). */
497 static inline int PWM_OFF_FROM_REG(int reg, int ix)
498 {
499 return (reg >> (ix + 5)) & 0x01;
500 }
501
502 static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
503 {
504 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
505 }
506
507 /* ---------------------------------------------------------------------
508 * Device I/O access
509 *
510 * ISA access is performed through an index/data register pair and needs to
511 * be protected by a mutex during runtime (not required for initialization).
512 * We use data->update_lock for this and need to ensure that we acquire it
513 * before calling dme1737_read or dme1737_write.
514 * --------------------------------------------------------------------- */
515
516 static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
517 {
518 struct i2c_client *client = data->client;
519 s32 val;
520
521 if (client) { /* I2C device */
522 val = i2c_smbus_read_byte_data(client, reg);
523
524 if (val < 0) {
525 dev_warn(&client->dev, "Read from register "
526 "0x%02x failed! Please report to the driver "
527 "maintainer.\n", reg);
528 }
529 } else { /* ISA device */
530 outb(reg, data->addr);
531 val = inb(data->addr + 1);
532 }
533
534 return val;
535 }
536
537 static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
538 {
539 struct i2c_client *client = data->client;
540 s32 res = 0;
541
542 if (client) { /* I2C device */
543 res = i2c_smbus_write_byte_data(client, reg, val);
544
545 if (res < 0) {
546 dev_warn(&client->dev, "Write to register "
547 "0x%02x failed! Please report to the driver "
548 "maintainer.\n", reg);
549 }
550 } else { /* ISA device */
551 outb(reg, data->addr);
552 outb(val, data->addr + 1);
553 }
554
555 return res;
556 }
557
558 static struct dme1737_data *dme1737_update_device(struct device *dev)
559 {
560 struct dme1737_data *data = dev_get_drvdata(dev);
561 int ix;
562 u8 lsb[5];
563
564 mutex_lock(&data->update_lock);
565
566 /* Enable a Vbat monitoring cycle every 10 mins */
567 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
568 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
569 DME1737_REG_CONFIG) | 0x10);
570 data->last_vbat = jiffies;
571 }
572
573 /* Sample register contents every 1 sec */
574 if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
575 if (data->type == dme1737) {
576 data->vid = dme1737_read(data, DME1737_REG_VID) &
577 0x3f;
578 }
579
580 /* In (voltage) registers */
581 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
582 /* Voltage inputs are stored as 16 bit values even
583 * though they have only 12 bits resolution. This is
584 * to make it consistent with the temp inputs. */
585 data->in[ix] = dme1737_read(data,
586 DME1737_REG_IN(ix)) << 8;
587 data->in_min[ix] = dme1737_read(data,
588 DME1737_REG_IN_MIN(ix));
589 data->in_max[ix] = dme1737_read(data,
590 DME1737_REG_IN_MAX(ix));
591 }
592
593 /* Temp registers */
594 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
595 /* Temp inputs are stored as 16 bit values even
596 * though they have only 12 bits resolution. This is
597 * to take advantage of implicit conversions between
598 * register values (2's complement) and temp values
599 * (signed decimal). */
600 data->temp[ix] = dme1737_read(data,
601 DME1737_REG_TEMP(ix)) << 8;
602 data->temp_min[ix] = dme1737_read(data,
603 DME1737_REG_TEMP_MIN(ix));
604 data->temp_max[ix] = dme1737_read(data,
605 DME1737_REG_TEMP_MAX(ix));
606 if (data->type != sch5027) {
607 data->temp_offset[ix] = dme1737_read(data,
608 DME1737_REG_TEMP_OFFSET(ix));
609 }
610 }
611
612 /* In and temp LSB registers
613 * The LSBs are latched when the MSBs are read, so the order in
614 * which the registers are read (MSB first, then LSB) is
615 * important! */
616 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
617 lsb[ix] = dme1737_read(data,
618 DME1737_REG_IN_TEMP_LSB(ix));
619 }
620 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
621 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
622 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
623 }
624 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
625 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
626 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
627 }
628
629 /* Fan registers */
630 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
631 /* Skip reading registers if optional fans are not
632 * present */
633 if (!(data->has_fan & (1 << ix))) {
634 continue;
635 }
636 data->fan[ix] = dme1737_read(data,
637 DME1737_REG_FAN(ix));
638 data->fan[ix] |= dme1737_read(data,
639 DME1737_REG_FAN(ix) + 1) << 8;
640 data->fan_min[ix] = dme1737_read(data,
641 DME1737_REG_FAN_MIN(ix));
642 data->fan_min[ix] |= dme1737_read(data,
643 DME1737_REG_FAN_MIN(ix) + 1) << 8;
644 data->fan_opt[ix] = dme1737_read(data,
645 DME1737_REG_FAN_OPT(ix));
646 /* fan_max exists only for fan[5-6] */
647 if (ix > 3) {
648 data->fan_max[ix - 4] = dme1737_read(data,
649 DME1737_REG_FAN_MAX(ix));
650 }
651 }
652
653 /* PWM registers */
654 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
655 /* Skip reading registers if optional PWMs are not
656 * present */
657 if (!(data->has_pwm & (1 << ix))) {
658 continue;
659 }
660 data->pwm[ix] = dme1737_read(data,
661 DME1737_REG_PWM(ix));
662 data->pwm_freq[ix] = dme1737_read(data,
663 DME1737_REG_PWM_FREQ(ix));
664 /* pwm_config and pwm_min exist only for pwm[1-3] */
665 if (ix < 3) {
666 data->pwm_config[ix] = dme1737_read(data,
667 DME1737_REG_PWM_CONFIG(ix));
668 data->pwm_min[ix] = dme1737_read(data,
669 DME1737_REG_PWM_MIN(ix));
670 }
671 }
672 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
673 data->pwm_rr[ix] = dme1737_read(data,
674 DME1737_REG_PWM_RR(ix));
675 }
676
677 /* Thermal zone registers */
678 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
679 data->zone_low[ix] = dme1737_read(data,
680 DME1737_REG_ZONE_LOW(ix));
681 data->zone_abs[ix] = dme1737_read(data,
682 DME1737_REG_ZONE_ABS(ix));
683 }
684 if (data->type != sch5027) {
685 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
686 data->zone_hyst[ix] = dme1737_read(data,
687 DME1737_REG_ZONE_HYST(ix));
688 }
689 }
690
691 /* Alarm registers */
692 data->alarms = dme1737_read(data,
693 DME1737_REG_ALARM1);
694 /* Bit 7 tells us if the other alarm registers are non-zero and
695 * therefore also need to be read */
696 if (data->alarms & 0x80) {
697 data->alarms |= dme1737_read(data,
698 DME1737_REG_ALARM2) << 8;
699 data->alarms |= dme1737_read(data,
700 DME1737_REG_ALARM3) << 16;
701 }
702
703 /* The ISA chips require explicit clearing of alarm bits.
704 * Don't worry, an alarm will come back if the condition
705 * that causes it still exists */
706 if (!data->client) {
707 if (data->alarms & 0xff0000) {
708 dme1737_write(data, DME1737_REG_ALARM3,
709 0xff);
710 }
711 if (data->alarms & 0xff00) {
712 dme1737_write(data, DME1737_REG_ALARM2,
713 0xff);
714 }
715 if (data->alarms & 0xff) {
716 dme1737_write(data, DME1737_REG_ALARM1,
717 0xff);
718 }
719 }
720
721 data->last_update = jiffies;
722 data->valid = 1;
723 }
724
725 mutex_unlock(&data->update_lock);
726
727 return data;
728 }
729
730 /* ---------------------------------------------------------------------
731 * Voltage sysfs attributes
732 * ix = [0-5]
733 * --------------------------------------------------------------------- */
734
735 #define SYS_IN_INPUT 0
736 #define SYS_IN_MIN 1
737 #define SYS_IN_MAX 2
738 #define SYS_IN_ALARM 3
739
740 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
741 char *buf)
742 {
743 struct dme1737_data *data = dme1737_update_device(dev);
744 struct sensor_device_attribute_2
745 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
746 int ix = sensor_attr_2->index;
747 int fn = sensor_attr_2->nr;
748 int res;
749
750 switch (fn) {
751 case SYS_IN_INPUT:
752 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
753 break;
754 case SYS_IN_MIN:
755 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
756 break;
757 case SYS_IN_MAX:
758 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
759 break;
760 case SYS_IN_ALARM:
761 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
762 break;
763 default:
764 res = 0;
765 dev_dbg(dev, "Unknown function %d.\n", fn);
766 }
767
768 return sprintf(buf, "%d\n", res);
769 }
770
771 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
772 const char *buf, size_t count)
773 {
774 struct dme1737_data *data = dev_get_drvdata(dev);
775 struct sensor_device_attribute_2
776 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
777 int ix = sensor_attr_2->index;
778 int fn = sensor_attr_2->nr;
779 long val = simple_strtol(buf, NULL, 10);
780
781 mutex_lock(&data->update_lock);
782 switch (fn) {
783 case SYS_IN_MIN:
784 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
785 dme1737_write(data, DME1737_REG_IN_MIN(ix),
786 data->in_min[ix]);
787 break;
788 case SYS_IN_MAX:
789 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
790 dme1737_write(data, DME1737_REG_IN_MAX(ix),
791 data->in_max[ix]);
792 break;
793 default:
794 dev_dbg(dev, "Unknown function %d.\n", fn);
795 }
796 mutex_unlock(&data->update_lock);
797
798 return count;
799 }
800
801 /* ---------------------------------------------------------------------
802 * Temperature sysfs attributes
803 * ix = [0-2]
804 * --------------------------------------------------------------------- */
805
806 #define SYS_TEMP_INPUT 0
807 #define SYS_TEMP_MIN 1
808 #define SYS_TEMP_MAX 2
809 #define SYS_TEMP_OFFSET 3
810 #define SYS_TEMP_ALARM 4
811 #define SYS_TEMP_FAULT 5
812
813 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
814 char *buf)
815 {
816 struct dme1737_data *data = dme1737_update_device(dev);
817 struct sensor_device_attribute_2
818 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
819 int ix = sensor_attr_2->index;
820 int fn = sensor_attr_2->nr;
821 int res;
822
823 switch (fn) {
824 case SYS_TEMP_INPUT:
825 res = TEMP_FROM_REG(data->temp[ix], 16);
826 break;
827 case SYS_TEMP_MIN:
828 res = TEMP_FROM_REG(data->temp_min[ix], 8);
829 break;
830 case SYS_TEMP_MAX:
831 res = TEMP_FROM_REG(data->temp_max[ix], 8);
832 break;
833 case SYS_TEMP_OFFSET:
834 res = TEMP_FROM_REG(data->temp_offset[ix], 8);
835 break;
836 case SYS_TEMP_ALARM:
837 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
838 break;
839 case SYS_TEMP_FAULT:
840 res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
841 break;
842 default:
843 res = 0;
844 dev_dbg(dev, "Unknown function %d.\n", fn);
845 }
846
847 return sprintf(buf, "%d\n", res);
848 }
849
850 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
851 const char *buf, size_t count)
852 {
853 struct dme1737_data *data = dev_get_drvdata(dev);
854 struct sensor_device_attribute_2
855 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
856 int ix = sensor_attr_2->index;
857 int fn = sensor_attr_2->nr;
858 long val = simple_strtol(buf, NULL, 10);
859
860 mutex_lock(&data->update_lock);
861 switch (fn) {
862 case SYS_TEMP_MIN:
863 data->temp_min[ix] = TEMP_TO_REG(val);
864 dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
865 data->temp_min[ix]);
866 break;
867 case SYS_TEMP_MAX:
868 data->temp_max[ix] = TEMP_TO_REG(val);
869 dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
870 data->temp_max[ix]);
871 break;
872 case SYS_TEMP_OFFSET:
873 data->temp_offset[ix] = TEMP_TO_REG(val);
874 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
875 data->temp_offset[ix]);
876 break;
877 default:
878 dev_dbg(dev, "Unknown function %d.\n", fn);
879 }
880 mutex_unlock(&data->update_lock);
881
882 return count;
883 }
884
885 /* ---------------------------------------------------------------------
886 * Zone sysfs attributes
887 * ix = [0-2]
888 * --------------------------------------------------------------------- */
889
890 #define SYS_ZONE_AUTO_CHANNELS_TEMP 0
891 #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
892 #define SYS_ZONE_AUTO_POINT1_TEMP 2
893 #define SYS_ZONE_AUTO_POINT2_TEMP 3
894 #define SYS_ZONE_AUTO_POINT3_TEMP 4
895
896 static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
897 char *buf)
898 {
899 struct dme1737_data *data = dme1737_update_device(dev);
900 struct sensor_device_attribute_2
901 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
902 int ix = sensor_attr_2->index;
903 int fn = sensor_attr_2->nr;
904 int res;
905
906 switch (fn) {
907 case SYS_ZONE_AUTO_CHANNELS_TEMP:
908 /* check config2 for non-standard temp-to-zone mapping */
909 if ((ix == 1) && (data->config2 & 0x02)) {
910 res = 4;
911 } else {
912 res = 1 << ix;
913 }
914 break;
915 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
916 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
917 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
918 break;
919 case SYS_ZONE_AUTO_POINT1_TEMP:
920 res = TEMP_FROM_REG(data->zone_low[ix], 8);
921 break;
922 case SYS_ZONE_AUTO_POINT2_TEMP:
923 /* pwm_freq holds the temp range bits in the upper nibble */
924 res = TEMP_FROM_REG(data->zone_low[ix], 8) +
925 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
926 break;
927 case SYS_ZONE_AUTO_POINT3_TEMP:
928 res = TEMP_FROM_REG(data->zone_abs[ix], 8);
929 break;
930 default:
931 res = 0;
932 dev_dbg(dev, "Unknown function %d.\n", fn);
933 }
934
935 return sprintf(buf, "%d\n", res);
936 }
937
938 static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
939 const char *buf, size_t count)
940 {
941 struct dme1737_data *data = dev_get_drvdata(dev);
942 struct sensor_device_attribute_2
943 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
944 int ix = sensor_attr_2->index;
945 int fn = sensor_attr_2->nr;
946 long val = simple_strtol(buf, NULL, 10);
947
948 mutex_lock(&data->update_lock);
949 switch (fn) {
950 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
951 /* Refresh the cache */
952 data->zone_low[ix] = dme1737_read(data,
953 DME1737_REG_ZONE_LOW(ix));
954 /* Modify the temp hyst value */
955 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(
956 TEMP_FROM_REG(data->zone_low[ix], 8) -
957 val, ix, dme1737_read(data,
958 DME1737_REG_ZONE_HYST(ix == 2)));
959 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
960 data->zone_hyst[ix == 2]);
961 break;
962 case SYS_ZONE_AUTO_POINT1_TEMP:
963 data->zone_low[ix] = TEMP_TO_REG(val);
964 dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
965 data->zone_low[ix]);
966 break;
967 case SYS_ZONE_AUTO_POINT2_TEMP:
968 /* Refresh the cache */
969 data->zone_low[ix] = dme1737_read(data,
970 DME1737_REG_ZONE_LOW(ix));
971 /* Modify the temp range value (which is stored in the upper
972 * nibble of the pwm_freq register) */
973 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
974 TEMP_FROM_REG(data->zone_low[ix], 8),
975 dme1737_read(data,
976 DME1737_REG_PWM_FREQ(ix)));
977 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
978 data->pwm_freq[ix]);
979 break;
980 case SYS_ZONE_AUTO_POINT3_TEMP:
981 data->zone_abs[ix] = TEMP_TO_REG(val);
982 dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
983 data->zone_abs[ix]);
984 break;
985 default:
986 dev_dbg(dev, "Unknown function %d.\n", fn);
987 }
988 mutex_unlock(&data->update_lock);
989
990 return count;
991 }
992
993 /* ---------------------------------------------------------------------
994 * Fan sysfs attributes
995 * ix = [0-5]
996 * --------------------------------------------------------------------- */
997
998 #define SYS_FAN_INPUT 0
999 #define SYS_FAN_MIN 1
1000 #define SYS_FAN_MAX 2
1001 #define SYS_FAN_ALARM 3
1002 #define SYS_FAN_TYPE 4
1003
1004 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1005 char *buf)
1006 {
1007 struct dme1737_data *data = dme1737_update_device(dev);
1008 struct sensor_device_attribute_2
1009 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1010 int ix = sensor_attr_2->index;
1011 int fn = sensor_attr_2->nr;
1012 int res;
1013
1014 switch (fn) {
1015 case SYS_FAN_INPUT:
1016 res = FAN_FROM_REG(data->fan[ix],
1017 ix < 4 ? 0 :
1018 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1019 break;
1020 case SYS_FAN_MIN:
1021 res = FAN_FROM_REG(data->fan_min[ix],
1022 ix < 4 ? 0 :
1023 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1024 break;
1025 case SYS_FAN_MAX:
1026 /* only valid for fan[5-6] */
1027 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
1028 break;
1029 case SYS_FAN_ALARM:
1030 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
1031 break;
1032 case SYS_FAN_TYPE:
1033 /* only valid for fan[1-4] */
1034 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
1035 break;
1036 default:
1037 res = 0;
1038 dev_dbg(dev, "Unknown function %d.\n", fn);
1039 }
1040
1041 return sprintf(buf, "%d\n", res);
1042 }
1043
1044 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1045 const char *buf, size_t count)
1046 {
1047 struct dme1737_data *data = dev_get_drvdata(dev);
1048 struct sensor_device_attribute_2
1049 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1050 int ix = sensor_attr_2->index;
1051 int fn = sensor_attr_2->nr;
1052 long val = simple_strtol(buf, NULL, 10);
1053
1054 mutex_lock(&data->update_lock);
1055 switch (fn) {
1056 case SYS_FAN_MIN:
1057 if (ix < 4) {
1058 data->fan_min[ix] = FAN_TO_REG(val, 0);
1059 } else {
1060 /* Refresh the cache */
1061 data->fan_opt[ix] = dme1737_read(data,
1062 DME1737_REG_FAN_OPT(ix));
1063 /* Modify the fan min value */
1064 data->fan_min[ix] = FAN_TO_REG(val,
1065 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1066 }
1067 dme1737_write(data, DME1737_REG_FAN_MIN(ix),
1068 data->fan_min[ix] & 0xff);
1069 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
1070 data->fan_min[ix] >> 8);
1071 break;
1072 case SYS_FAN_MAX:
1073 /* Only valid for fan[5-6] */
1074 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
1075 dme1737_write(data, DME1737_REG_FAN_MAX(ix),
1076 data->fan_max[ix - 4]);
1077 break;
1078 case SYS_FAN_TYPE:
1079 /* Only valid for fan[1-4] */
1080 if (!(val == 1 || val == 2 || val == 4)) {
1081 count = -EINVAL;
1082 dev_warn(dev, "Fan type value %ld not "
1083 "supported. Choose one of 1, 2, or 4.\n",
1084 val);
1085 goto exit;
1086 }
1087 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
1088 DME1737_REG_FAN_OPT(ix)));
1089 dme1737_write(data, DME1737_REG_FAN_OPT(ix),
1090 data->fan_opt[ix]);
1091 break;
1092 default:
1093 dev_dbg(dev, "Unknown function %d.\n", fn);
1094 }
1095 exit:
1096 mutex_unlock(&data->update_lock);
1097
1098 return count;
1099 }
1100
1101 /* ---------------------------------------------------------------------
1102 * PWM sysfs attributes
1103 * ix = [0-4]
1104 * --------------------------------------------------------------------- */
1105
1106 #define SYS_PWM 0
1107 #define SYS_PWM_FREQ 1
1108 #define SYS_PWM_ENABLE 2
1109 #define SYS_PWM_RAMP_RATE 3
1110 #define SYS_PWM_AUTO_CHANNELS_ZONE 4
1111 #define SYS_PWM_AUTO_PWM_MIN 5
1112 #define SYS_PWM_AUTO_POINT1_PWM 6
1113 #define SYS_PWM_AUTO_POINT2_PWM 7
1114
1115 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1116 char *buf)
1117 {
1118 struct dme1737_data *data = dme1737_update_device(dev);
1119 struct sensor_device_attribute_2
1120 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1121 int ix = sensor_attr_2->index;
1122 int fn = sensor_attr_2->nr;
1123 int res;
1124
1125 switch (fn) {
1126 case SYS_PWM:
1127 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) {
1128 res = 255;
1129 } else {
1130 res = data->pwm[ix];
1131 }
1132 break;
1133 case SYS_PWM_FREQ:
1134 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1135 break;
1136 case SYS_PWM_ENABLE:
1137 if (ix >= 3) {
1138 res = 1; /* pwm[5-6] hard-wired to manual mode */
1139 } else {
1140 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
1141 }
1142 break;
1143 case SYS_PWM_RAMP_RATE:
1144 /* Only valid for pwm[1-3] */
1145 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
1146 break;
1147 case SYS_PWM_AUTO_CHANNELS_ZONE:
1148 /* Only valid for pwm[1-3] */
1149 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1150 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
1151 } else {
1152 res = data->pwm_acz[ix];
1153 }
1154 break;
1155 case SYS_PWM_AUTO_PWM_MIN:
1156 /* Only valid for pwm[1-3] */
1157 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) {
1158 res = data->pwm_min[ix];
1159 } else {
1160 res = 0;
1161 }
1162 break;
1163 case SYS_PWM_AUTO_POINT1_PWM:
1164 /* Only valid for pwm[1-3] */
1165 res = data->pwm_min[ix];
1166 break;
1167 case SYS_PWM_AUTO_POINT2_PWM:
1168 /* Only valid for pwm[1-3] */
1169 res = 255; /* hard-wired */
1170 break;
1171 default:
1172 res = 0;
1173 dev_dbg(dev, "Unknown function %d.\n", fn);
1174 }
1175
1176 return sprintf(buf, "%d\n", res);
1177 }
1178
1179 static struct attribute *dme1737_pwm_chmod_attr[];
1180 static void dme1737_chmod_file(struct device*, struct attribute*, mode_t);
1181
1182 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1183 const char *buf, size_t count)
1184 {
1185 struct dme1737_data *data = dev_get_drvdata(dev);
1186 struct sensor_device_attribute_2
1187 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1188 int ix = sensor_attr_2->index;
1189 int fn = sensor_attr_2->nr;
1190 long val = simple_strtol(buf, NULL, 10);
1191
1192 mutex_lock(&data->update_lock);
1193 switch (fn) {
1194 case SYS_PWM:
1195 data->pwm[ix] = SENSORS_LIMIT(val, 0, 255);
1196 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
1197 break;
1198 case SYS_PWM_FREQ:
1199 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
1200 DME1737_REG_PWM_FREQ(ix)));
1201 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
1202 data->pwm_freq[ix]);
1203 break;
1204 case SYS_PWM_ENABLE:
1205 /* Only valid for pwm[1-3] */
1206 if (val < 0 || val > 2) {
1207 count = -EINVAL;
1208 dev_warn(dev, "PWM enable %ld not "
1209 "supported. Choose one of 0, 1, or 2.\n",
1210 val);
1211 goto exit;
1212 }
1213 /* Refresh the cache */
1214 data->pwm_config[ix] = dme1737_read(data,
1215 DME1737_REG_PWM_CONFIG(ix));
1216 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
1217 /* Bail out if no change */
1218 goto exit;
1219 }
1220 /* Do some housekeeping if we are currently in auto mode */
1221 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1222 /* Save the current zone channel assignment */
1223 data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
1224 data->pwm_config[ix]);
1225 /* Save the current ramp rate state and disable it */
1226 data->pwm_rr[ix > 0] = dme1737_read(data,
1227 DME1737_REG_PWM_RR(ix > 0));
1228 data->pwm_rr_en &= ~(1 << ix);
1229 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
1230 data->pwm_rr_en |= (1 << ix);
1231 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
1232 data->pwm_rr[ix > 0]);
1233 dme1737_write(data,
1234 DME1737_REG_PWM_RR(ix > 0),
1235 data->pwm_rr[ix > 0]);
1236 }
1237 }
1238 /* Set the new PWM mode */
1239 switch (val) {
1240 case 0:
1241 /* Change permissions of pwm[ix] to read-only */
1242 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1243 S_IRUGO);
1244 /* Turn fan fully on */
1245 data->pwm_config[ix] = PWM_EN_TO_REG(0,
1246 data->pwm_config[ix]);
1247 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1248 data->pwm_config[ix]);
1249 break;
1250 case 1:
1251 /* Turn on manual mode */
1252 data->pwm_config[ix] = PWM_EN_TO_REG(1,
1253 data->pwm_config[ix]);
1254 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1255 data->pwm_config[ix]);
1256 /* Change permissions of pwm[ix] to read-writeable */
1257 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1258 S_IRUGO | S_IWUSR);
1259 break;
1260 case 2:
1261 /* Change permissions of pwm[ix] to read-only */
1262 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
1263 S_IRUGO);
1264 /* Turn on auto mode using the saved zone channel
1265 * assignment */
1266 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1267 data->pwm_acz[ix],
1268 data->pwm_config[ix]);
1269 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1270 data->pwm_config[ix]);
1271 /* Enable PWM ramp rate if previously enabled */
1272 if (data->pwm_rr_en & (1 << ix)) {
1273 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
1274 dme1737_read(data,
1275 DME1737_REG_PWM_RR(ix > 0)));
1276 dme1737_write(data,
1277 DME1737_REG_PWM_RR(ix > 0),
1278 data->pwm_rr[ix > 0]);
1279 }
1280 break;
1281 }
1282 break;
1283 case SYS_PWM_RAMP_RATE:
1284 /* Only valid for pwm[1-3] */
1285 /* Refresh the cache */
1286 data->pwm_config[ix] = dme1737_read(data,
1287 DME1737_REG_PWM_CONFIG(ix));
1288 data->pwm_rr[ix > 0] = dme1737_read(data,
1289 DME1737_REG_PWM_RR(ix > 0));
1290 /* Set the ramp rate value */
1291 if (val > 0) {
1292 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1293 data->pwm_rr[ix > 0]);
1294 }
1295 /* Enable/disable the feature only if the associated PWM
1296 * output is in automatic mode. */
1297 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1298 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1299 data->pwm_rr[ix > 0]);
1300 }
1301 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
1302 data->pwm_rr[ix > 0]);
1303 break;
1304 case SYS_PWM_AUTO_CHANNELS_ZONE:
1305 /* Only valid for pwm[1-3] */
1306 if (!(val == 1 || val == 2 || val == 4 ||
1307 val == 6 || val == 7)) {
1308 count = -EINVAL;
1309 dev_warn(dev, "PWM auto channels zone %ld "
1310 "not supported. Choose one of 1, 2, 4, 6, "
1311 "or 7.\n", val);
1312 goto exit;
1313 }
1314 /* Refresh the cache */
1315 data->pwm_config[ix] = dme1737_read(data,
1316 DME1737_REG_PWM_CONFIG(ix));
1317 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1318 /* PWM is already in auto mode so update the temp
1319 * channel assignment */
1320 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1321 data->pwm_config[ix]);
1322 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
1323 data->pwm_config[ix]);
1324 } else {
1325 /* PWM is not in auto mode so we save the temp
1326 * channel assignment for later use */
1327 data->pwm_acz[ix] = val;
1328 }
1329 break;
1330 case SYS_PWM_AUTO_PWM_MIN:
1331 /* Only valid for pwm[1-3] */
1332 /* Refresh the cache */
1333 data->pwm_min[ix] = dme1737_read(data,
1334 DME1737_REG_PWM_MIN(ix));
1335 /* There are only 2 values supported for the auto_pwm_min
1336 * value: 0 or auto_point1_pwm. So if the temperature drops
1337 * below the auto_point1_temp_hyst value, the fan either turns
1338 * off or runs at auto_point1_pwm duty-cycle. */
1339 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1340 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
1341 dme1737_read(data,
1342 DME1737_REG_PWM_RR(0)));
1343 } else {
1344 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
1345 dme1737_read(data,
1346 DME1737_REG_PWM_RR(0)));
1347 }
1348 dme1737_write(data, DME1737_REG_PWM_RR(0),
1349 data->pwm_rr[0]);
1350 break;
1351 case SYS_PWM_AUTO_POINT1_PWM:
1352 /* Only valid for pwm[1-3] */
1353 data->pwm_min[ix] = SENSORS_LIMIT(val, 0, 255);
1354 dme1737_write(data, DME1737_REG_PWM_MIN(ix),
1355 data->pwm_min[ix]);
1356 break;
1357 default:
1358 dev_dbg(dev, "Unknown function %d.\n", fn);
1359 }
1360 exit:
1361 mutex_unlock(&data->update_lock);
1362
1363 return count;
1364 }
1365
1366 /* ---------------------------------------------------------------------
1367 * Miscellaneous sysfs attributes
1368 * --------------------------------------------------------------------- */
1369
1370 static ssize_t show_vrm(struct device *dev, struct device_attribute *attr,
1371 char *buf)
1372 {
1373 struct i2c_client *client = to_i2c_client(dev);
1374 struct dme1737_data *data = i2c_get_clientdata(client);
1375
1376 return sprintf(buf, "%d\n", data->vrm);
1377 }
1378
1379 static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1380 const char *buf, size_t count)
1381 {
1382 struct dme1737_data *data = dev_get_drvdata(dev);
1383 long val = simple_strtol(buf, NULL, 10);
1384
1385 data->vrm = val;
1386 return count;
1387 }
1388
1389 static ssize_t show_vid(struct device *dev, struct device_attribute *attr,
1390 char *buf)
1391 {
1392 struct dme1737_data *data = dme1737_update_device(dev);
1393
1394 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1395 }
1396
1397 static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1398 char *buf)
1399 {
1400 struct dme1737_data *data = dev_get_drvdata(dev);
1401
1402 return sprintf(buf, "%s\n", data->name);
1403 }
1404
1405 /* ---------------------------------------------------------------------
1406 * Sysfs device attribute defines and structs
1407 * --------------------------------------------------------------------- */
1408
1409 /* Voltages 0-6 */
1410
1411 #define SENSOR_DEVICE_ATTR_IN(ix) \
1412 static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
1413 show_in, NULL, SYS_IN_INPUT, ix); \
1414 static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
1415 show_in, set_in, SYS_IN_MIN, ix); \
1416 static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
1417 show_in, set_in, SYS_IN_MAX, ix); \
1418 static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
1419 show_in, NULL, SYS_IN_ALARM, ix)
1420
1421 SENSOR_DEVICE_ATTR_IN(0);
1422 SENSOR_DEVICE_ATTR_IN(1);
1423 SENSOR_DEVICE_ATTR_IN(2);
1424 SENSOR_DEVICE_ATTR_IN(3);
1425 SENSOR_DEVICE_ATTR_IN(4);
1426 SENSOR_DEVICE_ATTR_IN(5);
1427 SENSOR_DEVICE_ATTR_IN(6);
1428
1429 /* Temperatures 1-3 */
1430
1431 #define SENSOR_DEVICE_ATTR_TEMP(ix) \
1432 static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
1433 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
1434 static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
1435 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
1436 static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
1437 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
1438 static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
1439 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
1440 static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
1441 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
1442 static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
1443 show_temp, NULL, SYS_TEMP_FAULT, ix-1)
1444
1445 SENSOR_DEVICE_ATTR_TEMP(1);
1446 SENSOR_DEVICE_ATTR_TEMP(2);
1447 SENSOR_DEVICE_ATTR_TEMP(3);
1448
1449 /* Zones 1-3 */
1450
1451 #define SENSOR_DEVICE_ATTR_ZONE(ix) \
1452 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
1453 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
1454 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
1455 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
1456 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
1457 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
1458 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
1459 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
1460 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
1461 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
1462
1463 SENSOR_DEVICE_ATTR_ZONE(1);
1464 SENSOR_DEVICE_ATTR_ZONE(2);
1465 SENSOR_DEVICE_ATTR_ZONE(3);
1466
1467 /* Fans 1-4 */
1468
1469 #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
1470 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1471 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1472 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1473 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1474 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1475 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1476 static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
1477 show_fan, set_fan, SYS_FAN_TYPE, ix-1)
1478
1479 SENSOR_DEVICE_ATTR_FAN_1TO4(1);
1480 SENSOR_DEVICE_ATTR_FAN_1TO4(2);
1481 SENSOR_DEVICE_ATTR_FAN_1TO4(3);
1482 SENSOR_DEVICE_ATTR_FAN_1TO4(4);
1483
1484 /* Fans 5-6 */
1485
1486 #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
1487 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
1488 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
1489 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
1490 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
1491 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
1492 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
1493 static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
1494 show_fan, set_fan, SYS_FAN_MAX, ix-1)
1495
1496 SENSOR_DEVICE_ATTR_FAN_5TO6(5);
1497 SENSOR_DEVICE_ATTR_FAN_5TO6(6);
1498
1499 /* PWMs 1-3 */
1500
1501 #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
1502 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1503 show_pwm, set_pwm, SYS_PWM, ix-1); \
1504 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1505 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1506 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1507 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
1508 static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
1509 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
1510 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
1511 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
1512 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
1513 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
1514 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
1515 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
1516 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
1517 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
1518
1519 SENSOR_DEVICE_ATTR_PWM_1TO3(1);
1520 SENSOR_DEVICE_ATTR_PWM_1TO3(2);
1521 SENSOR_DEVICE_ATTR_PWM_1TO3(3);
1522
1523 /* PWMs 5-6 */
1524
1525 #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
1526 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
1527 show_pwm, set_pwm, SYS_PWM, ix-1); \
1528 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
1529 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
1530 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
1531 show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
1532
1533 SENSOR_DEVICE_ATTR_PWM_5TO6(5);
1534 SENSOR_DEVICE_ATTR_PWM_5TO6(6);
1535
1536 /* Misc */
1537
1538 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1539 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1540 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
1541
1542 /* This struct holds all the attributes that are always present and need to be
1543 * created unconditionally. The attributes that need modification of their
1544 * permissions are created read-only and write permissions are added or removed
1545 * on the fly when required */
1546 static struct attribute *dme1737_attr[] ={
1547 /* Voltages */
1548 &sensor_dev_attr_in0_input.dev_attr.attr,
1549 &sensor_dev_attr_in0_min.dev_attr.attr,
1550 &sensor_dev_attr_in0_max.dev_attr.attr,
1551 &sensor_dev_attr_in0_alarm.dev_attr.attr,
1552 &sensor_dev_attr_in1_input.dev_attr.attr,
1553 &sensor_dev_attr_in1_min.dev_attr.attr,
1554 &sensor_dev_attr_in1_max.dev_attr.attr,
1555 &sensor_dev_attr_in1_alarm.dev_attr.attr,
1556 &sensor_dev_attr_in2_input.dev_attr.attr,
1557 &sensor_dev_attr_in2_min.dev_attr.attr,
1558 &sensor_dev_attr_in2_max.dev_attr.attr,
1559 &sensor_dev_attr_in2_alarm.dev_attr.attr,
1560 &sensor_dev_attr_in3_input.dev_attr.attr,
1561 &sensor_dev_attr_in3_min.dev_attr.attr,
1562 &sensor_dev_attr_in3_max.dev_attr.attr,
1563 &sensor_dev_attr_in3_alarm.dev_attr.attr,
1564 &sensor_dev_attr_in4_input.dev_attr.attr,
1565 &sensor_dev_attr_in4_min.dev_attr.attr,
1566 &sensor_dev_attr_in4_max.dev_attr.attr,
1567 &sensor_dev_attr_in4_alarm.dev_attr.attr,
1568 &sensor_dev_attr_in5_input.dev_attr.attr,
1569 &sensor_dev_attr_in5_min.dev_attr.attr,
1570 &sensor_dev_attr_in5_max.dev_attr.attr,
1571 &sensor_dev_attr_in5_alarm.dev_attr.attr,
1572 &sensor_dev_attr_in6_input.dev_attr.attr,
1573 &sensor_dev_attr_in6_min.dev_attr.attr,
1574 &sensor_dev_attr_in6_max.dev_attr.attr,
1575 &sensor_dev_attr_in6_alarm.dev_attr.attr,
1576 /* Temperatures */
1577 &sensor_dev_attr_temp1_input.dev_attr.attr,
1578 &sensor_dev_attr_temp1_min.dev_attr.attr,
1579 &sensor_dev_attr_temp1_max.dev_attr.attr,
1580 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
1581 &sensor_dev_attr_temp1_fault.dev_attr.attr,
1582 &sensor_dev_attr_temp2_input.dev_attr.attr,
1583 &sensor_dev_attr_temp2_min.dev_attr.attr,
1584 &sensor_dev_attr_temp2_max.dev_attr.attr,
1585 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
1586 &sensor_dev_attr_temp2_fault.dev_attr.attr,
1587 &sensor_dev_attr_temp3_input.dev_attr.attr,
1588 &sensor_dev_attr_temp3_min.dev_attr.attr,
1589 &sensor_dev_attr_temp3_max.dev_attr.attr,
1590 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1591 &sensor_dev_attr_temp3_fault.dev_attr.attr,
1592 /* Zones */
1593 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1594 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1595 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1596 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
1597 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1598 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1599 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1600 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
1601 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1602 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1603 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1604 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
1605 NULL
1606 };
1607
1608 static const struct attribute_group dme1737_group = {
1609 .attrs = dme1737_attr,
1610 };
1611
1612 /* The following struct holds misc attributes, which are not available in all
1613 * chips. Their creation depends on the chip type which is determined during
1614 * module load. */
1615 static struct attribute *dme1737_misc_attr[] = {
1616 /* Temperatures */
1617 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1618 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1619 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1620 /* Zones */
1621 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1622 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1623 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
1624 NULL
1625 };
1626
1627 static const struct attribute_group dme1737_misc_group = {
1628 .attrs = dme1737_misc_attr,
1629 };
1630
1631 /* The following struct holds VID-related attributes. Their creation
1632 depends on the chip type which is determined during module load. */
1633 static struct attribute *dme1737_vid_attr[] = {
1634 &dev_attr_vrm.attr,
1635 &dev_attr_cpu0_vid.attr,
1636 NULL
1637 };
1638
1639 static const struct attribute_group dme1737_vid_group = {
1640 .attrs = dme1737_vid_attr,
1641 };
1642
1643 /* The following structs hold the PWM attributes, some of which are optional.
1644 * Their creation depends on the chip configuration which is determined during
1645 * module load. */
1646 static struct attribute *dme1737_pwm1_attr[] = {
1647 &sensor_dev_attr_pwm1.dev_attr.attr,
1648 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1649 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1650 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1651 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1652 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1653 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1654 NULL
1655 };
1656 static struct attribute *dme1737_pwm2_attr[] = {
1657 &sensor_dev_attr_pwm2.dev_attr.attr,
1658 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1659 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1660 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1661 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1662 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1663 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1664 NULL
1665 };
1666 static struct attribute *dme1737_pwm3_attr[] = {
1667 &sensor_dev_attr_pwm3.dev_attr.attr,
1668 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1669 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1670 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1671 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1672 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1673 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1674 NULL
1675 };
1676 static struct attribute *dme1737_pwm5_attr[] = {
1677 &sensor_dev_attr_pwm5.dev_attr.attr,
1678 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1679 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
1680 NULL
1681 };
1682 static struct attribute *dme1737_pwm6_attr[] = {
1683 &sensor_dev_attr_pwm6.dev_attr.attr,
1684 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1685 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
1686 NULL
1687 };
1688
1689 static const struct attribute_group dme1737_pwm_group[] = {
1690 { .attrs = dme1737_pwm1_attr },
1691 { .attrs = dme1737_pwm2_attr },
1692 { .attrs = dme1737_pwm3_attr },
1693 { .attrs = NULL },
1694 { .attrs = dme1737_pwm5_attr },
1695 { .attrs = dme1737_pwm6_attr },
1696 };
1697
1698 /* The following struct holds misc PWM attributes, which are not available in
1699 * all chips. Their creation depends on the chip type which is determined
1700 * during module load. */
1701 static struct attribute *dme1737_pwm_misc_attr[] = {
1702 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1703 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1704 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1705 };
1706
1707 /* The following structs hold the fan attributes, some of which are optional.
1708 * Their creation depends on the chip configuration which is determined during
1709 * module load. */
1710 static struct attribute *dme1737_fan1_attr[] = {
1711 &sensor_dev_attr_fan1_input.dev_attr.attr,
1712 &sensor_dev_attr_fan1_min.dev_attr.attr,
1713 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1714 &sensor_dev_attr_fan1_type.dev_attr.attr,
1715 NULL
1716 };
1717 static struct attribute *dme1737_fan2_attr[] = {
1718 &sensor_dev_attr_fan2_input.dev_attr.attr,
1719 &sensor_dev_attr_fan2_min.dev_attr.attr,
1720 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1721 &sensor_dev_attr_fan2_type.dev_attr.attr,
1722 NULL
1723 };
1724 static struct attribute *dme1737_fan3_attr[] = {
1725 &sensor_dev_attr_fan3_input.dev_attr.attr,
1726 &sensor_dev_attr_fan3_min.dev_attr.attr,
1727 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1728 &sensor_dev_attr_fan3_type.dev_attr.attr,
1729 NULL
1730 };
1731 static struct attribute *dme1737_fan4_attr[] = {
1732 &sensor_dev_attr_fan4_input.dev_attr.attr,
1733 &sensor_dev_attr_fan4_min.dev_attr.attr,
1734 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1735 &sensor_dev_attr_fan4_type.dev_attr.attr,
1736 NULL
1737 };
1738 static struct attribute *dme1737_fan5_attr[] = {
1739 &sensor_dev_attr_fan5_input.dev_attr.attr,
1740 &sensor_dev_attr_fan5_min.dev_attr.attr,
1741 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1742 &sensor_dev_attr_fan5_max.dev_attr.attr,
1743 NULL
1744 };
1745 static struct attribute *dme1737_fan6_attr[] = {
1746 &sensor_dev_attr_fan6_input.dev_attr.attr,
1747 &sensor_dev_attr_fan6_min.dev_attr.attr,
1748 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
1749 &sensor_dev_attr_fan6_max.dev_attr.attr,
1750 NULL
1751 };
1752
1753 static const struct attribute_group dme1737_fan_group[] = {
1754 { .attrs = dme1737_fan1_attr },
1755 { .attrs = dme1737_fan2_attr },
1756 { .attrs = dme1737_fan3_attr },
1757 { .attrs = dme1737_fan4_attr },
1758 { .attrs = dme1737_fan5_attr },
1759 { .attrs = dme1737_fan6_attr },
1760 };
1761
1762 /* The permissions of the following zone attributes are changed to read-
1763 * writeable if the chip is *not* locked. Otherwise they stay read-only. */
1764 static struct attribute *dme1737_zone_chmod_attr[] = {
1765 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1766 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1767 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1768 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1769 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1770 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1771 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1772 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1773 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1774 NULL
1775 };
1776
1777 static const struct attribute_group dme1737_zone_chmod_group = {
1778 .attrs = dme1737_zone_chmod_attr,
1779 };
1780
1781 /* The permissions of the following PWM attributes are changed to read-
1782 * writeable if the chip is *not* locked and the respective PWM is available.
1783 * Otherwise they stay read-only. */
1784 static struct attribute *dme1737_pwm1_chmod_attr[] = {
1785 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1786 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1787 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1788 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
1789 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1790 NULL
1791 };
1792 static struct attribute *dme1737_pwm2_chmod_attr[] = {
1793 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1794 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1795 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1796 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
1797 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1798 NULL
1799 };
1800 static struct attribute *dme1737_pwm3_chmod_attr[] = {
1801 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1802 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1803 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1804 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
1805 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1806 NULL
1807 };
1808 static struct attribute *dme1737_pwm5_chmod_attr[] = {
1809 &sensor_dev_attr_pwm5.dev_attr.attr,
1810 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1811 NULL
1812 };
1813 static struct attribute *dme1737_pwm6_chmod_attr[] = {
1814 &sensor_dev_attr_pwm6.dev_attr.attr,
1815 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1816 NULL
1817 };
1818
1819 static const struct attribute_group dme1737_pwm_chmod_group[] = {
1820 { .attrs = dme1737_pwm1_chmod_attr },
1821 { .attrs = dme1737_pwm2_chmod_attr },
1822 { .attrs = dme1737_pwm3_chmod_attr },
1823 { .attrs = NULL },
1824 { .attrs = dme1737_pwm5_chmod_attr },
1825 { .attrs = dme1737_pwm6_chmod_attr },
1826 };
1827
1828 /* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
1829 * chip is not locked. Otherwise they are read-only. */
1830 static struct attribute *dme1737_pwm_chmod_attr[] = {
1831 &sensor_dev_attr_pwm1.dev_attr.attr,
1832 &sensor_dev_attr_pwm2.dev_attr.attr,
1833 &sensor_dev_attr_pwm3.dev_attr.attr,
1834 };
1835
1836 /* ---------------------------------------------------------------------
1837 * Super-IO functions
1838 * --------------------------------------------------------------------- */
1839
1840 static inline void dme1737_sio_enter(int sio_cip)
1841 {
1842 outb(0x55, sio_cip);
1843 }
1844
1845 static inline void dme1737_sio_exit(int sio_cip)
1846 {
1847 outb(0xaa, sio_cip);
1848 }
1849
1850 static inline int dme1737_sio_inb(int sio_cip, int reg)
1851 {
1852 outb(reg, sio_cip);
1853 return inb(sio_cip + 1);
1854 }
1855
1856 static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
1857 {
1858 outb(reg, sio_cip);
1859 outb(val, sio_cip + 1);
1860 }
1861
1862 /* ---------------------------------------------------------------------
1863 * Device initialization
1864 * --------------------------------------------------------------------- */
1865
1866 static int dme1737_i2c_get_features(int, struct dme1737_data*);
1867
1868 static void dme1737_chmod_file(struct device *dev,
1869 struct attribute *attr, mode_t mode)
1870 {
1871 if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
1872 dev_warn(dev, "Failed to change permissions of %s.\n",
1873 attr->name);
1874 }
1875 }
1876
1877 static void dme1737_chmod_group(struct device *dev,
1878 const struct attribute_group *group,
1879 mode_t mode)
1880 {
1881 struct attribute **attr;
1882
1883 for (attr = group->attrs; *attr; attr++) {
1884 dme1737_chmod_file(dev, *attr, mode);
1885 }
1886 }
1887
1888 static void dme1737_remove_files(struct device *dev)
1889 {
1890 struct dme1737_data *data = dev_get_drvdata(dev);
1891 int ix;
1892
1893 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
1894 if (data->has_fan & (1 << ix)) {
1895 sysfs_remove_group(&dev->kobj,
1896 &dme1737_fan_group[ix]);
1897 }
1898 }
1899
1900 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
1901 if (data->has_pwm & (1 << ix)) {
1902 sysfs_remove_group(&dev->kobj,
1903 &dme1737_pwm_group[ix]);
1904 if (data->type != sch5027 && ix < 3) {
1905 sysfs_remove_file(&dev->kobj,
1906 dme1737_pwm_misc_attr[ix]);
1907 }
1908 }
1909 }
1910
1911 if (data->type != sch5027) {
1912 sysfs_remove_group(&dev->kobj, &dme1737_misc_group);
1913 }
1914 if (data->type == dme1737) {
1915 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
1916 }
1917
1918 sysfs_remove_group(&dev->kobj, &dme1737_group);
1919
1920 if (!data->client) {
1921 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
1922 }
1923 }
1924
1925 static int dme1737_create_files(struct device *dev)
1926 {
1927 struct dme1737_data *data = dev_get_drvdata(dev);
1928 int err, ix;
1929
1930 /* Create a name attribute for ISA devices */
1931 if (!data->client &&
1932 (err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr))) {
1933 goto exit;
1934 }
1935
1936 /* Create standard sysfs attributes */
1937 if ((err = sysfs_create_group(&dev->kobj, &dme1737_group))) {
1938 goto exit_remove;
1939 }
1940
1941 /* Create misc sysfs attributes */
1942 if ((data->type != sch5027) &&
1943 (err = sysfs_create_group(&dev->kobj,
1944 &dme1737_misc_group))) {
1945 goto exit_remove;
1946 }
1947
1948 /* Create VID-related sysfs attributes */
1949 if ((data->type == dme1737) &&
1950 (err = sysfs_create_group(&dev->kobj,
1951 &dme1737_vid_group))) {
1952 goto exit_remove;
1953 }
1954
1955 /* Create fan sysfs attributes */
1956 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
1957 if (data->has_fan & (1 << ix)) {
1958 if ((err = sysfs_create_group(&dev->kobj,
1959 &dme1737_fan_group[ix]))) {
1960 goto exit_remove;
1961 }
1962 }
1963 }
1964
1965 /* Create PWM sysfs attributes */
1966 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
1967 if (data->has_pwm & (1 << ix)) {
1968 if ((err = sysfs_create_group(&dev->kobj,
1969 &dme1737_pwm_group[ix]))) {
1970 goto exit_remove;
1971 }
1972 if (data->type != sch5027 && ix < 3 &&
1973 (err = sysfs_create_file(&dev->kobj,
1974 dme1737_pwm_misc_attr[ix]))) {
1975 goto exit_remove;
1976 }
1977 }
1978 }
1979
1980 /* Inform if the device is locked. Otherwise change the permissions of
1981 * selected attributes from read-only to read-writeable. */
1982 if (data->config & 0x02) {
1983 dev_info(dev, "Device is locked. Some attributes "
1984 "will be read-only.\n");
1985 } else {
1986 /* Change permissions of zone sysfs attributes */
1987 dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
1988 S_IRUGO | S_IWUSR);
1989
1990 /* Change permissions of misc sysfs attributes */
1991 if (data->type != sch5027) {
1992 dme1737_chmod_group(dev, &dme1737_misc_group,
1993 S_IRUGO | S_IWUSR);
1994 }
1995
1996 /* Change permissions of PWM sysfs attributes */
1997 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
1998 if (data->has_pwm & (1 << ix)) {
1999 dme1737_chmod_group(dev,
2000 &dme1737_pwm_chmod_group[ix],
2001 S_IRUGO | S_IWUSR);
2002 if (data->type != sch5027 && ix < 3) {
2003 dme1737_chmod_file(dev,
2004 dme1737_pwm_misc_attr[ix],
2005 S_IRUGO | S_IWUSR);
2006 }
2007 }
2008 }
2009
2010 /* Change permissions of pwm[1-3] if in manual mode */
2011 for (ix = 0; ix < 3; ix++) {
2012 if ((data->has_pwm & (1 << ix)) &&
2013 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
2014 dme1737_chmod_file(dev,
2015 dme1737_pwm_chmod_attr[ix],
2016 S_IRUGO | S_IWUSR);
2017 }
2018 }
2019 }
2020
2021 return 0;
2022
2023 exit_remove:
2024 dme1737_remove_files(dev);
2025 exit:
2026 return err;
2027 }
2028
2029 static int dme1737_init_device(struct device *dev)
2030 {
2031 struct dme1737_data *data = dev_get_drvdata(dev);
2032 struct i2c_client *client = data->client;
2033 int ix;
2034 u8 reg;
2035
2036 /* Point to the right nominal voltages array */
2037 data->in_nominal = IN_NOMINAL(data->type);
2038
2039 data->config = dme1737_read(data, DME1737_REG_CONFIG);
2040 /* Inform if part is not monitoring/started */
2041 if (!(data->config & 0x01)) {
2042 if (!force_start) {
2043 dev_err(dev, "Device is not monitoring. "
2044 "Use the force_start load parameter to "
2045 "override.\n");
2046 return -EFAULT;
2047 }
2048
2049 /* Force monitoring */
2050 data->config |= 0x01;
2051 dme1737_write(data, DME1737_REG_CONFIG, data->config);
2052 }
2053 /* Inform if part is not ready */
2054 if (!(data->config & 0x04)) {
2055 dev_err(dev, "Device is not ready.\n");
2056 return -EFAULT;
2057 }
2058
2059 /* Determine which optional fan and pwm features are enabled/present */
2060 if (client) { /* I2C chip */
2061 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
2062 /* Check if optional fan3 input is enabled */
2063 if (data->config2 & 0x04) {
2064 data->has_fan |= (1 << 2);
2065 }
2066
2067 /* Fan4 and pwm3 are only available if the client's I2C address
2068 * is the default 0x2e. Otherwise the I/Os associated with
2069 * these functions are used for addr enable/select. */
2070 if (client->addr == 0x2e) {
2071 data->has_fan |= (1 << 3);
2072 data->has_pwm |= (1 << 2);
2073 }
2074
2075 /* Determine which of the optional fan[5-6] and pwm[5-6]
2076 * features are enabled. For this, we need to query the runtime
2077 * registers through the Super-IO LPC interface. Try both
2078 * config ports 0x2e and 0x4e. */
2079 if (dme1737_i2c_get_features(0x2e, data) &&
2080 dme1737_i2c_get_features(0x4e, data)) {
2081 dev_warn(dev, "Failed to query Super-IO for optional "
2082 "features.\n");
2083 }
2084 } else { /* ISA chip */
2085 /* Fan3 and pwm3 are always available. Fan[4-5] and pwm[5-6]
2086 * don't exist in the ISA chip. */
2087 data->has_fan |= (1 << 2);
2088 data->has_pwm |= (1 << 2);
2089 }
2090
2091 /* Fan1, fan2, pwm1, and pwm2 are always present */
2092 data->has_fan |= 0x03;
2093 data->has_pwm |= 0x03;
2094
2095 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, "
2096 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
2097 (data->has_pwm & (1 << 2)) ? "yes" : "no",
2098 (data->has_pwm & (1 << 4)) ? "yes" : "no",
2099 (data->has_pwm & (1 << 5)) ? "yes" : "no",
2100 (data->has_fan & (1 << 2)) ? "yes" : "no",
2101 (data->has_fan & (1 << 3)) ? "yes" : "no",
2102 (data->has_fan & (1 << 4)) ? "yes" : "no",
2103 (data->has_fan & (1 << 5)) ? "yes" : "no");
2104
2105 reg = dme1737_read(data, DME1737_REG_TACH_PWM);
2106 /* Inform if fan-to-pwm mapping differs from the default */
2107 if (client && reg != 0xa4) { /* I2C chip */
2108 dev_warn(dev, "Non-standard fan to pwm mapping: "
2109 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, "
2110 "fan4->pwm%d. Please report to the driver "
2111 "maintainer.\n",
2112 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2113 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1);
2114 } else if (!client && reg != 0x24) { /* ISA chip */
2115 dev_warn(dev, "Non-standard fan to pwm mapping: "
2116 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. "
2117 "Please report to the driver maintainer.\n",
2118 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2119 ((reg >> 4) & 0x03) + 1);
2120 }
2121
2122 /* Switch pwm[1-3] to manual mode if they are currently disabled and
2123 * set the duty-cycles to 0% (which is identical to the PWMs being
2124 * disabled). */
2125 if (!(data->config & 0x02)) {
2126 for (ix = 0; ix < 3; ix++) {
2127 data->pwm_config[ix] = dme1737_read(data,
2128 DME1737_REG_PWM_CONFIG(ix));
2129 if ((data->has_pwm & (1 << ix)) &&
2130 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
2131 dev_info(dev, "Switching pwm%d to "
2132 "manual mode.\n", ix + 1);
2133 data->pwm_config[ix] = PWM_EN_TO_REG(1,
2134 data->pwm_config[ix]);
2135 dme1737_write(data, DME1737_REG_PWM(ix), 0);
2136 dme1737_write(data,
2137 DME1737_REG_PWM_CONFIG(ix),
2138 data->pwm_config[ix]);
2139 }
2140 }
2141 }
2142
2143 /* Initialize the default PWM auto channels zone (acz) assignments */
2144 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
2145 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
2146 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2147
2148 /* Set VRM */
2149 if (data->type == dme1737) {
2150 data->vrm = vid_which_vrm();
2151 }
2152
2153 return 0;
2154 }
2155
2156 /* ---------------------------------------------------------------------
2157 * I2C device detection and registration
2158 * --------------------------------------------------------------------- */
2159
2160 static struct i2c_driver dme1737_i2c_driver;
2161
2162 static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2163 {
2164 int err = 0, reg;
2165 u16 addr;
2166
2167 dme1737_sio_enter(sio_cip);
2168
2169 /* Check device ID
2170 * The DME1737 can return either 0x78 or 0x77 as its device ID.
2171 * The SCH5027 returns 0x89 as its device ID. */
2172 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2173 if (!(reg == 0x77 || reg == 0x78 || reg == 0x89)) {
2174 err = -ENODEV;
2175 goto exit;
2176 }
2177
2178 /* Select logical device A (runtime registers) */
2179 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2180
2181 /* Get the base address of the runtime registers */
2182 if (!(addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2183 dme1737_sio_inb(sio_cip, 0x61))) {
2184 err = -ENODEV;
2185 goto exit;
2186 }
2187
2188 /* Read the runtime registers to determine which optional features
2189 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
2190 * to '10' if the respective feature is enabled. */
2191 if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */
2192 data->has_fan |= (1 << 5);
2193 }
2194 if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */
2195 data->has_pwm |= (1 << 5);
2196 }
2197 if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */
2198 data->has_fan |= (1 << 4);
2199 }
2200 if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */
2201 data->has_pwm |= (1 << 4);
2202 }
2203
2204 exit:
2205 dme1737_sio_exit(sio_cip);
2206
2207 return err;
2208 }
2209
2210 /* Return 0 if detection is successful, -ENODEV otherwise */
2211 static int dme1737_i2c_detect(struct i2c_client *client, int kind,
2212 struct i2c_board_info *info)
2213 {
2214 struct i2c_adapter *adapter = client->adapter;
2215 struct device *dev = &adapter->dev;
2216 u8 company, verstep = 0;
2217 const char *name;
2218
2219 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
2220 return -ENODEV;
2221 }
2222
2223 /* A negative kind means that the driver was loaded with no force
2224 * parameter (default), so we must identify the chip. */
2225 if (kind < 0) {
2226 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2227 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
2228
2229 if (company == DME1737_COMPANY_SMSC &&
2230 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
2231 kind = dme1737;
2232 } else if (company == DME1737_COMPANY_SMSC &&
2233 verstep == SCH5027_VERSTEP) {
2234 kind = sch5027;
2235 } else {
2236 return -ENODEV;
2237 }
2238 }
2239
2240 if (kind == sch5027) {
2241 name = "sch5027";
2242 } else {
2243 kind = dme1737;
2244 name = "dme1737";
2245 }
2246
2247 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
2248 kind == sch5027 ? "SCH5027" : "DME1737", client->addr,
2249 verstep);
2250 strlcpy(info->type, name, I2C_NAME_SIZE);
2251
2252 return 0;
2253 }
2254
2255 static int dme1737_i2c_probe(struct i2c_client *client,
2256 const struct i2c_device_id *id)
2257 {
2258 struct dme1737_data *data;
2259 struct device *dev = &client->dev;
2260 int err;
2261
2262 data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL);
2263 if (!data) {
2264 err = -ENOMEM;
2265 goto exit;
2266 }
2267
2268 i2c_set_clientdata(client, data);
2269 data->type = id->driver_data;
2270 data->client = client;
2271 data->name = client->name;
2272 mutex_init(&data->update_lock);
2273
2274 /* Initialize the DME1737 chip */
2275 if ((err = dme1737_init_device(dev))) {
2276 dev_err(dev, "Failed to initialize device.\n");
2277 goto exit_kfree;
2278 }
2279
2280 /* Create sysfs files */
2281 if ((err = dme1737_create_files(dev))) {
2282 dev_err(dev, "Failed to create sysfs files.\n");
2283 goto exit_kfree;
2284 }
2285
2286 /* Register device */
2287 data->hwmon_dev = hwmon_device_register(dev);
2288 if (IS_ERR(data->hwmon_dev)) {
2289 dev_err(dev, "Failed to register device.\n");
2290 err = PTR_ERR(data->hwmon_dev);
2291 goto exit_remove;
2292 }
2293
2294 return 0;
2295
2296 exit_remove:
2297 dme1737_remove_files(dev);
2298 exit_kfree:
2299 kfree(data);
2300 exit:
2301 return err;
2302 }
2303
2304 static int dme1737_i2c_remove(struct i2c_client *client)
2305 {
2306 struct dme1737_data *data = i2c_get_clientdata(client);
2307
2308 hwmon_device_unregister(data->hwmon_dev);
2309 dme1737_remove_files(&client->dev);
2310
2311 kfree(data);
2312 return 0;
2313 }
2314
2315 static const struct i2c_device_id dme1737_id[] = {
2316 { "dme1737", dme1737 },
2317 { "sch5027", sch5027 },
2318 { }
2319 };
2320 MODULE_DEVICE_TABLE(i2c, dme1737_id);
2321
2322 static struct i2c_driver dme1737_i2c_driver = {
2323 .class = I2C_CLASS_HWMON,
2324 .driver = {
2325 .name = "dme1737",
2326 },
2327 .probe = dme1737_i2c_probe,
2328 .remove = dme1737_i2c_remove,
2329 .id_table = dme1737_id,
2330 .detect = dme1737_i2c_detect,
2331 .address_data = &addr_data,
2332 };
2333
2334 /* ---------------------------------------------------------------------
2335 * ISA device detection and registration
2336 * --------------------------------------------------------------------- */
2337
2338 static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2339 {
2340 int err = 0, reg;
2341 unsigned short base_addr;
2342
2343 dme1737_sio_enter(sio_cip);
2344
2345 /* Check device ID
2346 * We currently know about SCH3112 (0x7c), SCH3114 (0x7d), and
2347 * SCH3116 (0x7f). */
2348 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
2349 if (!(reg == 0x7c || reg == 0x7d || reg == 0x7f)) {
2350 err = -ENODEV;
2351 goto exit;
2352 }
2353
2354 /* Select logical device A (runtime registers) */
2355 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2356
2357 /* Get the base address of the runtime registers */
2358 if (!(base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2359 dme1737_sio_inb(sio_cip, 0x61))) {
2360 printk(KERN_ERR "dme1737: Base address not set.\n");
2361 err = -ENODEV;
2362 goto exit;
2363 }
2364
2365 /* Access to the hwmon registers is through an index/data register
2366 * pair located at offset 0x70/0x71. */
2367 *addr = base_addr + 0x70;
2368
2369 exit:
2370 dme1737_sio_exit(sio_cip);
2371 return err;
2372 }
2373
2374 static int __init dme1737_isa_device_add(unsigned short addr)
2375 {
2376 struct resource res = {
2377 .start = addr,
2378 .end = addr + DME1737_EXTENT - 1,
2379 .name = "dme1737",
2380 .flags = IORESOURCE_IO,
2381 };
2382 int err;
2383
2384 err = acpi_check_resource_conflict(&res);
2385 if (err)
2386 goto exit;
2387
2388 if (!(pdev = platform_device_alloc("dme1737", addr))) {
2389 printk(KERN_ERR "dme1737: Failed to allocate device.\n");
2390 err = -ENOMEM;
2391 goto exit;
2392 }
2393
2394 if ((err = platform_device_add_resources(pdev, &res, 1))) {
2395 printk(KERN_ERR "dme1737: Failed to add device resource "
2396 "(err = %d).\n", err);
2397 goto exit_device_put;
2398 }
2399
2400 if ((err = platform_device_add(pdev))) {
2401 printk(KERN_ERR "dme1737: Failed to add device (err = %d).\n",
2402 err);
2403 goto exit_device_put;
2404 }
2405
2406 return 0;
2407
2408 exit_device_put:
2409 platform_device_put(pdev);
2410 pdev = NULL;
2411 exit:
2412 return err;
2413 }
2414
2415 static int __devinit dme1737_isa_probe(struct platform_device *pdev)
2416 {
2417 u8 company, device;
2418 struct resource *res;
2419 struct dme1737_data *data;
2420 struct device *dev = &pdev->dev;
2421 int err;
2422
2423 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2424 if (!request_region(res->start, DME1737_EXTENT, "dme1737")) {
2425 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
2426 (unsigned short)res->start,
2427 (unsigned short)res->start + DME1737_EXTENT - 1);
2428 err = -EBUSY;
2429 goto exit;
2430 }
2431
2432 if (!(data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL))) {
2433 err = -ENOMEM;
2434 goto exit_release_region;
2435 }
2436
2437 data->addr = res->start;
2438 platform_set_drvdata(pdev, data);
2439
2440 /* Skip chip detection if module is loaded with force_id parameter */
2441 if (!force_id) {
2442 company = dme1737_read(data, DME1737_REG_COMPANY);
2443 device = dme1737_read(data, DME1737_REG_DEVICE);
2444
2445 if (!((company == DME1737_COMPANY_SMSC) &&
2446 (device == SCH311X_DEVICE))) {
2447 err = -ENODEV;
2448 goto exit_kfree;
2449 }
2450 }
2451 data->type = sch311x;
2452
2453 /* Fill in the remaining client fields and initialize the mutex */
2454 data->name = "sch311x";
2455 mutex_init(&data->update_lock);
2456
2457 dev_info(dev, "Found a SCH311x chip at 0x%04x\n", data->addr);
2458
2459 /* Initialize the chip */
2460 if ((err = dme1737_init_device(dev))) {
2461 dev_err(dev, "Failed to initialize device.\n");
2462 goto exit_kfree;
2463 }
2464
2465 /* Create sysfs files */
2466 if ((err = dme1737_create_files(dev))) {
2467 dev_err(dev, "Failed to create sysfs files.\n");
2468 goto exit_kfree;
2469 }
2470
2471 /* Register device */
2472 data->hwmon_dev = hwmon_device_register(dev);
2473 if (IS_ERR(data->hwmon_dev)) {
2474 dev_err(dev, "Failed to register device.\n");
2475 err = PTR_ERR(data->hwmon_dev);
2476 goto exit_remove_files;
2477 }
2478
2479 return 0;
2480
2481 exit_remove_files:
2482 dme1737_remove_files(dev);
2483 exit_kfree:
2484 platform_set_drvdata(pdev, NULL);
2485 kfree(data);
2486 exit_release_region:
2487 release_region(res->start, DME1737_EXTENT);
2488 exit:
2489 return err;
2490 }
2491
2492 static int __devexit dme1737_isa_remove(struct platform_device *pdev)
2493 {
2494 struct dme1737_data *data = platform_get_drvdata(pdev);
2495
2496 hwmon_device_unregister(data->hwmon_dev);
2497 dme1737_remove_files(&pdev->dev);
2498 release_region(data->addr, DME1737_EXTENT);
2499 platform_set_drvdata(pdev, NULL);
2500 kfree(data);
2501
2502 return 0;
2503 }
2504
2505 static struct platform_driver dme1737_isa_driver = {
2506 .driver = {
2507 .owner = THIS_MODULE,
2508 .name = "dme1737",
2509 },
2510 .probe = dme1737_isa_probe,
2511 .remove = __devexit_p(dme1737_isa_remove),
2512 };
2513
2514 /* ---------------------------------------------------------------------
2515 * Module initialization and cleanup
2516 * --------------------------------------------------------------------- */
2517
2518 static int __init dme1737_init(void)
2519 {
2520 int err;
2521 unsigned short addr;
2522
2523 if ((err = i2c_add_driver(&dme1737_i2c_driver))) {
2524 goto exit;
2525 }
2526
2527 if (dme1737_isa_detect(0x2e, &addr) &&
2528 dme1737_isa_detect(0x4e, &addr) &&
2529 (!probe_all_addr ||
2530 (dme1737_isa_detect(0x162e, &addr) &&
2531 dme1737_isa_detect(0x164e, &addr)))) {
2532 /* Return 0 if we didn't find an ISA device */
2533 return 0;
2534 }
2535
2536 if ((err = platform_driver_register(&dme1737_isa_driver))) {
2537 goto exit_del_i2c_driver;
2538 }
2539
2540 /* Sets global pdev as a side effect */
2541 if ((err = dme1737_isa_device_add(addr))) {
2542 goto exit_del_isa_driver;
2543 }
2544
2545 return 0;
2546
2547 exit_del_isa_driver:
2548 platform_driver_unregister(&dme1737_isa_driver);
2549 exit_del_i2c_driver:
2550 i2c_del_driver(&dme1737_i2c_driver);
2551 exit:
2552 return err;
2553 }
2554
2555 static void __exit dme1737_exit(void)
2556 {
2557 if (pdev) {
2558 platform_device_unregister(pdev);
2559 platform_driver_unregister(&dme1737_isa_driver);
2560 }
2561
2562 i2c_del_driver(&dme1737_i2c_driver);
2563 }
2564
2565 MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
2566 MODULE_DESCRIPTION("DME1737 sensors");
2567 MODULE_LICENSE("GPL");
2568
2569 module_init(dme1737_init);
2570 module_exit(dme1737_exit);
Support for the Chinese Samsung S3C2440 based development boards