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ptrace: kill __ptrace_detach(), fix ->exit_state check
[linux-2.6/mini2440.git] / drivers / char / synclinkmp.c
blob7b0c5b2dd2635cbefbb9a919158aba8d5cef9a0b
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266 char char_buf[MAX_ASYNC_BUFFER_SIZE];
267 bool drop_rts_on_tx_done;
268
269 struct _input_signal_events input_signal_events;
270
271 /* SPPP/Cisco HDLC device parts */
272 int netcount;
273 spinlock_t netlock;
274
275 #if SYNCLINK_GENERIC_HDLC
276 struct net_device *netdev;
277 #endif
278
279 } SLMP_INFO;
280
281 #define MGSL_MAGIC 0x5401
282
283 /*
284 * define serial signal status change macros
285 */
286 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
287 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
288 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
289 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
290
291 /* Common Register macros */
292 #define LPR 0x00
293 #define PABR0 0x02
294 #define PABR1 0x03
295 #define WCRL 0x04
296 #define WCRM 0x05
297 #define WCRH 0x06
298 #define DPCR 0x08
299 #define DMER 0x09
300 #define ISR0 0x10
301 #define ISR1 0x11
302 #define ISR2 0x12
303 #define IER0 0x14
304 #define IER1 0x15
305 #define IER2 0x16
306 #define ITCR 0x18
307 #define INTVR 0x1a
308 #define IMVR 0x1c
309
310 /* MSCI Register macros */
311 #define TRB 0x20
312 #define TRBL 0x20
313 #define TRBH 0x21
314 #define SR0 0x22
315 #define SR1 0x23
316 #define SR2 0x24
317 #define SR3 0x25
318 #define FST 0x26
319 #define IE0 0x28
320 #define IE1 0x29
321 #define IE2 0x2a
322 #define FIE 0x2b
323 #define CMD 0x2c
324 #define MD0 0x2e
325 #define MD1 0x2f
326 #define MD2 0x30
327 #define CTL 0x31
328 #define SA0 0x32
329 #define SA1 0x33
330 #define IDL 0x34
331 #define TMC 0x35
332 #define RXS 0x36
333 #define TXS 0x37
334 #define TRC0 0x38
335 #define TRC1 0x39
336 #define RRC 0x3a
337 #define CST0 0x3c
338 #define CST1 0x3d
339
340 /* Timer Register Macros */
341 #define TCNT 0x60
342 #define TCNTL 0x60
343 #define TCNTH 0x61
344 #define TCONR 0x62
345 #define TCONRL 0x62
346 #define TCONRH 0x63
347 #define TMCS 0x64
348 #define TEPR 0x65
349
350 /* DMA Controller Register macros */
351 #define DARL 0x80
352 #define DARH 0x81
353 #define DARB 0x82
354 #define BAR 0x80
355 #define BARL 0x80
356 #define BARH 0x81
357 #define BARB 0x82
358 #define SAR 0x84
359 #define SARL 0x84
360 #define SARH 0x85
361 #define SARB 0x86
362 #define CPB 0x86
363 #define CDA 0x88
364 #define CDAL 0x88
365 #define CDAH 0x89
366 #define EDA 0x8a
367 #define EDAL 0x8a
368 #define EDAH 0x8b
369 #define BFL 0x8c
370 #define BFLL 0x8c
371 #define BFLH 0x8d
372 #define BCR 0x8e
373 #define BCRL 0x8e
374 #define BCRH 0x8f
375 #define DSR 0x90
376 #define DMR 0x91
377 #define FCT 0x93
378 #define DIR 0x94
379 #define DCMD 0x95
380
381 /* combine with timer or DMA register address */
382 #define TIMER0 0x00
383 #define TIMER1 0x08
384 #define TIMER2 0x10
385 #define TIMER3 0x18
386 #define RXDMA 0x00
387 #define TXDMA 0x20
388
389 /* SCA Command Codes */
390 #define NOOP 0x00
391 #define TXRESET 0x01
392 #define TXENABLE 0x02
393 #define TXDISABLE 0x03
394 #define TXCRCINIT 0x04
395 #define TXCRCEXCL 0x05
396 #define TXEOM 0x06
397 #define TXABORT 0x07
398 #define MPON 0x08
399 #define TXBUFCLR 0x09
400 #define RXRESET 0x11
401 #define RXENABLE 0x12
402 #define RXDISABLE 0x13
403 #define RXCRCINIT 0x14
404 #define RXREJECT 0x15
405 #define SEARCHMP 0x16
406 #define RXCRCEXCL 0x17
407 #define RXCRCCALC 0x18
408 #define CHRESET 0x21
409 #define HUNT 0x31
410
411 /* DMA command codes */
412 #define SWABORT 0x01
413 #define FEICLEAR 0x02
414
415 /* IE0 */
416 #define TXINTE BIT7
417 #define RXINTE BIT6
418 #define TXRDYE BIT1
419 #define RXRDYE BIT0
420
421 /* IE1 & SR1 */
422 #define UDRN BIT7
423 #define IDLE BIT6
424 #define SYNCD BIT4
425 #define FLGD BIT4
426 #define CCTS BIT3
427 #define CDCD BIT2
428 #define BRKD BIT1
429 #define ABTD BIT1
430 #define GAPD BIT1
431 #define BRKE BIT0
432 #define IDLD BIT0
433
434 /* IE2 & SR2 */
435 #define EOM BIT7
436 #define PMP BIT6
437 #define SHRT BIT6
438 #define PE BIT5
439 #define ABT BIT5
440 #define FRME BIT4
441 #define RBIT BIT4
442 #define OVRN BIT3
443 #define CRCE BIT2
444
445
446 /*
447 * Global linked list of SyncLink devices
448 */
449 static SLMP_INFO *synclinkmp_device_list = NULL;
450 static int synclinkmp_adapter_count = -1;
451 static int synclinkmp_device_count = 0;
452
453 /*
454 * Set this param to non-zero to load eax with the
455 * .text section address and breakpoint on module load.
456 * This is useful for use with gdb and add-symbol-file command.
457 */
458 static int break_on_load = 0;
459
460 /*
461 * Driver major number, defaults to zero to get auto
462 * assigned major number. May be forced as module parameter.
463 */
464 static int ttymajor = 0;
465
466 /*
467 * Array of user specified options for ISA adapters.
468 */
469 static int debug_level = 0;
470 static int maxframe[MAX_DEVICES] = {0,};
471
472 module_param(break_on_load, bool, 0);
473 module_param(ttymajor, int, 0);
474 module_param(debug_level, int, 0);
475 module_param_array(maxframe, int, NULL, 0);
476
477 static char *driver_name = "SyncLink MultiPort driver";
478 static char *driver_version = "$Revision: 4.38 $";
479
480 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
481 static void synclinkmp_remove_one(struct pci_dev *dev);
482
483 static struct pci_device_id synclinkmp_pci_tbl[] = {
484 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
485 { 0, }, /* terminate list */
486 };
487 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
488
489 MODULE_LICENSE("GPL");
490
491 static struct pci_driver synclinkmp_pci_driver = {
492 .name = "synclinkmp",
493 .id_table = synclinkmp_pci_tbl,
494 .probe = synclinkmp_init_one,
495 .remove = __devexit_p(synclinkmp_remove_one),
496 };
497
498
499 static struct tty_driver *serial_driver;
500
501 /* number of characters left in xmit buffer before we ask for more */
502 #define WAKEUP_CHARS 256
503
504
505 /* tty callbacks */
506
507 static int open(struct tty_struct *tty, struct file * filp);
508 static void close(struct tty_struct *tty, struct file * filp);
509 static void hangup(struct tty_struct *tty);
510 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
511
512 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
513 static int put_char(struct tty_struct *tty, unsigned char ch);
514 static void send_xchar(struct tty_struct *tty, char ch);
515 static void wait_until_sent(struct tty_struct *tty, int timeout);
516 static int write_room(struct tty_struct *tty);
517 static void flush_chars(struct tty_struct *tty);
518 static void flush_buffer(struct tty_struct *tty);
519 static void tx_hold(struct tty_struct *tty);
520 static void tx_release(struct tty_struct *tty);
521
522 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
523 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
524 static int chars_in_buffer(struct tty_struct *tty);
525 static void throttle(struct tty_struct * tty);
526 static void unthrottle(struct tty_struct * tty);
527 static int set_break(struct tty_struct *tty, int break_state);
528
529 #if SYNCLINK_GENERIC_HDLC
530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
531 static void hdlcdev_tx_done(SLMP_INFO *info);
532 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
533 static int hdlcdev_init(SLMP_INFO *info);
534 static void hdlcdev_exit(SLMP_INFO *info);
535 #endif
536
537 /* ioctl handlers */
538
539 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
540 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
541 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
542 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
543 static int set_txidle(SLMP_INFO *info, int idle_mode);
544 static int tx_enable(SLMP_INFO *info, int enable);
545 static int tx_abort(SLMP_INFO *info);
546 static int rx_enable(SLMP_INFO *info, int enable);
547 static int modem_input_wait(SLMP_INFO *info,int arg);
548 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
549 static int tiocmget(struct tty_struct *tty, struct file *file);
550 static int tiocmset(struct tty_struct *tty, struct file *file,
551 unsigned int set, unsigned int clear);
552 static int set_break(struct tty_struct *tty, int break_state);
553
554 static void add_device(SLMP_INFO *info);
555 static void device_init(int adapter_num, struct pci_dev *pdev);
556 static int claim_resources(SLMP_INFO *info);
557 static void release_resources(SLMP_INFO *info);
558
559 static int startup(SLMP_INFO *info);
560 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
561 static int carrier_raised(struct tty_port *port);
562 static void shutdown(SLMP_INFO *info);
563 static void program_hw(SLMP_INFO *info);
564 static void change_params(SLMP_INFO *info);
565
566 static bool init_adapter(SLMP_INFO *info);
567 static bool register_test(SLMP_INFO *info);
568 static bool irq_test(SLMP_INFO *info);
569 static bool loopback_test(SLMP_INFO *info);
570 static int adapter_test(SLMP_INFO *info);
571 static bool memory_test(SLMP_INFO *info);
572
573 static void reset_adapter(SLMP_INFO *info);
574 static void reset_port(SLMP_INFO *info);
575 static void async_mode(SLMP_INFO *info);
576 static void hdlc_mode(SLMP_INFO *info);
577
578 static void rx_stop(SLMP_INFO *info);
579 static void rx_start(SLMP_INFO *info);
580 static void rx_reset_buffers(SLMP_INFO *info);
581 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
582 static bool rx_get_frame(SLMP_INFO *info);
583
584 static void tx_start(SLMP_INFO *info);
585 static void tx_stop(SLMP_INFO *info);
586 static void tx_load_fifo(SLMP_INFO *info);
587 static void tx_set_idle(SLMP_INFO *info);
588 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
589
590 static void get_signals(SLMP_INFO *info);
591 static void set_signals(SLMP_INFO *info);
592 static void enable_loopback(SLMP_INFO *info, int enable);
593 static void set_rate(SLMP_INFO *info, u32 data_rate);
594
595 static int bh_action(SLMP_INFO *info);
596 static void bh_handler(struct work_struct *work);
597 static void bh_receive(SLMP_INFO *info);
598 static void bh_transmit(SLMP_INFO *info);
599 static void bh_status(SLMP_INFO *info);
600 static void isr_timer(SLMP_INFO *info);
601 static void isr_rxint(SLMP_INFO *info);
602 static void isr_rxrdy(SLMP_INFO *info);
603 static void isr_txint(SLMP_INFO *info);
604 static void isr_txrdy(SLMP_INFO *info);
605 static void isr_rxdmaok(SLMP_INFO *info);
606 static void isr_rxdmaerror(SLMP_INFO *info);
607 static void isr_txdmaok(SLMP_INFO *info);
608 static void isr_txdmaerror(SLMP_INFO *info);
609 static void isr_io_pin(SLMP_INFO *info, u16 status);
610
611 static int alloc_dma_bufs(SLMP_INFO *info);
612 static void free_dma_bufs(SLMP_INFO *info);
613 static int alloc_buf_list(SLMP_INFO *info);
614 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
615 static int alloc_tmp_rx_buf(SLMP_INFO *info);
616 static void free_tmp_rx_buf(SLMP_INFO *info);
617
618 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
619 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
620 static void tx_timeout(unsigned long context);
621 static void status_timeout(unsigned long context);
622
623 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
624 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
625 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
626 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
627 static unsigned char read_status_reg(SLMP_INFO * info);
628 static void write_control_reg(SLMP_INFO * info);
629
630
631 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
632 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
633 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
634
635 static u32 misc_ctrl_value = 0x007e4040;
636 static u32 lcr1_brdr_value = 0x00800028;
637
638 static u32 read_ahead_count = 8;
639
640 /* DPCR, DMA Priority Control
641 *
642 * 07..05 Not used, must be 0
643 * 04 BRC, bus release condition: 0=all transfers complete
644 * 1=release after 1 xfer on all channels
645 * 03 CCC, channel change condition: 0=every cycle
646 * 1=after each channel completes all xfers
647 * 02..00 PR<2..0>, priority 100=round robin
648 *
649 * 00000100 = 0x00
650 */
651 static unsigned char dma_priority = 0x04;
652
653 // Number of bytes that can be written to shared RAM
654 // in a single write operation
655 static u32 sca_pci_load_interval = 64;
656
657 /*
658 * 1st function defined in .text section. Calling this function in
659 * init_module() followed by a breakpoint allows a remote debugger
660 * (gdb) to get the .text address for the add-symbol-file command.
661 * This allows remote debugging of dynamically loadable modules.
662 */
663 static void* synclinkmp_get_text_ptr(void);
664 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
665
666 static inline int sanity_check(SLMP_INFO *info,
667 char *name, const char *routine)
668 {
669 #ifdef SANITY_CHECK
670 static const char *badmagic =
671 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
672 static const char *badinfo =
673 "Warning: null synclinkmp_struct for (%s) in %s\n";
674
675 if (!info) {
676 printk(badinfo, name, routine);
677 return 1;
678 }
679 if (info->magic != MGSL_MAGIC) {
680 printk(badmagic, name, routine);
681 return 1;
682 }
683 #else
684 if (!info)
685 return 1;
686 #endif
687 return 0;
688 }
689
690 /**
691 * line discipline callback wrappers
692 *
693 * The wrappers maintain line discipline references
694 * while calling into the line discipline.
695 *
696 * ldisc_receive_buf - pass receive data to line discipline
697 */
698
699 static void ldisc_receive_buf(struct tty_struct *tty,
700 const __u8 *data, char *flags, int count)
701 {
702 struct tty_ldisc *ld;
703 if (!tty)
704 return;
705 ld = tty_ldisc_ref(tty);
706 if (ld) {
707 if (ld->ops->receive_buf)
708 ld->ops->receive_buf(tty, data, flags, count);
709 tty_ldisc_deref(ld);
710 }
711 }
712
713 /* tty callbacks */
714
715 /* Called when a port is opened. Init and enable port.
716 */
717 static int open(struct tty_struct *tty, struct file *filp)
718 {
719 SLMP_INFO *info;
720 int retval, line;
721 unsigned long flags;
722
723 line = tty->index;
724 if ((line < 0) || (line >= synclinkmp_device_count)) {
725 printk("%s(%d): open with invalid line #%d.\n",
726 __FILE__,__LINE__,line);
727 return -ENODEV;
728 }
729
730 info = synclinkmp_device_list;
731 while(info && info->line != line)
732 info = info->next_device;
733 if (sanity_check(info, tty->name, "open"))
734 return -ENODEV;
735 if ( info->init_error ) {
736 printk("%s(%d):%s device is not allocated, init error=%d\n",
737 __FILE__,__LINE__,info->device_name,info->init_error);
738 return -ENODEV;
739 }
740
741 tty->driver_data = info;
742 info->port.tty = tty;
743
744 if (debug_level >= DEBUG_LEVEL_INFO)
745 printk("%s(%d):%s open(), old ref count = %d\n",
746 __FILE__,__LINE__,tty->driver->name, info->port.count);
747
748 /* If port is closing, signal caller to try again */
749 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
750 if (info->port.flags & ASYNC_CLOSING)
751 interruptible_sleep_on(&info->port.close_wait);
752 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
753 -EAGAIN : -ERESTARTSYS);
754 goto cleanup;
755 }
756
757 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
758
759 spin_lock_irqsave(&info->netlock, flags);
760 if (info->netcount) {
761 retval = -EBUSY;
762 spin_unlock_irqrestore(&info->netlock, flags);
763 goto cleanup;
764 }
765 info->port.count++;
766 spin_unlock_irqrestore(&info->netlock, flags);
767
768 if (info->port.count == 1) {
769 /* 1st open on this device, init hardware */
770 retval = startup(info);
771 if (retval < 0)
772 goto cleanup;
773 }
774
775 retval = block_til_ready(tty, filp, info);
776 if (retval) {
777 if (debug_level >= DEBUG_LEVEL_INFO)
778 printk("%s(%d):%s block_til_ready() returned %d\n",
779 __FILE__,__LINE__, info->device_name, retval);
780 goto cleanup;
781 }
782
783 if (debug_level >= DEBUG_LEVEL_INFO)
784 printk("%s(%d):%s open() success\n",
785 __FILE__,__LINE__, info->device_name);
786 retval = 0;
787
788 cleanup:
789 if (retval) {
790 if (tty->count == 1)
791 info->port.tty = NULL; /* tty layer will release tty struct */
792 if(info->port.count)
793 info->port.count--;
794 }
795
796 return retval;
797 }
798
799 /* Called when port is closed. Wait for remaining data to be
800 * sent. Disable port and free resources.
801 */
802 static void close(struct tty_struct *tty, struct file *filp)
803 {
804 SLMP_INFO * info = tty->driver_data;
805
806 if (sanity_check(info, tty->name, "close"))
807 return;
808
809 if (debug_level >= DEBUG_LEVEL_INFO)
810 printk("%s(%d):%s close() entry, count=%d\n",
811 __FILE__,__LINE__, info->device_name, info->port.count);
812
813 if (tty_port_close_start(&info->port, tty, filp) == 0)
814 goto cleanup;
815
816 if (info->port.flags & ASYNC_INITIALIZED)
817 wait_until_sent(tty, info->timeout);
818
819 flush_buffer(tty);
820 tty_ldisc_flush(tty);
821 shutdown(info);
822
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
825 cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
829 }
830
831 /* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
833 */
834 static void hangup(struct tty_struct *tty)
835 {
836 SLMP_INFO *info = tty->driver_data;
837
838 if (debug_level >= DEBUG_LEVEL_INFO)
839 printk("%s(%d):%s hangup()\n",
840 __FILE__,__LINE__, info->device_name );
841
842 if (sanity_check(info, tty->name, "hangup"))
843 return;
844
845 flush_buffer(tty);
846 shutdown(info);
847
848 info->port.count = 0;
849 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
850 info->port.tty = NULL;
851
852 wake_up_interruptible(&info->port.open_wait);
853 }
854
855 /* Set new termios settings
856 */
857 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
858 {
859 SLMP_INFO *info = tty->driver_data;
860 unsigned long flags;
861
862 if (debug_level >= DEBUG_LEVEL_INFO)
863 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
864 tty->driver->name );
865
866 change_params(info);
867
868 /* Handle transition to B0 status */
869 if (old_termios->c_cflag & CBAUD &&
870 !(tty->termios->c_cflag & CBAUD)) {
871 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
872 spin_lock_irqsave(&info->lock,flags);
873 set_signals(info);
874 spin_unlock_irqrestore(&info->lock,flags);
875 }
876
877 /* Handle transition away from B0 status */
878 if (!(old_termios->c_cflag & CBAUD) &&
879 tty->termios->c_cflag & CBAUD) {
880 info->serial_signals |= SerialSignal_DTR;
881 if (!(tty->termios->c_cflag & CRTSCTS) ||
882 !test_bit(TTY_THROTTLED, &tty->flags)) {
883 info->serial_signals |= SerialSignal_RTS;
884 }
885 spin_lock_irqsave(&info->lock,flags);
886 set_signals(info);
887 spin_unlock_irqrestore(&info->lock,flags);
888 }
889
890 /* Handle turning off CRTSCTS */
891 if (old_termios->c_cflag & CRTSCTS &&
892 !(tty->termios->c_cflag & CRTSCTS)) {
893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896 }
897
898 /* Send a block of data
899 *
900 * Arguments:
901 *
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
905 *
906 * Return Value: number of characters written
907 */
908 static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910 {
911 int c, ret = 0;
912 SLMP_INFO *info = tty->driver_data;
913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
922 if (!info->tx_buf)
923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971 start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979 cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984 }
985
986 /* Add a character to the transmit buffer.
987 */
988 static int put_char(struct tty_struct *tty, unsigned char ch)
989 {
990 SLMP_INFO *info = tty->driver_data;
991 unsigned long flags;
992 int ret = 0;
993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
1000 return 0;
1001
1002 if (!info->tx_buf)
1003 return 0;
1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
1015 ret = 1;
1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
1020 return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024 */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048 */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
1064 lock_kernel();
1065
1066 if (!(info->port.flags & ASYNC_INITIALIZED))
1067 goto exit;
1068
1069 orig_jiffies = jiffies;
1070
1071 /* Set check interval to 1/5 of estimated time to
1072 * send a character, and make it at least 1. The check
1073 * interval should also be less than the timeout.
1074 * Note: use tight timings here to satisfy the NIST-PCTS.
1075 */
1076
1077 if ( info->params.data_rate ) {
1078 char_time = info->timeout/(32 * 5);
1079 if (!char_time)
1080 char_time++;
1081 } else
1082 char_time = 1;
1083
1084 if (timeout)
1085 char_time = min_t(unsigned long, char_time, timeout);
1086
1087 if ( info->params.mode == MGSL_MODE_HDLC ) {
1088 while (info->tx_active) {
1089 msleep_interruptible(jiffies_to_msecs(char_time));
1090 if (signal_pending(current))
1091 break;
1092 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1093 break;
1094 }
1095 } else {
1096 //TODO: determine if there is something similar to USC16C32
1097 // TXSTATUS_ALL_SENT status
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107 exit:
1108 unlock_kernel();
1109 if (debug_level >= DEBUG_LEVEL_INFO)
1110 printk("%s(%d):%s wait_until_sent() exit\n",
1111 __FILE__,__LINE__, info->device_name );
1112 }
1113
1114 /* Return the count of free bytes in transmit buffer
1115 */
1116 static int write_room(struct tty_struct *tty)
1117 {
1118 SLMP_INFO *info = tty->driver_data;
1119 int ret;
1120
1121 if (sanity_check(info, tty->name, "write_room"))
1122 return 0;
1123
1124 lock_kernel();
1125 if (info->params.mode == MGSL_MODE_HDLC) {
1126 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1127 } else {
1128 ret = info->max_frame_size - info->tx_count - 1;
1129 if (ret < 0)
1130 ret = 0;
1131 }
1132 unlock_kernel();
1133
1134 if (debug_level >= DEBUG_LEVEL_INFO)
1135 printk("%s(%d):%s write_room()=%d\n",
1136 __FILE__, __LINE__, info->device_name, ret);
1137
1138 return ret;
1139 }
1140
1141 /* enable transmitter and send remaining buffered characters
1142 */
1143 static void flush_chars(struct tty_struct *tty)
1144 {
1145 SLMP_INFO *info = tty->driver_data;
1146 unsigned long flags;
1147
1148 if ( debug_level >= DEBUG_LEVEL_INFO )
1149 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1150 __FILE__,__LINE__,info->device_name,info->tx_count);
1151
1152 if (sanity_check(info, tty->name, "flush_chars"))
1153 return;
1154
1155 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1156 !info->tx_buf)
1157 return;
1158
1159 if ( debug_level >= DEBUG_LEVEL_INFO )
1160 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1161 __FILE__,__LINE__,info->device_name );
1162
1163 spin_lock_irqsave(&info->lock,flags);
1164
1165 if (!info->tx_active) {
1166 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1167 info->tx_count ) {
1168 /* operating in synchronous (frame oriented) mode */
1169 /* copy data from circular tx_buf to */
1170 /* transmit DMA buffer. */
1171 tx_load_dma_buffer(info,
1172 info->tx_buf,info->tx_count);
1173 }
1174 tx_start(info);
1175 }
1176
1177 spin_unlock_irqrestore(&info->lock,flags);
1178 }
1179
1180 /* Discard all data in the send buffer
1181 */
1182 static void flush_buffer(struct tty_struct *tty)
1183 {
1184 SLMP_INFO *info = tty->driver_data;
1185 unsigned long flags;
1186
1187 if (debug_level >= DEBUG_LEVEL_INFO)
1188 printk("%s(%d):%s flush_buffer() entry\n",
1189 __FILE__,__LINE__, info->device_name );
1190
1191 if (sanity_check(info, tty->name, "flush_buffer"))
1192 return;
1193
1194 spin_lock_irqsave(&info->lock,flags);
1195 info->tx_count = info->tx_put = info->tx_get = 0;
1196 del_timer(&info->tx_timer);
1197 spin_unlock_irqrestore(&info->lock,flags);
1198
1199 tty_wakeup(tty);
1200 }
1201
1202 /* throttle (stop) transmitter
1203 */
1204 static void tx_hold(struct tty_struct *tty)
1205 {
1206 SLMP_INFO *info = tty->driver_data;
1207 unsigned long flags;
1208
1209 if (sanity_check(info, tty->name, "tx_hold"))
1210 return;
1211
1212 if ( debug_level >= DEBUG_LEVEL_INFO )
1213 printk("%s(%d):%s tx_hold()\n",
1214 __FILE__,__LINE__,info->device_name);
1215
1216 spin_lock_irqsave(&info->lock,flags);
1217 if (info->tx_enabled)
1218 tx_stop(info);
1219 spin_unlock_irqrestore(&info->lock,flags);
1220 }
1221
1222 /* release (start) transmitter
1223 */
1224 static void tx_release(struct tty_struct *tty)
1225 {
1226 SLMP_INFO *info = tty->driver_data;
1227 unsigned long flags;
1228
1229 if (sanity_check(info, tty->name, "tx_release"))
1230 return;
1231
1232 if ( debug_level >= DEBUG_LEVEL_INFO )
1233 printk("%s(%d):%s tx_release()\n",
1234 __FILE__,__LINE__,info->device_name);
1235
1236 spin_lock_irqsave(&info->lock,flags);
1237 if (!info->tx_enabled)
1238 tx_start(info);
1239 spin_unlock_irqrestore(&info->lock,flags);
1240 }
1241
1242 /* Service an IOCTL request
1243 *
1244 * Arguments:
1245 *
1246 * tty pointer to tty instance data
1247 * file pointer to associated file object for device
1248 * cmd IOCTL command code
1249 * arg command argument/context
1250 *
1251 * Return Value: 0 if success, otherwise error code
1252 */
1253 static int do_ioctl(struct tty_struct *tty, struct file *file,
1254 unsigned int cmd, unsigned long arg)
1255 {
1256 SLMP_INFO *info = tty->driver_data;
1257 int error;
1258 struct mgsl_icount cnow; /* kernel counter temps */
1259 struct serial_icounter_struct __user *p_cuser; /* user space */
1260 unsigned long flags;
1261 void __user *argp = (void __user *)arg;
1262
1263 if (debug_level >= DEBUG_LEVEL_INFO)
1264 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1265 info->device_name, cmd );
1266
1267 if (sanity_check(info, tty->name, "ioctl"))
1268 return -ENODEV;
1269
1270 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1271 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1272 if (tty->flags & (1 << TTY_IO_ERROR))
1273 return -EIO;
1274 }
1275
1276 switch (cmd) {
1277 case MGSL_IOCGPARAMS:
1278 return get_params(info, argp);
1279 case MGSL_IOCSPARAMS:
1280 return set_params(info, argp);
1281 case MGSL_IOCGTXIDLE:
1282 return get_txidle(info, argp);
1283 case MGSL_IOCSTXIDLE:
1284 return set_txidle(info, (int)arg);
1285 case MGSL_IOCTXENABLE:
1286 return tx_enable(info, (int)arg);
1287 case MGSL_IOCRXENABLE:
1288 return rx_enable(info, (int)arg);
1289 case MGSL_IOCTXABORT:
1290 return tx_abort(info);
1291 case MGSL_IOCGSTATS:
1292 return get_stats(info, argp);
1293 case MGSL_IOCWAITEVENT:
1294 return wait_mgsl_event(info, argp);
1295 case MGSL_IOCLOOPTXDONE:
1296 return 0; // TODO: Not supported, need to document
1297 /* Wait for modem input (DCD,RI,DSR,CTS) change
1298 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1299 */
1300 case TIOCMIWAIT:
1301 return modem_input_wait(info,(int)arg);
1302
1303 /*
1304 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1305 * Return: write counters to the user passed counter struct
1306 * NB: both 1->0 and 0->1 transitions are counted except for
1307 * RI where only 0->1 is counted.
1308 */
1309 case TIOCGICOUNT:
1310 spin_lock_irqsave(&info->lock,flags);
1311 cnow = info->icount;
1312 spin_unlock_irqrestore(&info->lock,flags);
1313 p_cuser = argp;
1314 PUT_USER(error,cnow.cts, &p_cuser->cts);
1315 if (error) return error;
1316 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1317 if (error) return error;
1318 PUT_USER(error,cnow.rng, &p_cuser->rng);
1319 if (error) return error;
1320 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1321 if (error) return error;
1322 PUT_USER(error,cnow.rx, &p_cuser->rx);
1323 if (error) return error;
1324 PUT_USER(error,cnow.tx, &p_cuser->tx);
1325 if (error) return error;
1326 PUT_USER(error,cnow.frame, &p_cuser->frame);
1327 if (error) return error;
1328 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1329 if (error) return error;
1330 PUT_USER(error,cnow.parity, &p_cuser->parity);
1331 if (error) return error;
1332 PUT_USER(error,cnow.brk, &p_cuser->brk);
1333 if (error) return error;
1334 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1335 if (error) return error;
1336 return 0;
1337 default:
1338 return -ENOIOCTLCMD;
1339 }
1340 return 0;
1341 }
1342
1343 static int ioctl(struct tty_struct *tty, struct file *file,
1344 unsigned int cmd, unsigned long arg)
1345 {
1346 int ret;
1347 lock_kernel();
1348 ret = do_ioctl(tty, file, cmd, arg);
1349 unlock_kernel();
1350 return ret;
1351 }
1352
1353 /*
1354 * /proc fs routines....
1355 */
1356
1357 static inline int line_info(char *buf, SLMP_INFO *info)
1358 {
1359 char stat_buf[30];
1360 int ret;
1361 unsigned long flags;
1362
1363 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1364 "\tIRQ=%d MaxFrameSize=%u\n",
1365 info->device_name,
1366 info->phys_sca_base,
1367 info->phys_memory_base,
1368 info->phys_statctrl_base,
1369 info->phys_lcr_base,
1370 info->irq_level,
1371 info->max_frame_size );
1372
1373 /* output current serial signal states */
1374 spin_lock_irqsave(&info->lock,flags);
1375 get_signals(info);
1376 spin_unlock_irqrestore(&info->lock,flags);
1377
1378 stat_buf[0] = 0;
1379 stat_buf[1] = 0;
1380 if (info->serial_signals & SerialSignal_RTS)
1381 strcat(stat_buf, "|RTS");
1382 if (info->serial_signals & SerialSignal_CTS)
1383 strcat(stat_buf, "|CTS");
1384 if (info->serial_signals & SerialSignal_DTR)
1385 strcat(stat_buf, "|DTR");
1386 if (info->serial_signals & SerialSignal_DSR)
1387 strcat(stat_buf, "|DSR");
1388 if (info->serial_signals & SerialSignal_DCD)
1389 strcat(stat_buf, "|CD");
1390 if (info->serial_signals & SerialSignal_RI)
1391 strcat(stat_buf, "|RI");
1392
1393 if (info->params.mode == MGSL_MODE_HDLC) {
1394 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1395 info->icount.txok, info->icount.rxok);
1396 if (info->icount.txunder)
1397 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1398 if (info->icount.txabort)
1399 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1400 if (info->icount.rxshort)
1401 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1402 if (info->icount.rxlong)
1403 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1404 if (info->icount.rxover)
1405 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1406 if (info->icount.rxcrc)
1407 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1408 } else {
1409 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1410 info->icount.tx, info->icount.rx);
1411 if (info->icount.frame)
1412 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1413 if (info->icount.parity)
1414 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1415 if (info->icount.brk)
1416 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1417 if (info->icount.overrun)
1418 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1419 }
1420
1421 /* Append serial signal status to end */
1422 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1423
1424 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1425 info->tx_active,info->bh_requested,info->bh_running,
1426 info->pending_bh);
1427
1428 return ret;
1429 }
1430
1431 /* Called to print information about devices
1432 */
1433 static int read_proc(char *page, char **start, off_t off, int count,
1434 int *eof, void *data)
1435 {
1436 int len = 0, l;
1437 off_t begin = 0;
1438 SLMP_INFO *info;
1439
1440 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1441
1442 info = synclinkmp_device_list;
1443 while( info ) {
1444 l = line_info(page + len, info);
1445 len += l;
1446 if (len+begin > off+count)
1447 goto done;
1448 if (len+begin < off) {
1449 begin += len;
1450 len = 0;
1451 }
1452 info = info->next_device;
1453 }
1454
1455 *eof = 1;
1456 done:
1457 if (off >= len+begin)
1458 return 0;
1459 *start = page + (off-begin);
1460 return ((count < begin+len-off) ? count : begin+len-off);
1461 }
1462
1463 /* Return the count of bytes in transmit buffer
1464 */
1465 static int chars_in_buffer(struct tty_struct *tty)
1466 {
1467 SLMP_INFO *info = tty->driver_data;
1468
1469 if (sanity_check(info, tty->name, "chars_in_buffer"))
1470 return 0;
1471
1472 if (debug_level >= DEBUG_LEVEL_INFO)
1473 printk("%s(%d):%s chars_in_buffer()=%d\n",
1474 __FILE__, __LINE__, info->device_name, info->tx_count);
1475
1476 return info->tx_count;
1477 }
1478
1479 /* Signal remote device to throttle send data (our receive data)
1480 */
1481 static void throttle(struct tty_struct * tty)
1482 {
1483 SLMP_INFO *info = tty->driver_data;
1484 unsigned long flags;
1485
1486 if (debug_level >= DEBUG_LEVEL_INFO)
1487 printk("%s(%d):%s throttle() entry\n",
1488 __FILE__,__LINE__, info->device_name );
1489
1490 if (sanity_check(info, tty->name, "throttle"))
1491 return;
1492
1493 if (I_IXOFF(tty))
1494 send_xchar(tty, STOP_CHAR(tty));
1495
1496 if (tty->termios->c_cflag & CRTSCTS) {
1497 spin_lock_irqsave(&info->lock,flags);
1498 info->serial_signals &= ~SerialSignal_RTS;
1499 set_signals(info);
1500 spin_unlock_irqrestore(&info->lock,flags);
1501 }
1502 }
1503
1504 /* Signal remote device to stop throttling send data (our receive data)
1505 */
1506 static void unthrottle(struct tty_struct * tty)
1507 {
1508 SLMP_INFO *info = tty->driver_data;
1509 unsigned long flags;
1510
1511 if (debug_level >= DEBUG_LEVEL_INFO)
1512 printk("%s(%d):%s unthrottle() entry\n",
1513 __FILE__,__LINE__, info->device_name );
1514
1515 if (sanity_check(info, tty->name, "unthrottle"))
1516 return;
1517
1518 if (I_IXOFF(tty)) {
1519 if (info->x_char)
1520 info->x_char = 0;
1521 else
1522 send_xchar(tty, START_CHAR(tty));
1523 }
1524
1525 if (tty->termios->c_cflag & CRTSCTS) {
1526 spin_lock_irqsave(&info->lock,flags);
1527 info->serial_signals |= SerialSignal_RTS;
1528 set_signals(info);
1529 spin_unlock_irqrestore(&info->lock,flags);
1530 }
1531 }
1532
1533 /* set or clear transmit break condition
1534 * break_state -1=set break condition, 0=clear
1535 */
1536 static int set_break(struct tty_struct *tty, int break_state)
1537 {
1538 unsigned char RegValue;
1539 SLMP_INFO * info = tty->driver_data;
1540 unsigned long flags;
1541
1542 if (debug_level >= DEBUG_LEVEL_INFO)
1543 printk("%s(%d):%s set_break(%d)\n",
1544 __FILE__,__LINE__, info->device_name, break_state);
1545
1546 if (sanity_check(info, tty->name, "set_break"))
1547 return -EINVAL;
1548
1549 spin_lock_irqsave(&info->lock,flags);
1550 RegValue = read_reg(info, CTL);
1551 if (break_state == -1)
1552 RegValue |= BIT3;
1553 else
1554 RegValue &= ~BIT3;
1555 write_reg(info, CTL, RegValue);
1556 spin_unlock_irqrestore(&info->lock,flags);
1557 return 0;
1558 }
1559
1560 #if SYNCLINK_GENERIC_HDLC
1561
1562 /**
1563 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1564 * set encoding and frame check sequence (FCS) options
1565 *
1566 * dev pointer to network device structure
1567 * encoding serial encoding setting
1568 * parity FCS setting
1569 *
1570 * returns 0 if success, otherwise error code
1571 */
1572 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1573 unsigned short parity)
1574 {
1575 SLMP_INFO *info = dev_to_port(dev);
1576 unsigned char new_encoding;
1577 unsigned short new_crctype;
1578
1579 /* return error if TTY interface open */
1580 if (info->port.count)
1581 return -EBUSY;
1582
1583 switch (encoding)
1584 {
1585 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1586 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1587 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1588 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1589 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1590 default: return -EINVAL;
1591 }
1592
1593 switch (parity)
1594 {
1595 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1596 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1597 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1598 default: return -EINVAL;
1599 }
1600
1601 info->params.encoding = new_encoding;
1602 info->params.crc_type = new_crctype;
1603
1604 /* if network interface up, reprogram hardware */
1605 if (info->netcount)
1606 program_hw(info);
1607
1608 return 0;
1609 }
1610
1611 /**
1612 * called by generic HDLC layer to send frame
1613 *
1614 * skb socket buffer containing HDLC frame
1615 * dev pointer to network device structure
1616 *
1617 * returns 0 if success, otherwise error code
1618 */
1619 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1620 {
1621 SLMP_INFO *info = dev_to_port(dev);
1622 unsigned long flags;
1623
1624 if (debug_level >= DEBUG_LEVEL_INFO)
1625 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1626
1627 /* stop sending until this frame completes */
1628 netif_stop_queue(dev);
1629
1630 /* copy data to device buffers */
1631 info->tx_count = skb->len;
1632 tx_load_dma_buffer(info, skb->data, skb->len);
1633
1634 /* update network statistics */
1635 dev->stats.tx_packets++;
1636 dev->stats.tx_bytes += skb->len;
1637
1638 /* done with socket buffer, so free it */
1639 dev_kfree_skb(skb);
1640
1641 /* save start time for transmit timeout detection */
1642 dev->trans_start = jiffies;
1643
1644 /* start hardware transmitter if necessary */
1645 spin_lock_irqsave(&info->lock,flags);
1646 if (!info->tx_active)
1647 tx_start(info);
1648 spin_unlock_irqrestore(&info->lock,flags);
1649
1650 return 0;
1651 }
1652
1653 /**
1654 * called by network layer when interface enabled
1655 * claim resources and initialize hardware
1656 *
1657 * dev pointer to network device structure
1658 *
1659 * returns 0 if success, otherwise error code
1660 */
1661 static int hdlcdev_open(struct net_device *dev)
1662 {
1663 SLMP_INFO *info = dev_to_port(dev);
1664 int rc;
1665 unsigned long flags;
1666
1667 if (debug_level >= DEBUG_LEVEL_INFO)
1668 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1669
1670 /* generic HDLC layer open processing */
1671 if ((rc = hdlc_open(dev)))
1672 return rc;
1673
1674 /* arbitrate between network and tty opens */
1675 spin_lock_irqsave(&info->netlock, flags);
1676 if (info->port.count != 0 || info->netcount != 0) {
1677 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1678 spin_unlock_irqrestore(&info->netlock, flags);
1679 return -EBUSY;
1680 }
1681 info->netcount=1;
1682 spin_unlock_irqrestore(&info->netlock, flags);
1683
1684 /* claim resources and init adapter */
1685 if ((rc = startup(info)) != 0) {
1686 spin_lock_irqsave(&info->netlock, flags);
1687 info->netcount=0;
1688 spin_unlock_irqrestore(&info->netlock, flags);
1689 return rc;
1690 }
1691
1692 /* assert DTR and RTS, apply hardware settings */
1693 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1694 program_hw(info);
1695
1696 /* enable network layer transmit */
1697 dev->trans_start = jiffies;
1698 netif_start_queue(dev);
1699
1700 /* inform generic HDLC layer of current DCD status */
1701 spin_lock_irqsave(&info->lock, flags);
1702 get_signals(info);
1703 spin_unlock_irqrestore(&info->lock, flags);
1704 if (info->serial_signals & SerialSignal_DCD)
1705 netif_carrier_on(dev);
1706 else
1707 netif_carrier_off(dev);
1708 return 0;
1709 }
1710
1711 /**
1712 * called by network layer when interface is disabled
1713 * shutdown hardware and release resources
1714 *
1715 * dev pointer to network device structure
1716 *
1717 * returns 0 if success, otherwise error code
1718 */
1719 static int hdlcdev_close(struct net_device *dev)
1720 {
1721 SLMP_INFO *info = dev_to_port(dev);
1722 unsigned long flags;
1723
1724 if (debug_level >= DEBUG_LEVEL_INFO)
1725 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1726
1727 netif_stop_queue(dev);
1728
1729 /* shutdown adapter and release resources */
1730 shutdown(info);
1731
1732 hdlc_close(dev);
1733
1734 spin_lock_irqsave(&info->netlock, flags);
1735 info->netcount=0;
1736 spin_unlock_irqrestore(&info->netlock, flags);
1737
1738 return 0;
1739 }
1740
1741 /**
1742 * called by network layer to process IOCTL call to network device
1743 *
1744 * dev pointer to network device structure
1745 * ifr pointer to network interface request structure
1746 * cmd IOCTL command code
1747 *
1748 * returns 0 if success, otherwise error code
1749 */
1750 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1751 {
1752 const size_t size = sizeof(sync_serial_settings);
1753 sync_serial_settings new_line;
1754 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1755 SLMP_INFO *info = dev_to_port(dev);
1756 unsigned int flags;
1757
1758 if (debug_level >= DEBUG_LEVEL_INFO)
1759 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1760
1761 /* return error if TTY interface open */
1762 if (info->port.count)
1763 return -EBUSY;
1764
1765 if (cmd != SIOCWANDEV)
1766 return hdlc_ioctl(dev, ifr, cmd);
1767
1768 switch(ifr->ifr_settings.type) {
1769 case IF_GET_IFACE: /* return current sync_serial_settings */
1770
1771 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1772 if (ifr->ifr_settings.size < size) {
1773 ifr->ifr_settings.size = size; /* data size wanted */
1774 return -ENOBUFS;
1775 }
1776
1777 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1778 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1779 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1780 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1781
1782 switch (flags){
1783 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1784 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1785 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1786 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1787 default: new_line.clock_type = CLOCK_DEFAULT;
1788 }
1789
1790 new_line.clock_rate = info->params.clock_speed;
1791 new_line.loopback = info->params.loopback ? 1:0;
1792
1793 if (copy_to_user(line, &new_line, size))
1794 return -EFAULT;
1795 return 0;
1796
1797 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1798
1799 if(!capable(CAP_NET_ADMIN))
1800 return -EPERM;
1801 if (copy_from_user(&new_line, line, size))
1802 return -EFAULT;
1803
1804 switch (new_line.clock_type)
1805 {
1806 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1807 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1808 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1809 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1810 case CLOCK_DEFAULT: flags = info->params.flags &
1811 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1812 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1813 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1814 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1815 default: return -EINVAL;
1816 }
1817
1818 if (new_line.loopback != 0 && new_line.loopback != 1)
1819 return -EINVAL;
1820
1821 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1822 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1823 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1824 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1825 info->params.flags |= flags;
1826
1827 info->params.loopback = new_line.loopback;
1828
1829 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1830 info->params.clock_speed = new_line.clock_rate;
1831 else
1832 info->params.clock_speed = 0;
1833
1834 /* if network interface up, reprogram hardware */
1835 if (info->netcount)
1836 program_hw(info);
1837 return 0;
1838
1839 default:
1840 return hdlc_ioctl(dev, ifr, cmd);
1841 }
1842 }
1843
1844 /**
1845 * called by network layer when transmit timeout is detected
1846 *
1847 * dev pointer to network device structure
1848 */
1849 static void hdlcdev_tx_timeout(struct net_device *dev)
1850 {
1851 SLMP_INFO *info = dev_to_port(dev);
1852 unsigned long flags;
1853
1854 if (debug_level >= DEBUG_LEVEL_INFO)
1855 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1856
1857 dev->stats.tx_errors++;
1858 dev->stats.tx_aborted_errors++;
1859
1860 spin_lock_irqsave(&info->lock,flags);
1861 tx_stop(info);
1862 spin_unlock_irqrestore(&info->lock,flags);
1863
1864 netif_wake_queue(dev);
1865 }
1866
1867 /**
1868 * called by device driver when transmit completes
1869 * reenable network layer transmit if stopped
1870 *
1871 * info pointer to device instance information
1872 */
1873 static void hdlcdev_tx_done(SLMP_INFO *info)
1874 {
1875 if (netif_queue_stopped(info->netdev))
1876 netif_wake_queue(info->netdev);
1877 }
1878
1879 /**
1880 * called by device driver when frame received
1881 * pass frame to network layer
1882 *
1883 * info pointer to device instance information
1884 * buf pointer to buffer contianing frame data
1885 * size count of data bytes in buf
1886 */
1887 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1888 {
1889 struct sk_buff *skb = dev_alloc_skb(size);
1890 struct net_device *dev = info->netdev;
1891
1892 if (debug_level >= DEBUG_LEVEL_INFO)
1893 printk("hdlcdev_rx(%s)\n",dev->name);
1894
1895 if (skb == NULL) {
1896 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1897 dev->name);
1898 dev->stats.rx_dropped++;
1899 return;
1900 }
1901
1902 memcpy(skb_put(skb, size), buf, size);
1903
1904 skb->protocol = hdlc_type_trans(skb, dev);
1905
1906 dev->stats.rx_packets++;
1907 dev->stats.rx_bytes += size;
1908
1909 netif_rx(skb);
1910
1911 dev->last_rx = jiffies;
1912 }
1913
1914 /**
1915 * called by device driver when adding device instance
1916 * do generic HDLC initialization
1917 *
1918 * info pointer to device instance information
1919 *
1920 * returns 0 if success, otherwise error code
1921 */
1922 static int hdlcdev_init(SLMP_INFO *info)
1923 {
1924 int rc;
1925 struct net_device *dev;
1926 hdlc_device *hdlc;
1927
1928 /* allocate and initialize network and HDLC layer objects */
1929
1930 if (!(dev = alloc_hdlcdev(info))) {
1931 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1932 return -ENOMEM;
1933 }
1934
1935 /* for network layer reporting purposes only */
1936 dev->mem_start = info->phys_sca_base;
1937 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1938 dev->irq = info->irq_level;
1939
1940 /* network layer callbacks and settings */
1941 dev->do_ioctl = hdlcdev_ioctl;
1942 dev->open = hdlcdev_open;
1943 dev->stop = hdlcdev_close;
1944 dev->tx_timeout = hdlcdev_tx_timeout;
1945 dev->watchdog_timeo = 10*HZ;
1946 dev->tx_queue_len = 50;
1947
1948 /* generic HDLC layer callbacks and settings */
1949 hdlc = dev_to_hdlc(dev);
1950 hdlc->attach = hdlcdev_attach;
1951 hdlc->xmit = hdlcdev_xmit;
1952
1953 /* register objects with HDLC layer */
1954 if ((rc = register_hdlc_device(dev))) {
1955 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1956 free_netdev(dev);
1957 return rc;
1958 }
1959
1960 info->netdev = dev;
1961 return 0;
1962 }
1963
1964 /**
1965 * called by device driver when removing device instance
1966 * do generic HDLC cleanup
1967 *
1968 * info pointer to device instance information
1969 */
1970 static void hdlcdev_exit(SLMP_INFO *info)
1971 {
1972 unregister_hdlc_device(info->netdev);
1973 free_netdev(info->netdev);
1974 info->netdev = NULL;
1975 }
1976
1977 #endif /* CONFIG_HDLC */
1978
1979
1980 /* Return next bottom half action to perform.
1981 * Return Value: BH action code or 0 if nothing to do.
1982 */
1983 static int bh_action(SLMP_INFO *info)
1984 {
1985 unsigned long flags;
1986 int rc = 0;
1987
1988 spin_lock_irqsave(&info->lock,flags);
1989
1990 if (info->pending_bh & BH_RECEIVE) {
1991 info->pending_bh &= ~BH_RECEIVE;
1992 rc = BH_RECEIVE;
1993 } else if (info->pending_bh & BH_TRANSMIT) {
1994 info->pending_bh &= ~BH_TRANSMIT;
1995 rc = BH_TRANSMIT;
1996 } else if (info->pending_bh & BH_STATUS) {
1997 info->pending_bh &= ~BH_STATUS;
1998 rc = BH_STATUS;
1999 }
2000
2001 if (!rc) {
2002 /* Mark BH routine as complete */
2003 info->bh_running = false;
2004 info->bh_requested = false;
2005 }
2006
2007 spin_unlock_irqrestore(&info->lock,flags);
2008
2009 return rc;
2010 }
2011
2012 /* Perform bottom half processing of work items queued by ISR.
2013 */
2014 static void bh_handler(struct work_struct *work)
2015 {
2016 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2017 int action;
2018
2019 if (!info)
2020 return;
2021
2022 if ( debug_level >= DEBUG_LEVEL_BH )
2023 printk( "%s(%d):%s bh_handler() entry\n",
2024 __FILE__,__LINE__,info->device_name);
2025
2026 info->bh_running = true;
2027
2028 while((action = bh_action(info)) != 0) {
2029
2030 /* Process work item */
2031 if ( debug_level >= DEBUG_LEVEL_BH )
2032 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2033 __FILE__,__LINE__,info->device_name, action);
2034
2035 switch (action) {
2036
2037 case BH_RECEIVE:
2038 bh_receive(info);
2039 break;
2040 case BH_TRANSMIT:
2041 bh_transmit(info);
2042 break;
2043 case BH_STATUS:
2044 bh_status(info);
2045 break;
2046 default:
2047 /* unknown work item ID */
2048 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2049 __FILE__,__LINE__,info->device_name,action);
2050 break;
2051 }
2052 }
2053
2054 if ( debug_level >= DEBUG_LEVEL_BH )
2055 printk( "%s(%d):%s bh_handler() exit\n",
2056 __FILE__,__LINE__,info->device_name);
2057 }
2058
2059 static void bh_receive(SLMP_INFO *info)
2060 {
2061 if ( debug_level >= DEBUG_LEVEL_BH )
2062 printk( "%s(%d):%s bh_receive()\n",
2063 __FILE__,__LINE__,info->device_name);
2064
2065 while( rx_get_frame(info) );
2066 }
2067
2068 static void bh_transmit(SLMP_INFO *info)
2069 {
2070 struct tty_struct *tty = info->port.tty;
2071
2072 if ( debug_level >= DEBUG_LEVEL_BH )
2073 printk( "%s(%d):%s bh_transmit() entry\n",
2074 __FILE__,__LINE__,info->device_name);
2075
2076 if (tty)
2077 tty_wakeup(tty);
2078 }
2079
2080 static void bh_status(SLMP_INFO *info)
2081 {
2082 if ( debug_level >= DEBUG_LEVEL_BH )
2083 printk( "%s(%d):%s bh_status() entry\n",
2084 __FILE__,__LINE__,info->device_name);
2085
2086 info->ri_chkcount = 0;
2087 info->dsr_chkcount = 0;
2088 info->dcd_chkcount = 0;
2089 info->cts_chkcount = 0;
2090 }
2091
2092 static void isr_timer(SLMP_INFO * info)
2093 {
2094 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2095
2096 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2097 write_reg(info, IER2, 0);
2098
2099 /* TMCS, Timer Control/Status Register
2100 *
2101 * 07 CMF, Compare match flag (read only) 1=match
2102 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2103 * 05 Reserved, must be 0
2104 * 04 TME, Timer Enable
2105 * 03..00 Reserved, must be 0
2106 *
2107 * 0000 0000
2108 */
2109 write_reg(info, (unsigned char)(timer + TMCS), 0);
2110
2111 info->irq_occurred = true;
2112
2113 if ( debug_level >= DEBUG_LEVEL_ISR )
2114 printk("%s(%d):%s isr_timer()\n",
2115 __FILE__,__LINE__,info->device_name);
2116 }
2117
2118 static void isr_rxint(SLMP_INFO * info)
2119 {
2120 struct tty_struct *tty = info->port.tty;
2121 struct mgsl_icount *icount = &info->icount;
2122 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2123 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2124
2125 /* clear status bits */
2126 if (status)
2127 write_reg(info, SR1, status);
2128
2129 if (status2)
2130 write_reg(info, SR2, status2);
2131
2132 if ( debug_level >= DEBUG_LEVEL_ISR )
2133 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2134 __FILE__,__LINE__,info->device_name,status,status2);
2135
2136 if (info->params.mode == MGSL_MODE_ASYNC) {
2137 if (status & BRKD) {
2138 icount->brk++;
2139
2140 /* process break detection if tty control
2141 * is not set to ignore it
2142 */
2143 if ( tty ) {
2144 if (!(status & info->ignore_status_mask1)) {
2145 if (info->read_status_mask1 & BRKD) {
2146 tty_insert_flip_char(tty, 0, TTY_BREAK);
2147 if (info->port.flags & ASYNC_SAK)
2148 do_SAK(tty);
2149 }
2150 }
2151 }
2152 }
2153 }
2154 else {
2155 if (status & (FLGD|IDLD)) {
2156 if (status & FLGD)
2157 info->icount.exithunt++;
2158 else if (status & IDLD)
2159 info->icount.rxidle++;
2160 wake_up_interruptible(&info->event_wait_q);
2161 }
2162 }
2163
2164 if (status & CDCD) {
2165 /* simulate a common modem status change interrupt
2166 * for our handler
2167 */
2168 get_signals( info );
2169 isr_io_pin(info,
2170 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2171 }
2172 }
2173
2174 /*
2175 * handle async rx data interrupts
2176 */
2177 static void isr_rxrdy(SLMP_INFO * info)
2178 {
2179 u16 status;
2180 unsigned char DataByte;
2181 struct tty_struct *tty = info->port.tty;
2182 struct mgsl_icount *icount = &info->icount;
2183
2184 if ( debug_level >= DEBUG_LEVEL_ISR )
2185 printk("%s(%d):%s isr_rxrdy\n",
2186 __FILE__,__LINE__,info->device_name);
2187
2188 while((status = read_reg(info,CST0)) & BIT0)
2189 {
2190 int flag = 0;
2191 bool over = false;
2192 DataByte = read_reg(info,TRB);
2193
2194 icount->rx++;
2195
2196 if ( status & (PE + FRME + OVRN) ) {
2197 printk("%s(%d):%s rxerr=%04X\n",
2198 __FILE__,__LINE__,info->device_name,status);
2199
2200 /* update error statistics */
2201 if (status & PE)
2202 icount->parity++;
2203 else if (status & FRME)
2204 icount->frame++;
2205 else if (status & OVRN)
2206 icount->overrun++;
2207
2208 /* discard char if tty control flags say so */
2209 if (status & info->ignore_status_mask2)
2210 continue;
2211
2212 status &= info->read_status_mask2;
2213
2214 if ( tty ) {
2215 if (status & PE)
2216 flag = TTY_PARITY;
2217 else if (status & FRME)
2218 flag = TTY_FRAME;
2219 if (status & OVRN) {
2220 /* Overrun is special, since it's
2221 * reported immediately, and doesn't
2222 * affect the current character
2223 */
2224 over = true;
2225 }
2226 }
2227 } /* end of if (error) */
2228
2229 if ( tty ) {
2230 tty_insert_flip_char(tty, DataByte, flag);
2231 if (over)
2232 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2233 }
2234 }
2235
2236 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2237 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2238 __FILE__,__LINE__,info->device_name,
2239 icount->rx,icount->brk,icount->parity,
2240 icount->frame,icount->overrun);
2241 }
2242
2243 if ( tty )
2244 tty_flip_buffer_push(tty);
2245 }
2246
2247 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2248 {
2249 if ( debug_level >= DEBUG_LEVEL_ISR )
2250 printk("%s(%d):%s isr_txeom status=%02x\n",
2251 __FILE__,__LINE__,info->device_name,status);
2252
2253 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2254 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2255 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2256
2257 if (status & UDRN) {
2258 write_reg(info, CMD, TXRESET);
2259 write_reg(info, CMD, TXENABLE);
2260 } else
2261 write_reg(info, CMD, TXBUFCLR);
2262
2263 /* disable and clear tx interrupts */
2264 info->ie0_value &= ~TXRDYE;
2265 info->ie1_value &= ~(IDLE + UDRN);
2266 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2267 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2268
2269 if ( info->tx_active ) {
2270 if (info->params.mode != MGSL_MODE_ASYNC) {
2271 if (status & UDRN)
2272 info->icount.txunder++;
2273 else if (status & IDLE)
2274 info->icount.txok++;
2275 }
2276
2277 info->tx_active = false;
2278 info->tx_count = info->tx_put = info->tx_get = 0;
2279
2280 del_timer(&info->tx_timer);
2281
2282 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2283 info->serial_signals &= ~SerialSignal_RTS;
2284 info->drop_rts_on_tx_done = false;
2285 set_signals(info);
2286 }
2287
2288 #if SYNCLINK_GENERIC_HDLC
2289 if (info->netcount)
2290 hdlcdev_tx_done(info);
2291 else
2292 #endif
2293 {
2294 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2295 tx_stop(info);
2296 return;
2297 }
2298 info->pending_bh |= BH_TRANSMIT;
2299 }
2300 }
2301 }
2302
2303
2304 /*
2305 * handle tx status interrupts
2306 */
2307 static void isr_txint(SLMP_INFO * info)
2308 {
2309 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2310
2311 /* clear status bits */
2312 write_reg(info, SR1, status);
2313
2314 if ( debug_level >= DEBUG_LEVEL_ISR )
2315 printk("%s(%d):%s isr_txint status=%02x\n",
2316 __FILE__,__LINE__,info->device_name,status);
2317
2318 if (status & (UDRN + IDLE))
2319 isr_txeom(info, status);
2320
2321 if (status & CCTS) {
2322 /* simulate a common modem status change interrupt
2323 * for our handler
2324 */
2325 get_signals( info );
2326 isr_io_pin(info,
2327 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2328
2329 }
2330 }
2331
2332 /*
2333 * handle async tx data interrupts
2334 */
2335 static void isr_txrdy(SLMP_INFO * info)
2336 {
2337 if ( debug_level >= DEBUG_LEVEL_ISR )
2338 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2339 __FILE__,__LINE__,info->device_name,info->tx_count);
2340
2341 if (info->params.mode != MGSL_MODE_ASYNC) {
2342 /* disable TXRDY IRQ, enable IDLE IRQ */
2343 info->ie0_value &= ~TXRDYE;
2344 info->ie1_value |= IDLE;
2345 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2346 return;
2347 }
2348
2349 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2350 tx_stop(info);
2351 return;
2352 }
2353
2354 if ( info->tx_count )
2355 tx_load_fifo( info );
2356 else {
2357 info->tx_active = false;
2358 info->ie0_value &= ~TXRDYE;
2359 write_reg(info, IE0, info->ie0_value);
2360 }
2361
2362 if (info->tx_count < WAKEUP_CHARS)
2363 info->pending_bh |= BH_TRANSMIT;
2364 }
2365
2366 static void isr_rxdmaok(SLMP_INFO * info)
2367 {
2368 /* BIT7 = EOT (end of transfer)
2369 * BIT6 = EOM (end of message/frame)
2370 */
2371 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2372
2373 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2374 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2375
2376 if ( debug_level >= DEBUG_LEVEL_ISR )
2377 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2378 __FILE__,__LINE__,info->device_name,status);
2379
2380 info->pending_bh |= BH_RECEIVE;
2381 }
2382
2383 static void isr_rxdmaerror(SLMP_INFO * info)
2384 {
2385 /* BIT5 = BOF (buffer overflow)
2386 * BIT4 = COF (counter overflow)
2387 */
2388 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2389
2390 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2391 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2392
2393 if ( debug_level >= DEBUG_LEVEL_ISR )
2394 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2395 __FILE__,__LINE__,info->device_name,status);
2396
2397 info->rx_overflow = true;
2398 info->pending_bh |= BH_RECEIVE;
2399 }
2400
2401 static void isr_txdmaok(SLMP_INFO * info)
2402 {
2403 unsigned char status_reg1 = read_reg(info, SR1);
2404
2405 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2406 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2407 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2408
2409 if ( debug_level >= DEBUG_LEVEL_ISR )
2410 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2411 __FILE__,__LINE__,info->device_name,status_reg1);
2412
2413 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2414 write_reg16(info, TRC0, 0);
2415 info->ie0_value |= TXRDYE;
2416 write_reg(info, IE0, info->ie0_value);
2417 }
2418
2419 static void isr_txdmaerror(SLMP_INFO * info)
2420 {
2421 /* BIT5 = BOF (buffer overflow)
2422 * BIT4 = COF (counter overflow)
2423 */
2424 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2425
2426 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2427 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2428
2429 if ( debug_level >= DEBUG_LEVEL_ISR )
2430 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2431 __FILE__,__LINE__,info->device_name,status);
2432 }
2433
2434 /* handle input serial signal changes
2435 */
2436 static void isr_io_pin( SLMP_INFO *info, u16 status )
2437 {
2438 struct mgsl_icount *icount;
2439
2440 if ( debug_level >= DEBUG_LEVEL_ISR )
2441 printk("%s(%d):isr_io_pin status=%04X\n",
2442 __FILE__,__LINE__,status);
2443
2444 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2445 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2446 icount = &info->icount;
2447 /* update input line counters */
2448 if (status & MISCSTATUS_RI_LATCHED) {
2449 icount->rng++;
2450 if ( status & SerialSignal_RI )
2451 info->input_signal_events.ri_up++;
2452 else
2453 info->input_signal_events.ri_down++;
2454 }
2455 if (status & MISCSTATUS_DSR_LATCHED) {
2456 icount->dsr++;
2457 if ( status & SerialSignal_DSR )
2458 info->input_signal_events.dsr_up++;
2459 else
2460 info->input_signal_events.dsr_down++;
2461 }
2462 if (status & MISCSTATUS_DCD_LATCHED) {
2463 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2464 info->ie1_value &= ~CDCD;
2465 write_reg(info, IE1, info->ie1_value);
2466 }
2467 icount->dcd++;
2468 if (status & SerialSignal_DCD) {
2469 info->input_signal_events.dcd_up++;
2470 } else
2471 info->input_signal_events.dcd_down++;
2472 #if SYNCLINK_GENERIC_HDLC
2473 if (info->netcount) {
2474 if (status & SerialSignal_DCD)
2475 netif_carrier_on(info->netdev);
2476 else
2477 netif_carrier_off(info->netdev);
2478 }
2479 #endif
2480 }
2481 if (status & MISCSTATUS_CTS_LATCHED)
2482 {
2483 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2484 info->ie1_value &= ~CCTS;
2485 write_reg(info, IE1, info->ie1_value);
2486 }
2487 icount->cts++;
2488 if ( status & SerialSignal_CTS )
2489 info->input_signal_events.cts_up++;
2490 else
2491 info->input_signal_events.cts_down++;
2492 }
2493 wake_up_interruptible(&info->status_event_wait_q);
2494 wake_up_interruptible(&info->event_wait_q);
2495
2496 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2497 (status & MISCSTATUS_DCD_LATCHED) ) {
2498 if ( debug_level >= DEBUG_LEVEL_ISR )
2499 printk("%s CD now %s...", info->device_name,
2500 (status & SerialSignal_DCD) ? "on" : "off");
2501 if (status & SerialSignal_DCD)
2502 wake_up_interruptible(&info->port.open_wait);
2503 else {
2504 if ( debug_level >= DEBUG_LEVEL_ISR )
2505 printk("doing serial hangup...");
2506 if (info->port.tty)
2507 tty_hangup(info->port.tty);
2508 }
2509 }
2510
2511 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2512 (status & MISCSTATUS_CTS_LATCHED) ) {
2513 if ( info->port.tty ) {
2514 if (info->port.tty->hw_stopped) {
2515 if (status & SerialSignal_CTS) {
2516 if ( debug_level >= DEBUG_LEVEL_ISR )
2517 printk("CTS tx start...");
2518 info->port.tty->hw_stopped = 0;
2519 tx_start(info);
2520 info->pending_bh |= BH_TRANSMIT;
2521 return;
2522 }
2523 } else {
2524 if (!(status & SerialSignal_CTS)) {
2525 if ( debug_level >= DEBUG_LEVEL_ISR )
2526 printk("CTS tx stop...");
2527 info->port.tty->hw_stopped = 1;
2528 tx_stop(info);
2529 }
2530 }
2531 }
2532 }
2533 }
2534
2535 info->pending_bh |= BH_STATUS;
2536 }
2537
2538 /* Interrupt service routine entry point.
2539 *
2540 * Arguments:
2541 * irq interrupt number that caused interrupt
2542 * dev_id device ID supplied during interrupt registration
2543 * regs interrupted processor context
2544 */
2545 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2546 {
2547 SLMP_INFO *info = dev_id;
2548 unsigned char status, status0, status1=0;
2549 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2550 unsigned char timerstatus0, timerstatus1=0;
2551 unsigned char shift;
2552 unsigned int i;
2553 unsigned short tmp;
2554
2555 if ( debug_level >= DEBUG_LEVEL_ISR )
2556 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2557 __FILE__, __LINE__, info->irq_level);
2558
2559 spin_lock(&info->lock);
2560
2561 for(;;) {
2562
2563 /* get status for SCA0 (ports 0-1) */
2564 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2565 status0 = (unsigned char)tmp;
2566 dmastatus0 = (unsigned char)(tmp>>8);
2567 timerstatus0 = read_reg(info, ISR2);
2568
2569 if ( debug_level >= DEBUG_LEVEL_ISR )
2570 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2571 __FILE__, __LINE__, info->device_name,
2572 status0, dmastatus0, timerstatus0);
2573
2574 if (info->port_count == 4) {
2575 /* get status for SCA1 (ports 2-3) */
2576 tmp = read_reg16(info->port_array[2], ISR0);
2577 status1 = (unsigned char)tmp;
2578 dmastatus1 = (unsigned char)(tmp>>8);
2579 timerstatus1 = read_reg(info->port_array[2], ISR2);
2580
2581 if ( debug_level >= DEBUG_LEVEL_ISR )
2582 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2583 __FILE__,__LINE__,info->device_name,
2584 status1,dmastatus1,timerstatus1);
2585 }
2586
2587 if (!status0 && !dmastatus0 && !timerstatus0 &&
2588 !status1 && !dmastatus1 && !timerstatus1)
2589 break;
2590
2591 for(i=0; i < info->port_count ; i++) {
2592 if (info->port_array[i] == NULL)
2593 continue;
2594 if (i < 2) {
2595 status = status0;
2596 dmastatus = dmastatus0;
2597 } else {
2598 status = status1;
2599 dmastatus = dmastatus1;
2600 }
2601
2602 shift = i & 1 ? 4 :0;
2603
2604 if (status & BIT0 << shift)
2605 isr_rxrdy(info->port_array[i]);
2606 if (status & BIT1 << shift)
2607 isr_txrdy(info->port_array[i]);
2608 if (status & BIT2 << shift)
2609 isr_rxint(info->port_array[i]);
2610 if (status & BIT3 << shift)
2611 isr_txint(info->port_array[i]);
2612
2613 if (dmastatus & BIT0 << shift)
2614 isr_rxdmaerror(info->port_array[i]);
2615 if (dmastatus & BIT1 << shift)
2616 isr_rxdmaok(info->port_array[i]);
2617 if (dmastatus & BIT2 << shift)
2618 isr_txdmaerror(info->port_array[i]);
2619 if (dmastatus & BIT3 << shift)
2620 isr_txdmaok(info->port_array[i]);
2621 }
2622
2623 if (timerstatus0 & (BIT5 | BIT4))
2624 isr_timer(info->port_array[0]);
2625 if (timerstatus0 & (BIT7 | BIT6))
2626 isr_timer(info->port_array[1]);
2627 if (timerstatus1 & (BIT5 | BIT4))
2628 isr_timer(info->port_array[2]);
2629 if (timerstatus1 & (BIT7 | BIT6))
2630 isr_timer(info->port_array[3]);
2631 }
2632
2633 for(i=0; i < info->port_count ; i++) {
2634 SLMP_INFO * port = info->port_array[i];
2635
2636 /* Request bottom half processing if there's something
2637 * for it to do and the bh is not already running.
2638 *
2639 * Note: startup adapter diags require interrupts.
2640 * do not request bottom half processing if the
2641 * device is not open in a normal mode.
2642 */
2643 if ( port && (port->port.count || port->netcount) &&
2644 port->pending_bh && !port->bh_running &&
2645 !port->bh_requested ) {
2646 if ( debug_level >= DEBUG_LEVEL_ISR )
2647 printk("%s(%d):%s queueing bh task.\n",
2648 __FILE__,__LINE__,port->device_name);
2649 schedule_work(&port->task);
2650 port->bh_requested = true;
2651 }
2652 }
2653
2654 spin_unlock(&info->lock);
2655
2656 if ( debug_level >= DEBUG_LEVEL_ISR )
2657 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2658 __FILE__, __LINE__, info->irq_level);
2659 return IRQ_HANDLED;
2660 }
2661
2662 /* Initialize and start device.
2663 */
2664 static int startup(SLMP_INFO * info)
2665 {
2666 if ( debug_level >= DEBUG_LEVEL_INFO )
2667 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2668
2669 if (info->port.flags & ASYNC_INITIALIZED)
2670 return 0;
2671
2672 if (!info->tx_buf) {
2673 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2674 if (!info->tx_buf) {
2675 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2676 __FILE__,__LINE__,info->device_name);
2677 return -ENOMEM;
2678 }
2679 }
2680
2681 info->pending_bh = 0;
2682
2683 memset(&info->icount, 0, sizeof(info->icount));
2684
2685 /* program hardware for current parameters */
2686 reset_port(info);
2687
2688 change_params(info);
2689
2690 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2691
2692 if (info->port.tty)
2693 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2694
2695 info->port.flags |= ASYNC_INITIALIZED;
2696
2697 return 0;
2698 }
2699
2700 /* Called by close() and hangup() to shutdown hardware
2701 */
2702 static void shutdown(SLMP_INFO * info)
2703 {
2704 unsigned long flags;
2705
2706 if (!(info->port.flags & ASYNC_INITIALIZED))
2707 return;
2708
2709 if (debug_level >= DEBUG_LEVEL_INFO)
2710 printk("%s(%d):%s synclinkmp_shutdown()\n",
2711 __FILE__,__LINE__, info->device_name );
2712
2713 /* clear status wait queue because status changes */
2714 /* can't happen after shutting down the hardware */
2715 wake_up_interruptible(&info->status_event_wait_q);
2716 wake_up_interruptible(&info->event_wait_q);
2717
2718 del_timer(&info->tx_timer);
2719 del_timer(&info->status_timer);
2720
2721 kfree(info->tx_buf);
2722 info->tx_buf = NULL;
2723
2724 spin_lock_irqsave(&info->lock,flags);
2725
2726 reset_port(info);
2727
2728 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2729 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2730 set_signals(info);
2731 }
2732
2733 spin_unlock_irqrestore(&info->lock,flags);
2734
2735 if (info->port.tty)
2736 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2737
2738 info->port.flags &= ~ASYNC_INITIALIZED;
2739 }
2740
2741 static void program_hw(SLMP_INFO *info)
2742 {
2743 unsigned long flags;
2744
2745 spin_lock_irqsave(&info->lock,flags);
2746
2747 rx_stop(info);
2748 tx_stop(info);
2749
2750 info->tx_count = info->tx_put = info->tx_get = 0;
2751
2752 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2753 hdlc_mode(info);
2754 else
2755 async_mode(info);
2756
2757 set_signals(info);
2758
2759 info->dcd_chkcount = 0;
2760 info->cts_chkcount = 0;
2761 info->ri_chkcount = 0;
2762 info->dsr_chkcount = 0;
2763
2764 info->ie1_value |= (CDCD|CCTS);
2765 write_reg(info, IE1, info->ie1_value);
2766
2767 get_signals(info);
2768
2769 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2770 rx_start(info);
2771
2772 spin_unlock_irqrestore(&info->lock,flags);
2773 }
2774
2775 /* Reconfigure adapter based on new parameters
2776 */
2777 static void change_params(SLMP_INFO *info)
2778 {
2779 unsigned cflag;
2780 int bits_per_char;
2781
2782 if (!info->port.tty || !info->port.tty->termios)
2783 return;
2784
2785 if (debug_level >= DEBUG_LEVEL_INFO)
2786 printk("%s(%d):%s change_params()\n",
2787 __FILE__,__LINE__, info->device_name );
2788
2789 cflag = info->port.tty->termios->c_cflag;
2790
2791 /* if B0 rate (hangup) specified then negate DTR and RTS */
2792 /* otherwise assert DTR and RTS */
2793 if (cflag & CBAUD)
2794 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2795 else
2796 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2797
2798 /* byte size and parity */
2799
2800 switch (cflag & CSIZE) {
2801 case CS5: info->params.data_bits = 5; break;
2802 case CS6: info->params.data_bits = 6; break;
2803 case CS7: info->params.data_bits = 7; break;
2804 case CS8: info->params.data_bits = 8; break;
2805 /* Never happens, but GCC is too dumb to figure it out */
2806 default: info->params.data_bits = 7; break;
2807 }
2808
2809 if (cflag & CSTOPB)
2810 info->params.stop_bits = 2;
2811 else
2812 info->params.stop_bits = 1;
2813
2814 info->params.parity = ASYNC_PARITY_NONE;
2815 if (cflag & PARENB) {
2816 if (cflag & PARODD)
2817 info->params.parity = ASYNC_PARITY_ODD;
2818 else
2819 info->params.parity = ASYNC_PARITY_EVEN;
2820 #ifdef CMSPAR
2821 if (cflag & CMSPAR)
2822 info->params.parity = ASYNC_PARITY_SPACE;
2823 #endif
2824 }
2825
2826 /* calculate number of jiffies to transmit a full
2827 * FIFO (32 bytes) at specified data rate
2828 */
2829 bits_per_char = info->params.data_bits +
2830 info->params.stop_bits + 1;
2831
2832 /* if port data rate is set to 460800 or less then
2833 * allow tty settings to override, otherwise keep the
2834 * current data rate.
2835 */
2836 if (info->params.data_rate <= 460800) {
2837 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2838 }
2839
2840 if ( info->params.data_rate ) {
2841 info->timeout = (32*HZ*bits_per_char) /
2842 info->params.data_rate;
2843 }
2844 info->timeout += HZ/50; /* Add .02 seconds of slop */
2845
2846 if (cflag & CRTSCTS)
2847 info->port.flags |= ASYNC_CTS_FLOW;
2848 else
2849 info->port.flags &= ~ASYNC_CTS_FLOW;
2850
2851 if (cflag & CLOCAL)
2852 info->port.flags &= ~ASYNC_CHECK_CD;
2853 else
2854 info->port.flags |= ASYNC_CHECK_CD;
2855
2856 /* process tty input control flags */
2857
2858 info->read_status_mask2 = OVRN;
2859 if (I_INPCK(info->port.tty))
2860 info->read_status_mask2 |= PE | FRME;
2861 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2862 info->read_status_mask1 |= BRKD;
2863 if (I_IGNPAR(info->port.tty))
2864 info->ignore_status_mask2 |= PE | FRME;
2865 if (I_IGNBRK(info->port.tty)) {
2866 info->ignore_status_mask1 |= BRKD;
2867 /* If ignoring parity and break indicators, ignore
2868 * overruns too. (For real raw support).
2869 */
2870 if (I_IGNPAR(info->port.tty))
2871 info->ignore_status_mask2 |= OVRN;
2872 }
2873
2874 program_hw(info);
2875 }
2876
2877 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2878 {
2879 int err;
2880
2881 if (debug_level >= DEBUG_LEVEL_INFO)
2882 printk("%s(%d):%s get_params()\n",
2883 __FILE__,__LINE__, info->device_name);
2884
2885 if (!user_icount) {
2886 memset(&info->icount, 0, sizeof(info->icount));
2887 } else {
2888 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2889 if (err)
2890 return -EFAULT;
2891 }
2892
2893 return 0;
2894 }
2895
2896 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2897 {
2898 int err;
2899 if (debug_level >= DEBUG_LEVEL_INFO)
2900 printk("%s(%d):%s get_params()\n",
2901 __FILE__,__LINE__, info->device_name);
2902
2903 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2904 if (err) {
2905 if ( debug_level >= DEBUG_LEVEL_INFO )
2906 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2907 __FILE__,__LINE__,info->device_name);
2908 return -EFAULT;
2909 }
2910
2911 return 0;
2912 }
2913
2914 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2915 {
2916 unsigned long flags;
2917 MGSL_PARAMS tmp_params;
2918 int err;
2919
2920 if (debug_level >= DEBUG_LEVEL_INFO)
2921 printk("%s(%d):%s set_params\n",
2922 __FILE__,__LINE__,info->device_name );
2923 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2924 if (err) {
2925 if ( debug_level >= DEBUG_LEVEL_INFO )
2926 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2927 __FILE__,__LINE__,info->device_name);
2928 return -EFAULT;
2929 }
2930
2931 spin_lock_irqsave(&info->lock,flags);
2932 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2933 spin_unlock_irqrestore(&info->lock,flags);
2934
2935 change_params(info);
2936
2937 return 0;
2938 }
2939
2940 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2941 {
2942 int err;
2943
2944 if (debug_level >= DEBUG_LEVEL_INFO)
2945 printk("%s(%d):%s get_txidle()=%d\n",
2946 __FILE__,__LINE__, info->device_name, info->idle_mode);
2947
2948 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2949 if (err) {
2950 if ( debug_level >= DEBUG_LEVEL_INFO )
2951 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2952 __FILE__,__LINE__,info->device_name);
2953 return -EFAULT;
2954 }
2955
2956 return 0;
2957 }
2958
2959 static int set_txidle(SLMP_INFO * info, int idle_mode)
2960 {
2961 unsigned long flags;
2962
2963 if (debug_level >= DEBUG_LEVEL_INFO)
2964 printk("%s(%d):%s set_txidle(%d)\n",
2965 __FILE__,__LINE__,info->device_name, idle_mode );
2966
2967 spin_lock_irqsave(&info->lock,flags);
2968 info->idle_mode = idle_mode;
2969 tx_set_idle( info );
2970 spin_unlock_irqrestore(&info->lock,flags);
2971 return 0;
2972 }
2973
2974 static int tx_enable(SLMP_INFO * info, int enable)
2975 {
2976 unsigned long flags;
2977
2978 if (debug_level >= DEBUG_LEVEL_INFO)
2979 printk("%s(%d):%s tx_enable(%d)\n",
2980 __FILE__,__LINE__,info->device_name, enable);
2981
2982 spin_lock_irqsave(&info->lock,flags);
2983 if ( enable ) {
2984 if ( !info->tx_enabled ) {
2985 tx_start(info);
2986 }
2987 } else {
2988 if ( info->tx_enabled )
2989 tx_stop(info);
2990 }
2991 spin_unlock_irqrestore(&info->lock,flags);
2992 return 0;
2993 }
2994
2995 /* abort send HDLC frame
2996 */
2997 static int tx_abort(SLMP_INFO * info)
2998 {
2999 unsigned long flags;
3000
3001 if (debug_level >= DEBUG_LEVEL_INFO)
3002 printk("%s(%d):%s tx_abort()\n",
3003 __FILE__,__LINE__,info->device_name);
3004
3005 spin_lock_irqsave(&info->lock,flags);
3006 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3007 info->ie1_value &= ~UDRN;
3008 info->ie1_value |= IDLE;
3009 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3010 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3011
3012 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3013 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3014
3015 write_reg(info, CMD, TXABORT);
3016 }
3017 spin_unlock_irqrestore(&info->lock,flags);
3018 return 0;
3019 }
3020
3021 static int rx_enable(SLMP_INFO * info, int enable)
3022 {
3023 unsigned long flags;
3024
3025 if (debug_level >= DEBUG_LEVEL_INFO)
3026 printk("%s(%d):%s rx_enable(%d)\n",
3027 __FILE__,__LINE__,info->device_name,enable);
3028
3029 spin_lock_irqsave(&info->lock,flags);
3030 if ( enable ) {
3031 if ( !info->rx_enabled )
3032 rx_start(info);
3033 } else {
3034 if ( info->rx_enabled )
3035 rx_stop(info);
3036 }
3037 spin_unlock_irqrestore(&info->lock,flags);
3038 return 0;
3039 }
3040
3041 /* wait for specified event to occur
3042 */
3043 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3044 {
3045 unsigned long flags;
3046 int s;
3047 int rc=0;
3048 struct mgsl_icount cprev, cnow;
3049 int events;
3050 int mask;
3051 struct _input_signal_events oldsigs, newsigs;
3052 DECLARE_WAITQUEUE(wait, current);
3053
3054 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3055 if (rc) {
3056 return -EFAULT;
3057 }
3058
3059 if (debug_level >= DEBUG_LEVEL_INFO)
3060 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3061 __FILE__,__LINE__,info->device_name,mask);
3062
3063 spin_lock_irqsave(&info->lock,flags);
3064
3065 /* return immediately if state matches requested events */
3066 get_signals(info);
3067 s = info->serial_signals;
3068
3069 events = mask &
3070 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3071 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3072 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3073 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3074 if (events) {
3075 spin_unlock_irqrestore(&info->lock,flags);
3076 goto exit;
3077 }
3078
3079 /* save current irq counts */
3080 cprev = info->icount;
3081 oldsigs = info->input_signal_events;
3082
3083 /* enable hunt and idle irqs if needed */
3084 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3085 unsigned char oldval = info->ie1_value;
3086 unsigned char newval = oldval +
3087 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3088 (mask & MgslEvent_IdleReceived ? IDLD:0);
3089 if ( oldval != newval ) {
3090 info->ie1_value = newval;
3091 write_reg(info, IE1, info->ie1_value);
3092 }
3093 }
3094
3095 set_current_state(TASK_INTERRUPTIBLE);
3096 add_wait_queue(&info->event_wait_q, &wait);
3097
3098 spin_unlock_irqrestore(&info->lock,flags);
3099
3100 for(;;) {
3101 schedule();
3102 if (signal_pending(current)) {
3103 rc = -ERESTARTSYS;
3104 break;
3105 }
3106
3107 /* get current irq counts */
3108 spin_lock_irqsave(&info->lock,flags);
3109 cnow = info->icount;
3110 newsigs = info->input_signal_events;
3111 set_current_state(TASK_INTERRUPTIBLE);
3112 spin_unlock_irqrestore(&info->lock,flags);
3113
3114 /* if no change, wait aborted for some reason */
3115 if (newsigs.dsr_up == oldsigs.dsr_up &&
3116 newsigs.dsr_down == oldsigs.dsr_down &&
3117 newsigs.dcd_up == oldsigs.dcd_up &&
3118 newsigs.dcd_down == oldsigs.dcd_down &&
3119 newsigs.cts_up == oldsigs.cts_up &&
3120 newsigs.cts_down == oldsigs.cts_down &&
3121 newsigs.ri_up == oldsigs.ri_up &&
3122 newsigs.ri_down == oldsigs.ri_down &&
3123 cnow.exithunt == cprev.exithunt &&
3124 cnow.rxidle == cprev.rxidle) {
3125 rc = -EIO;
3126 break;
3127 }
3128
3129 events = mask &
3130 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3131 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3132 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3133 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3134 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3135 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3136 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3137 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3138 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3139 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3140 if (events)
3141 break;
3142
3143 cprev = cnow;
3144 oldsigs = newsigs;
3145 }
3146
3147 remove_wait_queue(&info->event_wait_q, &wait);
3148 set_current_state(TASK_RUNNING);
3149
3150
3151 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3152 spin_lock_irqsave(&info->lock,flags);
3153 if (!waitqueue_active(&info->event_wait_q)) {
3154 /* disable enable exit hunt mode/idle rcvd IRQs */
3155 info->ie1_value &= ~(FLGD|IDLD);
3156 write_reg(info, IE1, info->ie1_value);
3157 }
3158 spin_unlock_irqrestore(&info->lock,flags);
3159 }
3160 exit:
3161 if ( rc == 0 )
3162 PUT_USER(rc, events, mask_ptr);
3163
3164 return rc;
3165 }
3166
3167 static int modem_input_wait(SLMP_INFO *info,int arg)
3168 {
3169 unsigned long flags;
3170 int rc;
3171 struct mgsl_icount cprev, cnow;
3172 DECLARE_WAITQUEUE(wait, current);
3173
3174 /* save current irq counts */
3175 spin_lock_irqsave(&info->lock,flags);
3176 cprev = info->icount;
3177 add_wait_queue(&info->status_event_wait_q, &wait);
3178 set_current_state(TASK_INTERRUPTIBLE);
3179 spin_unlock_irqrestore(&info->lock,flags);
3180
3181 for(;;) {
3182 schedule();
3183 if (signal_pending(current)) {
3184 rc = -ERESTARTSYS;
3185 break;
3186 }
3187
3188 /* get new irq counts */
3189 spin_lock_irqsave(&info->lock,flags);
3190 cnow = info->icount;
3191 set_current_state(TASK_INTERRUPTIBLE);
3192 spin_unlock_irqrestore(&info->lock,flags);
3193
3194 /* if no change, wait aborted for some reason */
3195 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3196 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3197 rc = -EIO;
3198 break;
3199 }
3200
3201 /* check for change in caller specified modem input */
3202 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3203 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3204 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3205 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3206 rc = 0;
3207 break;
3208 }
3209
3210 cprev = cnow;
3211 }
3212 remove_wait_queue(&info->status_event_wait_q, &wait);
3213 set_current_state(TASK_RUNNING);
3214 return rc;
3215 }
3216
3217 /* return the state of the serial control and status signals
3218 */
3219 static int tiocmget(struct tty_struct *tty, struct file *file)
3220 {
3221 SLMP_INFO *info = tty->driver_data;
3222 unsigned int result;
3223 unsigned long flags;
3224
3225 spin_lock_irqsave(&info->lock,flags);
3226 get_signals(info);
3227 spin_unlock_irqrestore(&info->lock,flags);
3228
3229 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3230 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3231 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3232 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3233 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3234 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3235
3236 if (debug_level >= DEBUG_LEVEL_INFO)
3237 printk("%s(%d):%s tiocmget() value=%08X\n",
3238 __FILE__,__LINE__, info->device_name, result );
3239 return result;
3240 }
3241
3242 /* set modem control signals (DTR/RTS)
3243 */
3244 static int tiocmset(struct tty_struct *tty, struct file *file,
3245 unsigned int set, unsigned int clear)
3246 {
3247 SLMP_INFO *info = tty->driver_data;
3248 unsigned long flags;
3249
3250 if (debug_level >= DEBUG_LEVEL_INFO)
3251 printk("%s(%d):%s tiocmset(%x,%x)\n",
3252 __FILE__,__LINE__,info->device_name, set, clear);
3253
3254 if (set & TIOCM_RTS)
3255 info->serial_signals |= SerialSignal_RTS;
3256 if (set & TIOCM_DTR)
3257 info->serial_signals |= SerialSignal_DTR;
3258 if (clear & TIOCM_RTS)
3259 info->serial_signals &= ~SerialSignal_RTS;
3260 if (clear & TIOCM_DTR)
3261 info->serial_signals &= ~SerialSignal_DTR;
3262
3263 spin_lock_irqsave(&info->lock,flags);
3264 set_signals(info);
3265 spin_unlock_irqrestore(&info->lock,flags);
3266
3267 return 0;
3268 }
3269
3270 static int carrier_raised(struct tty_port *port)
3271 {
3272 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3273 unsigned long flags;
3274
3275 spin_lock_irqsave(&info->lock,flags);
3276 get_signals(info);
3277 spin_unlock_irqrestore(&info->lock,flags);
3278
3279 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3280 }
3281
3282 static void raise_dtr_rts(struct tty_port *port)
3283 {
3284 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3285 unsigned long flags;
3286
3287 spin_lock_irqsave(&info->lock,flags);
3288 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3289 set_signals(info);
3290 spin_unlock_irqrestore(&info->lock,flags);
3291 }
3292
3293 /* Block the current process until the specified port is ready to open.
3294 */
3295 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3296 SLMP_INFO *info)
3297 {
3298 DECLARE_WAITQUEUE(wait, current);
3299 int retval;
3300 bool do_clocal = false;
3301 bool extra_count = false;
3302 unsigned long flags;
3303 int cd;
3304 struct tty_port *port = &info->port;
3305
3306 if (debug_level >= DEBUG_LEVEL_INFO)
3307 printk("%s(%d):%s block_til_ready()\n",
3308 __FILE__,__LINE__, tty->driver->name );
3309
3310 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3311 /* nonblock mode is set or port is not enabled */
3312 /* just verify that callout device is not active */
3313 port->flags |= ASYNC_NORMAL_ACTIVE;
3314 return 0;
3315 }
3316
3317 if (tty->termios->c_cflag & CLOCAL)
3318 do_clocal = true;
3319
3320 /* Wait for carrier detect and the line to become
3321 * free (i.e., not in use by the callout). While we are in
3322 * this loop, port->count is dropped by one, so that
3323 * close() knows when to free things. We restore it upon
3324 * exit, either normal or abnormal.
3325 */
3326
3327 retval = 0;
3328 add_wait_queue(&port->open_wait, &wait);
3329
3330 if (debug_level >= DEBUG_LEVEL_INFO)
3331 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3332 __FILE__,__LINE__, tty->driver->name, port->count );
3333
3334 spin_lock_irqsave(&info->lock, flags);
3335 if (!tty_hung_up_p(filp)) {
3336 extra_count = true;
3337 port->count--;
3338 }
3339 spin_unlock_irqrestore(&info->lock, flags);
3340 port->blocked_open++;
3341
3342 while (1) {
3343 if (tty->termios->c_cflag & CBAUD)
3344 tty_port_raise_dtr_rts(port);
3345
3346 set_current_state(TASK_INTERRUPTIBLE);
3347
3348 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3349 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3350 -EAGAIN : -ERESTARTSYS;
3351 break;
3352 }
3353
3354 cd = tty_port_carrier_raised(port);
3355
3356 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3357 break;
3358
3359 if (signal_pending(current)) {
3360 retval = -ERESTARTSYS;
3361 break;
3362 }
3363
3364 if (debug_level >= DEBUG_LEVEL_INFO)
3365 printk("%s(%d):%s block_til_ready() count=%d\n",
3366 __FILE__,__LINE__, tty->driver->name, port->count );
3367
3368 schedule();
3369 }
3370
3371 set_current_state(TASK_RUNNING);
3372 remove_wait_queue(&port->open_wait, &wait);
3373
3374 if (extra_count)
3375 port->count++;
3376 port->blocked_open--;
3377
3378 if (debug_level >= DEBUG_LEVEL_INFO)
3379 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3380 __FILE__,__LINE__, tty->driver->name, port->count );
3381
3382 if (!retval)
3383 port->flags |= ASYNC_NORMAL_ACTIVE;
3384
3385 return retval;
3386 }
3387
3388 static int alloc_dma_bufs(SLMP_INFO *info)
3389 {
3390 unsigned short BuffersPerFrame;
3391 unsigned short BufferCount;
3392
3393 // Force allocation to start at 64K boundary for each port.
3394 // This is necessary because *all* buffer descriptors for a port
3395 // *must* be in the same 64K block. All descriptors on a port
3396 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3397 // into the CBP register.
3398 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3399
3400 /* Calculate the number of DMA buffers necessary to hold the */
3401 /* largest allowable frame size. Note: If the max frame size is */
3402 /* not an even multiple of the DMA buffer size then we need to */
3403 /* round the buffer count per frame up one. */
3404
3405 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3406 if ( info->max_frame_size % SCABUFSIZE )
3407 BuffersPerFrame++;
3408
3409 /* calculate total number of data buffers (SCABUFSIZE) possible
3410 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3411 * for the descriptor list (BUFFERLISTSIZE).
3412 */
3413 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3414
3415 /* limit number of buffers to maximum amount of descriptors */
3416 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3417 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3418
3419 /* use enough buffers to transmit one max size frame */
3420 info->tx_buf_count = BuffersPerFrame + 1;
3421
3422 /* never use more than half the available buffers for transmit */
3423 if (info->tx_buf_count > (BufferCount/2))
3424 info->tx_buf_count = BufferCount/2;
3425
3426 if (info->tx_buf_count > SCAMAXDESC)
3427 info->tx_buf_count = SCAMAXDESC;
3428
3429 /* use remaining buffers for receive */
3430 info->rx_buf_count = BufferCount - info->tx_buf_count;
3431
3432 if (info->rx_buf_count > SCAMAXDESC)
3433 info->rx_buf_count = SCAMAXDESC;
3434
3435 if ( debug_level >= DEBUG_LEVEL_INFO )
3436 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3437 __FILE__,__LINE__, info->device_name,
3438 info->tx_buf_count,info->rx_buf_count);
3439
3440 if ( alloc_buf_list( info ) < 0 ||
3441 alloc_frame_bufs(info,
3442 info->rx_buf_list,
3443 info->rx_buf_list_ex,
3444 info->rx_buf_count) < 0 ||
3445 alloc_frame_bufs(info,
3446 info->tx_buf_list,
3447 info->tx_buf_list_ex,
3448 info->tx_buf_count) < 0 ||
3449 alloc_tmp_rx_buf(info) < 0 ) {
3450 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3451 __FILE__,__LINE__, info->device_name);
3452 return -ENOMEM;
3453 }
3454
3455 rx_reset_buffers( info );
3456
3457 return 0;
3458 }
3459
3460 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3461 */
3462 static int alloc_buf_list(SLMP_INFO *info)
3463 {
3464 unsigned int i;
3465
3466 /* build list in adapter shared memory */
3467 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3468 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3469 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3470
3471 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3472
3473 /* Save virtual address pointers to the receive and */
3474 /* transmit buffer lists. (Receive 1st). These pointers will */
3475 /* be used by the processor to access the lists. */
3476 info->rx_buf_list = (SCADESC *)info->buffer_list;
3477
3478 info->tx_buf_list = (SCADESC *)info->buffer_list;
3479 info->tx_buf_list += info->rx_buf_count;
3480
3481 /* Build links for circular buffer entry lists (tx and rx)
3482 *
3483 * Note: links are physical addresses read by the SCA device
3484 * to determine the next buffer entry to use.
3485 */
3486
3487 for ( i = 0; i < info->rx_buf_count; i++ ) {
3488 /* calculate and store physical address of this buffer entry */
3489 info->rx_buf_list_ex[i].phys_entry =
3490 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3491
3492 /* calculate and store physical address of */
3493 /* next entry in cirular list of entries */
3494 info->rx_buf_list[i].next = info->buffer_list_phys;
3495 if ( i < info->rx_buf_count - 1 )
3496 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3497
3498 info->rx_buf_list[i].length = SCABUFSIZE;
3499 }
3500
3501 for ( i = 0; i < info->tx_buf_count; i++ ) {
3502 /* calculate and store physical address of this buffer entry */
3503 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3504 ((info->rx_buf_count + i) * sizeof(SCADESC));
3505
3506 /* calculate and store physical address of */
3507 /* next entry in cirular list of entries */
3508
3509 info->tx_buf_list[i].next = info->buffer_list_phys +
3510 info->rx_buf_count * sizeof(SCADESC);
3511
3512 if ( i < info->tx_buf_count - 1 )
3513 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3514 }
3515
3516 return 0;
3517 }
3518
3519 /* Allocate the frame DMA buffers used by the specified buffer list.
3520 */
3521 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3522 {
3523 int i;
3524 unsigned long phys_addr;
3525
3526 for ( i = 0; i < count; i++ ) {
3527 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3528 phys_addr = info->port_array[0]->last_mem_alloc;
3529 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3530
3531 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3532 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3533 }
3534
3535 return 0;
3536 }
3537
3538 static void free_dma_bufs(SLMP_INFO *info)
3539 {
3540 info->buffer_list = NULL;
3541 info->rx_buf_list = NULL;
3542 info->tx_buf_list = NULL;
3543 }
3544
3545 /* allocate buffer large enough to hold max_frame_size.
3546 * This buffer is used to pass an assembled frame to the line discipline.
3547 */
3548 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3549 {
3550 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3551 if (info->tmp_rx_buf == NULL)
3552 return -ENOMEM;
3553 return 0;
3554 }
3555
3556 static void free_tmp_rx_buf(SLMP_INFO *info)
3557 {
3558 kfree(info->tmp_rx_buf);
3559 info->tmp_rx_buf = NULL;
3560 }
3561
3562 static int claim_resources(SLMP_INFO *info)
3563 {
3564 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3565 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3566 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3567 info->init_error = DiagStatus_AddressConflict;
3568 goto errout;
3569 }
3570 else
3571 info->shared_mem_requested = true;
3572
3573 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3574 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3575 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3576 info->init_error = DiagStatus_AddressConflict;
3577 goto errout;
3578 }
3579 else
3580 info->lcr_mem_requested = true;
3581
3582 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3583 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3584 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3585 info->init_error = DiagStatus_AddressConflict;
3586 goto errout;
3587 }
3588 else
3589 info->sca_base_requested = true;
3590
3591 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3592 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3593 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3594 info->init_error = DiagStatus_AddressConflict;
3595 goto errout;
3596 }
3597 else
3598 info->sca_statctrl_requested = true;
3599
3600 info->memory_base = ioremap_nocache(info->phys_memory_base,
3601 SCA_MEM_SIZE);
3602 if (!info->memory_base) {
3603 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3604 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3605 info->init_error = DiagStatus_CantAssignPciResources;
3606 goto errout;
3607 }
3608
3609 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3610 if (!info->lcr_base) {
3611 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3612 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3613 info->init_error = DiagStatus_CantAssignPciResources;
3614 goto errout;
3615 }
3616 info->lcr_base += info->lcr_offset;
3617
3618 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3619 if (!info->sca_base) {
3620 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3621 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3622 info->init_error = DiagStatus_CantAssignPciResources;
3623 goto errout;
3624 }
3625 info->sca_base += info->sca_offset;
3626
3627 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3628 PAGE_SIZE);
3629 if (!info->statctrl_base) {
3630 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3631 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3632 info->init_error = DiagStatus_CantAssignPciResources;
3633 goto errout;
3634 }
3635 info->statctrl_base += info->statctrl_offset;
3636
3637 if ( !memory_test(info) ) {
3638 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3639 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3640 info->init_error = DiagStatus_MemoryError;
3641 goto errout;
3642 }
3643
3644 return 0;
3645
3646 errout:
3647 release_resources( info );
3648 return -ENODEV;
3649 }
3650
3651 static void release_resources(SLMP_INFO *info)
3652 {
3653 if ( debug_level >= DEBUG_LEVEL_INFO )
3654 printk( "%s(%d):%s release_resources() entry\n",
3655 __FILE__,__LINE__,info->device_name );
3656
3657 if ( info->irq_requested ) {
3658 free_irq(info->irq_level, info);
3659 info->irq_requested = false;
3660 }
3661
3662 if ( info->shared_mem_requested ) {
3663 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3664 info->shared_mem_requested = false;
3665 }
3666 if ( info->lcr_mem_requested ) {
3667 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3668 info->lcr_mem_requested = false;
3669 }
3670 if ( info->sca_base_requested ) {
3671 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3672 info->sca_base_requested = false;
3673 }
3674 if ( info->sca_statctrl_requested ) {
3675 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3676 info->sca_statctrl_requested = false;
3677 }
3678
3679 if (info->memory_base){
3680 iounmap(info->memory_base);
3681 info->memory_base = NULL;
3682 }
3683
3684 if (info->sca_base) {
3685 iounmap(info->sca_base - info->sca_offset);
3686 info->sca_base=NULL;
3687 }
3688
3689 if (info->statctrl_base) {
3690 iounmap(info->statctrl_base - info->statctrl_offset);
3691 info->statctrl_base=NULL;
3692 }
3693
3694 if (info->lcr_base){
3695 iounmap(info->lcr_base - info->lcr_offset);
3696 info->lcr_base = NULL;
3697 }
3698
3699 if ( debug_level >= DEBUG_LEVEL_INFO )
3700 printk( "%s(%d):%s release_resources() exit\n",
3701 __FILE__,__LINE__,info->device_name );
3702 }
3703
3704 /* Add the specified device instance data structure to the
3705 * global linked list of devices and increment the device count.
3706 */
3707 static void add_device(SLMP_INFO *info)
3708 {
3709 info->next_device = NULL;
3710 info->line = synclinkmp_device_count;
3711 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3712
3713 if (info->line < MAX_DEVICES) {
3714 if (maxframe[info->line])
3715 info->max_frame_size = maxframe[info->line];
3716 }
3717
3718 synclinkmp_device_count++;
3719
3720 if ( !synclinkmp_device_list )
3721 synclinkmp_device_list = info;
3722 else {
3723 SLMP_INFO *current_dev = synclinkmp_device_list;
3724 while( current_dev->next_device )
3725 current_dev = current_dev->next_device;
3726 current_dev->next_device = info;
3727 }
3728
3729 if ( info->max_frame_size < 4096 )
3730 info->max_frame_size = 4096;
3731 else if ( info->max_frame_size > 65535 )
3732 info->max_frame_size = 65535;
3733
3734 printk( "SyncLink MultiPort %s: "
3735 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3736 info->device_name,
3737 info->phys_sca_base,
3738 info->phys_memory_base,
3739 info->phys_statctrl_base,
3740 info->phys_lcr_base,
3741 info->irq_level,
3742 info->max_frame_size );
3743
3744 #if SYNCLINK_GENERIC_HDLC
3745 hdlcdev_init(info);
3746 #endif
3747 }
3748
3749 static const struct tty_port_operations port_ops = {
3750 .carrier_raised = carrier_raised,
3751 .raise_dtr_rts = raise_dtr_rts,
3752 };
3753
3754 /* Allocate and initialize a device instance structure
3755 *
3756 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3757 */
3758 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3759 {
3760 SLMP_INFO *info;
3761
3762 info = kzalloc(sizeof(SLMP_INFO),
3763 GFP_KERNEL);
3764
3765 if (!info) {
3766 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3767 __FILE__,__LINE__, adapter_num, port_num);
3768 } else {
3769 tty_port_init(&info->port);
3770 info->port.ops = &port_ops;
3771 info->magic = MGSL_MAGIC;
3772 INIT_WORK(&info->task, bh_handler);
3773 info->max_frame_size = 4096;
3774 info->port.close_delay = 5*HZ/10;
3775 info->port.closing_wait = 30*HZ;
3776 init_waitqueue_head(&info->status_event_wait_q);
3777 init_waitqueue_head(&info->event_wait_q);
3778 spin_lock_init(&info->netlock);
3779 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3780 info->idle_mode = HDLC_TXIDLE_FLAGS;
3781 info->adapter_num = adapter_num;
3782 info->port_num = port_num;
3783
3784 /* Copy configuration info to device instance data */
3785 info->irq_level = pdev->irq;
3786 info->phys_lcr_base = pci_resource_start(pdev,0);
3787 info->phys_sca_base = pci_resource_start(pdev,2);
3788 info->phys_memory_base = pci_resource_start(pdev,3);
3789 info->phys_statctrl_base = pci_resource_start(pdev,4);
3790
3791 /* Because veremap only works on page boundaries we must map
3792 * a larger area than is actually implemented for the LCR
3793 * memory range. We map a full page starting at the page boundary.
3794 */
3795 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3796 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3797
3798 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3799 info->phys_sca_base &= ~(PAGE_SIZE-1);
3800
3801 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3802 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3803
3804 info->bus_type = MGSL_BUS_TYPE_PCI;
3805 info->irq_flags = IRQF_SHARED;
3806
3807 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3808 setup_timer(&info->status_timer, status_timeout,
3809 (unsigned long)info);
3810
3811 /* Store the PCI9050 misc control register value because a flaw
3812 * in the PCI9050 prevents LCR registers from being read if
3813 * BIOS assigns an LCR base address with bit 7 set.
3814 *
3815 * Only the misc control register is accessed for which only
3816 * write access is needed, so set an initial value and change
3817 * bits to the device instance data as we write the value
3818 * to the actual misc control register.
3819 */
3820 info->misc_ctrl_value = 0x087e4546;
3821
3822 /* initial port state is unknown - if startup errors
3823 * occur, init_error will be set to indicate the
3824 * problem. Once the port is fully initialized,
3825 * this value will be set to 0 to indicate the
3826 * port is available.
3827 */
3828 info->init_error = -1;
3829 }
3830
3831 return info;
3832 }
3833
3834 static void device_init(int adapter_num, struct pci_dev *pdev)
3835 {
3836 SLMP_INFO *port_array[SCA_MAX_PORTS];
3837 int port;
3838
3839 /* allocate device instances for up to SCA_MAX_PORTS devices */
3840 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3841 port_array[port] = alloc_dev(adapter_num,port,pdev);
3842 if( port_array[port] == NULL ) {
3843 for ( --port; port >= 0; --port )
3844 kfree(port_array[port]);
3845 return;
3846 }
3847 }
3848
3849 /* give copy of port_array to all ports and add to device list */
3850 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3851 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3852 add_device( port_array[port] );
3853 spin_lock_init(&port_array[port]->lock);
3854 }
3855
3856 /* Allocate and claim adapter resources */
3857 if ( !claim_resources(port_array[0]) ) {
3858
3859 alloc_dma_bufs(port_array[0]);
3860
3861 /* copy resource information from first port to others */
3862 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3863 port_array[port]->lock = port_array[0]->lock;
3864 port_array[port]->irq_level = port_array[0]->irq_level;
3865 port_array[port]->memory_base = port_array[0]->memory_base;
3866 port_array[port]->sca_base = port_array[0]->sca_base;
3867 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3868 port_array[port]->lcr_base = port_array[0]->lcr_base;
3869 alloc_dma_bufs(port_array[port]);
3870 }
3871
3872 if ( request_irq(port_array[0]->irq_level,
3873 synclinkmp_interrupt,
3874 port_array[0]->irq_flags,
3875 port_array[0]->device_name,
3876 port_array[0]) < 0 ) {
3877 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3878 __FILE__,__LINE__,
3879 port_array[0]->device_name,
3880 port_array[0]->irq_level );
3881 }
3882 else {
3883 port_array[0]->irq_requested = true;
3884 adapter_test(port_array[0]);
3885 }
3886 }
3887 }
3888
3889 static const struct tty_operations ops = {
3890 .open = open,
3891 .close = close,
3892 .write = write,
3893 .put_char = put_char,
3894 .flush_chars = flush_chars,
3895 .write_room = write_room,
3896 .chars_in_buffer = chars_in_buffer,
3897 .flush_buffer = flush_buffer,
3898 .ioctl = ioctl,
3899 .throttle = throttle,
3900 .unthrottle = unthrottle,
3901 .send_xchar = send_xchar,
3902 .break_ctl = set_break,
3903 .wait_until_sent = wait_until_sent,
3904 .read_proc = read_proc,
3905 .set_termios = set_termios,
3906 .stop = tx_hold,
3907 .start = tx_release,
3908 .hangup = hangup,
3909 .tiocmget = tiocmget,
3910 .tiocmset = tiocmset,
3911 };
3912
3913
3914 static void synclinkmp_cleanup(void)
3915 {
3916 int rc;
3917 SLMP_INFO *info;
3918 SLMP_INFO *tmp;
3919
3920 printk("Unloading %s %s\n", driver_name, driver_version);
3921
3922 if (serial_driver) {
3923 if ((rc = tty_unregister_driver(serial_driver)))
3924 printk("%s(%d) failed to unregister tty driver err=%d\n",
3925 __FILE__,__LINE__,rc);
3926 put_tty_driver(serial_driver);
3927 }
3928
3929 /* reset devices */
3930 info = synclinkmp_device_list;
3931 while(info) {
3932 reset_port(info);
3933 info = info->next_device;
3934 }
3935
3936 /* release devices */
3937 info = synclinkmp_device_list;
3938 while(info) {
3939 #if SYNCLINK_GENERIC_HDLC
3940 hdlcdev_exit(info);
3941 #endif
3942 free_dma_bufs(info);
3943 free_tmp_rx_buf(info);
3944 if ( info->port_num == 0 ) {
3945 if (info->sca_base)
3946 write_reg(info, LPR, 1); /* set low power mode */
3947 release_resources(info);
3948 }
3949 tmp = info;
3950 info = info->next_device;
3951 kfree(tmp);
3952 }
3953
3954 pci_unregister_driver(&synclinkmp_pci_driver);
3955 }
3956
3957 /* Driver initialization entry point.
3958 */
3959
3960 static int __init synclinkmp_init(void)
3961 {
3962 int rc;
3963
3964 if (break_on_load) {
3965 synclinkmp_get_text_ptr();
3966 BREAKPOINT();
3967 }
3968
3969 printk("%s %s\n", driver_name, driver_version);
3970
3971 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3972 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3973 return rc;
3974 }
3975
3976 serial_driver = alloc_tty_driver(128);
3977 if (!serial_driver) {
3978 rc = -ENOMEM;
3979 goto error;
3980 }
3981
3982 /* Initialize the tty_driver structure */
3983
3984 serial_driver->owner = THIS_MODULE;
3985 serial_driver->driver_name = "synclinkmp";
3986 serial_driver->name = "ttySLM";
3987 serial_driver->major = ttymajor;
3988 serial_driver->minor_start = 64;
3989 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3990 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3991 serial_driver->init_termios = tty_std_termios;
3992 serial_driver->init_termios.c_cflag =
3993 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3994 serial_driver->init_termios.c_ispeed = 9600;
3995 serial_driver->init_termios.c_ospeed = 9600;
3996 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3997 tty_set_operations(serial_driver, &ops);
3998 if ((rc = tty_register_driver(serial_driver)) < 0) {
3999 printk("%s(%d):Couldn't register serial driver\n",
4000 __FILE__,__LINE__);
4001 put_tty_driver(serial_driver);
4002 serial_driver = NULL;
4003 goto error;
4004 }
4005
4006 printk("%s %s, tty major#%d\n",
4007 driver_name, driver_version,
4008 serial_driver->major);
4009
4010 return 0;
4011
4012 error:
4013 synclinkmp_cleanup();
4014 return rc;
4015 }
4016
4017 static void __exit synclinkmp_exit(void)
4018 {
4019 synclinkmp_cleanup();
4020 }
4021
4022 module_init(synclinkmp_init);
4023 module_exit(synclinkmp_exit);
4024
4025 /* Set the port for internal loopback mode.
4026 * The TxCLK and RxCLK signals are generated from the BRG and
4027 * the TxD is looped back to the RxD internally.
4028 */
4029 static void enable_loopback(SLMP_INFO *info, int enable)
4030 {
4031 if (enable) {
4032 /* MD2 (Mode Register 2)
4033 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4034 */
4035 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4036
4037 /* degate external TxC clock source */
4038 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4039 write_control_reg(info);
4040
4041 /* RXS/TXS (Rx/Tx clock source)
4042 * 07 Reserved, must be 0
4043 * 06..04 Clock Source, 100=BRG
4044 * 03..00 Clock Divisor, 0000=1
4045 */
4046 write_reg(info, RXS, 0x40);
4047 write_reg(info, TXS, 0x40);
4048
4049 } else {
4050 /* MD2 (Mode Register 2)
4051 * 01..00 CNCT<1..0> Channel connection, 0=normal
4052 */
4053 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4054
4055 /* RXS/TXS (Rx/Tx clock source)
4056 * 07 Reserved, must be 0
4057 * 06..04 Clock Source, 000=RxC/TxC Pin
4058 * 03..00 Clock Divisor, 0000=1
4059 */
4060 write_reg(info, RXS, 0x00);
4061 write_reg(info, TXS, 0x00);
4062 }
4063
4064 /* set LinkSpeed if available, otherwise default to 2Mbps */
4065 if (info->params.clock_speed)
4066 set_rate(info, info->params.clock_speed);
4067 else
4068 set_rate(info, 3686400);
4069 }
4070
4071 /* Set the baud rate register to the desired speed
4072 *
4073 * data_rate data rate of clock in bits per second
4074 * A data rate of 0 disables the AUX clock.
4075 */
4076 static void set_rate( SLMP_INFO *info, u32 data_rate )
4077 {
4078 u32 TMCValue;
4079 unsigned char BRValue;
4080 u32 Divisor=0;
4081
4082 /* fBRG = fCLK/(TMC * 2^BR)
4083 */
4084 if (data_rate != 0) {
4085 Divisor = 14745600/data_rate;
4086 if (!Divisor)
4087 Divisor = 1;
4088
4089 TMCValue = Divisor;
4090
4091 BRValue = 0;
4092 if (TMCValue != 1 && TMCValue != 2) {
4093 /* BRValue of 0 provides 50/50 duty cycle *only* when
4094 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4095 * 50/50 duty cycle.
4096 */
4097 BRValue = 1;
4098 TMCValue >>= 1;
4099 }
4100
4101 /* while TMCValue is too big for TMC register, divide
4102 * by 2 and increment BR exponent.
4103 */
4104 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4105 TMCValue >>= 1;
4106
4107 write_reg(info, TXS,
4108 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4109 write_reg(info, RXS,
4110 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4111 write_reg(info, TMC, (unsigned char)TMCValue);
4112 }
4113 else {
4114 write_reg(info, TXS,0);
4115 write_reg(info, RXS,0);
4116 write_reg(info, TMC, 0);
4117 }
4118 }
4119
4120 /* Disable receiver
4121 */
4122 static void rx_stop(SLMP_INFO *info)
4123 {
4124 if (debug_level >= DEBUG_LEVEL_ISR)
4125 printk("%s(%d):%s rx_stop()\n",
4126 __FILE__,__LINE__, info->device_name );
4127
4128 write_reg(info, CMD, RXRESET);
4129
4130 info->ie0_value &= ~RXRDYE;
4131 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4132
4133 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4134 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4135 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4136
4137 info->rx_enabled = false;
4138 info->rx_overflow = false;
4139 }
4140
4141 /* enable the receiver
4142 */
4143 static void rx_start(SLMP_INFO *info)
4144 {
4145 int i;
4146
4147 if (debug_level >= DEBUG_LEVEL_ISR)
4148 printk("%s(%d):%s rx_start()\n",
4149 __FILE__,__LINE__, info->device_name );
4150
4151 write_reg(info, CMD, RXRESET);
4152
4153 if ( info->params.mode == MGSL_MODE_HDLC ) {
4154 /* HDLC, disabe IRQ on rxdata */
4155 info->ie0_value &= ~RXRDYE;
4156 write_reg(info, IE0, info->ie0_value);
4157
4158 /* Reset all Rx DMA buffers and program rx dma */
4159 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4160 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4161
4162 for (i = 0; i < info->rx_buf_count; i++) {
4163 info->rx_buf_list[i].status = 0xff;
4164
4165 // throttle to 4 shared memory writes at a time to prevent
4166 // hogging local bus (keep latency time for DMA requests low).
4167 if (!(i % 4))
4168 read_status_reg(info);
4169 }
4170 info->current_rx_buf = 0;
4171
4172 /* set current/1st descriptor address */
4173 write_reg16(info, RXDMA + CDA,
4174 info->rx_buf_list_ex[0].phys_entry);
4175
4176 /* set new last rx descriptor address */
4177 write_reg16(info, RXDMA + EDA,
4178 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4179
4180 /* set buffer length (shared by all rx dma data buffers) */
4181 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4182
4183 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4184 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4185 } else {
4186 /* async, enable IRQ on rxdata */
4187 info->ie0_value |= RXRDYE;
4188 write_reg(info, IE0, info->ie0_value);
4189 }
4190
4191 write_reg(info, CMD, RXENABLE);
4192
4193 info->rx_overflow = false;
4194 info->rx_enabled = true;
4195 }
4196
4197 /* Enable the transmitter and send a transmit frame if
4198 * one is loaded in the DMA buffers.
4199 */
4200 static void tx_start(SLMP_INFO *info)
4201 {
4202 if (debug_level >= DEBUG_LEVEL_ISR)
4203 printk("%s(%d):%s tx_start() tx_count=%d\n",
4204 __FILE__,__LINE__, info->device_name,info->tx_count );
4205
4206 if (!info->tx_enabled ) {
4207 write_reg(info, CMD, TXRESET);
4208 write_reg(info, CMD, TXENABLE);
4209 info->tx_enabled = true;
4210 }
4211
4212 if ( info->tx_count ) {
4213
4214 /* If auto RTS enabled and RTS is inactive, then assert */
4215 /* RTS and set a flag indicating that the driver should */
4216 /* negate RTS when the transmission completes. */
4217
4218 info->drop_rts_on_tx_done = false;
4219
4220 if (info->params.mode != MGSL_MODE_ASYNC) {
4221
4222 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4223 get_signals( info );
4224 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4225 info->serial_signals |= SerialSignal_RTS;
4226 set_signals( info );
4227 info->drop_rts_on_tx_done = true;
4228 }
4229 }
4230
4231 write_reg16(info, TRC0,
4232 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4233
4234 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4235 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4236
4237 /* set TX CDA (current descriptor address) */
4238 write_reg16(info, TXDMA + CDA,
4239 info->tx_buf_list_ex[0].phys_entry);
4240
4241 /* set TX EDA (last descriptor address) */
4242 write_reg16(info, TXDMA + EDA,
4243 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4244
4245 /* enable underrun IRQ */
4246 info->ie1_value &= ~IDLE;
4247 info->ie1_value |= UDRN;
4248 write_reg(info, IE1, info->ie1_value);
4249 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4250
4251 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4252 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4253
4254 mod_timer(&info->tx_timer, jiffies +
4255 msecs_to_jiffies(5000));
4256 }
4257 else {
4258 tx_load_fifo(info);
4259 /* async, enable IRQ on txdata */
4260 info->ie0_value |= TXRDYE;
4261 write_reg(info, IE0, info->ie0_value);
4262 }
4263
4264 info->tx_active = true;
4265 }
4266 }
4267
4268 /* stop the transmitter and DMA
4269 */
4270 static void tx_stop( SLMP_INFO *info )
4271 {
4272 if (debug_level >= DEBUG_LEVEL_ISR)
4273 printk("%s(%d):%s tx_stop()\n",
4274 __FILE__,__LINE__, info->device_name );
4275
4276 del_timer(&info->tx_timer);
4277
4278 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4279 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4280
4281 write_reg(info, CMD, TXRESET);
4282
4283 info->ie1_value &= ~(UDRN + IDLE);
4284 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4285 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4286
4287 info->ie0_value &= ~TXRDYE;
4288 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4289
4290 info->tx_enabled = false;
4291 info->tx_active = false;
4292 }
4293
4294 /* Fill the transmit FIFO until the FIFO is full or
4295 * there is no more data to load.
4296 */
4297 static void tx_load_fifo(SLMP_INFO *info)
4298 {
4299 u8 TwoBytes[2];
4300
4301 /* do nothing is now tx data available and no XON/XOFF pending */
4302
4303 if ( !info->tx_count && !info->x_char )
4304 return;
4305
4306 /* load the Transmit FIFO until FIFOs full or all data sent */
4307
4308 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4309
4310 /* there is more space in the transmit FIFO and */
4311 /* there is more data in transmit buffer */
4312
4313 if ( (info->tx_count > 1) && !info->x_char ) {
4314 /* write 16-bits */
4315 TwoBytes[0] = info->tx_buf[info->tx_get++];
4316 if (info->tx_get >= info->max_frame_size)
4317 info->tx_get -= info->max_frame_size;
4318 TwoBytes[1] = info->tx_buf[info->tx_get++];
4319 if (info->tx_get >= info->max_frame_size)
4320 info->tx_get -= info->max_frame_size;
4321
4322 write_reg16(info, TRB, *((u16 *)TwoBytes));
4323
4324 info->tx_count -= 2;
4325 info->icount.tx += 2;
4326 } else {
4327 /* only 1 byte left to transmit or 1 FIFO slot left */
4328
4329 if (info->x_char) {
4330 /* transmit pending high priority char */
4331 write_reg(info, TRB, info->x_char);
4332 info->x_char = 0;
4333 } else {
4334 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4335 if (info->tx_get >= info->max_frame_size)
4336 info->tx_get -= info->max_frame_size;
4337 info->tx_count--;
4338 }
4339 info->icount.tx++;
4340 }
4341 }
4342 }
4343
4344 /* Reset a port to a known state
4345 */
4346 static void reset_port(SLMP_INFO *info)
4347 {
4348 if (info->sca_base) {
4349
4350 tx_stop(info);
4351 rx_stop(info);
4352
4353 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4354 set_signals(info);
4355
4356 /* disable all port interrupts */
4357 info->ie0_value = 0;
4358 info->ie1_value = 0;
4359 info->ie2_value = 0;
4360 write_reg(info, IE0, info->ie0_value);
4361 write_reg(info, IE1, info->ie1_value);
4362 write_reg(info, IE2, info->ie2_value);
4363
4364 write_reg(info, CMD, CHRESET);
4365 }
4366 }
4367
4368 /* Reset all the ports to a known state.
4369 */
4370 static void reset_adapter(SLMP_INFO *info)
4371 {
4372 int i;
4373
4374 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4375 if (info->port_array[i])
4376 reset_port(info->port_array[i]);
4377 }
4378 }
4379
4380 /* Program port for asynchronous communications.
4381 */
4382 static void async_mode(SLMP_INFO *info)
4383 {
4384
4385 unsigned char RegValue;
4386
4387 tx_stop(info);
4388 rx_stop(info);
4389
4390 /* MD0, Mode Register 0
4391 *
4392 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4393 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4394 * 03 Reserved, must be 0
4395 * 02 CRCCC, CRC Calculation, 0=disabled
4396 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4397 *
4398 * 0000 0000
4399 */
4400 RegValue = 0x00;
4401 if (info->params.stop_bits != 1)
4402 RegValue |= BIT1;
4403 write_reg(info, MD0, RegValue);
4404
4405 /* MD1, Mode Register 1
4406 *
4407 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4408 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4409 * 03..02 RXCHR<1..0>, rx char size
4410 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4411 *
4412 * 0100 0000
4413 */
4414 RegValue = 0x40;
4415 switch (info->params.data_bits) {
4416 case 7: RegValue |= BIT4 + BIT2; break;
4417 case 6: RegValue |= BIT5 + BIT3; break;
4418 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4419 }
4420 if (info->params.parity != ASYNC_PARITY_NONE) {
4421 RegValue |= BIT1;
4422 if (info->params.parity == ASYNC_PARITY_ODD)
4423 RegValue |= BIT0;
4424 }
4425 write_reg(info, MD1, RegValue);
4426
4427 /* MD2, Mode Register 2
4428 *
4429 * 07..02 Reserved, must be 0
4430 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4431 *
4432 * 0000 0000
4433 */
4434 RegValue = 0x00;
4435 if (info->params.loopback)
4436 RegValue |= (BIT1 + BIT0);
4437 write_reg(info, MD2, RegValue);
4438
4439 /* RXS, Receive clock source
4440 *
4441 * 07 Reserved, must be 0
4442 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4443 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4444 */
4445 RegValue=BIT6;
4446 write_reg(info, RXS, RegValue);
4447
4448 /* TXS, Transmit clock source
4449 *
4450 * 07 Reserved, must be 0
4451 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4452 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4453 */
4454 RegValue=BIT6;
4455 write_reg(info, TXS, RegValue);
4456
4457 /* Control Register
4458 *
4459 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4460 */
4461 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4462 write_control_reg(info);
4463
4464 tx_set_idle(info);
4465
4466 /* RRC Receive Ready Control 0
4467 *
4468 * 07..05 Reserved, must be 0
4469 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4470 */
4471 write_reg(info, RRC, 0x00);
4472
4473 /* TRC0 Transmit Ready Control 0
4474 *
4475 * 07..05 Reserved, must be 0
4476 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4477 */
4478 write_reg(info, TRC0, 0x10);
4479
4480 /* TRC1 Transmit Ready Control 1
4481 *
4482 * 07..05 Reserved, must be 0
4483 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4484 */
4485 write_reg(info, TRC1, 0x1e);
4486
4487 /* CTL, MSCI control register
4488 *
4489 * 07..06 Reserved, set to 0
4490 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4491 * 04 IDLC, idle control, 0=mark 1=idle register
4492 * 03 BRK, break, 0=off 1 =on (async)
4493 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4494 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4495 * 00 RTS, RTS output control, 0=active 1=inactive
4496 *
4497 * 0001 0001
4498 */
4499 RegValue = 0x10;
4500 if (!(info->serial_signals & SerialSignal_RTS))
4501 RegValue |= 0x01;
4502 write_reg(info, CTL, RegValue);
4503
4504 /* enable status interrupts */
4505 info->ie0_value |= TXINTE + RXINTE;
4506 write_reg(info, IE0, info->ie0_value);
4507
4508 /* enable break detect interrupt */
4509 info->ie1_value = BRKD;
4510 write_reg(info, IE1, info->ie1_value);
4511
4512 /* enable rx overrun interrupt */
4513 info->ie2_value = OVRN;
4514 write_reg(info, IE2, info->ie2_value);
4515
4516 set_rate( info, info->params.data_rate * 16 );
4517 }
4518
4519 /* Program the SCA for HDLC communications.
4520 */
4521 static void hdlc_mode(SLMP_INFO *info)
4522 {
4523 unsigned char RegValue;
4524 u32 DpllDivisor;
4525
4526 // Can't use DPLL because SCA outputs recovered clock on RxC when
4527 // DPLL mode selected. This causes output contention with RxC receiver.
4528 // Use of DPLL would require external hardware to disable RxC receiver
4529 // when DPLL mode selected.
4530 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4531
4532 /* disable DMA interrupts */
4533 write_reg(info, TXDMA + DIR, 0);
4534 write_reg(info, RXDMA + DIR, 0);
4535
4536 /* MD0, Mode Register 0
4537 *
4538 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4539 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4540 * 03 Reserved, must be 0
4541 * 02 CRCCC, CRC Calculation, 1=enabled
4542 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4543 * 00 CRC0, CRC initial value, 1 = all 1s
4544 *
4545 * 1000 0001
4546 */
4547 RegValue = 0x81;
4548 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4549 RegValue |= BIT4;
4550 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4551 RegValue |= BIT4;
4552 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4553 RegValue |= BIT2 + BIT1;
4554 write_reg(info, MD0, RegValue);
4555
4556 /* MD1, Mode Register 1
4557 *
4558 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4559 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4560 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4561 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4562 *
4563 * 0000 0000
4564 */
4565 RegValue = 0x00;
4566 write_reg(info, MD1, RegValue);
4567
4568 /* MD2, Mode Register 2
4569 *
4570 * 07 NRZFM, 0=NRZ, 1=FM
4571 * 06..05 CODE<1..0> Encoding, 00=NRZ
4572 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4573 * 02 Reserved, must be 0
4574 * 01..00 CNCT<1..0> Channel connection, 0=normal
4575 *
4576 * 0000 0000
4577 */
4578 RegValue = 0x00;
4579 switch(info->params.encoding) {
4580 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4581 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4582 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4583 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4584 #if 0
4585 case HDLC_ENCODING_NRZB: /* not supported */
4586 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4587 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4588 #endif
4589 }
4590 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4591 DpllDivisor = 16;
4592 RegValue |= BIT3;
4593 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4594 DpllDivisor = 8;
4595 } else {
4596 DpllDivisor = 32;
4597 RegValue |= BIT4;
4598 }
4599 write_reg(info, MD2, RegValue);
4600
4601
4602 /* RXS, Receive clock source
4603 *
4604 * 07 Reserved, must be 0
4605 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4606 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4607 */
4608 RegValue=0;
4609 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4610 RegValue |= BIT6;
4611 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4612 RegValue |= BIT6 + BIT5;
4613 write_reg(info, RXS, RegValue);
4614
4615 /* TXS, Transmit clock source
4616 *
4617 * 07 Reserved, must be 0
4618 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4619 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4620 */
4621 RegValue=0;
4622 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4623 RegValue |= BIT6;
4624 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4625 RegValue |= BIT6 + BIT5;
4626 write_reg(info, TXS, RegValue);
4627
4628 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4629 set_rate(info, info->params.clock_speed * DpllDivisor);
4630 else
4631 set_rate(info, info->params.clock_speed);
4632
4633 /* GPDATA (General Purpose I/O Data Register)
4634 *
4635 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4636 */
4637 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4638 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4639 else
4640 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4641 write_control_reg(info);
4642
4643 /* RRC Receive Ready Control 0
4644 *
4645 * 07..05 Reserved, must be 0
4646 * 04..00 RRC<4..0> Rx FIFO trigger active
4647 */
4648 write_reg(info, RRC, rx_active_fifo_level);
4649
4650 /* TRC0 Transmit Ready Control 0
4651 *
4652 * 07..05 Reserved, must be 0
4653 * 04..00 TRC<4..0> Tx FIFO trigger active
4654 */
4655 write_reg(info, TRC0, tx_active_fifo_level);
4656
4657 /* TRC1 Transmit Ready Control 1
4658 *
4659 * 07..05 Reserved, must be 0
4660 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4661 */
4662 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4663
4664 /* DMR, DMA Mode Register
4665 *
4666 * 07..05 Reserved, must be 0
4667 * 04 TMOD, Transfer Mode: 1=chained-block
4668 * 03 Reserved, must be 0
4669 * 02 NF, Number of Frames: 1=multi-frame
4670 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4671 * 00 Reserved, must be 0
4672 *
4673 * 0001 0100
4674 */
4675 write_reg(info, TXDMA + DMR, 0x14);
4676 write_reg(info, RXDMA + DMR, 0x14);
4677
4678 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4679 write_reg(info, RXDMA + CPB,
4680 (unsigned char)(info->buffer_list_phys >> 16));
4681
4682 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4683 write_reg(info, TXDMA + CPB,
4684 (unsigned char)(info->buffer_list_phys >> 16));
4685
4686 /* enable status interrupts. other code enables/disables
4687 * the individual sources for these two interrupt classes.
4688 */
4689 info->ie0_value |= TXINTE + RXINTE;
4690 write_reg(info, IE0, info->ie0_value);
4691
4692 /* CTL, MSCI control register
4693 *
4694 * 07..06 Reserved, set to 0
4695 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4696 * 04 IDLC, idle control, 0=mark 1=idle register
4697 * 03 BRK, break, 0=off 1 =on (async)
4698 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4699 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4700 * 00 RTS, RTS output control, 0=active 1=inactive
4701 *
4702 * 0001 0001
4703 */
4704 RegValue = 0x10;
4705 if (!(info->serial_signals & SerialSignal_RTS))
4706 RegValue |= 0x01;
4707 write_reg(info, CTL, RegValue);
4708
4709 /* preamble not supported ! */
4710
4711 tx_set_idle(info);
4712 tx_stop(info);
4713 rx_stop(info);
4714
4715 set_rate(info, info->params.clock_speed);
4716
4717 if (info->params.loopback)
4718 enable_loopback(info,1);
4719 }
4720
4721 /* Set the transmit HDLC idle mode
4722 */
4723 static void tx_set_idle(SLMP_INFO *info)
4724 {
4725 unsigned char RegValue = 0xff;
4726
4727 /* Map API idle mode to SCA register bits */
4728 switch(info->idle_mode) {
4729 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4730 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4731 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4732 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4733 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4734 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4735 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4736 }
4737
4738 write_reg(info, IDL, RegValue);
4739 }
4740
4741 /* Query the adapter for the state of the V24 status (input) signals.
4742 */
4743 static void get_signals(SLMP_INFO *info)
4744 {
4745 u16 status = read_reg(info, SR3);
4746 u16 gpstatus = read_status_reg(info);
4747 u16 testbit;
4748
4749 /* clear all serial signals except DTR and RTS */
4750 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4751
4752 /* set serial signal bits to reflect MISR */
4753
4754 if (!(status & BIT3))
4755 info->serial_signals |= SerialSignal_CTS;
4756
4757 if ( !(status & BIT2))
4758 info->serial_signals |= SerialSignal_DCD;
4759
4760 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4761 if (!(gpstatus & testbit))
4762 info->serial_signals |= SerialSignal_RI;
4763
4764 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4765 if (!(gpstatus & testbit))
4766 info->serial_signals |= SerialSignal_DSR;
4767 }
4768
4769 /* Set the state of DTR and RTS based on contents of
4770 * serial_signals member of device context.
4771 */
4772 static void set_signals(SLMP_INFO *info)
4773 {
4774 unsigned char RegValue;
4775 u16 EnableBit;
4776
4777 RegValue = read_reg(info, CTL);
4778 if (info->serial_signals & SerialSignal_RTS)
4779 RegValue &= ~BIT0;
4780 else
4781 RegValue |= BIT0;
4782 write_reg(info, CTL, RegValue);
4783
4784 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4785 EnableBit = BIT1 << (info->port_num*2);
4786 if (info->serial_signals & SerialSignal_DTR)
4787 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4788 else
4789 info->port_array[0]->ctrlreg_value |= EnableBit;
4790 write_control_reg(info);
4791 }
4792
4793 /*******************/
4794 /* DMA Buffer Code */
4795 /*******************/
4796
4797 /* Set the count for all receive buffers to SCABUFSIZE
4798 * and set the current buffer to the first buffer. This effectively
4799 * makes all buffers free and discards any data in buffers.
4800 */
4801 static void rx_reset_buffers(SLMP_INFO *info)
4802 {
4803 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4804 }
4805
4806 /* Free the buffers used by a received frame
4807 *
4808 * info pointer to device instance data
4809 * first index of 1st receive buffer of frame
4810 * last index of last receive buffer of frame
4811 */
4812 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4813 {
4814 bool done = false;
4815
4816 while(!done) {
4817 /* reset current buffer for reuse */
4818 info->rx_buf_list[first].status = 0xff;
4819
4820 if (first == last) {
4821 done = true;
4822 /* set new last rx descriptor address */
4823 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4824 }
4825
4826 first++;
4827 if (first == info->rx_buf_count)
4828 first = 0;
4829 }
4830
4831 /* set current buffer to next buffer after last buffer of frame */
4832 info->current_rx_buf = first;
4833 }
4834
4835 /* Return a received frame from the receive DMA buffers.
4836 * Only frames received without errors are returned.
4837 *
4838 * Return Value: true if frame returned, otherwise false
4839 */
4840 static bool rx_get_frame(SLMP_INFO *info)
4841 {
4842 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4843 unsigned short status;
4844 unsigned int framesize = 0;
4845 bool ReturnCode = false;
4846 unsigned long flags;
4847 struct tty_struct *tty = info->port.tty;
4848 unsigned char addr_field = 0xff;
4849 SCADESC *desc;
4850 SCADESC_EX *desc_ex;
4851
4852 CheckAgain:
4853 /* assume no frame returned, set zero length */
4854 framesize = 0;
4855 addr_field = 0xff;
4856
4857 /*
4858 * current_rx_buf points to the 1st buffer of the next available
4859 * receive frame. To find the last buffer of the frame look for
4860 * a non-zero status field in the buffer entries. (The status
4861 * field is set by the 16C32 after completing a receive frame.
4862 */
4863 StartIndex = EndIndex = info->current_rx_buf;
4864
4865 for ( ;; ) {
4866 desc = &info->rx_buf_list[EndIndex];
4867 desc_ex = &info->rx_buf_list_ex[EndIndex];
4868
4869 if (desc->status == 0xff)
4870 goto Cleanup; /* current desc still in use, no frames available */
4871
4872 if (framesize == 0 && info->params.addr_filter != 0xff)
4873 addr_field = desc_ex->virt_addr[0];
4874
4875 framesize += desc->length;
4876
4877 /* Status != 0 means last buffer of frame */
4878 if (desc->status)
4879 break;
4880
4881 EndIndex++;
4882 if (EndIndex == info->rx_buf_count)
4883 EndIndex = 0;
4884
4885 if (EndIndex == info->current_rx_buf) {
4886 /* all buffers have been 'used' but none mark */
4887 /* the end of a frame. Reset buffers and receiver. */
4888 if ( info->rx_enabled ){
4889 spin_lock_irqsave(&info->lock,flags);
4890 rx_start(info);
4891 spin_unlock_irqrestore(&info->lock,flags);
4892 }
4893 goto Cleanup;
4894 }
4895
4896 }
4897
4898 /* check status of receive frame */
4899
4900 /* frame status is byte stored after frame data
4901 *
4902 * 7 EOM (end of msg), 1 = last buffer of frame
4903 * 6 Short Frame, 1 = short frame
4904 * 5 Abort, 1 = frame aborted
4905 * 4 Residue, 1 = last byte is partial
4906 * 3 Overrun, 1 = overrun occurred during frame reception
4907 * 2 CRC, 1 = CRC error detected
4908 *
4909 */
4910 status = desc->status;
4911
4912 /* ignore CRC bit if not using CRC (bit is undefined) */
4913 /* Note:CRC is not save to data buffer */
4914 if (info->params.crc_type == HDLC_CRC_NONE)
4915 status &= ~BIT2;
4916
4917 if (framesize == 0 ||
4918 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4919 /* discard 0 byte frames, this seems to occur sometime
4920 * when remote is idling flags.
4921 */
4922 rx_free_frame_buffers(info, StartIndex, EndIndex);
4923 goto CheckAgain;
4924 }
4925
4926 if (framesize < 2)
4927 status |= BIT6;
4928
4929 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4930 /* received frame has errors,
4931 * update counts and mark frame size as 0
4932 */
4933 if (status & BIT6)
4934 info->icount.rxshort++;
4935 else if (status & BIT5)
4936 info->icount.rxabort++;
4937 else if (status & BIT3)
4938 info->icount.rxover++;
4939 else
4940 info->icount.rxcrc++;
4941
4942 framesize = 0;
4943 #if SYNCLINK_GENERIC_HDLC
4944 {
4945 info->netdev->stats.rx_errors++;
4946 info->netdev->stats.rx_frame_errors++;
4947 }
4948 #endif
4949 }
4950
4951 if ( debug_level >= DEBUG_LEVEL_BH )
4952 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4953 __FILE__,__LINE__,info->device_name,status,framesize);
4954
4955 if ( debug_level >= DEBUG_LEVEL_DATA )
4956 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4957 min_t(int, framesize,SCABUFSIZE),0);
4958
4959 if (framesize) {
4960 if (framesize > info->max_frame_size)
4961 info->icount.rxlong++;
4962 else {
4963 /* copy dma buffer(s) to contiguous intermediate buffer */
4964 int copy_count = framesize;
4965 int index = StartIndex;
4966 unsigned char *ptmp = info->tmp_rx_buf;
4967 info->tmp_rx_buf_count = framesize;
4968
4969 info->icount.rxok++;
4970
4971 while(copy_count) {
4972 int partial_count = min(copy_count,SCABUFSIZE);
4973 memcpy( ptmp,
4974 info->rx_buf_list_ex[index].virt_addr,
4975 partial_count );
4976 ptmp += partial_count;
4977 copy_count -= partial_count;
4978
4979 if ( ++index == info->rx_buf_count )
4980 index = 0;
4981 }
4982
4983 #if SYNCLINK_GENERIC_HDLC
4984 if (info->netcount)
4985 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4986 else
4987 #endif
4988 ldisc_receive_buf(tty,info->tmp_rx_buf,
4989 info->flag_buf, framesize);
4990 }
4991 }
4992 /* Free the buffers used by this frame. */
4993 rx_free_frame_buffers( info, StartIndex, EndIndex );
4994
4995 ReturnCode = true;
4996
4997 Cleanup:
4998 if ( info->rx_enabled && info->rx_overflow ) {
4999 /* Receiver is enabled, but needs to restarted due to
5000 * rx buffer overflow. If buffers are empty, restart receiver.
5001 */
5002 if (info->rx_buf_list[EndIndex].status == 0xff) {
5003 spin_lock_irqsave(&info->lock,flags);
5004 rx_start(info);
5005 spin_unlock_irqrestore(&info->lock,flags);
5006 }
5007 }
5008
5009 return ReturnCode;
5010 }
5011
5012 /* load the transmit DMA buffer with data
5013 */
5014 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5015 {
5016 unsigned short copy_count;
5017 unsigned int i = 0;
5018 SCADESC *desc;
5019 SCADESC_EX *desc_ex;
5020
5021 if ( debug_level >= DEBUG_LEVEL_DATA )
5022 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5023
5024 /* Copy source buffer to one or more DMA buffers, starting with
5025 * the first transmit dma buffer.
5026 */
5027 for(i=0;;)
5028 {
5029 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5030
5031 desc = &info->tx_buf_list[i];
5032 desc_ex = &info->tx_buf_list_ex[i];
5033
5034 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5035
5036 desc->length = copy_count;
5037 desc->status = 0;
5038
5039 buf += copy_count;
5040 count -= copy_count;
5041
5042 if (!count)
5043 break;
5044
5045 i++;
5046 if (i >= info->tx_buf_count)
5047 i = 0;
5048 }
5049
5050 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5051 info->last_tx_buf = ++i;
5052 }
5053
5054 static bool register_test(SLMP_INFO *info)
5055 {
5056 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5057 static unsigned int count = ARRAY_SIZE(testval);
5058 unsigned int i;
5059 bool rc = true;
5060 unsigned long flags;
5061
5062 spin_lock_irqsave(&info->lock,flags);
5063 reset_port(info);
5064
5065 /* assume failure */
5066 info->init_error = DiagStatus_AddressFailure;
5067
5068 /* Write bit patterns to various registers but do it out of */
5069 /* sync, then read back and verify values. */
5070
5071 for (i = 0 ; i < count ; i++) {
5072 write_reg(info, TMC, testval[i]);
5073 write_reg(info, IDL, testval[(i+1)%count]);
5074 write_reg(info, SA0, testval[(i+2)%count]);
5075 write_reg(info, SA1, testval[(i+3)%count]);
5076
5077 if ( (read_reg(info, TMC) != testval[i]) ||
5078 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5079 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5080 (read_reg(info, SA1) != testval[(i+3)%count]) )
5081 {
5082 rc = false;
5083 break;
5084 }
5085 }
5086
5087 reset_port(info);
5088 spin_unlock_irqrestore(&info->lock,flags);
5089
5090 return rc;
5091 }
5092
5093 static bool irq_test(SLMP_INFO *info)
5094 {
5095 unsigned long timeout;
5096 unsigned long flags;
5097
5098 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5099
5100 spin_lock_irqsave(&info->lock,flags);
5101 reset_port(info);
5102
5103 /* assume failure */
5104 info->init_error = DiagStatus_IrqFailure;
5105 info->irq_occurred = false;
5106
5107 /* setup timer0 on SCA0 to interrupt */
5108
5109 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5110 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5111
5112 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5113 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5114
5115
5116 /* TMCS, Timer Control/Status Register
5117 *
5118 * 07 CMF, Compare match flag (read only) 1=match
5119 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5120 * 05 Reserved, must be 0
5121 * 04 TME, Timer Enable
5122 * 03..00 Reserved, must be 0
5123 *
5124 * 0101 0000
5125 */
5126 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5127
5128 spin_unlock_irqrestore(&info->lock,flags);
5129
5130 timeout=100;
5131 while( timeout-- && !info->irq_occurred ) {
5132 msleep_interruptible(10);
5133 }
5134
5135 spin_lock_irqsave(&info->lock,flags);
5136 reset_port(info);
5137 spin_unlock_irqrestore(&info->lock,flags);
5138
5139 return info->irq_occurred;
5140 }
5141
5142 /* initialize individual SCA device (2 ports)
5143 */
5144 static bool sca_init(SLMP_INFO *info)
5145 {
5146 /* set wait controller to single mem partition (low), no wait states */
5147 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5148 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5149 write_reg(info, WCRL, 0); /* wait controller low range */
5150 write_reg(info, WCRM, 0); /* wait controller mid range */
5151 write_reg(info, WCRH, 0); /* wait controller high range */
5152
5153 /* DPCR, DMA Priority Control
5154 *
5155 * 07..05 Not used, must be 0
5156 * 04 BRC, bus release condition: 0=all transfers complete
5157 * 03 CCC, channel change condition: 0=every cycle
5158 * 02..00 PR<2..0>, priority 100=round robin
5159 *
5160 * 00000100 = 0x04
5161 */
5162 write_reg(info, DPCR, dma_priority);
5163
5164 /* DMA Master Enable, BIT7: 1=enable all channels */
5165 write_reg(info, DMER, 0x80);
5166
5167 /* enable all interrupt classes */
5168 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5169 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5170 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5171
5172 /* ITCR, interrupt control register
5173 * 07 IPC, interrupt priority, 0=MSCI->DMA
5174 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5175 * 04 VOS, Vector Output, 0=unmodified vector
5176 * 03..00 Reserved, must be 0
5177 */
5178 write_reg(info, ITCR, 0);
5179
5180 return true;
5181 }
5182
5183 /* initialize adapter hardware
5184 */
5185 static bool init_adapter(SLMP_INFO *info)
5186 {
5187 int i;
5188
5189 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5190 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5191 u32 readval;
5192
5193 info->misc_ctrl_value |= BIT30;
5194 *MiscCtrl = info->misc_ctrl_value;
5195
5196 /*
5197 * Force at least 170ns delay before clearing
5198 * reset bit. Each read from LCR takes at least
5199 * 30ns so 10 times for 300ns to be safe.
5200 */
5201 for(i=0;i<10;i++)
5202 readval = *MiscCtrl;
5203
5204 info->misc_ctrl_value &= ~BIT30;
5205 *MiscCtrl = info->misc_ctrl_value;
5206
5207 /* init control reg (all DTRs off, all clksel=input) */
5208 info->ctrlreg_value = 0xaa;
5209 write_control_reg(info);
5210
5211 {
5212 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5213 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5214
5215 switch(read_ahead_count)
5216 {
5217 case 16:
5218 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5219 break;
5220 case 8:
5221 lcr1_brdr_value |= BIT5 + BIT4;
5222 break;
5223 case 4:
5224 lcr1_brdr_value |= BIT5 + BIT3;
5225 break;
5226 case 0:
5227 lcr1_brdr_value |= BIT5;
5228 break;
5229 }
5230
5231 *LCR1BRDR = lcr1_brdr_value;
5232 *MiscCtrl = misc_ctrl_value;
5233 }
5234
5235 sca_init(info->port_array[0]);
5236 sca_init(info->port_array[2]);
5237
5238 return true;
5239 }
5240
5241 /* Loopback an HDLC frame to test the hardware
5242 * interrupt and DMA functions.
5243 */
5244 static bool loopback_test(SLMP_INFO *info)
5245 {
5246 #define TESTFRAMESIZE 20
5247
5248 unsigned long timeout;
5249 u16 count = TESTFRAMESIZE;
5250 unsigned char buf[TESTFRAMESIZE];
5251 bool rc = false;
5252 unsigned long flags;
5253
5254 struct tty_struct *oldtty = info->port.tty;
5255 u32 speed = info->params.clock_speed;
5256
5257 info->params.clock_speed = 3686400;
5258 info->port.tty = NULL;
5259
5260 /* assume failure */
5261 info->init_error = DiagStatus_DmaFailure;
5262
5263 /* build and send transmit frame */
5264 for (count = 0; count < TESTFRAMESIZE;++count)
5265 buf[count] = (unsigned char)count;
5266
5267 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5268
5269 /* program hardware for HDLC and enabled receiver */
5270 spin_lock_irqsave(&info->lock,flags);
5271 hdlc_mode(info);
5272 enable_loopback(info,1);
5273 rx_start(info);
5274 info->tx_count = count;
5275 tx_load_dma_buffer(info,buf,count);
5276 tx_start(info);
5277 spin_unlock_irqrestore(&info->lock,flags);
5278
5279 /* wait for receive complete */
5280 /* Set a timeout for waiting for interrupt. */
5281 for ( timeout = 100; timeout; --timeout ) {
5282 msleep_interruptible(10);
5283
5284 if (rx_get_frame(info)) {
5285 rc = true;
5286 break;
5287 }
5288 }
5289
5290 /* verify received frame length and contents */
5291 if (rc &&
5292 ( info->tmp_rx_buf_count != count ||
5293 memcmp(buf, info->tmp_rx_buf,count))) {
5294 rc = false;
5295 }
5296
5297 spin_lock_irqsave(&info->lock,flags);
5298 reset_adapter(info);
5299 spin_unlock_irqrestore(&info->lock,flags);
5300
5301 info->params.clock_speed = speed;
5302 info->port.tty = oldtty;
5303
5304 return rc;
5305 }
5306
5307 /* Perform diagnostics on hardware
5308 */
5309 static int adapter_test( SLMP_INFO *info )
5310 {
5311 unsigned long flags;
5312 if ( debug_level >= DEBUG_LEVEL_INFO )
5313 printk( "%s(%d):Testing device %s\n",
5314 __FILE__,__LINE__,info->device_name );
5315
5316 spin_lock_irqsave(&info->lock,flags);
5317 init_adapter(info);
5318 spin_unlock_irqrestore(&info->lock,flags);
5319
5320 info->port_array[0]->port_count = 0;
5321
5322 if ( register_test(info->port_array[0]) &&
5323 register_test(info->port_array[1])) {
5324
5325 info->port_array[0]->port_count = 2;
5326
5327 if ( register_test(info->port_array[2]) &&
5328 register_test(info->port_array[3]) )
5329 info->port_array[0]->port_count += 2;
5330 }
5331 else {
5332 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5333 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5334 return -ENODEV;
5335 }
5336
5337 if ( !irq_test(info->port_array[0]) ||
5338 !irq_test(info->port_array[1]) ||
5339 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5340 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5341 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5342 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5343 return -ENODEV;
5344 }
5345
5346 if (!loopback_test(info->port_array[0]) ||
5347 !loopback_test(info->port_array[1]) ||
5348 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5349 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5350 printk( "%s(%d):DMA test failure for device %s\n",
5351 __FILE__,__LINE__,info->device_name);
5352 return -ENODEV;
5353 }
5354
5355 if ( debug_level >= DEBUG_LEVEL_INFO )
5356 printk( "%s(%d):device %s passed diagnostics\n",
5357 __FILE__,__LINE__,info->device_name );
5358
5359 info->port_array[0]->init_error = 0;
5360 info->port_array[1]->init_error = 0;
5361 if ( info->port_count > 2 ) {
5362 info->port_array[2]->init_error = 0;
5363 info->port_array[3]->init_error = 0;
5364 }
5365
5366 return 0;
5367 }
5368
5369 /* Test the shared memory on a PCI adapter.
5370 */
5371 static bool memory_test(SLMP_INFO *info)
5372 {
5373 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5374 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5375 unsigned long count = ARRAY_SIZE(testval);
5376 unsigned long i;
5377 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5378 unsigned long * addr = (unsigned long *)info->memory_base;
5379
5380 /* Test data lines with test pattern at one location. */
5381
5382 for ( i = 0 ; i < count ; i++ ) {
5383 *addr = testval[i];
5384 if ( *addr != testval[i] )
5385 return false;
5386 }
5387
5388 /* Test address lines with incrementing pattern over */
5389 /* entire address range. */
5390
5391 for ( i = 0 ; i < limit ; i++ ) {
5392 *addr = i * 4;
5393 addr++;
5394 }
5395
5396 addr = (unsigned long *)info->memory_base;
5397
5398 for ( i = 0 ; i < limit ; i++ ) {
5399 if ( *addr != i * 4 )
5400 return false;
5401 addr++;
5402 }
5403
5404 memset( info->memory_base, 0, SCA_MEM_SIZE );
5405 return true;
5406 }
5407
5408 /* Load data into PCI adapter shared memory.
5409 *
5410 * The PCI9050 releases control of the local bus
5411 * after completing the current read or write operation.
5412 *
5413 * While the PCI9050 write FIFO not empty, the
5414 * PCI9050 treats all of the writes as a single transaction
5415 * and does not release the bus. This causes DMA latency problems
5416 * at high speeds when copying large data blocks to the shared memory.
5417 *
5418 * This function breaks a write into multiple transations by
5419 * interleaving a read which flushes the write FIFO and 'completes'
5420 * the write transation. This allows any pending DMA request to gain control
5421 * of the local bus in a timely fasion.
5422 */
5423 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5424 {
5425 /* A load interval of 16 allows for 4 32-bit writes at */
5426 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5427
5428 unsigned short interval = count / sca_pci_load_interval;
5429 unsigned short i;
5430
5431 for ( i = 0 ; i < interval ; i++ )
5432 {
5433 memcpy(dest, src, sca_pci_load_interval);
5434 read_status_reg(info);
5435 dest += sca_pci_load_interval;
5436 src += sca_pci_load_interval;
5437 }
5438
5439 memcpy(dest, src, count % sca_pci_load_interval);
5440 }
5441
5442 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5443 {
5444 int i;
5445 int linecount;
5446 if (xmit)
5447 printk("%s tx data:\n",info->device_name);
5448 else
5449 printk("%s rx data:\n",info->device_name);
5450
5451 while(count) {
5452 if (count > 16)
5453 linecount = 16;
5454 else
5455 linecount = count;
5456
5457 for(i=0;i<linecount;i++)
5458 printk("%02X ",(unsigned char)data[i]);
5459 for(;i<17;i++)
5460 printk(" ");
5461 for(i=0;i<linecount;i++) {
5462 if (data[i]>=040 && data[i]<=0176)
5463 printk("%c",data[i]);
5464 else
5465 printk(".");
5466 }
5467 printk("\n");
5468
5469 data += linecount;
5470 count -= linecount;
5471 }
5472 } /* end of trace_block() */
5473
5474 /* called when HDLC frame times out
5475 * update stats and do tx completion processing
5476 */
5477 static void tx_timeout(unsigned long context)
5478 {
5479 SLMP_INFO *info = (SLMP_INFO*)context;
5480 unsigned long flags;
5481
5482 if ( debug_level >= DEBUG_LEVEL_INFO )
5483 printk( "%s(%d):%s tx_timeout()\n",
5484 __FILE__,__LINE__,info->device_name);
5485 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5486 info->icount.txtimeout++;
5487 }
5488 spin_lock_irqsave(&info->lock,flags);
5489 info->tx_active = false;
5490 info->tx_count = info->tx_put = info->tx_get = 0;
5491
5492 spin_unlock_irqrestore(&info->lock,flags);
5493
5494 #if SYNCLINK_GENERIC_HDLC
5495 if (info->netcount)
5496 hdlcdev_tx_done(info);
5497 else
5498 #endif
5499 bh_transmit(info);
5500 }
5501
5502 /* called to periodically check the DSR/RI modem signal input status
5503 */
5504 static void status_timeout(unsigned long context)
5505 {
5506 u16 status = 0;
5507 SLMP_INFO *info = (SLMP_INFO*)context;
5508 unsigned long flags;
5509 unsigned char delta;
5510
5511
5512 spin_lock_irqsave(&info->lock,flags);
5513 get_signals(info);
5514 spin_unlock_irqrestore(&info->lock,flags);
5515
5516 /* check for DSR/RI state change */
5517
5518 delta = info->old_signals ^ info->serial_signals;
5519 info->old_signals = info->serial_signals;
5520
5521 if (delta & SerialSignal_DSR)
5522 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5523
5524 if (delta & SerialSignal_RI)
5525 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5526
5527 if (delta & SerialSignal_DCD)
5528 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5529
5530 if (delta & SerialSignal_CTS)
5531 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5532
5533 if (status)
5534 isr_io_pin(info,status);
5535
5536 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5537 }
5538
5539
5540 /* Register Access Routines -
5541 * All registers are memory mapped
5542 */
5543 #define CALC_REGADDR() \
5544 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5545 if (info->port_num > 1) \
5546 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5547 if ( info->port_num & 1) { \
5548 if (Addr > 0x7f) \
5549 RegAddr += 0x40; /* DMA access */ \
5550 else if (Addr > 0x1f && Addr < 0x60) \
5551 RegAddr += 0x20; /* MSCI access */ \
5552 }
5553
5554
5555 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5556 {
5557 CALC_REGADDR();
5558 return *RegAddr;
5559 }
5560 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5561 {
5562 CALC_REGADDR();
5563 *RegAddr = Value;
5564 }
5565
5566 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5567 {
5568 CALC_REGADDR();
5569 return *((u16 *)RegAddr);
5570 }
5571
5572 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5573 {
5574 CALC_REGADDR();
5575 *((u16 *)RegAddr) = Value;
5576 }
5577
5578 static unsigned char read_status_reg(SLMP_INFO * info)
5579 {
5580 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5581 return *RegAddr;
5582 }
5583
5584 static void write_control_reg(SLMP_INFO * info)
5585 {
5586 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5587 *RegAddr = info->port_array[0]->ctrlreg_value;
5588 }
5589
5590
5591 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5592 const struct pci_device_id *ent)
5593 {
5594 if (pci_enable_device(dev)) {
5595 printk("error enabling pci device %p\n", dev);
5596 return -EIO;
5597 }
5598 device_init( ++synclinkmp_adapter_count, dev );
5599 return 0;
5600 }
5601
5602 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5603 {
5604 }
Support for the Chinese Samsung S3C2440 based development boards