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md: Fix unfortunate interaction with evms
[linux-2.6/mini2440.git] / drivers / char / synclink_gt.c
blob91f20a92fddf2f9afb76dc10b7ab1d86a150954f
1 /*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24 /*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 //#define DBGTBUF(info) dump_tbufs(info)
44 //#define DBGRBUF(info) dump_rbufs(info)
45
46
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
62 #include <linux/mm.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/smp_lock.h>
66 #include <linux/netdevice.h>
67 #include <linux/vmalloc.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/ioctl.h>
71 #include <linux/termios.h>
72 #include <linux/bitops.h>
73 #include <linux/workqueue.h>
74 #include <linux/hdlc.h>
75 #include <linux/synclink.h>
76
77 #include <asm/system.h>
78 #include <asm/io.h>
79 #include <asm/irq.h>
80 #include <asm/dma.h>
81 #include <asm/types.h>
82 #include <asm/uaccess.h>
83
84 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
85 #define SYNCLINK_GENERIC_HDLC 1
86 #else
87 #define SYNCLINK_GENERIC_HDLC 0
88 #endif
89
90 /*
91 * module identification
92 */
93 static char *driver_name = "SyncLink GT";
94 static char *tty_driver_name = "synclink_gt";
95 static char *tty_dev_prefix = "ttySLG";
96 MODULE_LICENSE("GPL");
97 #define MGSL_MAGIC 0x5401
98 #define MAX_DEVICES 32
99
100 static struct pci_device_id pci_table[] = {
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {0,}, /* terminate list */
106 };
107 MODULE_DEVICE_TABLE(pci, pci_table);
108
109 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
110 static void remove_one(struct pci_dev *dev);
111 static struct pci_driver pci_driver = {
112 .name = "synclink_gt",
113 .id_table = pci_table,
114 .probe = init_one,
115 .remove = __devexit_p(remove_one),
116 };
117
118 static bool pci_registered;
119
120 /*
121 * module configuration and status
122 */
123 static struct slgt_info *slgt_device_list;
124 static int slgt_device_count;
125
126 static int ttymajor;
127 static int debug_level;
128 static int maxframe[MAX_DEVICES];
129
130 module_param(ttymajor, int, 0);
131 module_param(debug_level, int, 0);
132 module_param_array(maxframe, int, NULL, 0);
133
134 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
135 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
136 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
137
138 /*
139 * tty support and callbacks
140 */
141 static struct tty_driver *serial_driver;
142
143 static int open(struct tty_struct *tty, struct file * filp);
144 static void close(struct tty_struct *tty, struct file * filp);
145 static void hangup(struct tty_struct *tty);
146 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
147
148 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
149 static int put_char(struct tty_struct *tty, unsigned char ch);
150 static void send_xchar(struct tty_struct *tty, char ch);
151 static void wait_until_sent(struct tty_struct *tty, int timeout);
152 static int write_room(struct tty_struct *tty);
153 static void flush_chars(struct tty_struct *tty);
154 static void flush_buffer(struct tty_struct *tty);
155 static void tx_hold(struct tty_struct *tty);
156 static void tx_release(struct tty_struct *tty);
157
158 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
159 static int chars_in_buffer(struct tty_struct *tty);
160 static void throttle(struct tty_struct * tty);
161 static void unthrottle(struct tty_struct * tty);
162 static int set_break(struct tty_struct *tty, int break_state);
163
164 /*
165 * generic HDLC support and callbacks
166 */
167 #if SYNCLINK_GENERIC_HDLC
168 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
169 static void hdlcdev_tx_done(struct slgt_info *info);
170 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
171 static int hdlcdev_init(struct slgt_info *info);
172 static void hdlcdev_exit(struct slgt_info *info);
173 #endif
174
175
176 /*
177 * device specific structures, macros and functions
178 */
179
180 #define SLGT_MAX_PORTS 4
181 #define SLGT_REG_SIZE 256
182
183 /*
184 * conditional wait facility
185 */
186 struct cond_wait {
187 struct cond_wait *next;
188 wait_queue_head_t q;
189 wait_queue_t wait;
190 unsigned int data;
191 };
192 static void init_cond_wait(struct cond_wait *w, unsigned int data);
193 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
194 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
195 static void flush_cond_wait(struct cond_wait **head);
196
197 /*
198 * DMA buffer descriptor and access macros
199 */
200 struct slgt_desc
201 {
202 __le16 count;
203 __le16 status;
204 __le32 pbuf; /* physical address of data buffer */
205 __le32 next; /* physical address of next descriptor */
206
207 /* driver book keeping */
208 char *buf; /* virtual address of data buffer */
209 unsigned int pdesc; /* physical address of this descriptor */
210 dma_addr_t buf_dma_addr;
211 unsigned short buf_count;
212 };
213
214 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
215 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
216 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
217 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
218 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
219 #define desc_count(a) (le16_to_cpu((a).count))
220 #define desc_status(a) (le16_to_cpu((a).status))
221 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
222 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
223 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
224 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
225 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
226
227 struct _input_signal_events {
228 int ri_up;
229 int ri_down;
230 int dsr_up;
231 int dsr_down;
232 int dcd_up;
233 int dcd_down;
234 int cts_up;
235 int cts_down;
236 };
237
238 /*
239 * device instance data structure
240 */
241 struct slgt_info {
242 void *if_ptr; /* General purpose pointer (used by SPPP) */
243 struct tty_port port;
244
245 struct slgt_info *next_device; /* device list link */
246
247 int magic;
248
249 char device_name[25];
250 struct pci_dev *pdev;
251
252 int port_count; /* count of ports on adapter */
253 int adapter_num; /* adapter instance number */
254 int port_num; /* port instance number */
255
256 /* array of pointers to port contexts on this adapter */
257 struct slgt_info *port_array[SLGT_MAX_PORTS];
258
259 int line; /* tty line instance number */
260
261 struct mgsl_icount icount;
262
263 int timeout;
264 int x_char; /* xon/xoff character */
265 unsigned int read_status_mask;
266 unsigned int ignore_status_mask;
267
268 wait_queue_head_t status_event_wait_q;
269 wait_queue_head_t event_wait_q;
270 struct timer_list tx_timer;
271 struct timer_list rx_timer;
272
273 unsigned int gpio_present;
274 struct cond_wait *gpio_wait_q;
275
276 spinlock_t lock; /* spinlock for synchronizing with ISR */
277
278 struct work_struct task;
279 u32 pending_bh;
280 bool bh_requested;
281 bool bh_running;
282
283 int isr_overflow;
284 bool irq_requested; /* true if IRQ requested */
285 bool irq_occurred; /* for diagnostics use */
286
287 /* device configuration */
288
289 unsigned int bus_type;
290 unsigned int irq_level;
291 unsigned long irq_flags;
292
293 unsigned char __iomem * reg_addr; /* memory mapped registers address */
294 u32 phys_reg_addr;
295 bool reg_addr_requested;
296
297 MGSL_PARAMS params; /* communications parameters */
298 u32 idle_mode;
299 u32 max_frame_size; /* as set by device config */
300
301 unsigned int rbuf_fill_level;
302 unsigned int rx_pio;
303 unsigned int if_mode;
304 unsigned int base_clock;
305
306 /* device status */
307
308 bool rx_enabled;
309 bool rx_restart;
310
311 bool tx_enabled;
312 bool tx_active;
313
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
316
317 unsigned char *tx_buf;
318 int tx_count;
319
320 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
321 char char_buf[MAX_ASYNC_BUFFER_SIZE];
322 bool drop_rts_on_tx_done;
323 struct _input_signal_events input_signal_events;
324
325 int dcd_chkcount; /* check counts to prevent */
326 int cts_chkcount; /* too many IRQs if a signal */
327 int dsr_chkcount; /* is floating */
328 int ri_chkcount;
329
330 char *bufs; /* virtual address of DMA buffer lists */
331 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
332
333 unsigned int rbuf_count;
334 struct slgt_desc *rbufs;
335 unsigned int rbuf_current;
336 unsigned int rbuf_index;
337 unsigned int rbuf_fill_index;
338 unsigned short rbuf_fill_count;
339
340 unsigned int tbuf_count;
341 struct slgt_desc *tbufs;
342 unsigned int tbuf_current;
343 unsigned int tbuf_start;
344
345 unsigned char *tmp_rbuf;
346 unsigned int tmp_rbuf_count;
347
348 /* SPPP/Cisco HDLC device parts */
349
350 int netcount;
351 spinlock_t netlock;
352 #if SYNCLINK_GENERIC_HDLC
353 struct net_device *netdev;
354 #endif
355
356 };
357
358 static MGSL_PARAMS default_params = {
359 .mode = MGSL_MODE_HDLC,
360 .loopback = 0,
361 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
362 .encoding = HDLC_ENCODING_NRZI_SPACE,
363 .clock_speed = 0,
364 .addr_filter = 0xff,
365 .crc_type = HDLC_CRC_16_CCITT,
366 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
367 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
368 .data_rate = 9600,
369 .data_bits = 8,
370 .stop_bits = 1,
371 .parity = ASYNC_PARITY_NONE
372 };
373
374
375 #define BH_RECEIVE 1
376 #define BH_TRANSMIT 2
377 #define BH_STATUS 4
378 #define IO_PIN_SHUTDOWN_LIMIT 100
379
380 #define DMABUFSIZE 256
381 #define DESC_LIST_SIZE 4096
382
383 #define MASK_PARITY BIT1
384 #define MASK_FRAMING BIT0
385 #define MASK_BREAK BIT14
386 #define MASK_OVERRUN BIT4
387
388 #define GSR 0x00 /* global status */
389 #define JCR 0x04 /* JTAG control */
390 #define IODR 0x08 /* GPIO direction */
391 #define IOER 0x0c /* GPIO interrupt enable */
392 #define IOVR 0x10 /* GPIO value */
393 #define IOSR 0x14 /* GPIO interrupt status */
394 #define TDR 0x80 /* tx data */
395 #define RDR 0x80 /* rx data */
396 #define TCR 0x82 /* tx control */
397 #define TIR 0x84 /* tx idle */
398 #define TPR 0x85 /* tx preamble */
399 #define RCR 0x86 /* rx control */
400 #define VCR 0x88 /* V.24 control */
401 #define CCR 0x89 /* clock control */
402 #define BDR 0x8a /* baud divisor */
403 #define SCR 0x8c /* serial control */
404 #define SSR 0x8e /* serial status */
405 #define RDCSR 0x90 /* rx DMA control/status */
406 #define TDCSR 0x94 /* tx DMA control/status */
407 #define RDDAR 0x98 /* rx DMA descriptor address */
408 #define TDDAR 0x9c /* tx DMA descriptor address */
409
410 #define RXIDLE BIT14
411 #define RXBREAK BIT14
412 #define IRQ_TXDATA BIT13
413 #define IRQ_TXIDLE BIT12
414 #define IRQ_TXUNDER BIT11 /* HDLC */
415 #define IRQ_RXDATA BIT10
416 #define IRQ_RXIDLE BIT9 /* HDLC */
417 #define IRQ_RXBREAK BIT9 /* async */
418 #define IRQ_RXOVER BIT8
419 #define IRQ_DSR BIT7
420 #define IRQ_CTS BIT6
421 #define IRQ_DCD BIT5
422 #define IRQ_RI BIT4
423 #define IRQ_ALL 0x3ff0
424 #define IRQ_MASTER BIT0
425
426 #define slgt_irq_on(info, mask) \
427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
428 #define slgt_irq_off(info, mask) \
429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
430
431 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
432 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
433 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
434 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
435 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
436 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
437
438 static void msc_set_vcr(struct slgt_info *info);
439
440 static int startup(struct slgt_info *info);
441 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
442 static void shutdown(struct slgt_info *info);
443 static void program_hw(struct slgt_info *info);
444 static void change_params(struct slgt_info *info);
445
446 static int register_test(struct slgt_info *info);
447 static int irq_test(struct slgt_info *info);
448 static int loopback_test(struct slgt_info *info);
449 static int adapter_test(struct slgt_info *info);
450
451 static void reset_adapter(struct slgt_info *info);
452 static void reset_port(struct slgt_info *info);
453 static void async_mode(struct slgt_info *info);
454 static void sync_mode(struct slgt_info *info);
455
456 static void rx_stop(struct slgt_info *info);
457 static void rx_start(struct slgt_info *info);
458 static void reset_rbufs(struct slgt_info *info);
459 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
460 static void rdma_reset(struct slgt_info *info);
461 static bool rx_get_frame(struct slgt_info *info);
462 static bool rx_get_buf(struct slgt_info *info);
463
464 static void tx_start(struct slgt_info *info);
465 static void tx_stop(struct slgt_info *info);
466 static void tx_set_idle(struct slgt_info *info);
467 static unsigned int free_tbuf_count(struct slgt_info *info);
468 static unsigned int tbuf_bytes(struct slgt_info *info);
469 static void reset_tbufs(struct slgt_info *info);
470 static void tdma_reset(struct slgt_info *info);
471 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
472
473 static void get_signals(struct slgt_info *info);
474 static void set_signals(struct slgt_info *info);
475 static void enable_loopback(struct slgt_info *info);
476 static void set_rate(struct slgt_info *info, u32 data_rate);
477
478 static int bh_action(struct slgt_info *info);
479 static void bh_handler(struct work_struct *work);
480 static void bh_transmit(struct slgt_info *info);
481 static void isr_serial(struct slgt_info *info);
482 static void isr_rdma(struct slgt_info *info);
483 static void isr_txeom(struct slgt_info *info, unsigned short status);
484 static void isr_tdma(struct slgt_info *info);
485
486 static int alloc_dma_bufs(struct slgt_info *info);
487 static void free_dma_bufs(struct slgt_info *info);
488 static int alloc_desc(struct slgt_info *info);
489 static void free_desc(struct slgt_info *info);
490 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492
493 static int alloc_tmp_rbuf(struct slgt_info *info);
494 static void free_tmp_rbuf(struct slgt_info *info);
495
496 static void tx_timeout(unsigned long context);
497 static void rx_timeout(unsigned long context);
498
499 /*
500 * ioctl handlers
501 */
502 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
503 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
506 static int set_txidle(struct slgt_info *info, int idle_mode);
507 static int tx_enable(struct slgt_info *info, int enable);
508 static int tx_abort(struct slgt_info *info);
509 static int rx_enable(struct slgt_info *info, int enable);
510 static int modem_input_wait(struct slgt_info *info,int arg);
511 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
512 static int tiocmget(struct tty_struct *tty, struct file *file);
513 static int tiocmset(struct tty_struct *tty, struct file *file,
514 unsigned int set, unsigned int clear);
515 static int set_break(struct tty_struct *tty, int break_state);
516 static int get_interface(struct slgt_info *info, int __user *if_mode);
517 static int set_interface(struct slgt_info *info, int if_mode);
518 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521
522 /*
523 * driver functions
524 */
525 static void add_device(struct slgt_info *info);
526 static void device_init(int adapter_num, struct pci_dev *pdev);
527 static int claim_resources(struct slgt_info *info);
528 static void release_resources(struct slgt_info *info);
529
530 /*
531 * DEBUG OUTPUT CODE
532 */
533 #ifndef DBGINFO
534 #define DBGINFO(fmt)
535 #endif
536 #ifndef DBGERR
537 #define DBGERR(fmt)
538 #endif
539 #ifndef DBGBH
540 #define DBGBH(fmt)
541 #endif
542 #ifndef DBGISR
543 #define DBGISR(fmt)
544 #endif
545
546 #ifdef DBGDATA
547 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
548 {
549 int i;
550 int linecount;
551 printk("%s %s data:\n",info->device_name, label);
552 while(count) {
553 linecount = (count > 16) ? 16 : count;
554 for(i=0; i < linecount; i++)
555 printk("%02X ",(unsigned char)data[i]);
556 for(;i<17;i++)
557 printk(" ");
558 for(i=0;i<linecount;i++) {
559 if (data[i]>=040 && data[i]<=0176)
560 printk("%c",data[i]);
561 else
562 printk(".");
563 }
564 printk("\n");
565 data += linecount;
566 count -= linecount;
567 }
568 }
569 #else
570 #define DBGDATA(info, buf, size, label)
571 #endif
572
573 #ifdef DBGTBUF
574 static void dump_tbufs(struct slgt_info *info)
575 {
576 int i;
577 printk("tbuf_current=%d\n", info->tbuf_current);
578 for (i=0 ; i < info->tbuf_count ; i++) {
579 printk("%d: count=%04X status=%04X\n",
580 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
581 }
582 }
583 #else
584 #define DBGTBUF(info)
585 #endif
586
587 #ifdef DBGRBUF
588 static void dump_rbufs(struct slgt_info *info)
589 {
590 int i;
591 printk("rbuf_current=%d\n", info->rbuf_current);
592 for (i=0 ; i < info->rbuf_count ; i++) {
593 printk("%d: count=%04X status=%04X\n",
594 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
595 }
596 }
597 #else
598 #define DBGRBUF(info)
599 #endif
600
601 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
602 {
603 #ifdef SANITY_CHECK
604 if (!info) {
605 printk("null struct slgt_info for (%s) in %s\n", devname, name);
606 return 1;
607 }
608 if (info->magic != MGSL_MAGIC) {
609 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
610 return 1;
611 }
612 #else
613 if (!info)
614 return 1;
615 #endif
616 return 0;
617 }
618
619 /**
620 * line discipline callback wrappers
621 *
622 * The wrappers maintain line discipline references
623 * while calling into the line discipline.
624 *
625 * ldisc_receive_buf - pass receive data to line discipline
626 */
627 static void ldisc_receive_buf(struct tty_struct *tty,
628 const __u8 *data, char *flags, int count)
629 {
630 struct tty_ldisc *ld;
631 if (!tty)
632 return;
633 ld = tty_ldisc_ref(tty);
634 if (ld) {
635 if (ld->ops->receive_buf)
636 ld->ops->receive_buf(tty, data, flags, count);
637 tty_ldisc_deref(ld);
638 }
639 }
640
641 /* tty callbacks */
642
643 static int open(struct tty_struct *tty, struct file *filp)
644 {
645 struct slgt_info *info;
646 int retval, line;
647 unsigned long flags;
648
649 line = tty->index;
650 if ((line < 0) || (line >= slgt_device_count)) {
651 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
652 return -ENODEV;
653 }
654
655 info = slgt_device_list;
656 while(info && info->line != line)
657 info = info->next_device;
658 if (sanity_check(info, tty->name, "open"))
659 return -ENODEV;
660 if (info->init_error) {
661 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
662 return -ENODEV;
663 }
664
665 tty->driver_data = info;
666 info->port.tty = tty;
667
668 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
669
670 /* If port is closing, signal caller to try again */
671 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
672 if (info->port.flags & ASYNC_CLOSING)
673 interruptible_sleep_on(&info->port.close_wait);
674 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
675 -EAGAIN : -ERESTARTSYS);
676 goto cleanup;
677 }
678
679 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
680
681 spin_lock_irqsave(&info->netlock, flags);
682 if (info->netcount) {
683 retval = -EBUSY;
684 spin_unlock_irqrestore(&info->netlock, flags);
685 goto cleanup;
686 }
687 info->port.count++;
688 spin_unlock_irqrestore(&info->netlock, flags);
689
690 if (info->port.count == 1) {
691 /* 1st open on this device, init hardware */
692 retval = startup(info);
693 if (retval < 0)
694 goto cleanup;
695 }
696
697 retval = block_til_ready(tty, filp, info);
698 if (retval) {
699 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
700 goto cleanup;
701 }
702
703 retval = 0;
704
705 cleanup:
706 if (retval) {
707 if (tty->count == 1)
708 info->port.tty = NULL; /* tty layer will release tty struct */
709 if(info->port.count)
710 info->port.count--;
711 }
712
713 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
714 return retval;
715 }
716
717 static void close(struct tty_struct *tty, struct file *filp)
718 {
719 struct slgt_info *info = tty->driver_data;
720
721 if (sanity_check(info, tty->name, "close"))
722 return;
723 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
724
725 if (tty_port_close_start(&info->port, tty, filp) == 0)
726 goto cleanup;
727
728 if (info->port.flags & ASYNC_INITIALIZED)
729 wait_until_sent(tty, info->timeout);
730 flush_buffer(tty);
731 tty_ldisc_flush(tty);
732
733 shutdown(info);
734
735 tty_port_close_end(&info->port, tty);
736 info->port.tty = NULL;
737 cleanup:
738 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
739 }
740
741 static void hangup(struct tty_struct *tty)
742 {
743 struct slgt_info *info = tty->driver_data;
744
745 if (sanity_check(info, tty->name, "hangup"))
746 return;
747 DBGINFO(("%s hangup\n", info->device_name));
748
749 flush_buffer(tty);
750 shutdown(info);
751
752 info->port.count = 0;
753 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
754 info->port.tty = NULL;
755
756 wake_up_interruptible(&info->port.open_wait);
757 }
758
759 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
760 {
761 struct slgt_info *info = tty->driver_data;
762 unsigned long flags;
763
764 DBGINFO(("%s set_termios\n", tty->driver->name));
765
766 change_params(info);
767
768 /* Handle transition to B0 status */
769 if (old_termios->c_cflag & CBAUD &&
770 !(tty->termios->c_cflag & CBAUD)) {
771 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
772 spin_lock_irqsave(&info->lock,flags);
773 set_signals(info);
774 spin_unlock_irqrestore(&info->lock,flags);
775 }
776
777 /* Handle transition away from B0 status */
778 if (!(old_termios->c_cflag & CBAUD) &&
779 tty->termios->c_cflag & CBAUD) {
780 info->signals |= SerialSignal_DTR;
781 if (!(tty->termios->c_cflag & CRTSCTS) ||
782 !test_bit(TTY_THROTTLED, &tty->flags)) {
783 info->signals |= SerialSignal_RTS;
784 }
785 spin_lock_irqsave(&info->lock,flags);
786 set_signals(info);
787 spin_unlock_irqrestore(&info->lock,flags);
788 }
789
790 /* Handle turning off CRTSCTS */
791 if (old_termios->c_cflag & CRTSCTS &&
792 !(tty->termios->c_cflag & CRTSCTS)) {
793 tty->hw_stopped = 0;
794 tx_release(tty);
795 }
796 }
797
798 static void update_tx_timer(struct slgt_info *info)
799 {
800 /*
801 * use worst case speed of 1200bps to calculate transmit timeout
802 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
803 */
804 if (info->params.mode == MGSL_MODE_HDLC) {
805 int timeout = (tbuf_bytes(info) * 7) + 1000;
806 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
807 }
808 }
809
810 static int write(struct tty_struct *tty,
811 const unsigned char *buf, int count)
812 {
813 int ret = 0;
814 struct slgt_info *info = tty->driver_data;
815 unsigned long flags;
816 unsigned int bufs_needed;
817
818 if (sanity_check(info, tty->name, "write"))
819 goto cleanup;
820 DBGINFO(("%s write count=%d\n", info->device_name, count));
821
822 if (!info->tx_buf)
823 goto cleanup;
824
825 if (count > info->max_frame_size) {
826 ret = -EIO;
827 goto cleanup;
828 }
829
830 if (!count)
831 goto cleanup;
832
833 if (!info->tx_active && info->tx_count) {
834 /* send accumulated data from send_char() */
835 tx_load(info, info->tx_buf, info->tx_count);
836 goto start;
837 }
838 bufs_needed = (count/DMABUFSIZE);
839 if (count % DMABUFSIZE)
840 ++bufs_needed;
841 if (bufs_needed > free_tbuf_count(info))
842 goto cleanup;
843
844 ret = info->tx_count = count;
845 tx_load(info, buf, count);
846 goto start;
847
848 start:
849 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
850 spin_lock_irqsave(&info->lock,flags);
851 if (!info->tx_active)
852 tx_start(info);
853 else if (!(rd_reg32(info, TDCSR) & BIT0)) {
854 /* transmit still active but transmit DMA stopped */
855 unsigned int i = info->tbuf_current;
856 if (!i)
857 i = info->tbuf_count;
858 i--;
859 /* if DMA buf unsent must try later after tx idle */
860 if (desc_count(info->tbufs[i]))
861 ret = 0;
862 }
863 if (ret > 0)
864 update_tx_timer(info);
865 spin_unlock_irqrestore(&info->lock,flags);
866 }
867
868 cleanup:
869 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
870 return ret;
871 }
872
873 static int put_char(struct tty_struct *tty, unsigned char ch)
874 {
875 struct slgt_info *info = tty->driver_data;
876 unsigned long flags;
877 int ret = 0;
878
879 if (sanity_check(info, tty->name, "put_char"))
880 return 0;
881 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
882 if (!info->tx_buf)
883 return 0;
884 spin_lock_irqsave(&info->lock,flags);
885 if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
886 info->tx_buf[info->tx_count++] = ch;
887 ret = 1;
888 }
889 spin_unlock_irqrestore(&info->lock,flags);
890 return ret;
891 }
892
893 static void send_xchar(struct tty_struct *tty, char ch)
894 {
895 struct slgt_info *info = tty->driver_data;
896 unsigned long flags;
897
898 if (sanity_check(info, tty->name, "send_xchar"))
899 return;
900 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
901 info->x_char = ch;
902 if (ch) {
903 spin_lock_irqsave(&info->lock,flags);
904 if (!info->tx_enabled)
905 tx_start(info);
906 spin_unlock_irqrestore(&info->lock,flags);
907 }
908 }
909
910 static void wait_until_sent(struct tty_struct *tty, int timeout)
911 {
912 struct slgt_info *info = tty->driver_data;
913 unsigned long orig_jiffies, char_time;
914
915 if (!info )
916 return;
917 if (sanity_check(info, tty->name, "wait_until_sent"))
918 return;
919 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
920 if (!(info->port.flags & ASYNC_INITIALIZED))
921 goto exit;
922
923 orig_jiffies = jiffies;
924
925 /* Set check interval to 1/5 of estimated time to
926 * send a character, and make it at least 1. The check
927 * interval should also be less than the timeout.
928 * Note: use tight timings here to satisfy the NIST-PCTS.
929 */
930
931 lock_kernel();
932
933 if (info->params.data_rate) {
934 char_time = info->timeout/(32 * 5);
935 if (!char_time)
936 char_time++;
937 } else
938 char_time = 1;
939
940 if (timeout)
941 char_time = min_t(unsigned long, char_time, timeout);
942
943 while (info->tx_active) {
944 msleep_interruptible(jiffies_to_msecs(char_time));
945 if (signal_pending(current))
946 break;
947 if (timeout && time_after(jiffies, orig_jiffies + timeout))
948 break;
949 }
950 unlock_kernel();
951
952 exit:
953 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
954 }
955
956 static int write_room(struct tty_struct *tty)
957 {
958 struct slgt_info *info = tty->driver_data;
959 int ret;
960
961 if (sanity_check(info, tty->name, "write_room"))
962 return 0;
963 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
964 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
965 return ret;
966 }
967
968 static void flush_chars(struct tty_struct *tty)
969 {
970 struct slgt_info *info = tty->driver_data;
971 unsigned long flags;
972
973 if (sanity_check(info, tty->name, "flush_chars"))
974 return;
975 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
976
977 if (info->tx_count <= 0 || tty->stopped ||
978 tty->hw_stopped || !info->tx_buf)
979 return;
980
981 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
982
983 spin_lock_irqsave(&info->lock,flags);
984 if (!info->tx_active && info->tx_count) {
985 tx_load(info, info->tx_buf,info->tx_count);
986 tx_start(info);
987 }
988 spin_unlock_irqrestore(&info->lock,flags);
989 }
990
991 static void flush_buffer(struct tty_struct *tty)
992 {
993 struct slgt_info *info = tty->driver_data;
994 unsigned long flags;
995
996 if (sanity_check(info, tty->name, "flush_buffer"))
997 return;
998 DBGINFO(("%s flush_buffer\n", info->device_name));
999
1000 spin_lock_irqsave(&info->lock,flags);
1001 if (!info->tx_active)
1002 info->tx_count = 0;
1003 spin_unlock_irqrestore(&info->lock,flags);
1004
1005 tty_wakeup(tty);
1006 }
1007
1008 /*
1009 * throttle (stop) transmitter
1010 */
1011 static void tx_hold(struct tty_struct *tty)
1012 {
1013 struct slgt_info *info = tty->driver_data;
1014 unsigned long flags;
1015
1016 if (sanity_check(info, tty->name, "tx_hold"))
1017 return;
1018 DBGINFO(("%s tx_hold\n", info->device_name));
1019 spin_lock_irqsave(&info->lock,flags);
1020 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1021 tx_stop(info);
1022 spin_unlock_irqrestore(&info->lock,flags);
1023 }
1024
1025 /*
1026 * release (start) transmitter
1027 */
1028 static void tx_release(struct tty_struct *tty)
1029 {
1030 struct slgt_info *info = tty->driver_data;
1031 unsigned long flags;
1032
1033 if (sanity_check(info, tty->name, "tx_release"))
1034 return;
1035 DBGINFO(("%s tx_release\n", info->device_name));
1036 spin_lock_irqsave(&info->lock,flags);
1037 if (!info->tx_active && info->tx_count) {
1038 tx_load(info, info->tx_buf, info->tx_count);
1039 tx_start(info);
1040 }
1041 spin_unlock_irqrestore(&info->lock,flags);
1042 }
1043
1044 /*
1045 * Service an IOCTL request
1046 *
1047 * Arguments
1048 *
1049 * tty pointer to tty instance data
1050 * file pointer to associated file object for device
1051 * cmd IOCTL command code
1052 * arg command argument/context
1053 *
1054 * Return 0 if success, otherwise error code
1055 */
1056 static int ioctl(struct tty_struct *tty, struct file *file,
1057 unsigned int cmd, unsigned long arg)
1058 {
1059 struct slgt_info *info = tty->driver_data;
1060 struct mgsl_icount cnow; /* kernel counter temps */
1061 struct serial_icounter_struct __user *p_cuser; /* user space */
1062 unsigned long flags;
1063 void __user *argp = (void __user *)arg;
1064 int ret;
1065
1066 if (sanity_check(info, tty->name, "ioctl"))
1067 return -ENODEV;
1068 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1069
1070 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1071 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1072 if (tty->flags & (1 << TTY_IO_ERROR))
1073 return -EIO;
1074 }
1075
1076 lock_kernel();
1077
1078 switch (cmd) {
1079 case MGSL_IOCGPARAMS:
1080 ret = get_params(info, argp);
1081 break;
1082 case MGSL_IOCSPARAMS:
1083 ret = set_params(info, argp);
1084 break;
1085 case MGSL_IOCGTXIDLE:
1086 ret = get_txidle(info, argp);
1087 break;
1088 case MGSL_IOCSTXIDLE:
1089 ret = set_txidle(info, (int)arg);
1090 break;
1091 case MGSL_IOCTXENABLE:
1092 ret = tx_enable(info, (int)arg);
1093 break;
1094 case MGSL_IOCRXENABLE:
1095 ret = rx_enable(info, (int)arg);
1096 break;
1097 case MGSL_IOCTXABORT:
1098 ret = tx_abort(info);
1099 break;
1100 case MGSL_IOCGSTATS:
1101 ret = get_stats(info, argp);
1102 break;
1103 case MGSL_IOCWAITEVENT:
1104 ret = wait_mgsl_event(info, argp);
1105 break;
1106 case TIOCMIWAIT:
1107 ret = modem_input_wait(info,(int)arg);
1108 break;
1109 case MGSL_IOCGIF:
1110 ret = get_interface(info, argp);
1111 break;
1112 case MGSL_IOCSIF:
1113 ret = set_interface(info,(int)arg);
1114 break;
1115 case MGSL_IOCSGPIO:
1116 ret = set_gpio(info, argp);
1117 break;
1118 case MGSL_IOCGGPIO:
1119 ret = get_gpio(info, argp);
1120 break;
1121 case MGSL_IOCWAITGPIO:
1122 ret = wait_gpio(info, argp);
1123 break;
1124 case TIOCGICOUNT:
1125 spin_lock_irqsave(&info->lock,flags);
1126 cnow = info->icount;
1127 spin_unlock_irqrestore(&info->lock,flags);
1128 p_cuser = argp;
1129 if (put_user(cnow.cts, &p_cuser->cts) ||
1130 put_user(cnow.dsr, &p_cuser->dsr) ||
1131 put_user(cnow.rng, &p_cuser->rng) ||
1132 put_user(cnow.dcd, &p_cuser->dcd) ||
1133 put_user(cnow.rx, &p_cuser->rx) ||
1134 put_user(cnow.tx, &p_cuser->tx) ||
1135 put_user(cnow.frame, &p_cuser->frame) ||
1136 put_user(cnow.overrun, &p_cuser->overrun) ||
1137 put_user(cnow.parity, &p_cuser->parity) ||
1138 put_user(cnow.brk, &p_cuser->brk) ||
1139 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1140 ret = -EFAULT;
1141 ret = 0;
1142 break;
1143 default:
1144 ret = -ENOIOCTLCMD;
1145 }
1146 unlock_kernel();
1147 return ret;
1148 }
1149
1150 /*
1151 * support for 32 bit ioctl calls on 64 bit systems
1152 */
1153 #ifdef CONFIG_COMPAT
1154 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1155 {
1156 struct MGSL_PARAMS32 tmp_params;
1157
1158 DBGINFO(("%s get_params32\n", info->device_name));
1159 tmp_params.mode = (compat_ulong_t)info->params.mode;
1160 tmp_params.loopback = info->params.loopback;
1161 tmp_params.flags = info->params.flags;
1162 tmp_params.encoding = info->params.encoding;
1163 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1164 tmp_params.addr_filter = info->params.addr_filter;
1165 tmp_params.crc_type = info->params.crc_type;
1166 tmp_params.preamble_length = info->params.preamble_length;
1167 tmp_params.preamble = info->params.preamble;
1168 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1169 tmp_params.data_bits = info->params.data_bits;
1170 tmp_params.stop_bits = info->params.stop_bits;
1171 tmp_params.parity = info->params.parity;
1172 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1173 return -EFAULT;
1174 return 0;
1175 }
1176
1177 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1178 {
1179 struct MGSL_PARAMS32 tmp_params;
1180
1181 DBGINFO(("%s set_params32\n", info->device_name));
1182 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1183 return -EFAULT;
1184
1185 spin_lock(&info->lock);
1186 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1187 info->base_clock = tmp_params.clock_speed;
1188 } else {
1189 info->params.mode = tmp_params.mode;
1190 info->params.loopback = tmp_params.loopback;
1191 info->params.flags = tmp_params.flags;
1192 info->params.encoding = tmp_params.encoding;
1193 info->params.clock_speed = tmp_params.clock_speed;
1194 info->params.addr_filter = tmp_params.addr_filter;
1195 info->params.crc_type = tmp_params.crc_type;
1196 info->params.preamble_length = tmp_params.preamble_length;
1197 info->params.preamble = tmp_params.preamble;
1198 info->params.data_rate = tmp_params.data_rate;
1199 info->params.data_bits = tmp_params.data_bits;
1200 info->params.stop_bits = tmp_params.stop_bits;
1201 info->params.parity = tmp_params.parity;
1202 }
1203 spin_unlock(&info->lock);
1204
1205 program_hw(info);
1206
1207 return 0;
1208 }
1209
1210 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1211 unsigned int cmd, unsigned long arg)
1212 {
1213 struct slgt_info *info = tty->driver_data;
1214 int rc = -ENOIOCTLCMD;
1215
1216 if (sanity_check(info, tty->name, "compat_ioctl"))
1217 return -ENODEV;
1218 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1219
1220 switch (cmd) {
1221
1222 case MGSL_IOCSPARAMS32:
1223 rc = set_params32(info, compat_ptr(arg));
1224 break;
1225
1226 case MGSL_IOCGPARAMS32:
1227 rc = get_params32(info, compat_ptr(arg));
1228 break;
1229
1230 case MGSL_IOCGPARAMS:
1231 case MGSL_IOCSPARAMS:
1232 case MGSL_IOCGTXIDLE:
1233 case MGSL_IOCGSTATS:
1234 case MGSL_IOCWAITEVENT:
1235 case MGSL_IOCGIF:
1236 case MGSL_IOCSGPIO:
1237 case MGSL_IOCGGPIO:
1238 case MGSL_IOCWAITGPIO:
1239 case TIOCGICOUNT:
1240 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1241 break;
1242
1243 case MGSL_IOCSTXIDLE:
1244 case MGSL_IOCTXENABLE:
1245 case MGSL_IOCRXENABLE:
1246 case MGSL_IOCTXABORT:
1247 case TIOCMIWAIT:
1248 case MGSL_IOCSIF:
1249 rc = ioctl(tty, file, cmd, arg);
1250 break;
1251 }
1252
1253 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1254 return rc;
1255 }
1256 #else
1257 #define slgt_compat_ioctl NULL
1258 #endif /* ifdef CONFIG_COMPAT */
1259
1260 /*
1261 * proc fs support
1262 */
1263 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1264 {
1265 char stat_buf[30];
1266 unsigned long flags;
1267
1268 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1269 info->device_name, info->phys_reg_addr,
1270 info->irq_level, info->max_frame_size);
1271
1272 /* output current serial signal states */
1273 spin_lock_irqsave(&info->lock,flags);
1274 get_signals(info);
1275 spin_unlock_irqrestore(&info->lock,flags);
1276
1277 stat_buf[0] = 0;
1278 stat_buf[1] = 0;
1279 if (info->signals & SerialSignal_RTS)
1280 strcat(stat_buf, "|RTS");
1281 if (info->signals & SerialSignal_CTS)
1282 strcat(stat_buf, "|CTS");
1283 if (info->signals & SerialSignal_DTR)
1284 strcat(stat_buf, "|DTR");
1285 if (info->signals & SerialSignal_DSR)
1286 strcat(stat_buf, "|DSR");
1287 if (info->signals & SerialSignal_DCD)
1288 strcat(stat_buf, "|CD");
1289 if (info->signals & SerialSignal_RI)
1290 strcat(stat_buf, "|RI");
1291
1292 if (info->params.mode != MGSL_MODE_ASYNC) {
1293 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1294 info->icount.txok, info->icount.rxok);
1295 if (info->icount.txunder)
1296 seq_printf(m, " txunder:%d", info->icount.txunder);
1297 if (info->icount.txabort)
1298 seq_printf(m, " txabort:%d", info->icount.txabort);
1299 if (info->icount.rxshort)
1300 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1301 if (info->icount.rxlong)
1302 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1303 if (info->icount.rxover)
1304 seq_printf(m, " rxover:%d", info->icount.rxover);
1305 if (info->icount.rxcrc)
1306 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1307 } else {
1308 seq_printf(m, "\tASYNC tx:%d rx:%d",
1309 info->icount.tx, info->icount.rx);
1310 if (info->icount.frame)
1311 seq_printf(m, " fe:%d", info->icount.frame);
1312 if (info->icount.parity)
1313 seq_printf(m, " pe:%d", info->icount.parity);
1314 if (info->icount.brk)
1315 seq_printf(m, " brk:%d", info->icount.brk);
1316 if (info->icount.overrun)
1317 seq_printf(m, " oe:%d", info->icount.overrun);
1318 }
1319
1320 /* Append serial signal status to end */
1321 seq_printf(m, " %s\n", stat_buf+1);
1322
1323 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1324 info->tx_active,info->bh_requested,info->bh_running,
1325 info->pending_bh);
1326 }
1327
1328 /* Called to print information about devices
1329 */
1330 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1331 {
1332 struct slgt_info *info;
1333
1334 seq_puts(m, "synclink_gt driver\n");
1335
1336 info = slgt_device_list;
1337 while( info ) {
1338 line_info(m, info);
1339 info = info->next_device;
1340 }
1341 return 0;
1342 }
1343
1344 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1345 {
1346 return single_open(file, synclink_gt_proc_show, NULL);
1347 }
1348
1349 static const struct file_operations synclink_gt_proc_fops = {
1350 .owner = THIS_MODULE,
1351 .open = synclink_gt_proc_open,
1352 .read = seq_read,
1353 .llseek = seq_lseek,
1354 .release = single_release,
1355 };
1356
1357 /*
1358 * return count of bytes in transmit buffer
1359 */
1360 static int chars_in_buffer(struct tty_struct *tty)
1361 {
1362 struct slgt_info *info = tty->driver_data;
1363 int count;
1364 if (sanity_check(info, tty->name, "chars_in_buffer"))
1365 return 0;
1366 count = tbuf_bytes(info);
1367 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1368 return count;
1369 }
1370
1371 /*
1372 * signal remote device to throttle send data (our receive data)
1373 */
1374 static void throttle(struct tty_struct * tty)
1375 {
1376 struct slgt_info *info = tty->driver_data;
1377 unsigned long flags;
1378
1379 if (sanity_check(info, tty->name, "throttle"))
1380 return;
1381 DBGINFO(("%s throttle\n", info->device_name));
1382 if (I_IXOFF(tty))
1383 send_xchar(tty, STOP_CHAR(tty));
1384 if (tty->termios->c_cflag & CRTSCTS) {
1385 spin_lock_irqsave(&info->lock,flags);
1386 info->signals &= ~SerialSignal_RTS;
1387 set_signals(info);
1388 spin_unlock_irqrestore(&info->lock,flags);
1389 }
1390 }
1391
1392 /*
1393 * signal remote device to stop throttling send data (our receive data)
1394 */
1395 static void unthrottle(struct tty_struct * tty)
1396 {
1397 struct slgt_info *info = tty->driver_data;
1398 unsigned long flags;
1399
1400 if (sanity_check(info, tty->name, "unthrottle"))
1401 return;
1402 DBGINFO(("%s unthrottle\n", info->device_name));
1403 if (I_IXOFF(tty)) {
1404 if (info->x_char)
1405 info->x_char = 0;
1406 else
1407 send_xchar(tty, START_CHAR(tty));
1408 }
1409 if (tty->termios->c_cflag & CRTSCTS) {
1410 spin_lock_irqsave(&info->lock,flags);
1411 info->signals |= SerialSignal_RTS;
1412 set_signals(info);
1413 spin_unlock_irqrestore(&info->lock,flags);
1414 }
1415 }
1416
1417 /*
1418 * set or clear transmit break condition
1419 * break_state -1=set break condition, 0=clear
1420 */
1421 static int set_break(struct tty_struct *tty, int break_state)
1422 {
1423 struct slgt_info *info = tty->driver_data;
1424 unsigned short value;
1425 unsigned long flags;
1426
1427 if (sanity_check(info, tty->name, "set_break"))
1428 return -EINVAL;
1429 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1430
1431 spin_lock_irqsave(&info->lock,flags);
1432 value = rd_reg16(info, TCR);
1433 if (break_state == -1)
1434 value |= BIT6;
1435 else
1436 value &= ~BIT6;
1437 wr_reg16(info, TCR, value);
1438 spin_unlock_irqrestore(&info->lock,flags);
1439 return 0;
1440 }
1441
1442 #if SYNCLINK_GENERIC_HDLC
1443
1444 /**
1445 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1446 * set encoding and frame check sequence (FCS) options
1447 *
1448 * dev pointer to network device structure
1449 * encoding serial encoding setting
1450 * parity FCS setting
1451 *
1452 * returns 0 if success, otherwise error code
1453 */
1454 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1455 unsigned short parity)
1456 {
1457 struct slgt_info *info = dev_to_port(dev);
1458 unsigned char new_encoding;
1459 unsigned short new_crctype;
1460
1461 /* return error if TTY interface open */
1462 if (info->port.count)
1463 return -EBUSY;
1464
1465 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1466
1467 switch (encoding)
1468 {
1469 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1470 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1471 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1472 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1473 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1474 default: return -EINVAL;
1475 }
1476
1477 switch (parity)
1478 {
1479 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1480 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1481 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1482 default: return -EINVAL;
1483 }
1484
1485 info->params.encoding = new_encoding;
1486 info->params.crc_type = new_crctype;
1487
1488 /* if network interface up, reprogram hardware */
1489 if (info->netcount)
1490 program_hw(info);
1491
1492 return 0;
1493 }
1494
1495 /**
1496 * called by generic HDLC layer to send frame
1497 *
1498 * skb socket buffer containing HDLC frame
1499 * dev pointer to network device structure
1500 *
1501 * returns 0 if success, otherwise error code
1502 */
1503 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1504 {
1505 struct slgt_info *info = dev_to_port(dev);
1506 unsigned long flags;
1507
1508 DBGINFO(("%s hdlc_xmit\n", dev->name));
1509
1510 /* stop sending until this frame completes */
1511 netif_stop_queue(dev);
1512
1513 /* copy data to device buffers */
1514 info->tx_count = skb->len;
1515 tx_load(info, skb->data, skb->len);
1516
1517 /* update network statistics */
1518 dev->stats.tx_packets++;
1519 dev->stats.tx_bytes += skb->len;
1520
1521 /* done with socket buffer, so free it */
1522 dev_kfree_skb(skb);
1523
1524 /* save start time for transmit timeout detection */
1525 dev->trans_start = jiffies;
1526
1527 spin_lock_irqsave(&info->lock,flags);
1528 tx_start(info);
1529 update_tx_timer(info);
1530 spin_unlock_irqrestore(&info->lock,flags);
1531
1532 return 0;
1533 }
1534
1535 /**
1536 * called by network layer when interface enabled
1537 * claim resources and initialize hardware
1538 *
1539 * dev pointer to network device structure
1540 *
1541 * returns 0 if success, otherwise error code
1542 */
1543 static int hdlcdev_open(struct net_device *dev)
1544 {
1545 struct slgt_info *info = dev_to_port(dev);
1546 int rc;
1547 unsigned long flags;
1548
1549 if (!try_module_get(THIS_MODULE))
1550 return -EBUSY;
1551
1552 DBGINFO(("%s hdlcdev_open\n", dev->name));
1553
1554 /* generic HDLC layer open processing */
1555 if ((rc = hdlc_open(dev)))
1556 return rc;
1557
1558 /* arbitrate between network and tty opens */
1559 spin_lock_irqsave(&info->netlock, flags);
1560 if (info->port.count != 0 || info->netcount != 0) {
1561 DBGINFO(("%s hdlc_open busy\n", dev->name));
1562 spin_unlock_irqrestore(&info->netlock, flags);
1563 return -EBUSY;
1564 }
1565 info->netcount=1;
1566 spin_unlock_irqrestore(&info->netlock, flags);
1567
1568 /* claim resources and init adapter */
1569 if ((rc = startup(info)) != 0) {
1570 spin_lock_irqsave(&info->netlock, flags);
1571 info->netcount=0;
1572 spin_unlock_irqrestore(&info->netlock, flags);
1573 return rc;
1574 }
1575
1576 /* assert DTR and RTS, apply hardware settings */
1577 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1578 program_hw(info);
1579
1580 /* enable network layer transmit */
1581 dev->trans_start = jiffies;
1582 netif_start_queue(dev);
1583
1584 /* inform generic HDLC layer of current DCD status */
1585 spin_lock_irqsave(&info->lock, flags);
1586 get_signals(info);
1587 spin_unlock_irqrestore(&info->lock, flags);
1588 if (info->signals & SerialSignal_DCD)
1589 netif_carrier_on(dev);
1590 else
1591 netif_carrier_off(dev);
1592 return 0;
1593 }
1594
1595 /**
1596 * called by network layer when interface is disabled
1597 * shutdown hardware and release resources
1598 *
1599 * dev pointer to network device structure
1600 *
1601 * returns 0 if success, otherwise error code
1602 */
1603 static int hdlcdev_close(struct net_device *dev)
1604 {
1605 struct slgt_info *info = dev_to_port(dev);
1606 unsigned long flags;
1607
1608 DBGINFO(("%s hdlcdev_close\n", dev->name));
1609
1610 netif_stop_queue(dev);
1611
1612 /* shutdown adapter and release resources */
1613 shutdown(info);
1614
1615 hdlc_close(dev);
1616
1617 spin_lock_irqsave(&info->netlock, flags);
1618 info->netcount=0;
1619 spin_unlock_irqrestore(&info->netlock, flags);
1620
1621 module_put(THIS_MODULE);
1622 return 0;
1623 }
1624
1625 /**
1626 * called by network layer to process IOCTL call to network device
1627 *
1628 * dev pointer to network device structure
1629 * ifr pointer to network interface request structure
1630 * cmd IOCTL command code
1631 *
1632 * returns 0 if success, otherwise error code
1633 */
1634 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1635 {
1636 const size_t size = sizeof(sync_serial_settings);
1637 sync_serial_settings new_line;
1638 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1639 struct slgt_info *info = dev_to_port(dev);
1640 unsigned int flags;
1641
1642 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1643
1644 /* return error if TTY interface open */
1645 if (info->port.count)
1646 return -EBUSY;
1647
1648 if (cmd != SIOCWANDEV)
1649 return hdlc_ioctl(dev, ifr, cmd);
1650
1651 switch(ifr->ifr_settings.type) {
1652 case IF_GET_IFACE: /* return current sync_serial_settings */
1653
1654 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1655 if (ifr->ifr_settings.size < size) {
1656 ifr->ifr_settings.size = size; /* data size wanted */
1657 return -ENOBUFS;
1658 }
1659
1660 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1661 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1662 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1663 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1664
1665 switch (flags){
1666 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1667 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1668 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1669 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1670 default: new_line.clock_type = CLOCK_DEFAULT;
1671 }
1672
1673 new_line.clock_rate = info->params.clock_speed;
1674 new_line.loopback = info->params.loopback ? 1:0;
1675
1676 if (copy_to_user(line, &new_line, size))
1677 return -EFAULT;
1678 return 0;
1679
1680 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1681
1682 if(!capable(CAP_NET_ADMIN))
1683 return -EPERM;
1684 if (copy_from_user(&new_line, line, size))
1685 return -EFAULT;
1686
1687 switch (new_line.clock_type)
1688 {
1689 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1690 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1691 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1692 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1693 case CLOCK_DEFAULT: flags = info->params.flags &
1694 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1695 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1696 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1697 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1698 default: return -EINVAL;
1699 }
1700
1701 if (new_line.loopback != 0 && new_line.loopback != 1)
1702 return -EINVAL;
1703
1704 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1705 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1706 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1707 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1708 info->params.flags |= flags;
1709
1710 info->params.loopback = new_line.loopback;
1711
1712 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1713 info->params.clock_speed = new_line.clock_rate;
1714 else
1715 info->params.clock_speed = 0;
1716
1717 /* if network interface up, reprogram hardware */
1718 if (info->netcount)
1719 program_hw(info);
1720 return 0;
1721
1722 default:
1723 return hdlc_ioctl(dev, ifr, cmd);
1724 }
1725 }
1726
1727 /**
1728 * called by network layer when transmit timeout is detected
1729 *
1730 * dev pointer to network device structure
1731 */
1732 static void hdlcdev_tx_timeout(struct net_device *dev)
1733 {
1734 struct slgt_info *info = dev_to_port(dev);
1735 unsigned long flags;
1736
1737 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1738
1739 dev->stats.tx_errors++;
1740 dev->stats.tx_aborted_errors++;
1741
1742 spin_lock_irqsave(&info->lock,flags);
1743 tx_stop(info);
1744 spin_unlock_irqrestore(&info->lock,flags);
1745
1746 netif_wake_queue(dev);
1747 }
1748
1749 /**
1750 * called by device driver when transmit completes
1751 * reenable network layer transmit if stopped
1752 *
1753 * info pointer to device instance information
1754 */
1755 static void hdlcdev_tx_done(struct slgt_info *info)
1756 {
1757 if (netif_queue_stopped(info->netdev))
1758 netif_wake_queue(info->netdev);
1759 }
1760
1761 /**
1762 * called by device driver when frame received
1763 * pass frame to network layer
1764 *
1765 * info pointer to device instance information
1766 * buf pointer to buffer contianing frame data
1767 * size count of data bytes in buf
1768 */
1769 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1770 {
1771 struct sk_buff *skb = dev_alloc_skb(size);
1772 struct net_device *dev = info->netdev;
1773
1774 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1775
1776 if (skb == NULL) {
1777 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1778 dev->stats.rx_dropped++;
1779 return;
1780 }
1781
1782 memcpy(skb_put(skb, size), buf, size);
1783
1784 skb->protocol = hdlc_type_trans(skb, dev);
1785
1786 dev->stats.rx_packets++;
1787 dev->stats.rx_bytes += size;
1788
1789 netif_rx(skb);
1790 }
1791
1792 static const struct net_device_ops hdlcdev_ops = {
1793 .ndo_open = hdlcdev_open,
1794 .ndo_stop = hdlcdev_close,
1795 .ndo_change_mtu = hdlc_change_mtu,
1796 .ndo_start_xmit = hdlc_start_xmit,
1797 .ndo_do_ioctl = hdlcdev_ioctl,
1798 .ndo_tx_timeout = hdlcdev_tx_timeout,
1799 };
1800
1801 /**
1802 * called by device driver when adding device instance
1803 * do generic HDLC initialization
1804 *
1805 * info pointer to device instance information
1806 *
1807 * returns 0 if success, otherwise error code
1808 */
1809 static int hdlcdev_init(struct slgt_info *info)
1810 {
1811 int rc;
1812 struct net_device *dev;
1813 hdlc_device *hdlc;
1814
1815 /* allocate and initialize network and HDLC layer objects */
1816
1817 if (!(dev = alloc_hdlcdev(info))) {
1818 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1819 return -ENOMEM;
1820 }
1821
1822 /* for network layer reporting purposes only */
1823 dev->mem_start = info->phys_reg_addr;
1824 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1825 dev->irq = info->irq_level;
1826
1827 /* network layer callbacks and settings */
1828 dev->netdev_ops = &hdlcdev_ops;
1829 dev->watchdog_timeo = 10 * HZ;
1830 dev->tx_queue_len = 50;
1831
1832 /* generic HDLC layer callbacks and settings */
1833 hdlc = dev_to_hdlc(dev);
1834 hdlc->attach = hdlcdev_attach;
1835 hdlc->xmit = hdlcdev_xmit;
1836
1837 /* register objects with HDLC layer */
1838 if ((rc = register_hdlc_device(dev))) {
1839 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1840 free_netdev(dev);
1841 return rc;
1842 }
1843
1844 info->netdev = dev;
1845 return 0;
1846 }
1847
1848 /**
1849 * called by device driver when removing device instance
1850 * do generic HDLC cleanup
1851 *
1852 * info pointer to device instance information
1853 */
1854 static void hdlcdev_exit(struct slgt_info *info)
1855 {
1856 unregister_hdlc_device(info->netdev);
1857 free_netdev(info->netdev);
1858 info->netdev = NULL;
1859 }
1860
1861 #endif /* ifdef CONFIG_HDLC */
1862
1863 /*
1864 * get async data from rx DMA buffers
1865 */
1866 static void rx_async(struct slgt_info *info)
1867 {
1868 struct tty_struct *tty = info->port.tty;
1869 struct mgsl_icount *icount = &info->icount;
1870 unsigned int start, end;
1871 unsigned char *p;
1872 unsigned char status;
1873 struct slgt_desc *bufs = info->rbufs;
1874 int i, count;
1875 int chars = 0;
1876 int stat;
1877 unsigned char ch;
1878
1879 start = end = info->rbuf_current;
1880
1881 while(desc_complete(bufs[end])) {
1882 count = desc_count(bufs[end]) - info->rbuf_index;
1883 p = bufs[end].buf + info->rbuf_index;
1884
1885 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1886 DBGDATA(info, p, count, "rx");
1887
1888 for(i=0 ; i < count; i+=2, p+=2) {
1889 ch = *p;
1890 icount->rx++;
1891
1892 stat = 0;
1893
1894 if ((status = *(p+1) & (BIT1 + BIT0))) {
1895 if (status & BIT1)
1896 icount->parity++;
1897 else if (status & BIT0)
1898 icount->frame++;
1899 /* discard char if tty control flags say so */
1900 if (status & info->ignore_status_mask)
1901 continue;
1902 if (status & BIT1)
1903 stat = TTY_PARITY;
1904 else if (status & BIT0)
1905 stat = TTY_FRAME;
1906 }
1907 if (tty) {
1908 tty_insert_flip_char(tty, ch, stat);
1909 chars++;
1910 }
1911 }
1912
1913 if (i < count) {
1914 /* receive buffer not completed */
1915 info->rbuf_index += i;
1916 mod_timer(&info->rx_timer, jiffies + 1);
1917 break;
1918 }
1919
1920 info->rbuf_index = 0;
1921 free_rbufs(info, end, end);
1922
1923 if (++end == info->rbuf_count)
1924 end = 0;
1925
1926 /* if entire list searched then no frame available */
1927 if (end == start)
1928 break;
1929 }
1930
1931 if (tty && chars)
1932 tty_flip_buffer_push(tty);
1933 }
1934
1935 /*
1936 * return next bottom half action to perform
1937 */
1938 static int bh_action(struct slgt_info *info)
1939 {
1940 unsigned long flags;
1941 int rc;
1942
1943 spin_lock_irqsave(&info->lock,flags);
1944
1945 if (info->pending_bh & BH_RECEIVE) {
1946 info->pending_bh &= ~BH_RECEIVE;
1947 rc = BH_RECEIVE;
1948 } else if (info->pending_bh & BH_TRANSMIT) {
1949 info->pending_bh &= ~BH_TRANSMIT;
1950 rc = BH_TRANSMIT;
1951 } else if (info->pending_bh & BH_STATUS) {
1952 info->pending_bh &= ~BH_STATUS;
1953 rc = BH_STATUS;
1954 } else {
1955 /* Mark BH routine as complete */
1956 info->bh_running = false;
1957 info->bh_requested = false;
1958 rc = 0;
1959 }
1960
1961 spin_unlock_irqrestore(&info->lock,flags);
1962
1963 return rc;
1964 }
1965
1966 /*
1967 * perform bottom half processing
1968 */
1969 static void bh_handler(struct work_struct *work)
1970 {
1971 struct slgt_info *info = container_of(work, struct slgt_info, task);
1972 int action;
1973
1974 if (!info)
1975 return;
1976 info->bh_running = true;
1977
1978 while((action = bh_action(info))) {
1979 switch (action) {
1980 case BH_RECEIVE:
1981 DBGBH(("%s bh receive\n", info->device_name));
1982 switch(info->params.mode) {
1983 case MGSL_MODE_ASYNC:
1984 rx_async(info);
1985 break;
1986 case MGSL_MODE_HDLC:
1987 while(rx_get_frame(info));
1988 break;
1989 case MGSL_MODE_RAW:
1990 case MGSL_MODE_MONOSYNC:
1991 case MGSL_MODE_BISYNC:
1992 while(rx_get_buf(info));
1993 break;
1994 }
1995 /* restart receiver if rx DMA buffers exhausted */
1996 if (info->rx_restart)
1997 rx_start(info);
1998 break;
1999 case BH_TRANSMIT:
2000 bh_transmit(info);
2001 break;
2002 case BH_STATUS:
2003 DBGBH(("%s bh status\n", info->device_name));
2004 info->ri_chkcount = 0;
2005 info->dsr_chkcount = 0;
2006 info->dcd_chkcount = 0;
2007 info->cts_chkcount = 0;
2008 break;
2009 default:
2010 DBGBH(("%s unknown action\n", info->device_name));
2011 break;
2012 }
2013 }
2014 DBGBH(("%s bh_handler exit\n", info->device_name));
2015 }
2016
2017 static void bh_transmit(struct slgt_info *info)
2018 {
2019 struct tty_struct *tty = info->port.tty;
2020
2021 DBGBH(("%s bh_transmit\n", info->device_name));
2022 if (tty)
2023 tty_wakeup(tty);
2024 }
2025
2026 static void dsr_change(struct slgt_info *info, unsigned short status)
2027 {
2028 if (status & BIT3) {
2029 info->signals |= SerialSignal_DSR;
2030 info->input_signal_events.dsr_up++;
2031 } else {
2032 info->signals &= ~SerialSignal_DSR;
2033 info->input_signal_events.dsr_down++;
2034 }
2035 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2036 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2037 slgt_irq_off(info, IRQ_DSR);
2038 return;
2039 }
2040 info->icount.dsr++;
2041 wake_up_interruptible(&info->status_event_wait_q);
2042 wake_up_interruptible(&info->event_wait_q);
2043 info->pending_bh |= BH_STATUS;
2044 }
2045
2046 static void cts_change(struct slgt_info *info, unsigned short status)
2047 {
2048 if (status & BIT2) {
2049 info->signals |= SerialSignal_CTS;
2050 info->input_signal_events.cts_up++;
2051 } else {
2052 info->signals &= ~SerialSignal_CTS;
2053 info->input_signal_events.cts_down++;
2054 }
2055 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2056 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2057 slgt_irq_off(info, IRQ_CTS);
2058 return;
2059 }
2060 info->icount.cts++;
2061 wake_up_interruptible(&info->status_event_wait_q);
2062 wake_up_interruptible(&info->event_wait_q);
2063 info->pending_bh |= BH_STATUS;
2064
2065 if (info->port.flags & ASYNC_CTS_FLOW) {
2066 if (info->port.tty) {
2067 if (info->port.tty->hw_stopped) {
2068 if (info->signals & SerialSignal_CTS) {
2069 info->port.tty->hw_stopped = 0;
2070 info->pending_bh |= BH_TRANSMIT;
2071 return;
2072 }
2073 } else {
2074 if (!(info->signals & SerialSignal_CTS))
2075 info->port.tty->hw_stopped = 1;
2076 }
2077 }
2078 }
2079 }
2080
2081 static void dcd_change(struct slgt_info *info, unsigned short status)
2082 {
2083 if (status & BIT1) {
2084 info->signals |= SerialSignal_DCD;
2085 info->input_signal_events.dcd_up++;
2086 } else {
2087 info->signals &= ~SerialSignal_DCD;
2088 info->input_signal_events.dcd_down++;
2089 }
2090 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2091 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2092 slgt_irq_off(info, IRQ_DCD);
2093 return;
2094 }
2095 info->icount.dcd++;
2096 #if SYNCLINK_GENERIC_HDLC
2097 if (info->netcount) {
2098 if (info->signals & SerialSignal_DCD)
2099 netif_carrier_on(info->netdev);
2100 else
2101 netif_carrier_off(info->netdev);
2102 }
2103 #endif
2104 wake_up_interruptible(&info->status_event_wait_q);
2105 wake_up_interruptible(&info->event_wait_q);
2106 info->pending_bh |= BH_STATUS;
2107
2108 if (info->port.flags & ASYNC_CHECK_CD) {
2109 if (info->signals & SerialSignal_DCD)
2110 wake_up_interruptible(&info->port.open_wait);
2111 else {
2112 if (info->port.tty)
2113 tty_hangup(info->port.tty);
2114 }
2115 }
2116 }
2117
2118 static void ri_change(struct slgt_info *info, unsigned short status)
2119 {
2120 if (status & BIT0) {
2121 info->signals |= SerialSignal_RI;
2122 info->input_signal_events.ri_up++;
2123 } else {
2124 info->signals &= ~SerialSignal_RI;
2125 info->input_signal_events.ri_down++;
2126 }
2127 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2128 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2129 slgt_irq_off(info, IRQ_RI);
2130 return;
2131 }
2132 info->icount.rng++;
2133 wake_up_interruptible(&info->status_event_wait_q);
2134 wake_up_interruptible(&info->event_wait_q);
2135 info->pending_bh |= BH_STATUS;
2136 }
2137
2138 static void isr_rxdata(struct slgt_info *info)
2139 {
2140 unsigned int count = info->rbuf_fill_count;
2141 unsigned int i = info->rbuf_fill_index;
2142 unsigned short reg;
2143
2144 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2145 reg = rd_reg16(info, RDR);
2146 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2147 if (desc_complete(info->rbufs[i])) {
2148 /* all buffers full */
2149 rx_stop(info);
2150 info->rx_restart = 1;
2151 continue;
2152 }
2153 info->rbufs[i].buf[count++] = (unsigned char)reg;
2154 /* async mode saves status byte to buffer for each data byte */
2155 if (info->params.mode == MGSL_MODE_ASYNC)
2156 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2157 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2158 /* buffer full or end of frame */
2159 set_desc_count(info->rbufs[i], count);
2160 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2161 info->rbuf_fill_count = count = 0;
2162 if (++i == info->rbuf_count)
2163 i = 0;
2164 info->pending_bh |= BH_RECEIVE;
2165 }
2166 }
2167
2168 info->rbuf_fill_index = i;
2169 info->rbuf_fill_count = count;
2170 }
2171
2172 static void isr_serial(struct slgt_info *info)
2173 {
2174 unsigned short status = rd_reg16(info, SSR);
2175
2176 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2177
2178 wr_reg16(info, SSR, status); /* clear pending */
2179
2180 info->irq_occurred = true;
2181
2182 if (info->params.mode == MGSL_MODE_ASYNC) {
2183 if (status & IRQ_TXIDLE) {
2184 if (info->tx_count)
2185 isr_txeom(info, status);
2186 }
2187 if (info->rx_pio && (status & IRQ_RXDATA))
2188 isr_rxdata(info);
2189 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2190 info->icount.brk++;
2191 /* process break detection if tty control allows */
2192 if (info->port.tty) {
2193 if (!(status & info->ignore_status_mask)) {
2194 if (info->read_status_mask & MASK_BREAK) {
2195 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2196 if (info->port.flags & ASYNC_SAK)
2197 do_SAK(info->port.tty);
2198 }
2199 }
2200 }
2201 }
2202 } else {
2203 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2204 isr_txeom(info, status);
2205 if (info->rx_pio && (status & IRQ_RXDATA))
2206 isr_rxdata(info);
2207 if (status & IRQ_RXIDLE) {
2208 if (status & RXIDLE)
2209 info->icount.rxidle++;
2210 else
2211 info->icount.exithunt++;
2212 wake_up_interruptible(&info->event_wait_q);
2213 }
2214
2215 if (status & IRQ_RXOVER)
2216 rx_start(info);
2217 }
2218
2219 if (status & IRQ_DSR)
2220 dsr_change(info, status);
2221 if (status & IRQ_CTS)
2222 cts_change(info, status);
2223 if (status & IRQ_DCD)
2224 dcd_change(info, status);
2225 if (status & IRQ_RI)
2226 ri_change(info, status);
2227 }
2228
2229 static void isr_rdma(struct slgt_info *info)
2230 {
2231 unsigned int status = rd_reg32(info, RDCSR);
2232
2233 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2234
2235 /* RDCSR (rx DMA control/status)
2236 *
2237 * 31..07 reserved
2238 * 06 save status byte to DMA buffer
2239 * 05 error
2240 * 04 eol (end of list)
2241 * 03 eob (end of buffer)
2242 * 02 IRQ enable
2243 * 01 reset
2244 * 00 enable
2245 */
2246 wr_reg32(info, RDCSR, status); /* clear pending */
2247
2248 if (status & (BIT5 + BIT4)) {
2249 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2250 info->rx_restart = true;
2251 }
2252 info->pending_bh |= BH_RECEIVE;
2253 }
2254
2255 static void isr_tdma(struct slgt_info *info)
2256 {
2257 unsigned int status = rd_reg32(info, TDCSR);
2258
2259 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2260
2261 /* TDCSR (tx DMA control/status)
2262 *
2263 * 31..06 reserved
2264 * 05 error
2265 * 04 eol (end of list)
2266 * 03 eob (end of buffer)
2267 * 02 IRQ enable
2268 * 01 reset
2269 * 00 enable
2270 */
2271 wr_reg32(info, TDCSR, status); /* clear pending */
2272
2273 if (status & (BIT5 + BIT4 + BIT3)) {
2274 // another transmit buffer has completed
2275 // run bottom half to get more send data from user
2276 info->pending_bh |= BH_TRANSMIT;
2277 }
2278 }
2279
2280 static void isr_txeom(struct slgt_info *info, unsigned short status)
2281 {
2282 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2283
2284 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2285 tdma_reset(info);
2286 reset_tbufs(info);
2287 if (status & IRQ_TXUNDER) {
2288 unsigned short val = rd_reg16(info, TCR);
2289 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2290 wr_reg16(info, TCR, val); /* clear reset bit */
2291 }
2292
2293 if (info->tx_active) {
2294 if (info->params.mode != MGSL_MODE_ASYNC) {
2295 if (status & IRQ_TXUNDER)
2296 info->icount.txunder++;
2297 else if (status & IRQ_TXIDLE)
2298 info->icount.txok++;
2299 }
2300
2301 info->tx_active = false;
2302 info->tx_count = 0;
2303
2304 del_timer(&info->tx_timer);
2305
2306 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2307 info->signals &= ~SerialSignal_RTS;
2308 info->drop_rts_on_tx_done = false;
2309 set_signals(info);
2310 }
2311
2312 #if SYNCLINK_GENERIC_HDLC
2313 if (info->netcount)
2314 hdlcdev_tx_done(info);
2315 else
2316 #endif
2317 {
2318 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2319 tx_stop(info);
2320 return;
2321 }
2322 info->pending_bh |= BH_TRANSMIT;
2323 }
2324 }
2325 }
2326
2327 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2328 {
2329 struct cond_wait *w, *prev;
2330
2331 /* wake processes waiting for specific transitions */
2332 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2333 if (w->data & changed) {
2334 w->data = state;
2335 wake_up_interruptible(&w->q);
2336 if (prev != NULL)
2337 prev->next = w->next;
2338 else
2339 info->gpio_wait_q = w->next;
2340 } else
2341 prev = w;
2342 }
2343 }
2344
2345 /* interrupt service routine
2346 *
2347 * irq interrupt number
2348 * dev_id device ID supplied during interrupt registration
2349 */
2350 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2351 {
2352 struct slgt_info *info = dev_id;
2353 unsigned int gsr;
2354 unsigned int i;
2355
2356 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2357
2358 spin_lock(&info->lock);
2359
2360 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2361 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2362 info->irq_occurred = true;
2363 for(i=0; i < info->port_count ; i++) {
2364 if (info->port_array[i] == NULL)
2365 continue;
2366 if (gsr & (BIT8 << i))
2367 isr_serial(info->port_array[i]);
2368 if (gsr & (BIT16 << (i*2)))
2369 isr_rdma(info->port_array[i]);
2370 if (gsr & (BIT17 << (i*2)))
2371 isr_tdma(info->port_array[i]);
2372 }
2373 }
2374
2375 if (info->gpio_present) {
2376 unsigned int state;
2377 unsigned int changed;
2378 while ((changed = rd_reg32(info, IOSR)) != 0) {
2379 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2380 /* read latched state of GPIO signals */
2381 state = rd_reg32(info, IOVR);
2382 /* clear pending GPIO interrupt bits */
2383 wr_reg32(info, IOSR, changed);
2384 for (i=0 ; i < info->port_count ; i++) {
2385 if (info->port_array[i] != NULL)
2386 isr_gpio(info->port_array[i], changed, state);
2387 }
2388 }
2389 }
2390
2391 for(i=0; i < info->port_count ; i++) {
2392 struct slgt_info *port = info->port_array[i];
2393
2394 if (port && (port->port.count || port->netcount) &&
2395 port->pending_bh && !port->bh_running &&
2396 !port->bh_requested) {
2397 DBGISR(("%s bh queued\n", port->device_name));
2398 schedule_work(&port->task);
2399 port->bh_requested = true;
2400 }
2401 }
2402
2403 spin_unlock(&info->lock);
2404
2405 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2406 return IRQ_HANDLED;
2407 }
2408
2409 static int startup(struct slgt_info *info)
2410 {
2411 DBGINFO(("%s startup\n", info->device_name));
2412
2413 if (info->port.flags & ASYNC_INITIALIZED)
2414 return 0;
2415
2416 if (!info->tx_buf) {
2417 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2418 if (!info->tx_buf) {
2419 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2420 return -ENOMEM;
2421 }
2422 }
2423
2424 info->pending_bh = 0;
2425
2426 memset(&info->icount, 0, sizeof(info->icount));
2427
2428 /* program hardware for current parameters */
2429 change_params(info);
2430
2431 if (info->port.tty)
2432 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2433
2434 info->port.flags |= ASYNC_INITIALIZED;
2435
2436 return 0;
2437 }
2438
2439 /*
2440 * called by close() and hangup() to shutdown hardware
2441 */
2442 static void shutdown(struct slgt_info *info)
2443 {
2444 unsigned long flags;
2445
2446 if (!(info->port.flags & ASYNC_INITIALIZED))
2447 return;
2448
2449 DBGINFO(("%s shutdown\n", info->device_name));
2450
2451 /* clear status wait queue because status changes */
2452 /* can't happen after shutting down the hardware */
2453 wake_up_interruptible(&info->status_event_wait_q);
2454 wake_up_interruptible(&info->event_wait_q);
2455
2456 del_timer_sync(&info->tx_timer);
2457 del_timer_sync(&info->rx_timer);
2458
2459 kfree(info->tx_buf);
2460 info->tx_buf = NULL;
2461
2462 spin_lock_irqsave(&info->lock,flags);
2463
2464 tx_stop(info);
2465 rx_stop(info);
2466
2467 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2468
2469 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2470 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2471 set_signals(info);
2472 }
2473
2474 flush_cond_wait(&info->gpio_wait_q);
2475
2476 spin_unlock_irqrestore(&info->lock,flags);
2477
2478 if (info->port.tty)
2479 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2480
2481 info->port.flags &= ~ASYNC_INITIALIZED;
2482 }
2483
2484 static void program_hw(struct slgt_info *info)
2485 {
2486 unsigned long flags;
2487
2488 spin_lock_irqsave(&info->lock,flags);
2489
2490 rx_stop(info);
2491 tx_stop(info);
2492
2493 if (info->params.mode != MGSL_MODE_ASYNC ||
2494 info->netcount)
2495 sync_mode(info);
2496 else
2497 async_mode(info);
2498
2499 set_signals(info);
2500
2501 info->dcd_chkcount = 0;
2502 info->cts_chkcount = 0;
2503 info->ri_chkcount = 0;
2504 info->dsr_chkcount = 0;
2505
2506 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2507 get_signals(info);
2508
2509 if (info->netcount ||
2510 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2511 rx_start(info);
2512
2513 spin_unlock_irqrestore(&info->lock,flags);
2514 }
2515
2516 /*
2517 * reconfigure adapter based on new parameters
2518 */
2519 static void change_params(struct slgt_info *info)
2520 {
2521 unsigned cflag;
2522 int bits_per_char;
2523
2524 if (!info->port.tty || !info->port.tty->termios)
2525 return;
2526 DBGINFO(("%s change_params\n", info->device_name));
2527
2528 cflag = info->port.tty->termios->c_cflag;
2529
2530 /* if B0 rate (hangup) specified then negate DTR and RTS */
2531 /* otherwise assert DTR and RTS */
2532 if (cflag & CBAUD)
2533 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2534 else
2535 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2536
2537 /* byte size and parity */
2538
2539 switch (cflag & CSIZE) {
2540 case CS5: info->params.data_bits = 5; break;
2541 case CS6: info->params.data_bits = 6; break;
2542 case CS7: info->params.data_bits = 7; break;
2543 case CS8: info->params.data_bits = 8; break;
2544 default: info->params.data_bits = 7; break;
2545 }
2546
2547 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2548
2549 if (cflag & PARENB)
2550 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2551 else
2552 info->params.parity = ASYNC_PARITY_NONE;
2553
2554 /* calculate number of jiffies to transmit a full
2555 * FIFO (32 bytes) at specified data rate
2556 */
2557 bits_per_char = info->params.data_bits +
2558 info->params.stop_bits + 1;
2559
2560 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2561
2562 if (info->params.data_rate) {
2563 info->timeout = (32*HZ*bits_per_char) /
2564 info->params.data_rate;
2565 }
2566 info->timeout += HZ/50; /* Add .02 seconds of slop */
2567
2568 if (cflag & CRTSCTS)
2569 info->port.flags |= ASYNC_CTS_FLOW;
2570 else
2571 info->port.flags &= ~ASYNC_CTS_FLOW;
2572
2573 if (cflag & CLOCAL)
2574 info->port.flags &= ~ASYNC_CHECK_CD;
2575 else
2576 info->port.flags |= ASYNC_CHECK_CD;
2577
2578 /* process tty input control flags */
2579
2580 info->read_status_mask = IRQ_RXOVER;
2581 if (I_INPCK(info->port.tty))
2582 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2583 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2584 info->read_status_mask |= MASK_BREAK;
2585 if (I_IGNPAR(info->port.tty))
2586 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2587 if (I_IGNBRK(info->port.tty)) {
2588 info->ignore_status_mask |= MASK_BREAK;
2589 /* If ignoring parity and break indicators, ignore
2590 * overruns too. (For real raw support).
2591 */
2592 if (I_IGNPAR(info->port.tty))
2593 info->ignore_status_mask |= MASK_OVERRUN;
2594 }
2595
2596 program_hw(info);
2597 }
2598
2599 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2600 {
2601 DBGINFO(("%s get_stats\n", info->device_name));
2602 if (!user_icount) {
2603 memset(&info->icount, 0, sizeof(info->icount));
2604 } else {
2605 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2606 return -EFAULT;
2607 }
2608 return 0;
2609 }
2610
2611 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2612 {
2613 DBGINFO(("%s get_params\n", info->device_name));
2614 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2615 return -EFAULT;
2616 return 0;
2617 }
2618
2619 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2620 {
2621 unsigned long flags;
2622 MGSL_PARAMS tmp_params;
2623
2624 DBGINFO(("%s set_params\n", info->device_name));
2625 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2626 return -EFAULT;
2627
2628 spin_lock_irqsave(&info->lock, flags);
2629 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2630 info->base_clock = tmp_params.clock_speed;
2631 else
2632 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2633 spin_unlock_irqrestore(&info->lock, flags);
2634
2635 program_hw(info);
2636
2637 return 0;
2638 }
2639
2640 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2641 {
2642 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2643 if (put_user(info->idle_mode, idle_mode))
2644 return -EFAULT;
2645 return 0;
2646 }
2647
2648 static int set_txidle(struct slgt_info *info, int idle_mode)
2649 {
2650 unsigned long flags;
2651 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2652 spin_lock_irqsave(&info->lock,flags);
2653 info->idle_mode = idle_mode;
2654 if (info->params.mode != MGSL_MODE_ASYNC)
2655 tx_set_idle(info);
2656 spin_unlock_irqrestore(&info->lock,flags);
2657 return 0;
2658 }
2659
2660 static int tx_enable(struct slgt_info *info, int enable)
2661 {
2662 unsigned long flags;
2663 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2664 spin_lock_irqsave(&info->lock,flags);
2665 if (enable) {
2666 if (!info->tx_enabled)
2667 tx_start(info);
2668 } else {
2669 if (info->tx_enabled)
2670 tx_stop(info);
2671 }
2672 spin_unlock_irqrestore(&info->lock,flags);
2673 return 0;
2674 }
2675
2676 /*
2677 * abort transmit HDLC frame
2678 */
2679 static int tx_abort(struct slgt_info *info)
2680 {
2681 unsigned long flags;
2682 DBGINFO(("%s tx_abort\n", info->device_name));
2683 spin_lock_irqsave(&info->lock,flags);
2684 tdma_reset(info);
2685 spin_unlock_irqrestore(&info->lock,flags);
2686 return 0;
2687 }
2688
2689 static int rx_enable(struct slgt_info *info, int enable)
2690 {
2691 unsigned long flags;
2692 unsigned int rbuf_fill_level;
2693 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2694 spin_lock_irqsave(&info->lock,flags);
2695 /*
2696 * enable[31..16] = receive DMA buffer fill level
2697 * 0 = noop (leave fill level unchanged)
2698 * fill level must be multiple of 4 and <= buffer size
2699 */
2700 rbuf_fill_level = ((unsigned int)enable) >> 16;
2701 if (rbuf_fill_level) {
2702 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2703 spin_unlock_irqrestore(&info->lock, flags);
2704 return -EINVAL;
2705 }
2706 info->rbuf_fill_level = rbuf_fill_level;
2707 if (rbuf_fill_level < 128)
2708 info->rx_pio = 1; /* PIO mode */
2709 else
2710 info->rx_pio = 0; /* DMA mode */
2711 rx_stop(info); /* restart receiver to use new fill level */
2712 }
2713
2714 /*
2715 * enable[1..0] = receiver enable command
2716 * 0 = disable
2717 * 1 = enable
2718 * 2 = enable or force hunt mode if already enabled
2719 */
2720 enable &= 3;
2721 if (enable) {
2722 if (!info->rx_enabled)
2723 rx_start(info);
2724 else if (enable == 2) {
2725 /* force hunt mode (write 1 to RCR[3]) */
2726 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2727 }
2728 } else {
2729 if (info->rx_enabled)
2730 rx_stop(info);
2731 }
2732 spin_unlock_irqrestore(&info->lock,flags);
2733 return 0;
2734 }
2735
2736 /*
2737 * wait for specified event to occur
2738 */
2739 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2740 {
2741 unsigned long flags;
2742 int s;
2743 int rc=0;
2744 struct mgsl_icount cprev, cnow;
2745 int events;
2746 int mask;
2747 struct _input_signal_events oldsigs, newsigs;
2748 DECLARE_WAITQUEUE(wait, current);
2749
2750 if (get_user(mask, mask_ptr))
2751 return -EFAULT;
2752
2753 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2754
2755 spin_lock_irqsave(&info->lock,flags);
2756
2757 /* return immediately if state matches requested events */
2758 get_signals(info);
2759 s = info->signals;
2760
2761 events = mask &
2762 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2763 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2764 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2765 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2766 if (events) {
2767 spin_unlock_irqrestore(&info->lock,flags);
2768 goto exit;
2769 }
2770
2771 /* save current irq counts */
2772 cprev = info->icount;
2773 oldsigs = info->input_signal_events;
2774
2775 /* enable hunt and idle irqs if needed */
2776 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2777 unsigned short val = rd_reg16(info, SCR);
2778 if (!(val & IRQ_RXIDLE))
2779 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2780 }
2781
2782 set_current_state(TASK_INTERRUPTIBLE);
2783 add_wait_queue(&info->event_wait_q, &wait);
2784
2785 spin_unlock_irqrestore(&info->lock,flags);
2786
2787 for(;;) {
2788 schedule();
2789 if (signal_pending(current)) {
2790 rc = -ERESTARTSYS;
2791 break;
2792 }
2793
2794 /* get current irq counts */
2795 spin_lock_irqsave(&info->lock,flags);
2796 cnow = info->icount;
2797 newsigs = info->input_signal_events;
2798 set_current_state(TASK_INTERRUPTIBLE);
2799 spin_unlock_irqrestore(&info->lock,flags);
2800
2801 /* if no change, wait aborted for some reason */
2802 if (newsigs.dsr_up == oldsigs.dsr_up &&
2803 newsigs.dsr_down == oldsigs.dsr_down &&
2804 newsigs.dcd_up == oldsigs.dcd_up &&
2805 newsigs.dcd_down == oldsigs.dcd_down &&
2806 newsigs.cts_up == oldsigs.cts_up &&
2807 newsigs.cts_down == oldsigs.cts_down &&
2808 newsigs.ri_up == oldsigs.ri_up &&
2809 newsigs.ri_down == oldsigs.ri_down &&
2810 cnow.exithunt == cprev.exithunt &&
2811 cnow.rxidle == cprev.rxidle) {
2812 rc = -EIO;
2813 break;
2814 }
2815
2816 events = mask &
2817 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2818 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2819 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2820 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2821 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2822 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2823 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2824 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2825 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2826 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2827 if (events)
2828 break;
2829
2830 cprev = cnow;
2831 oldsigs = newsigs;
2832 }
2833
2834 remove_wait_queue(&info->event_wait_q, &wait);
2835 set_current_state(TASK_RUNNING);
2836
2837
2838 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2839 spin_lock_irqsave(&info->lock,flags);
2840 if (!waitqueue_active(&info->event_wait_q)) {
2841 /* disable enable exit hunt mode/idle rcvd IRQs */
2842 wr_reg16(info, SCR,
2843 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2844 }
2845 spin_unlock_irqrestore(&info->lock,flags);
2846 }
2847 exit:
2848 if (rc == 0)
2849 rc = put_user(events, mask_ptr);
2850 return rc;
2851 }
2852
2853 static int get_interface(struct slgt_info *info, int __user *if_mode)
2854 {
2855 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2856 if (put_user(info->if_mode, if_mode))
2857 return -EFAULT;
2858 return 0;
2859 }
2860
2861 static int set_interface(struct slgt_info *info, int if_mode)
2862 {
2863 unsigned long flags;
2864 unsigned short val;
2865
2866 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2867 spin_lock_irqsave(&info->lock,flags);
2868 info->if_mode = if_mode;
2869
2870 msc_set_vcr(info);
2871
2872 /* TCR (tx control) 07 1=RTS driver control */
2873 val = rd_reg16(info, TCR);
2874 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2875 val |= BIT7;
2876 else
2877 val &= ~BIT7;
2878 wr_reg16(info, TCR, val);
2879
2880 spin_unlock_irqrestore(&info->lock,flags);
2881 return 0;
2882 }
2883
2884 /*
2885 * set general purpose IO pin state and direction
2886 *
2887 * user_gpio fields:
2888 * state each bit indicates a pin state
2889 * smask set bit indicates pin state to set
2890 * dir each bit indicates a pin direction (0=input, 1=output)
2891 * dmask set bit indicates pin direction to set
2892 */
2893 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2894 {
2895 unsigned long flags;
2896 struct gpio_desc gpio;
2897 __u32 data;
2898
2899 if (!info->gpio_present)
2900 return -EINVAL;
2901 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2902 return -EFAULT;
2903 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2904 info->device_name, gpio.state, gpio.smask,
2905 gpio.dir, gpio.dmask));
2906
2907 spin_lock_irqsave(&info->lock,flags);
2908 if (gpio.dmask) {
2909 data = rd_reg32(info, IODR);
2910 data |= gpio.dmask & gpio.dir;
2911 data &= ~(gpio.dmask & ~gpio.dir);
2912 wr_reg32(info, IODR, data);
2913 }
2914 if (gpio.smask) {
2915 data = rd_reg32(info, IOVR);
2916 data |= gpio.smask & gpio.state;
2917 data &= ~(gpio.smask & ~gpio.state);
2918 wr_reg32(info, IOVR, data);
2919 }
2920 spin_unlock_irqrestore(&info->lock,flags);
2921
2922 return 0;
2923 }
2924
2925 /*
2926 * get general purpose IO pin state and direction
2927 */
2928 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2929 {
2930 struct gpio_desc gpio;
2931 if (!info->gpio_present)
2932 return -EINVAL;
2933 gpio.state = rd_reg32(info, IOVR);
2934 gpio.smask = 0xffffffff;
2935 gpio.dir = rd_reg32(info, IODR);
2936 gpio.dmask = 0xffffffff;
2937 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2938 return -EFAULT;
2939 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2940 info->device_name, gpio.state, gpio.dir));
2941 return 0;
2942 }
2943
2944 /*
2945 * conditional wait facility
2946 */
2947 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2948 {
2949 init_waitqueue_head(&w->q);
2950 init_waitqueue_entry(&w->wait, current);
2951 w->data = data;
2952 }
2953
2954 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2955 {
2956 set_current_state(TASK_INTERRUPTIBLE);
2957 add_wait_queue(&w->q, &w->wait);
2958 w->next = *head;
2959 *head = w;
2960 }
2961
2962 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2963 {
2964 struct cond_wait *w, *prev;
2965 remove_wait_queue(&cw->q, &cw->wait);
2966 set_current_state(TASK_RUNNING);
2967 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2968 if (w == cw) {
2969 if (prev != NULL)
2970 prev->next = w->next;
2971 else
2972 *head = w->next;
2973 break;
2974 }
2975 }
2976 }
2977
2978 static void flush_cond_wait(struct cond_wait **head)
2979 {
2980 while (*head != NULL) {
2981 wake_up_interruptible(&(*head)->q);
2982 *head = (*head)->next;
2983 }
2984 }
2985
2986 /*
2987 * wait for general purpose I/O pin(s) to enter specified state
2988 *
2989 * user_gpio fields:
2990 * state - bit indicates target pin state
2991 * smask - set bit indicates watched pin
2992 *
2993 * The wait ends when at least one watched pin enters the specified
2994 * state. When 0 (no error) is returned, user_gpio->state is set to the
2995 * state of all GPIO pins when the wait ends.
2996 *
2997 * Note: Each pin may be a dedicated input, dedicated output, or
2998 * configurable input/output. The number and configuration of pins
2999 * varies with the specific adapter model. Only input pins (dedicated
3000 * or configured) can be monitored with this function.
3001 */
3002 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3003 {
3004 unsigned long flags;
3005 int rc = 0;
3006 struct gpio_desc gpio;
3007 struct cond_wait wait;
3008 u32 state;
3009
3010 if (!info->gpio_present)
3011 return -EINVAL;
3012 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3013 return -EFAULT;
3014 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3015 info->device_name, gpio.state, gpio.smask));
3016 /* ignore output pins identified by set IODR bit */
3017 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3018 return -EINVAL;
3019 init_cond_wait(&wait, gpio.smask);
3020
3021 spin_lock_irqsave(&info->lock, flags);
3022 /* enable interrupts for watched pins */
3023 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3024 /* get current pin states */
3025 state = rd_reg32(info, IOVR);
3026
3027 if (gpio.smask & ~(state ^ gpio.state)) {
3028 /* already in target state */
3029 gpio.state = state;
3030 } else {
3031 /* wait for target state */
3032 add_cond_wait(&info->gpio_wait_q, &wait);
3033 spin_unlock_irqrestore(&info->lock, flags);
3034 schedule();
3035 if (signal_pending(current))
3036 rc = -ERESTARTSYS;
3037 else
3038 gpio.state = wait.data;
3039 spin_lock_irqsave(&info->lock, flags);
3040 remove_cond_wait(&info->gpio_wait_q, &wait);
3041 }
3042
3043 /* disable all GPIO interrupts if no waiting processes */
3044 if (info->gpio_wait_q == NULL)
3045 wr_reg32(info, IOER, 0);
3046 spin_unlock_irqrestore(&info->lock,flags);
3047
3048 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3049 rc = -EFAULT;
3050 return rc;
3051 }
3052
3053 static int modem_input_wait(struct slgt_info *info,int arg)
3054 {
3055 unsigned long flags;
3056 int rc;
3057 struct mgsl_icount cprev, cnow;
3058 DECLARE_WAITQUEUE(wait, current);
3059
3060 /* save current irq counts */
3061 spin_lock_irqsave(&info->lock,flags);
3062 cprev = info->icount;
3063 add_wait_queue(&info->status_event_wait_q, &wait);
3064 set_current_state(TASK_INTERRUPTIBLE);
3065 spin_unlock_irqrestore(&info->lock,flags);
3066
3067 for(;;) {
3068 schedule();
3069 if (signal_pending(current)) {
3070 rc = -ERESTARTSYS;
3071 break;
3072 }
3073
3074 /* get new irq counts */
3075 spin_lock_irqsave(&info->lock,flags);
3076 cnow = info->icount;
3077 set_current_state(TASK_INTERRUPTIBLE);
3078 spin_unlock_irqrestore(&info->lock,flags);
3079
3080 /* if no change, wait aborted for some reason */
3081 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3082 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3083 rc = -EIO;
3084 break;
3085 }
3086
3087 /* check for change in caller specified modem input */
3088 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3089 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3090 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3091 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3092 rc = 0;
3093 break;
3094 }
3095
3096 cprev = cnow;
3097 }
3098 remove_wait_queue(&info->status_event_wait_q, &wait);
3099 set_current_state(TASK_RUNNING);
3100 return rc;
3101 }
3102
3103 /*
3104 * return state of serial control and status signals
3105 */
3106 static int tiocmget(struct tty_struct *tty, struct file *file)
3107 {
3108 struct slgt_info *info = tty->driver_data;
3109 unsigned int result;
3110 unsigned long flags;
3111
3112 spin_lock_irqsave(&info->lock,flags);
3113 get_signals(info);
3114 spin_unlock_irqrestore(&info->lock,flags);
3115
3116 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3117 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3118 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3119 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3120 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3121 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3122
3123 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3124 return result;
3125 }
3126
3127 /*
3128 * set modem control signals (DTR/RTS)
3129 *
3130 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3131 * TIOCMSET = set/clear signal values
3132 * value bit mask for command
3133 */
3134 static int tiocmset(struct tty_struct *tty, struct file *file,
3135 unsigned int set, unsigned int clear)
3136 {
3137 struct slgt_info *info = tty->driver_data;
3138 unsigned long flags;
3139
3140 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3141
3142 if (set & TIOCM_RTS)
3143 info->signals |= SerialSignal_RTS;
3144 if (set & TIOCM_DTR)
3145 info->signals |= SerialSignal_DTR;
3146 if (clear & TIOCM_RTS)
3147 info->signals &= ~SerialSignal_RTS;
3148 if (clear & TIOCM_DTR)
3149 info->signals &= ~SerialSignal_DTR;
3150
3151 spin_lock_irqsave(&info->lock,flags);
3152 set_signals(info);
3153 spin_unlock_irqrestore(&info->lock,flags);
3154 return 0;
3155 }
3156
3157 static int carrier_raised(struct tty_port *port)
3158 {
3159 unsigned long flags;
3160 struct slgt_info *info = container_of(port, struct slgt_info, port);
3161
3162 spin_lock_irqsave(&info->lock,flags);
3163 get_signals(info);
3164 spin_unlock_irqrestore(&info->lock,flags);
3165 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3166 }
3167
3168 static void dtr_rts(struct tty_port *port, int on)
3169 {
3170 unsigned long flags;
3171 struct slgt_info *info = container_of(port, struct slgt_info, port);
3172
3173 spin_lock_irqsave(&info->lock,flags);
3174 if (on)
3175 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3176 else
3177 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3178 set_signals(info);
3179 spin_unlock_irqrestore(&info->lock,flags);
3180 }
3181
3182
3183 /*
3184 * block current process until the device is ready to open
3185 */
3186 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3187 struct slgt_info *info)
3188 {
3189 DECLARE_WAITQUEUE(wait, current);
3190 int retval;
3191 bool do_clocal = false;
3192 bool extra_count = false;
3193 unsigned long flags;
3194 int cd;
3195 struct tty_port *port = &info->port;
3196
3197 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3198
3199 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3200 /* nonblock mode is set or port is not enabled */
3201 port->flags |= ASYNC_NORMAL_ACTIVE;
3202 return 0;
3203 }
3204
3205 if (tty->termios->c_cflag & CLOCAL)
3206 do_clocal = true;
3207
3208 /* Wait for carrier detect and the line to become
3209 * free (i.e., not in use by the callout). While we are in
3210 * this loop, port->count is dropped by one, so that
3211 * close() knows when to free things. We restore it upon
3212 * exit, either normal or abnormal.
3213 */
3214
3215 retval = 0;
3216 add_wait_queue(&port->open_wait, &wait);
3217
3218 spin_lock_irqsave(&info->lock, flags);
3219 if (!tty_hung_up_p(filp)) {
3220 extra_count = true;
3221 port->count--;
3222 }
3223 spin_unlock_irqrestore(&info->lock, flags);
3224 port->blocked_open++;
3225
3226 while (1) {
3227 if ((tty->termios->c_cflag & CBAUD))
3228 tty_port_raise_dtr_rts(port);
3229
3230 set_current_state(TASK_INTERRUPTIBLE);
3231
3232 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3233 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3234 -EAGAIN : -ERESTARTSYS;
3235 break;
3236 }
3237
3238 cd = tty_port_carrier_raised(port);
3239
3240 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3241 break;
3242
3243 if (signal_pending(current)) {
3244 retval = -ERESTARTSYS;
3245 break;
3246 }
3247
3248 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3249 schedule();
3250 }
3251
3252 set_current_state(TASK_RUNNING);
3253 remove_wait_queue(&port->open_wait, &wait);
3254
3255 if (extra_count)
3256 port->count++;
3257 port->blocked_open--;
3258
3259 if (!retval)
3260 port->flags |= ASYNC_NORMAL_ACTIVE;
3261
3262 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3263 return retval;
3264 }
3265
3266 static int alloc_tmp_rbuf(struct slgt_info *info)
3267 {
3268 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3269 if (info->tmp_rbuf == NULL)
3270 return -ENOMEM;
3271 return 0;
3272 }
3273
3274 static void free_tmp_rbuf(struct slgt_info *info)
3275 {
3276 kfree(info->tmp_rbuf);
3277 info->tmp_rbuf = NULL;
3278 }
3279
3280 /*
3281 * allocate DMA descriptor lists.
3282 */
3283 static int alloc_desc(struct slgt_info *info)
3284 {
3285 unsigned int i;
3286 unsigned int pbufs;
3287
3288 /* allocate memory to hold descriptor lists */
3289 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3290 if (info->bufs == NULL)
3291 return -ENOMEM;
3292
3293 memset(info->bufs, 0, DESC_LIST_SIZE);
3294
3295 info->rbufs = (struct slgt_desc*)info->bufs;
3296 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3297
3298 pbufs = (unsigned int)info->bufs_dma_addr;
3299
3300 /*
3301 * Build circular lists of descriptors
3302 */
3303
3304 for (i=0; i < info->rbuf_count; i++) {
3305 /* physical address of this descriptor */
3306 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3307
3308 /* physical address of next descriptor */
3309 if (i == info->rbuf_count - 1)
3310 info->rbufs[i].next = cpu_to_le32(pbufs);
3311 else
3312 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3313 set_desc_count(info->rbufs[i], DMABUFSIZE);
3314 }
3315
3316 for (i=0; i < info->tbuf_count; i++) {
3317 /* physical address of this descriptor */
3318 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3319
3320 /* physical address of next descriptor */
3321 if (i == info->tbuf_count - 1)
3322 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3323 else
3324 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3325 }
3326
3327 return 0;
3328 }
3329
3330 static void free_desc(struct slgt_info *info)
3331 {
3332 if (info->bufs != NULL) {
3333 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3334 info->bufs = NULL;
3335 info->rbufs = NULL;
3336 info->tbufs = NULL;
3337 }
3338 }
3339
3340 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3341 {
3342 int i;
3343 for (i=0; i < count; i++) {
3344 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3345 return -ENOMEM;
3346 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3347 }
3348 return 0;
3349 }
3350
3351 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3352 {
3353 int i;
3354 for (i=0; i < count; i++) {
3355 if (bufs[i].buf == NULL)
3356 continue;
3357 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3358 bufs[i].buf = NULL;
3359 }
3360 }
3361
3362 static int alloc_dma_bufs(struct slgt_info *info)
3363 {
3364 info->rbuf_count = 32;
3365 info->tbuf_count = 32;
3366
3367 if (alloc_desc(info) < 0 ||
3368 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3369 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3370 alloc_tmp_rbuf(info) < 0) {
3371 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3372 return -ENOMEM;
3373 }
3374 reset_rbufs(info);
3375 return 0;
3376 }
3377
3378 static void free_dma_bufs(struct slgt_info *info)
3379 {
3380 if (info->bufs) {
3381 free_bufs(info, info->rbufs, info->rbuf_count);
3382 free_bufs(info, info->tbufs, info->tbuf_count);
3383 free_desc(info);
3384 }
3385 free_tmp_rbuf(info);
3386 }
3387
3388 static int claim_resources(struct slgt_info *info)
3389 {
3390 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3391 DBGERR(("%s reg addr conflict, addr=%08X\n",
3392 info->device_name, info->phys_reg_addr));
3393 info->init_error = DiagStatus_AddressConflict;
3394 goto errout;
3395 }
3396 else
3397 info->reg_addr_requested = true;
3398
3399 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3400 if (!info->reg_addr) {
3401 DBGERR(("%s cant map device registers, addr=%08X\n",
3402 info->device_name, info->phys_reg_addr));
3403 info->init_error = DiagStatus_CantAssignPciResources;
3404 goto errout;
3405 }
3406 return 0;
3407
3408 errout:
3409 release_resources(info);
3410 return -ENODEV;
3411 }
3412
3413 static void release_resources(struct slgt_info *info)
3414 {
3415 if (info->irq_requested) {
3416 free_irq(info->irq_level, info);
3417 info->irq_requested = false;
3418 }
3419
3420 if (info->reg_addr_requested) {
3421 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3422 info->reg_addr_requested = false;
3423 }
3424
3425 if (info->reg_addr) {
3426 iounmap(info->reg_addr);
3427 info->reg_addr = NULL;
3428 }
3429 }
3430
3431 /* Add the specified device instance data structure to the
3432 * global linked list of devices and increment the device count.
3433 */
3434 static void add_device(struct slgt_info *info)
3435 {
3436 char *devstr;
3437
3438 info->next_device = NULL;
3439 info->line = slgt_device_count;
3440 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3441
3442 if (info->line < MAX_DEVICES) {
3443 if (maxframe[info->line])
3444 info->max_frame_size = maxframe[info->line];
3445 }
3446
3447 slgt_device_count++;
3448
3449 if (!slgt_device_list)
3450 slgt_device_list = info;
3451 else {
3452 struct slgt_info *current_dev = slgt_device_list;
3453 while(current_dev->next_device)
3454 current_dev = current_dev->next_device;
3455 current_dev->next_device = info;
3456 }
3457
3458 if (info->max_frame_size < 4096)
3459 info->max_frame_size = 4096;
3460 else if (info->max_frame_size > 65535)
3461 info->max_frame_size = 65535;
3462
3463 switch(info->pdev->device) {
3464 case SYNCLINK_GT_DEVICE_ID:
3465 devstr = "GT";
3466 break;
3467 case SYNCLINK_GT2_DEVICE_ID:
3468 devstr = "GT2";
3469 break;
3470 case SYNCLINK_GT4_DEVICE_ID:
3471 devstr = "GT4";
3472 break;
3473 case SYNCLINK_AC_DEVICE_ID:
3474 devstr = "AC";
3475 info->params.mode = MGSL_MODE_ASYNC;
3476 break;
3477 default:
3478 devstr = "(unknown model)";
3479 }
3480 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3481 devstr, info->device_name, info->phys_reg_addr,
3482 info->irq_level, info->max_frame_size);
3483
3484 #if SYNCLINK_GENERIC_HDLC
3485 hdlcdev_init(info);
3486 #endif
3487 }
3488
3489 static const struct tty_port_operations slgt_port_ops = {
3490 .carrier_raised = carrier_raised,
3491 .dtr_rts = dtr_rts,
3492 };
3493
3494 /*
3495 * allocate device instance structure, return NULL on failure
3496 */
3497 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3498 {
3499 struct slgt_info *info;
3500
3501 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3502
3503 if (!info) {
3504 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3505 driver_name, adapter_num, port_num));
3506 } else {
3507 tty_port_init(&info->port);
3508 info->port.ops = &slgt_port_ops;
3509 info->magic = MGSL_MAGIC;
3510 INIT_WORK(&info->task, bh_handler);
3511 info->max_frame_size = 4096;
3512 info->base_clock = 14745600;
3513 info->rbuf_fill_level = DMABUFSIZE;
3514 info->port.close_delay = 5*HZ/10;
3515 info->port.closing_wait = 30*HZ;
3516 init_waitqueue_head(&info->status_event_wait_q);
3517 init_waitqueue_head(&info->event_wait_q);
3518 spin_lock_init(&info->netlock);
3519 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3520 info->idle_mode = HDLC_TXIDLE_FLAGS;
3521 info->adapter_num = adapter_num;
3522 info->port_num = port_num;
3523
3524 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3525 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3526
3527 /* Copy configuration info to device instance data */
3528 info->pdev = pdev;
3529 info->irq_level = pdev->irq;
3530 info->phys_reg_addr = pci_resource_start(pdev,0);
3531
3532 info->bus_type = MGSL_BUS_TYPE_PCI;
3533 info->irq_flags = IRQF_SHARED;
3534
3535 info->init_error = -1; /* assume error, set to 0 on successful init */
3536 }
3537
3538 return info;
3539 }
3540
3541 static void device_init(int adapter_num, struct pci_dev *pdev)
3542 {
3543 struct slgt_info *port_array[SLGT_MAX_PORTS];
3544 int i;
3545 int port_count = 1;
3546
3547 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3548 port_count = 2;
3549 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3550 port_count = 4;
3551
3552 /* allocate device instances for all ports */
3553 for (i=0; i < port_count; ++i) {
3554 port_array[i] = alloc_dev(adapter_num, i, pdev);
3555 if (port_array[i] == NULL) {
3556 for (--i; i >= 0; --i)
3557 kfree(port_array[i]);
3558 return;
3559 }
3560 }
3561
3562 /* give copy of port_array to all ports and add to device list */
3563 for (i=0; i < port_count; ++i) {
3564 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3565 add_device(port_array[i]);
3566 port_array[i]->port_count = port_count;
3567 spin_lock_init(&port_array[i]->lock);
3568 }
3569
3570 /* Allocate and claim adapter resources */
3571 if (!claim_resources(port_array[0])) {
3572
3573 alloc_dma_bufs(port_array[0]);
3574
3575 /* copy resource information from first port to others */
3576 for (i = 1; i < port_count; ++i) {
3577 port_array[i]->lock = port_array[0]->lock;
3578 port_array[i]->irq_level = port_array[0]->irq_level;
3579 port_array[i]->reg_addr = port_array[0]->reg_addr;
3580 alloc_dma_bufs(port_array[i]);
3581 }
3582
3583 if (request_irq(port_array[0]->irq_level,
3584 slgt_interrupt,
3585 port_array[0]->irq_flags,
3586 port_array[0]->device_name,
3587 port_array[0]) < 0) {
3588 DBGERR(("%s request_irq failed IRQ=%d\n",
3589 port_array[0]->device_name,
3590 port_array[0]->irq_level));
3591 } else {
3592 port_array[0]->irq_requested = true;
3593 adapter_test(port_array[0]);
3594 for (i=1 ; i < port_count ; i++) {
3595 port_array[i]->init_error = port_array[0]->init_error;
3596 port_array[i]->gpio_present = port_array[0]->gpio_present;
3597 }
3598 }
3599 }
3600
3601 for (i=0; i < port_count; ++i)
3602 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3603 }
3604
3605 static int __devinit init_one(struct pci_dev *dev,
3606 const struct pci_device_id *ent)
3607 {
3608 if (pci_enable_device(dev)) {
3609 printk("error enabling pci device %p\n", dev);
3610 return -EIO;
3611 }
3612 pci_set_master(dev);
3613 device_init(slgt_device_count, dev);
3614 return 0;
3615 }
3616
3617 static void __devexit remove_one(struct pci_dev *dev)
3618 {
3619 }
3620
3621 static const struct tty_operations ops = {
3622 .open = open,
3623 .close = close,
3624 .write = write,
3625 .put_char = put_char,
3626 .flush_chars = flush_chars,
3627 .write_room = write_room,
3628 .chars_in_buffer = chars_in_buffer,
3629 .flush_buffer = flush_buffer,
3630 .ioctl = ioctl,
3631 .compat_ioctl = slgt_compat_ioctl,
3632 .throttle = throttle,
3633 .unthrottle = unthrottle,
3634 .send_xchar = send_xchar,
3635 .break_ctl = set_break,
3636 .wait_until_sent = wait_until_sent,
3637 .set_termios = set_termios,
3638 .stop = tx_hold,
3639 .start = tx_release,
3640 .hangup = hangup,
3641 .tiocmget = tiocmget,
3642 .tiocmset = tiocmset,
3643 .proc_fops = &synclink_gt_proc_fops,
3644 };
3645
3646 static void slgt_cleanup(void)
3647 {
3648 int rc;
3649 struct slgt_info *info;
3650 struct slgt_info *tmp;
3651
3652 printk(KERN_INFO "unload %s\n", driver_name);
3653
3654 if (serial_driver) {
3655 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3656 tty_unregister_device(serial_driver, info->line);
3657 if ((rc = tty_unregister_driver(serial_driver)))
3658 DBGERR(("tty_unregister_driver error=%d\n", rc));
3659 put_tty_driver(serial_driver);
3660 }
3661
3662 /* reset devices */
3663 info = slgt_device_list;
3664 while(info) {
3665 reset_port(info);
3666 info = info->next_device;
3667 }
3668
3669 /* release devices */
3670 info = slgt_device_list;
3671 while(info) {
3672 #if SYNCLINK_GENERIC_HDLC
3673 hdlcdev_exit(info);
3674 #endif
3675 free_dma_bufs(info);
3676 free_tmp_rbuf(info);
3677 if (info->port_num == 0)
3678 release_resources(info);
3679 tmp = info;
3680 info = info->next_device;
3681 kfree(tmp);
3682 }
3683
3684 if (pci_registered)
3685 pci_unregister_driver(&pci_driver);
3686 }
3687
3688 /*
3689 * Driver initialization entry point.
3690 */
3691 static int __init slgt_init(void)
3692 {
3693 int rc;
3694
3695 printk(KERN_INFO "%s\n", driver_name);
3696
3697 serial_driver = alloc_tty_driver(MAX_DEVICES);
3698 if (!serial_driver) {
3699 printk("%s can't allocate tty driver\n", driver_name);
3700 return -ENOMEM;
3701 }
3702
3703 /* Initialize the tty_driver structure */
3704
3705 serial_driver->owner = THIS_MODULE;
3706 serial_driver->driver_name = tty_driver_name;
3707 serial_driver->name = tty_dev_prefix;
3708 serial_driver->major = ttymajor;
3709 serial_driver->minor_start = 64;
3710 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3711 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3712 serial_driver->init_termios = tty_std_termios;
3713 serial_driver->init_termios.c_cflag =
3714 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3715 serial_driver->init_termios.c_ispeed = 9600;
3716 serial_driver->init_termios.c_ospeed = 9600;
3717 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3718 tty_set_operations(serial_driver, &ops);
3719 if ((rc = tty_register_driver(serial_driver)) < 0) {
3720 DBGERR(("%s can't register serial driver\n", driver_name));
3721 put_tty_driver(serial_driver);
3722 serial_driver = NULL;
3723 goto error;
3724 }
3725
3726 printk(KERN_INFO "%s, tty major#%d\n",
3727 driver_name, serial_driver->major);
3728
3729 slgt_device_count = 0;
3730 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3731 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3732 goto error;
3733 }
3734 pci_registered = true;
3735
3736 if (!slgt_device_list)
3737 printk("%s no devices found\n",driver_name);
3738
3739 return 0;
3740
3741 error:
3742 slgt_cleanup();
3743 return rc;
3744 }
3745
3746 static void __exit slgt_exit(void)
3747 {
3748 slgt_cleanup();
3749 }
3750
3751 module_init(slgt_init);
3752 module_exit(slgt_exit);
3753
3754 /*
3755 * register access routines
3756 */
3757
3758 #define CALC_REGADDR() \
3759 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3760 if (addr >= 0x80) \
3761 reg_addr += (info->port_num) * 32;
3762
3763 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3764 {
3765 CALC_REGADDR();
3766 return readb((void __iomem *)reg_addr);
3767 }
3768
3769 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3770 {
3771 CALC_REGADDR();
3772 writeb(value, (void __iomem *)reg_addr);
3773 }
3774
3775 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3776 {
3777 CALC_REGADDR();
3778 return readw((void __iomem *)reg_addr);
3779 }
3780
3781 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3782 {
3783 CALC_REGADDR();
3784 writew(value, (void __iomem *)reg_addr);
3785 }
3786
3787 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3788 {
3789 CALC_REGADDR();
3790 return readl((void __iomem *)reg_addr);
3791 }
3792
3793 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3794 {
3795 CALC_REGADDR();
3796 writel(value, (void __iomem *)reg_addr);
3797 }
3798
3799 static void rdma_reset(struct slgt_info *info)
3800 {
3801 unsigned int i;
3802
3803 /* set reset bit */
3804 wr_reg32(info, RDCSR, BIT1);
3805
3806 /* wait for enable bit cleared */
3807 for(i=0 ; i < 1000 ; i++)
3808 if (!(rd_reg32(info, RDCSR) & BIT0))
3809 break;
3810 }
3811
3812 static void tdma_reset(struct slgt_info *info)
3813 {
3814 unsigned int i;
3815
3816 /* set reset bit */
3817 wr_reg32(info, TDCSR, BIT1);
3818
3819 /* wait for enable bit cleared */
3820 for(i=0 ; i < 1000 ; i++)
3821 if (!(rd_reg32(info, TDCSR) & BIT0))
3822 break;
3823 }
3824
3825 /*
3826 * enable internal loopback
3827 * TxCLK and RxCLK are generated from BRG
3828 * and TxD is looped back to RxD internally.
3829 */
3830 static void enable_loopback(struct slgt_info *info)
3831 {
3832 /* SCR (serial control) BIT2=looopback enable */
3833 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3834
3835 if (info->params.mode != MGSL_MODE_ASYNC) {
3836 /* CCR (clock control)
3837 * 07..05 tx clock source (010 = BRG)
3838 * 04..02 rx clock source (010 = BRG)
3839 * 01 auxclk enable (0 = disable)
3840 * 00 BRG enable (1 = enable)
3841 *
3842 * 0100 1001
3843 */
3844 wr_reg8(info, CCR, 0x49);
3845
3846 /* set speed if available, otherwise use default */
3847 if (info->params.clock_speed)
3848 set_rate(info, info->params.clock_speed);
3849 else
3850 set_rate(info, 3686400);
3851 }
3852 }
3853
3854 /*
3855 * set baud rate generator to specified rate
3856 */
3857 static void set_rate(struct slgt_info *info, u32 rate)
3858 {
3859 unsigned int div;
3860 unsigned int osc = info->base_clock;
3861
3862 /* div = osc/rate - 1
3863 *
3864 * Round div up if osc/rate is not integer to
3865 * force to next slowest rate.
3866 */
3867
3868 if (rate) {
3869 div = osc/rate;
3870 if (!(osc % rate) && div)
3871 div--;
3872 wr_reg16(info, BDR, (unsigned short)div);
3873 }
3874 }
3875
3876 static void rx_stop(struct slgt_info *info)
3877 {
3878 unsigned short val;
3879
3880 /* disable and reset receiver */
3881 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3882 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3883 wr_reg16(info, RCR, val); /* clear reset bit */
3884
3885 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3886
3887 /* clear pending rx interrupts */
3888 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3889
3890 rdma_reset(info);
3891
3892 info->rx_enabled = false;
3893 info->rx_restart = false;
3894 }
3895
3896 static void rx_start(struct slgt_info *info)
3897 {
3898 unsigned short val;
3899
3900 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3901
3902 /* clear pending rx overrun IRQ */
3903 wr_reg16(info, SSR, IRQ_RXOVER);
3904
3905 /* reset and disable receiver */
3906 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3907 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3908 wr_reg16(info, RCR, val); /* clear reset bit */
3909
3910 rdma_reset(info);
3911 reset_rbufs(info);
3912
3913 if (info->rx_pio) {
3914 /* rx request when rx FIFO not empty */
3915 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3916 slgt_irq_on(info, IRQ_RXDATA);
3917 if (info->params.mode == MGSL_MODE_ASYNC) {
3918 /* enable saving of rx status */
3919 wr_reg32(info, RDCSR, BIT6);
3920 }
3921 } else {
3922 /* rx request when rx FIFO half full */
3923 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3924 /* set 1st descriptor address */
3925 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3926
3927 if (info->params.mode != MGSL_MODE_ASYNC) {
3928 /* enable rx DMA and DMA interrupt */
3929 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3930 } else {
3931 /* enable saving of rx status, rx DMA and DMA interrupt */
3932 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3933 }
3934 }
3935
3936 slgt_irq_on(info, IRQ_RXOVER);
3937
3938 /* enable receiver */
3939 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3940
3941 info->rx_restart = false;
3942 info->rx_enabled = true;
3943 }
3944
3945 static void tx_start(struct slgt_info *info)
3946 {
3947 if (!info->tx_enabled) {
3948 wr_reg16(info, TCR,
3949 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3950 info->tx_enabled = true;
3951 }
3952
3953 if (info->tx_count) {
3954 info->drop_rts_on_tx_done = false;
3955
3956 if (info->params.mode != MGSL_MODE_ASYNC) {
3957 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3958 get_signals(info);
3959 if (!(info->signals & SerialSignal_RTS)) {
3960 info->signals |= SerialSignal_RTS;
3961 set_signals(info);
3962 info->drop_rts_on_tx_done = true;
3963 }
3964 }
3965
3966 slgt_irq_off(info, IRQ_TXDATA);
3967 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3968 /* clear tx idle and underrun status bits */
3969 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3970 } else {
3971 slgt_irq_off(info, IRQ_TXDATA);
3972 slgt_irq_on(info, IRQ_TXIDLE);
3973 /* clear tx idle status bit */
3974 wr_reg16(info, SSR, IRQ_TXIDLE);
3975 }
3976 /* set 1st descriptor address and start DMA */
3977 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3978 wr_reg32(info, TDCSR, BIT2 + BIT0);
3979 info->tx_active = true;
3980 }
3981 }
3982
3983 static void tx_stop(struct slgt_info *info)
3984 {
3985 unsigned short val;
3986
3987 del_timer(&info->tx_timer);
3988
3989 tdma_reset(info);
3990
3991 /* reset and disable transmitter */
3992 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3993 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3994
3995 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3996
3997 /* clear tx idle and underrun status bit */
3998 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3999
4000 reset_tbufs(info);
4001
4002 info->tx_enabled = false;
4003 info->tx_active = false;
4004 }
4005
4006 static void reset_port(struct slgt_info *info)
4007 {
4008 if (!info->reg_addr)
4009 return;
4010
4011 tx_stop(info);
4012 rx_stop(info);
4013
4014 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4015 set_signals(info);
4016
4017 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4018 }
4019
4020 static void reset_adapter(struct slgt_info *info)
4021 {
4022 int i;
4023 for (i=0; i < info->port_count; ++i) {
4024 if (info->port_array[i])
4025 reset_port(info->port_array[i]);
4026 }
4027 }
4028
4029 static void async_mode(struct slgt_info *info)
4030 {
4031 unsigned short val;
4032
4033 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4034 tx_stop(info);
4035 rx_stop(info);
4036
4037 /* TCR (tx control)
4038 *
4039 * 15..13 mode, 010=async
4040 * 12..10 encoding, 000=NRZ
4041 * 09 parity enable
4042 * 08 1=odd parity, 0=even parity
4043 * 07 1=RTS driver control
4044 * 06 1=break enable
4045 * 05..04 character length
4046 * 00=5 bits
4047 * 01=6 bits
4048 * 10=7 bits
4049 * 11=8 bits
4050 * 03 0=1 stop bit, 1=2 stop bits
4051 * 02 reset
4052 * 01 enable
4053 * 00 auto-CTS enable
4054 */
4055 val = 0x4000;
4056
4057 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4058 val |= BIT7;
4059
4060 if (info->params.parity != ASYNC_PARITY_NONE) {
4061 val |= BIT9;
4062 if (info->params.parity == ASYNC_PARITY_ODD)
4063 val |= BIT8;
4064 }
4065
4066 switch (info->params.data_bits)
4067 {
4068 case 6: val |= BIT4; break;
4069 case 7: val |= BIT5; break;
4070 case 8: val |= BIT5 + BIT4; break;
4071 }
4072
4073 if (info->params.stop_bits != 1)
4074 val |= BIT3;
4075
4076 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4077 val |= BIT0;
4078
4079 wr_reg16(info, TCR, val);
4080
4081 /* RCR (rx control)
4082 *
4083 * 15..13 mode, 010=async
4084 * 12..10 encoding, 000=NRZ
4085 * 09 parity enable
4086 * 08 1=odd parity, 0=even parity
4087 * 07..06 reserved, must be 0
4088 * 05..04 character length
4089 * 00=5 bits
4090 * 01=6 bits
4091 * 10=7 bits
4092 * 11=8 bits
4093 * 03 reserved, must be zero
4094 * 02 reset
4095 * 01 enable
4096 * 00 auto-DCD enable
4097 */
4098 val = 0x4000;
4099
4100 if (info->params.parity != ASYNC_PARITY_NONE) {
4101 val |= BIT9;
4102 if (info->params.parity == ASYNC_PARITY_ODD)
4103 val |= BIT8;
4104 }
4105
4106 switch (info->params.data_bits)
4107 {
4108 case 6: val |= BIT4; break;
4109 case 7: val |= BIT5; break;
4110 case 8: val |= BIT5 + BIT4; break;
4111 }
4112
4113 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4114 val |= BIT0;
4115
4116 wr_reg16(info, RCR, val);
4117
4118 /* CCR (clock control)
4119 *
4120 * 07..05 011 = tx clock source is BRG/16
4121 * 04..02 010 = rx clock source is BRG
4122 * 01 0 = auxclk disabled
4123 * 00 1 = BRG enabled
4124 *
4125 * 0110 1001
4126 */
4127 wr_reg8(info, CCR, 0x69);
4128
4129 msc_set_vcr(info);
4130
4131 /* SCR (serial control)
4132 *
4133 * 15 1=tx req on FIFO half empty
4134 * 14 1=rx req on FIFO half full
4135 * 13 tx data IRQ enable
4136 * 12 tx idle IRQ enable
4137 * 11 rx break on IRQ enable
4138 * 10 rx data IRQ enable
4139 * 09 rx break off IRQ enable
4140 * 08 overrun IRQ enable
4141 * 07 DSR IRQ enable
4142 * 06 CTS IRQ enable
4143 * 05 DCD IRQ enable
4144 * 04 RI IRQ enable
4145 * 03 0=16x sampling, 1=8x sampling
4146 * 02 1=txd->rxd internal loopback enable
4147 * 01 reserved, must be zero
4148 * 00 1=master IRQ enable
4149 */
4150 val = BIT15 + BIT14 + BIT0;
4151 /* JCR[8] : 1 = x8 async mode feature available */
4152 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4153 ((info->base_clock < (info->params.data_rate * 16)) ||
4154 (info->base_clock % (info->params.data_rate * 16)))) {
4155 /* use 8x sampling */
4156 val |= BIT3;
4157 set_rate(info, info->params.data_rate * 8);
4158 } else {
4159 /* use 16x sampling */
4160 set_rate(info, info->params.data_rate * 16);
4161 }
4162 wr_reg16(info, SCR, val);
4163
4164 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4165
4166 if (info->params.loopback)
4167 enable_loopback(info);
4168 }
4169
4170 static void sync_mode(struct slgt_info *info)
4171 {
4172 unsigned short val;
4173
4174 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4175 tx_stop(info);
4176 rx_stop(info);
4177
4178 /* TCR (tx control)
4179 *
4180 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4181 * 12..10 encoding
4182 * 09 CRC enable
4183 * 08 CRC32
4184 * 07 1=RTS driver control
4185 * 06 preamble enable
4186 * 05..04 preamble length
4187 * 03 share open/close flag
4188 * 02 reset
4189 * 01 enable
4190 * 00 auto-CTS enable
4191 */
4192 val = BIT2;
4193
4194 switch(info->params.mode) {
4195 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4196 case MGSL_MODE_BISYNC: val |= BIT15; break;
4197 case MGSL_MODE_RAW: val |= BIT13; break;
4198 }
4199 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4200 val |= BIT7;
4201
4202 switch(info->params.encoding)
4203 {
4204 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4205 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4206 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4207 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4208 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4209 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4210 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4211 }
4212
4213 switch (info->params.crc_type & HDLC_CRC_MASK)
4214 {
4215 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4216 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4217 }
4218
4219 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4220 val |= BIT6;
4221
4222 switch (info->params.preamble_length)
4223 {
4224 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4225 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4226 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4227 }
4228
4229 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4230 val |= BIT0;
4231
4232 wr_reg16(info, TCR, val);
4233
4234 /* TPR (transmit preamble) */
4235
4236 switch (info->params.preamble)
4237 {
4238 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4239 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4240 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4241 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4242 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4243 default: val = 0x7e; break;
4244 }
4245 wr_reg8(info, TPR, (unsigned char)val);
4246
4247 /* RCR (rx control)
4248 *
4249 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4250 * 12..10 encoding
4251 * 09 CRC enable
4252 * 08 CRC32
4253 * 07..03 reserved, must be 0
4254 * 02 reset
4255 * 01 enable
4256 * 00 auto-DCD enable
4257 */
4258 val = 0;
4259
4260 switch(info->params.mode) {
4261 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4262 case MGSL_MODE_BISYNC: val |= BIT15; break;
4263 case MGSL_MODE_RAW: val |= BIT13; break;
4264 }
4265
4266 switch(info->params.encoding)
4267 {
4268 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4269 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4270 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4271 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4272 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4273 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4274 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4275 }
4276
4277 switch (info->params.crc_type & HDLC_CRC_MASK)
4278 {
4279 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4280 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4281 }
4282
4283 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4284 val |= BIT0;
4285
4286 wr_reg16(info, RCR, val);
4287
4288 /* CCR (clock control)
4289 *
4290 * 07..05 tx clock source
4291 * 04..02 rx clock source
4292 * 01 auxclk enable
4293 * 00 BRG enable
4294 */
4295 val = 0;
4296
4297 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4298 {
4299 // when RxC source is DPLL, BRG generates 16X DPLL
4300 // reference clock, so take TxC from BRG/16 to get
4301 // transmit clock at actual data rate
4302 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4303 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4304 else
4305 val |= BIT6; /* 010, txclk = BRG */
4306 }
4307 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4308 val |= BIT7; /* 100, txclk = DPLL Input */
4309 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4310 val |= BIT5; /* 001, txclk = RXC Input */
4311
4312 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4313 val |= BIT3; /* 010, rxclk = BRG */
4314 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4315 val |= BIT4; /* 100, rxclk = DPLL */
4316 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4317 val |= BIT2; /* 001, rxclk = TXC Input */
4318
4319 if (info->params.clock_speed)
4320 val |= BIT1 + BIT0;
4321
4322 wr_reg8(info, CCR, (unsigned char)val);
4323
4324 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4325 {
4326 // program DPLL mode
4327 switch(info->params.encoding)
4328 {
4329 case HDLC_ENCODING_BIPHASE_MARK:
4330 case HDLC_ENCODING_BIPHASE_SPACE:
4331 val = BIT7; break;
4332 case HDLC_ENCODING_BIPHASE_LEVEL:
4333 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4334 val = BIT7 + BIT6; break;
4335 default: val = BIT6; // NRZ encodings
4336 }
4337 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4338
4339 // DPLL requires a 16X reference clock from BRG
4340 set_rate(info, info->params.clock_speed * 16);
4341 }
4342 else
4343 set_rate(info, info->params.clock_speed);
4344
4345 tx_set_idle(info);
4346
4347 msc_set_vcr(info);
4348
4349 /* SCR (serial control)
4350 *
4351 * 15 1=tx req on FIFO half empty
4352 * 14 1=rx req on FIFO half full
4353 * 13 tx data IRQ enable
4354 * 12 tx idle IRQ enable
4355 * 11 underrun IRQ enable
4356 * 10 rx data IRQ enable
4357 * 09 rx idle IRQ enable
4358 * 08 overrun IRQ enable
4359 * 07 DSR IRQ enable
4360 * 06 CTS IRQ enable
4361 * 05 DCD IRQ enable
4362 * 04 RI IRQ enable
4363 * 03 reserved, must be zero
4364 * 02 1=txd->rxd internal loopback enable
4365 * 01 reserved, must be zero
4366 * 00 1=master IRQ enable
4367 */
4368 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4369
4370 if (info->params.loopback)
4371 enable_loopback(info);
4372 }
4373
4374 /*
4375 * set transmit idle mode
4376 */
4377 static void tx_set_idle(struct slgt_info *info)
4378 {
4379 unsigned char val;
4380 unsigned short tcr;
4381
4382 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4383 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4384 */
4385 tcr = rd_reg16(info, TCR);
4386 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4387 /* disable preamble, set idle size to 16 bits */
4388 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4389 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4390 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4391 } else if (!(tcr & BIT6)) {
4392 /* preamble is disabled, set idle size to 8 bits */
4393 tcr &= ~(BIT5 + BIT4);
4394 }
4395 wr_reg16(info, TCR, tcr);
4396
4397 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4398 /* LSB of custom tx idle specified in tx idle register */
4399 val = (unsigned char)(info->idle_mode & 0xff);
4400 } else {
4401 /* standard 8 bit idle patterns */
4402 switch(info->idle_mode)
4403 {
4404 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4405 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4406 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4407 case HDLC_TXIDLE_ZEROS:
4408 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4409 default: val = 0xff;
4410 }
4411 }
4412
4413 wr_reg8(info, TIR, val);
4414 }
4415
4416 /*
4417 * get state of V24 status (input) signals
4418 */
4419 static void get_signals(struct slgt_info *info)
4420 {
4421 unsigned short status = rd_reg16(info, SSR);
4422
4423 /* clear all serial signals except DTR and RTS */
4424 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4425
4426 if (status & BIT3)
4427 info->signals |= SerialSignal_DSR;
4428 if (status & BIT2)
4429 info->signals |= SerialSignal_CTS;
4430 if (status & BIT1)
4431 info->signals |= SerialSignal_DCD;
4432 if (status & BIT0)
4433 info->signals |= SerialSignal_RI;
4434 }
4435
4436 /*
4437 * set V.24 Control Register based on current configuration
4438 */
4439 static void msc_set_vcr(struct slgt_info *info)
4440 {
4441 unsigned char val = 0;
4442
4443 /* VCR (V.24 control)
4444 *
4445 * 07..04 serial IF select
4446 * 03 DTR
4447 * 02 RTS
4448 * 01 LL
4449 * 00 RL
4450 */
4451
4452 switch(info->if_mode & MGSL_INTERFACE_MASK)
4453 {
4454 case MGSL_INTERFACE_RS232:
4455 val |= BIT5; /* 0010 */
4456 break;
4457 case MGSL_INTERFACE_V35:
4458 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4459 break;
4460 case MGSL_INTERFACE_RS422:
4461 val |= BIT6; /* 0100 */
4462 break;
4463 }
4464
4465 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4466 val |= BIT4;
4467 if (info->signals & SerialSignal_DTR)
4468 val |= BIT3;
4469 if (info->signals & SerialSignal_RTS)
4470 val |= BIT2;
4471 if (info->if_mode & MGSL_INTERFACE_LL)
4472 val |= BIT1;
4473 if (info->if_mode & MGSL_INTERFACE_RL)
4474 val |= BIT0;
4475 wr_reg8(info, VCR, val);
4476 }
4477
4478 /*
4479 * set state of V24 control (output) signals
4480 */
4481 static void set_signals(struct slgt_info *info)
4482 {
4483 unsigned char val = rd_reg8(info, VCR);
4484 if (info->signals & SerialSignal_DTR)
4485 val |= BIT3;
4486 else
4487 val &= ~BIT3;
4488 if (info->signals & SerialSignal_RTS)
4489 val |= BIT2;
4490 else
4491 val &= ~BIT2;
4492 wr_reg8(info, VCR, val);
4493 }
4494
4495 /*
4496 * free range of receive DMA buffers (i to last)
4497 */
4498 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4499 {
4500 int done = 0;
4501
4502 while(!done) {
4503 /* reset current buffer for reuse */
4504 info->rbufs[i].status = 0;
4505 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4506 if (i == last)
4507 done = 1;
4508 if (++i == info->rbuf_count)
4509 i = 0;
4510 }
4511 info->rbuf_current = i;
4512 }
4513
4514 /*
4515 * mark all receive DMA buffers as free
4516 */
4517 static void reset_rbufs(struct slgt_info *info)
4518 {
4519 free_rbufs(info, 0, info->rbuf_count - 1);
4520 info->rbuf_fill_index = 0;
4521 info->rbuf_fill_count = 0;
4522 }
4523
4524 /*
4525 * pass receive HDLC frame to upper layer
4526 *
4527 * return true if frame available, otherwise false
4528 */
4529 static bool rx_get_frame(struct slgt_info *info)
4530 {
4531 unsigned int start, end;
4532 unsigned short status;
4533 unsigned int framesize = 0;
4534 unsigned long flags;
4535 struct tty_struct *tty = info->port.tty;
4536 unsigned char addr_field = 0xff;
4537 unsigned int crc_size = 0;
4538
4539 switch (info->params.crc_type & HDLC_CRC_MASK) {
4540 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4541 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4542 }
4543
4544 check_again:
4545
4546 framesize = 0;
4547 addr_field = 0xff;
4548 start = end = info->rbuf_current;
4549
4550 for (;;) {
4551 if (!desc_complete(info->rbufs[end]))
4552 goto cleanup;
4553
4554 if (framesize == 0 && info->params.addr_filter != 0xff)
4555 addr_field = info->rbufs[end].buf[0];
4556
4557 framesize += desc_count(info->rbufs[end]);
4558
4559 if (desc_eof(info->rbufs[end]))
4560 break;
4561
4562 if (++end == info->rbuf_count)
4563 end = 0;
4564
4565 if (end == info->rbuf_current) {
4566 if (info->rx_enabled){
4567 spin_lock_irqsave(&info->lock,flags);
4568 rx_start(info);
4569 spin_unlock_irqrestore(&info->lock,flags);
4570 }
4571 goto cleanup;
4572 }
4573 }
4574
4575 /* status
4576 *
4577 * 15 buffer complete
4578 * 14..06 reserved
4579 * 05..04 residue
4580 * 02 eof (end of frame)
4581 * 01 CRC error
4582 * 00 abort
4583 */
4584 status = desc_status(info->rbufs[end]);
4585
4586 /* ignore CRC bit if not using CRC (bit is undefined) */
4587 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4588 status &= ~BIT1;
4589
4590 if (framesize == 0 ||
4591 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4592 free_rbufs(info, start, end);
4593 goto check_again;
4594 }
4595
4596 if (framesize < (2 + crc_size) || status & BIT0) {
4597 info->icount.rxshort++;
4598 framesize = 0;
4599 } else if (status & BIT1) {
4600 info->icount.rxcrc++;
4601 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4602 framesize = 0;
4603 }
4604
4605 #if SYNCLINK_GENERIC_HDLC
4606 if (framesize == 0) {
4607 info->netdev->stats.rx_errors++;
4608 info->netdev->stats.rx_frame_errors++;
4609 }
4610 #endif
4611
4612 DBGBH(("%s rx frame status=%04X size=%d\n",
4613 info->device_name, status, framesize));
4614 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4615
4616 if (framesize) {
4617 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4618 framesize -= crc_size;
4619 crc_size = 0;
4620 }
4621
4622 if (framesize > info->max_frame_size + crc_size)
4623 info->icount.rxlong++;
4624 else {
4625 /* copy dma buffer(s) to contiguous temp buffer */
4626 int copy_count = framesize;
4627 int i = start;
4628 unsigned char *p = info->tmp_rbuf;
4629 info->tmp_rbuf_count = framesize;
4630
4631 info->icount.rxok++;
4632
4633 while(copy_count) {
4634 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4635 memcpy(p, info->rbufs[i].buf, partial_count);
4636 p += partial_count;
4637 copy_count -= partial_count;
4638 if (++i == info->rbuf_count)
4639 i = 0;
4640 }
4641
4642 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4643 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4644 framesize++;
4645 }
4646
4647 #if SYNCLINK_GENERIC_HDLC
4648 if (info->netcount)
4649 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4650 else
4651 #endif
4652 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4653 }
4654 }
4655 free_rbufs(info, start, end);
4656 return true;
4657
4658 cleanup:
4659 return false;
4660 }
4661
4662 /*
4663 * pass receive buffer (RAW synchronous mode) to tty layer
4664 * return true if buffer available, otherwise false
4665 */
4666 static bool rx_get_buf(struct slgt_info *info)
4667 {
4668 unsigned int i = info->rbuf_current;
4669 unsigned int count;
4670
4671 if (!desc_complete(info->rbufs[i]))
4672 return false;
4673 count = desc_count(info->rbufs[i]);
4674 switch(info->params.mode) {
4675 case MGSL_MODE_MONOSYNC:
4676 case MGSL_MODE_BISYNC:
4677 /* ignore residue in byte synchronous modes */
4678 if (desc_residue(info->rbufs[i]))
4679 count--;
4680 break;
4681 }
4682 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4683 DBGINFO(("rx_get_buf size=%d\n", count));
4684 if (count)
4685 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4686 info->flag_buf, count);
4687 free_rbufs(info, i, i);
4688 return true;
4689 }
4690
4691 static void reset_tbufs(struct slgt_info *info)
4692 {
4693 unsigned int i;
4694 info->tbuf_current = 0;
4695 for (i=0 ; i < info->tbuf_count ; i++) {
4696 info->tbufs[i].status = 0;
4697 info->tbufs[i].count = 0;
4698 }
4699 }
4700
4701 /*
4702 * return number of free transmit DMA buffers
4703 */
4704 static unsigned int free_tbuf_count(struct slgt_info *info)
4705 {
4706 unsigned int count = 0;
4707 unsigned int i = info->tbuf_current;
4708
4709 do
4710 {
4711 if (desc_count(info->tbufs[i]))
4712 break; /* buffer in use */
4713 ++count;
4714 if (++i == info->tbuf_count)
4715 i=0;
4716 } while (i != info->tbuf_current);
4717
4718 /* if tx DMA active, last zero count buffer is in use */
4719 if (count && (rd_reg32(info, TDCSR) & BIT0))
4720 --count;
4721
4722 return count;
4723 }
4724
4725 /*
4726 * return number of bytes in unsent transmit DMA buffers
4727 * and the serial controller tx FIFO
4728 */
4729 static unsigned int tbuf_bytes(struct slgt_info *info)
4730 {
4731 unsigned int total_count = 0;
4732 unsigned int i = info->tbuf_current;
4733 unsigned int reg_value;
4734 unsigned int count;
4735 unsigned int active_buf_count = 0;
4736
4737 /*
4738 * Add descriptor counts for all tx DMA buffers.
4739 * If count is zero (cleared by DMA controller after read),
4740 * the buffer is complete or is actively being read from.
4741 *
4742 * Record buf_count of last buffer with zero count starting
4743 * from current ring position. buf_count is mirror
4744 * copy of count and is not cleared by serial controller.
4745 * If DMA controller is active, that buffer is actively
4746 * being read so add to total.
4747 */
4748 do {
4749 count = desc_count(info->tbufs[i]);
4750 if (count)
4751 total_count += count;
4752 else if (!total_count)
4753 active_buf_count = info->tbufs[i].buf_count;
4754 if (++i == info->tbuf_count)
4755 i = 0;
4756 } while (i != info->tbuf_current);
4757
4758 /* read tx DMA status register */
4759 reg_value = rd_reg32(info, TDCSR);
4760
4761 /* if tx DMA active, last zero count buffer is in use */
4762 if (reg_value & BIT0)
4763 total_count += active_buf_count;
4764
4765 /* add tx FIFO count = reg_value[15..8] */
4766 total_count += (reg_value >> 8) & 0xff;
4767
4768 /* if transmitter active add one byte for shift register */
4769 if (info->tx_active)
4770 total_count++;
4771
4772 return total_count;
4773 }
4774
4775 /*
4776 * load transmit DMA buffer(s) with data
4777 */
4778 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4779 {
4780 unsigned short count;
4781 unsigned int i;
4782 struct slgt_desc *d;
4783
4784 if (size == 0)
4785 return;
4786
4787 DBGDATA(info, buf, size, "tx");
4788
4789 info->tbuf_start = i = info->tbuf_current;
4790
4791 while (size) {
4792 d = &info->tbufs[i];
4793 if (++i == info->tbuf_count)
4794 i = 0;
4795
4796 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4797 memcpy(d->buf, buf, count);
4798
4799 size -= count;
4800 buf += count;
4801
4802 /*
4803 * set EOF bit for last buffer of HDLC frame or
4804 * for every buffer in raw mode
4805 */
4806 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4807 info->params.mode == MGSL_MODE_RAW)
4808 set_desc_eof(*d, 1);
4809 else
4810 set_desc_eof(*d, 0);
4811
4812 set_desc_count(*d, count);
4813 d->buf_count = count;
4814 }
4815
4816 info->tbuf_current = i;
4817 }
4818
4819 static int register_test(struct slgt_info *info)
4820 {
4821 static unsigned short patterns[] =
4822 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4823 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4824 unsigned int i;
4825 int rc = 0;
4826
4827 for (i=0 ; i < count ; i++) {
4828 wr_reg16(info, TIR, patterns[i]);
4829 wr_reg16(info, BDR, patterns[(i+1)%count]);
4830 if ((rd_reg16(info, TIR) != patterns[i]) ||
4831 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4832 rc = -ENODEV;
4833 break;
4834 }
4835 }
4836 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4837 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4838 return rc;
4839 }
4840
4841 static int irq_test(struct slgt_info *info)
4842 {
4843 unsigned long timeout;
4844 unsigned long flags;
4845 struct tty_struct *oldtty = info->port.tty;
4846 u32 speed = info->params.data_rate;
4847
4848 info->params.data_rate = 921600;
4849 info->port.tty = NULL;
4850
4851 spin_lock_irqsave(&info->lock, flags);
4852 async_mode(info);
4853 slgt_irq_on(info, IRQ_TXIDLE);
4854
4855 /* enable transmitter */
4856 wr_reg16(info, TCR,
4857 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4858
4859 /* write one byte and wait for tx idle */
4860 wr_reg16(info, TDR, 0);
4861
4862 /* assume failure */
4863 info->init_error = DiagStatus_IrqFailure;
4864 info->irq_occurred = false;
4865
4866 spin_unlock_irqrestore(&info->lock, flags);
4867
4868 timeout=100;
4869 while(timeout-- && !info->irq_occurred)
4870 msleep_interruptible(10);
4871
4872 spin_lock_irqsave(&info->lock,flags);
4873 reset_port(info);
4874 spin_unlock_irqrestore(&info->lock,flags);
4875
4876 info->params.data_rate = speed;
4877 info->port.tty = oldtty;
4878
4879 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4880 return info->irq_occurred ? 0 : -ENODEV;
4881 }
4882
4883 static int loopback_test_rx(struct slgt_info *info)
4884 {
4885 unsigned char *src, *dest;
4886 int count;
4887
4888 if (desc_complete(info->rbufs[0])) {
4889 count = desc_count(info->rbufs[0]);
4890 src = info->rbufs[0].buf;
4891 dest = info->tmp_rbuf;
4892
4893 for( ; count ; count-=2, src+=2) {
4894 /* src=data byte (src+1)=status byte */
4895 if (!(*(src+1) & (BIT9 + BIT8))) {
4896 *dest = *src;
4897 dest++;
4898 info->tmp_rbuf_count++;
4899 }
4900 }
4901 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4902 return 1;
4903 }
4904 return 0;
4905 }
4906
4907 static int loopback_test(struct slgt_info *info)
4908 {
4909 #define TESTFRAMESIZE 20
4910
4911 unsigned long timeout;
4912 u16 count = TESTFRAMESIZE;
4913 unsigned char buf[TESTFRAMESIZE];
4914 int rc = -ENODEV;
4915 unsigned long flags;
4916
4917 struct tty_struct *oldtty = info->port.tty;
4918 MGSL_PARAMS params;
4919
4920 memcpy(&params, &info->params, sizeof(params));
4921
4922 info->params.mode = MGSL_MODE_ASYNC;
4923 info->params.data_rate = 921600;
4924 info->params.loopback = 1;
4925 info->port.tty = NULL;
4926
4927 /* build and send transmit frame */
4928 for (count = 0; count < TESTFRAMESIZE; ++count)
4929 buf[count] = (unsigned char)count;
4930
4931 info->tmp_rbuf_count = 0;
4932 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4933
4934 /* program hardware for HDLC and enabled receiver */
4935 spin_lock_irqsave(&info->lock,flags);
4936 async_mode(info);
4937 rx_start(info);
4938 info->tx_count = count;
4939 tx_load(info, buf, count);
4940 tx_start(info);
4941 spin_unlock_irqrestore(&info->lock, flags);
4942
4943 /* wait for receive complete */
4944 for (timeout = 100; timeout; --timeout) {
4945 msleep_interruptible(10);
4946 if (loopback_test_rx(info)) {
4947 rc = 0;
4948 break;
4949 }
4950 }
4951
4952 /* verify received frame length and contents */
4953 if (!rc && (info->tmp_rbuf_count != count ||
4954 memcmp(buf, info->tmp_rbuf, count))) {
4955 rc = -ENODEV;
4956 }
4957
4958 spin_lock_irqsave(&info->lock,flags);
4959 reset_adapter(info);
4960 spin_unlock_irqrestore(&info->lock,flags);
4961
4962 memcpy(&info->params, &params, sizeof(info->params));
4963 info->port.tty = oldtty;
4964
4965 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4966 return rc;
4967 }
4968
4969 static int adapter_test(struct slgt_info *info)
4970 {
4971 DBGINFO(("testing %s\n", info->device_name));
4972 if (register_test(info) < 0) {
4973 printk("register test failure %s addr=%08X\n",
4974 info->device_name, info->phys_reg_addr);
4975 } else if (irq_test(info) < 0) {
4976 printk("IRQ test failure %s IRQ=%d\n",
4977 info->device_name, info->irq_level);
4978 } else if (loopback_test(info) < 0) {
4979 printk("loopback test failure %s\n", info->device_name);
4980 }
4981 return info->init_error;
4982 }
4983
4984 /*
4985 * transmit timeout handler
4986 */
4987 static void tx_timeout(unsigned long context)
4988 {
4989 struct slgt_info *info = (struct slgt_info*)context;
4990 unsigned long flags;
4991
4992 DBGINFO(("%s tx_timeout\n", info->device_name));
4993 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4994 info->icount.txtimeout++;
4995 }
4996 spin_lock_irqsave(&info->lock,flags);
4997 tx_stop(info);
4998 spin_unlock_irqrestore(&info->lock,flags);
4999
5000 #if SYNCLINK_GENERIC_HDLC
5001 if (info->netcount)
5002 hdlcdev_tx_done(info);
5003 else
5004 #endif
5005 bh_transmit(info);
5006 }
5007
5008 /*
5009 * receive buffer polling timer
5010 */
5011 static void rx_timeout(unsigned long context)
5012 {
5013 struct slgt_info *info = (struct slgt_info*)context;
5014 unsigned long flags;
5015
5016 DBGINFO(("%s rx_timeout\n", info->device_name));
5017 spin_lock_irqsave(&info->lock, flags);
5018 info->pending_bh |= BH_RECEIVE;
5019 spin_unlock_irqrestore(&info->lock, flags);
5020 bh_handler(&info->task);
5021 }
5022
Support for the Chinese Samsung S3C2440 based development boards