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drm: handle depth & bpp changes correctly
[linux-2.6/mini2440.git] / drivers / gpu / drm / i915 / intel_display.c
blob4372acff5a016327d336e452e76be2f41bd27a97
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/i2c.h>
28 #include "drmP.h"
29 #include "intel_drv.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32
33 #include "drm_crtc_helper.h"
34
35 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
36
37 typedef struct {
38 /* given values */
39 int n;
40 int m1, m2;
41 int p1, p2;
42 /* derived values */
43 int dot;
44 int vco;
45 int m;
46 int p;
47 } intel_clock_t;
48
49 typedef struct {
50 int min, max;
51 } intel_range_t;
52
53 typedef struct {
54 int dot_limit;
55 int p2_slow, p2_fast;
56 } intel_p2_t;
57
58 #define INTEL_P2_NUM 2
59
60 typedef struct {
61 intel_range_t dot, vco, n, m, m1, m2, p, p1;
62 intel_p2_t p2;
63 } intel_limit_t;
64
65 #define I8XX_DOT_MIN 25000
66 #define I8XX_DOT_MAX 350000
67 #define I8XX_VCO_MIN 930000
68 #define I8XX_VCO_MAX 1400000
69 #define I8XX_N_MIN 3
70 #define I8XX_N_MAX 16
71 #define I8XX_M_MIN 96
72 #define I8XX_M_MAX 140
73 #define I8XX_M1_MIN 18
74 #define I8XX_M1_MAX 26
75 #define I8XX_M2_MIN 6
76 #define I8XX_M2_MAX 16
77 #define I8XX_P_MIN 4
78 #define I8XX_P_MAX 128
79 #define I8XX_P1_MIN 2
80 #define I8XX_P1_MAX 33
81 #define I8XX_P1_LVDS_MIN 1
82 #define I8XX_P1_LVDS_MAX 6
83 #define I8XX_P2_SLOW 4
84 #define I8XX_P2_FAST 2
85 #define I8XX_P2_LVDS_SLOW 14
86 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
87 #define I8XX_P2_SLOW_LIMIT 165000
88
89 #define I9XX_DOT_MIN 20000
90 #define I9XX_DOT_MAX 400000
91 #define I9XX_VCO_MIN 1400000
92 #define I9XX_VCO_MAX 2800000
93 #define I9XX_N_MIN 3
94 #define I9XX_N_MAX 8
95 #define I9XX_M_MIN 70
96 #define I9XX_M_MAX 120
97 #define I9XX_M1_MIN 10
98 #define I9XX_M1_MAX 20
99 #define I9XX_M2_MIN 5
100 #define I9XX_M2_MAX 9
101 #define I9XX_P_SDVO_DAC_MIN 5
102 #define I9XX_P_SDVO_DAC_MAX 80
103 #define I9XX_P_LVDS_MIN 7
104 #define I9XX_P_LVDS_MAX 98
105 #define I9XX_P1_MIN 1
106 #define I9XX_P1_MAX 8
107 #define I9XX_P2_SDVO_DAC_SLOW 10
108 #define I9XX_P2_SDVO_DAC_FAST 5
109 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
110 #define I9XX_P2_LVDS_SLOW 14
111 #define I9XX_P2_LVDS_FAST 7
112 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
113
114 #define INTEL_LIMIT_I8XX_DVO_DAC 0
115 #define INTEL_LIMIT_I8XX_LVDS 1
116 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
117 #define INTEL_LIMIT_I9XX_LVDS 3
118
119 static const intel_limit_t intel_limits[] = {
120 { /* INTEL_LIMIT_I8XX_DVO_DAC */
121 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
122 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
123 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
124 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
125 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
126 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
127 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
128 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
129 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
130 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
131 },
132 { /* INTEL_LIMIT_I8XX_LVDS */
133 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
134 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
135 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
136 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
137 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
138 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
139 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
140 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
141 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
142 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
143 },
144 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
145 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
146 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
147 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
148 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
149 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
150 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
151 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
152 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
153 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
154 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
155 },
156 { /* INTEL_LIMIT_I9XX_LVDS */
157 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
158 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
159 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
160 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
161 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
162 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
163 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
164 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
165 /* The single-channel range is 25-112Mhz, and dual-channel
166 * is 80-224Mhz. Prefer single channel as much as possible.
167 */
168 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
169 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
170 },
171 };
172
173 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
174 {
175 struct drm_device *dev = crtc->dev;
176 const intel_limit_t *limit;
177
178 if (IS_I9XX(dev)) {
179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
180 limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
181 else
182 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
183 } else {
184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
185 limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
186 else
187 limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
188 }
189 return limit;
190 }
191
192 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
193
194 static void i8xx_clock(int refclk, intel_clock_t *clock)
195 {
196 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
197 clock->p = clock->p1 * clock->p2;
198 clock->vco = refclk * clock->m / (clock->n + 2);
199 clock->dot = clock->vco / clock->p;
200 }
201
202 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
203
204 static void i9xx_clock(int refclk, intel_clock_t *clock)
205 {
206 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
207 clock->p = clock->p1 * clock->p2;
208 clock->vco = refclk * clock->m / (clock->n + 2);
209 clock->dot = clock->vco / clock->p;
210 }
211
212 static void intel_clock(struct drm_device *dev, int refclk,
213 intel_clock_t *clock)
214 {
215 if (IS_I9XX(dev))
216 i9xx_clock (refclk, clock);
217 else
218 i8xx_clock (refclk, clock);
219 }
220
221 /**
222 * Returns whether any output on the specified pipe is of the specified type
223 */
224 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
225 {
226 struct drm_device *dev = crtc->dev;
227 struct drm_mode_config *mode_config = &dev->mode_config;
228 struct drm_connector *l_entry;
229
230 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
231 if (l_entry->encoder &&
232 l_entry->encoder->crtc == crtc) {
233 struct intel_output *intel_output = to_intel_output(l_entry);
234 if (intel_output->type == type)
235 return true;
236 }
237 }
238 return false;
239 }
240
241 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
242 /**
243 * Returns whether the given set of divisors are valid for a given refclk with
244 * the given connectors.
245 */
246
247 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
248 {
249 const intel_limit_t *limit = intel_limit (crtc);
250
251 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
252 INTELPllInvalid ("p1 out of range\n");
253 if (clock->p < limit->p.min || limit->p.max < clock->p)
254 INTELPllInvalid ("p out of range\n");
255 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
256 INTELPllInvalid ("m2 out of range\n");
257 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
258 INTELPllInvalid ("m1 out of range\n");
259 if (clock->m1 <= clock->m2)
260 INTELPllInvalid ("m1 <= m2\n");
261 if (clock->m < limit->m.min || limit->m.max < clock->m)
262 INTELPllInvalid ("m out of range\n");
263 if (clock->n < limit->n.min || limit->n.max < clock->n)
264 INTELPllInvalid ("n out of range\n");
265 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
266 INTELPllInvalid ("vco out of range\n");
267 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
268 * connector, etc., rather than just a single range.
269 */
270 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
271 INTELPllInvalid ("dot out of range\n");
272
273 return true;
274 }
275
276 /**
277 * Returns a set of divisors for the desired target clock with the given
278 * refclk, or FALSE. The returned values represent the clock equation:
279 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
280 */
281 static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
282 int refclk, intel_clock_t *best_clock)
283 {
284 struct drm_device *dev = crtc->dev;
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 intel_clock_t clock;
287 const intel_limit_t *limit = intel_limit(crtc);
288 int err = target;
289
290 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
291 (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
292 /*
293 * For LVDS, if the panel is on, just rely on its current
294 * settings for dual-channel. We haven't figured out how to
295 * reliably set up different single/dual channel state, if we
296 * even can.
297 */
298 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
299 LVDS_CLKB_POWER_UP)
300 clock.p2 = limit->p2.p2_fast;
301 else
302 clock.p2 = limit->p2.p2_slow;
303 } else {
304 if (target < limit->p2.dot_limit)
305 clock.p2 = limit->p2.p2_slow;
306 else
307 clock.p2 = limit->p2.p2_fast;
308 }
309
310 memset (best_clock, 0, sizeof (*best_clock));
311
312 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
313 for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
314 clock.m2 <= limit->m2.max; clock.m2++) {
315 for (clock.n = limit->n.min; clock.n <= limit->n.max;
316 clock.n++) {
317 for (clock.p1 = limit->p1.min;
318 clock.p1 <= limit->p1.max; clock.p1++) {
319 int this_err;
320
321 intel_clock(dev, refclk, &clock);
322
323 if (!intel_PLL_is_valid(crtc, &clock))
324 continue;
325
326 this_err = abs(clock.dot - target);
327 if (this_err < err) {
328 *best_clock = clock;
329 err = this_err;
330 }
331 }
332 }
333 }
334 }
335
336 return (err != target);
337 }
338
339 void
340 intel_wait_for_vblank(struct drm_device *dev)
341 {
342 /* Wait for 20ms, i.e. one cycle at 50hz. */
343 udelay(20000);
344 }
345
346 static void
347 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
348 struct drm_framebuffer *old_fb)
349 {
350 struct drm_device *dev = crtc->dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
352 struct drm_i915_master_private *master_priv;
353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
354 struct intel_framebuffer *intel_fb;
355 struct drm_i915_gem_object *obj_priv;
356 struct drm_gem_object *obj;
357 int pipe = intel_crtc->pipe;
358 unsigned long Start, Offset;
359 int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
360 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
361 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
362 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
363 u32 dspcntr, alignment;
364
365 /* no fb bound */
366 if (!crtc->fb) {
367 DRM_DEBUG("No FB bound\n");
368 return;
369 }
370
371 intel_fb = to_intel_framebuffer(crtc->fb);
372 obj = intel_fb->obj;
373 obj_priv = obj->driver_private;
374
375 switch (obj_priv->tiling_mode) {
376 case I915_TILING_NONE:
377 alignment = 64 * 1024;
378 break;
379 case I915_TILING_X:
380 if (IS_I9XX(dev))
381 alignment = 1024 * 1024;
382 else
383 alignment = 512 * 1024;
384 break;
385 case I915_TILING_Y:
386 /* FIXME: Is this true? */
387 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
388 return;
389 default:
390 BUG();
391 }
392
393 if (i915_gem_object_pin(intel_fb->obj, alignment))
394 return;
395
396 i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
397
398 Start = obj_priv->gtt_offset;
399 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
400
401 I915_WRITE(dspstride, crtc->fb->pitch);
402
403 dspcntr = I915_READ(dspcntr_reg);
404 /* Mask out pixel format bits in case we change it */
405 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
406 switch (crtc->fb->bits_per_pixel) {
407 case 8:
408 dspcntr |= DISPPLANE_8BPP;
409 break;
410 case 16:
411 if (crtc->fb->depth == 15)
412 dspcntr |= DISPPLANE_15_16BPP;
413 else
414 dspcntr |= DISPPLANE_16BPP;
415 break;
416 case 24:
417 case 32:
418 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
419 break;
420 default:
421 DRM_ERROR("Unknown color depth\n");
422 return;
423 }
424 I915_WRITE(dspcntr_reg, dspcntr);
425
426 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
427 if (IS_I965G(dev)) {
428 I915_WRITE(dspbase, Offset);
429 I915_READ(dspbase);
430 I915_WRITE(dspsurf, Start);
431 I915_READ(dspsurf);
432 } else {
433 I915_WRITE(dspbase, Start + Offset);
434 I915_READ(dspbase);
435 }
436
437 intel_wait_for_vblank(dev);
438
439 if (old_fb) {
440 intel_fb = to_intel_framebuffer(old_fb);
441 i915_gem_object_unpin(intel_fb->obj);
442 }
443
444 if (!dev->primary->master)
445 return;
446
447 master_priv = dev->primary->master->driver_priv;
448 if (!master_priv->sarea_priv)
449 return;
450
451 switch (pipe) {
452 case 0:
453 master_priv->sarea_priv->pipeA_x = x;
454 master_priv->sarea_priv->pipeA_y = y;
455 break;
456 case 1:
457 master_priv->sarea_priv->pipeB_x = x;
458 master_priv->sarea_priv->pipeB_y = y;
459 break;
460 default:
461 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
462 break;
463 }
464 }
465
466
467
468 /**
469 * Sets the power management mode of the pipe and plane.
470 *
471 * This code should probably grow support for turning the cursor off and back
472 * on appropriately at the same time as we're turning the pipe off/on.
473 */
474 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
475 {
476 struct drm_device *dev = crtc->dev;
477 struct drm_i915_master_private *master_priv;
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
480 int pipe = intel_crtc->pipe;
481 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
482 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
483 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
484 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
485 u32 temp;
486 bool enabled;
487
488 /* XXX: When our outputs are all unaware of DPMS modes other than off
489 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
490 */
491 switch (mode) {
492 case DRM_MODE_DPMS_ON:
493 case DRM_MODE_DPMS_STANDBY:
494 case DRM_MODE_DPMS_SUSPEND:
495 /* Enable the DPLL */
496 temp = I915_READ(dpll_reg);
497 if ((temp & DPLL_VCO_ENABLE) == 0) {
498 I915_WRITE(dpll_reg, temp);
499 I915_READ(dpll_reg);
500 /* Wait for the clocks to stabilize. */
501 udelay(150);
502 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
503 I915_READ(dpll_reg);
504 /* Wait for the clocks to stabilize. */
505 udelay(150);
506 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
507 I915_READ(dpll_reg);
508 /* Wait for the clocks to stabilize. */
509 udelay(150);
510 }
511
512 /* Enable the pipe */
513 temp = I915_READ(pipeconf_reg);
514 if ((temp & PIPEACONF_ENABLE) == 0)
515 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
516
517 /* Enable the plane */
518 temp = I915_READ(dspcntr_reg);
519 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
520 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
521 /* Flush the plane changes */
522 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
523 }
524
525 intel_crtc_load_lut(crtc);
526
527 /* Give the overlay scaler a chance to enable if it's on this pipe */
528 //intel_crtc_dpms_video(crtc, true); TODO
529 break;
530 case DRM_MODE_DPMS_OFF:
531 /* Give the overlay scaler a chance to disable if it's on this pipe */
532 //intel_crtc_dpms_video(crtc, FALSE); TODO
533
534 /* Disable the VGA plane that we never use */
535 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
536
537 /* Disable display plane */
538 temp = I915_READ(dspcntr_reg);
539 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
540 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
541 /* Flush the plane changes */
542 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
543 I915_READ(dspbase_reg);
544 }
545
546 if (!IS_I9XX(dev)) {
547 /* Wait for vblank for the disable to take effect */
548 intel_wait_for_vblank(dev);
549 }
550
551 /* Next, disable display pipes */
552 temp = I915_READ(pipeconf_reg);
553 if ((temp & PIPEACONF_ENABLE) != 0) {
554 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
555 I915_READ(pipeconf_reg);
556 }
557
558 /* Wait for vblank for the disable to take effect. */
559 intel_wait_for_vblank(dev);
560
561 temp = I915_READ(dpll_reg);
562 if ((temp & DPLL_VCO_ENABLE) != 0) {
563 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
564 I915_READ(dpll_reg);
565 }
566
567 /* Wait for the clocks to turn off. */
568 udelay(150);
569 break;
570 }
571
572 if (!dev->primary->master)
573 return;
574
575 master_priv = dev->primary->master->driver_priv;
576 if (!master_priv->sarea_priv)
577 return;
578
579 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
580
581 switch (pipe) {
582 case 0:
583 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
584 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
585 break;
586 case 1:
587 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
588 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
589 break;
590 default:
591 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
592 break;
593 }
594
595 intel_crtc->dpms_mode = mode;
596 }
597
598 static void intel_crtc_prepare (struct drm_crtc *crtc)
599 {
600 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
601 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
602 }
603
604 static void intel_crtc_commit (struct drm_crtc *crtc)
605 {
606 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
607 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
608 }
609
610 void intel_encoder_prepare (struct drm_encoder *encoder)
611 {
612 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
613 /* lvds has its own version of prepare see intel_lvds_prepare */
614 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
615 }
616
617 void intel_encoder_commit (struct drm_encoder *encoder)
618 {
619 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
620 /* lvds has its own version of commit see intel_lvds_commit */
621 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
622 }
623
624 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
625 struct drm_display_mode *mode,
626 struct drm_display_mode *adjusted_mode)
627 {
628 return true;
629 }
630
631
632 /** Returns the core display clock speed for i830 - i945 */
633 static int intel_get_core_clock_speed(struct drm_device *dev)
634 {
635
636 /* Core clock values taken from the published datasheets.
637 * The 830 may go up to 166 Mhz, which we should check.
638 */
639 if (IS_I945G(dev))
640 return 400000;
641 else if (IS_I915G(dev))
642 return 333000;
643 else if (IS_I945GM(dev) || IS_845G(dev))
644 return 200000;
645 else if (IS_I915GM(dev)) {
646 u16 gcfgc = 0;
647
648 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
649
650 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
651 return 133000;
652 else {
653 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
654 case GC_DISPLAY_CLOCK_333_MHZ:
655 return 333000;
656 default:
657 case GC_DISPLAY_CLOCK_190_200_MHZ:
658 return 190000;
659 }
660 }
661 } else if (IS_I865G(dev))
662 return 266000;
663 else if (IS_I855(dev)) {
664 u16 hpllcc = 0;
665 /* Assume that the hardware is in the high speed state. This
666 * should be the default.
667 */
668 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
669 case GC_CLOCK_133_200:
670 case GC_CLOCK_100_200:
671 return 200000;
672 case GC_CLOCK_166_250:
673 return 250000;
674 case GC_CLOCK_100_133:
675 return 133000;
676 }
677 } else /* 852, 830 */
678 return 133000;
679
680 return 0; /* Silence gcc warning */
681 }
682
683
684 /**
685 * Return the pipe currently connected to the panel fitter,
686 * or -1 if the panel fitter is not present or not in use
687 */
688 static int intel_panel_fitter_pipe (struct drm_device *dev)
689 {
690 struct drm_i915_private *dev_priv = dev->dev_private;
691 u32 pfit_control;
692
693 /* i830 doesn't have a panel fitter */
694 if (IS_I830(dev))
695 return -1;
696
697 pfit_control = I915_READ(PFIT_CONTROL);
698
699 /* See if the panel fitter is in use */
700 if ((pfit_control & PFIT_ENABLE) == 0)
701 return -1;
702
703 /* 965 can place panel fitter on either pipe */
704 if (IS_I965G(dev))
705 return (pfit_control >> 29) & 0x3;
706
707 /* older chips can only use pipe 1 */
708 return 1;
709 }
710
711 static void intel_crtc_mode_set(struct drm_crtc *crtc,
712 struct drm_display_mode *mode,
713 struct drm_display_mode *adjusted_mode,
714 int x, int y,
715 struct drm_framebuffer *old_fb)
716 {
717 struct drm_device *dev = crtc->dev;
718 struct drm_i915_private *dev_priv = dev->dev_private;
719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
720 int pipe = intel_crtc->pipe;
721 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
722 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
723 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
724 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
725 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
726 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
727 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
728 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
729 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
730 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
731 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
732 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
733 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
734 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
735 int refclk;
736 intel_clock_t clock;
737 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
738 bool ok, is_sdvo = false, is_dvo = false;
739 bool is_crt = false, is_lvds = false, is_tv = false;
740 struct drm_mode_config *mode_config = &dev->mode_config;
741 struct drm_connector *connector;
742
743 drm_vblank_pre_modeset(dev, pipe);
744
745 list_for_each_entry(connector, &mode_config->connector_list, head) {
746 struct intel_output *intel_output = to_intel_output(connector);
747
748 if (!connector->encoder || connector->encoder->crtc != crtc)
749 continue;
750
751 switch (intel_output->type) {
752 case INTEL_OUTPUT_LVDS:
753 is_lvds = true;
754 break;
755 case INTEL_OUTPUT_SDVO:
756 case INTEL_OUTPUT_HDMI:
757 is_sdvo = true;
758 break;
759 case INTEL_OUTPUT_DVO:
760 is_dvo = true;
761 break;
762 case INTEL_OUTPUT_TVOUT:
763 is_tv = true;
764 break;
765 case INTEL_OUTPUT_ANALOG:
766 is_crt = true;
767 break;
768 }
769 }
770
771 if (IS_I9XX(dev)) {
772 refclk = 96000;
773 } else {
774 refclk = 48000;
775 }
776
777 ok = intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, &clock);
778 if (!ok) {
779 DRM_ERROR("Couldn't find PLL settings for mode!\n");
780 return;
781 }
782
783 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
784
785 dpll = DPLL_VGA_MODE_DIS;
786 if (IS_I9XX(dev)) {
787 if (is_lvds)
788 dpll |= DPLLB_MODE_LVDS;
789 else
790 dpll |= DPLLB_MODE_DAC_SERIAL;
791 if (is_sdvo) {
792 dpll |= DPLL_DVO_HIGH_SPEED;
793 if (IS_I945G(dev) || IS_I945GM(dev)) {
794 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
795 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
796 }
797 }
798
799 /* compute bitmask from p1 value */
800 dpll |= (1 << (clock.p1 - 1)) << 16;
801 switch (clock.p2) {
802 case 5:
803 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
804 break;
805 case 7:
806 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
807 break;
808 case 10:
809 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
810 break;
811 case 14:
812 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
813 break;
814 }
815 if (IS_I965G(dev))
816 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
817 } else {
818 if (is_lvds) {
819 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
820 } else {
821 if (clock.p1 == 2)
822 dpll |= PLL_P1_DIVIDE_BY_TWO;
823 else
824 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
825 if (clock.p2 == 4)
826 dpll |= PLL_P2_DIVIDE_BY_4;
827 }
828 }
829
830 if (is_tv) {
831 /* XXX: just matching BIOS for now */
832 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
833 dpll |= 3;
834 }
835 else
836 dpll |= PLL_REF_INPUT_DREFCLK;
837
838 /* setup pipeconf */
839 pipeconf = I915_READ(pipeconf_reg);
840
841 /* Set up the display plane register */
842 dspcntr = DISPPLANE_GAMMA_ENABLE;
843
844 if (pipe == 0)
845 dspcntr |= DISPPLANE_SEL_PIPE_A;
846 else
847 dspcntr |= DISPPLANE_SEL_PIPE_B;
848
849 if (pipe == 0 && !IS_I965G(dev)) {
850 /* Enable pixel doubling when the dot clock is > 90% of the (display)
851 * core speed.
852 *
853 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
854 * pipe == 0 check?
855 */
856 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
857 pipeconf |= PIPEACONF_DOUBLE_WIDE;
858 else
859 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
860 }
861
862 dspcntr |= DISPLAY_PLANE_ENABLE;
863 pipeconf |= PIPEACONF_ENABLE;
864 dpll |= DPLL_VCO_ENABLE;
865
866
867 /* Disable the panel fitter if it was on our pipe */
868 if (intel_panel_fitter_pipe(dev) == pipe)
869 I915_WRITE(PFIT_CONTROL, 0);
870
871 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
872 drm_mode_debug_printmodeline(mode);
873
874
875 if (dpll & DPLL_VCO_ENABLE) {
876 I915_WRITE(fp_reg, fp);
877 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
878 I915_READ(dpll_reg);
879 udelay(150);
880 }
881
882 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
883 * This is an exception to the general rule that mode_set doesn't turn
884 * things on.
885 */
886 if (is_lvds) {
887 u32 lvds = I915_READ(LVDS);
888
889 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
890 /* Set the B0-B3 data pairs corresponding to whether we're going to
891 * set the DPLLs for dual-channel mode or not.
892 */
893 if (clock.p2 == 7)
894 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
895 else
896 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
897
898 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
899 * appropriately here, but we need to look more thoroughly into how
900 * panels behave in the two modes.
901 */
902
903 I915_WRITE(LVDS, lvds);
904 I915_READ(LVDS);
905 }
906
907 I915_WRITE(fp_reg, fp);
908 I915_WRITE(dpll_reg, dpll);
909 I915_READ(dpll_reg);
910 /* Wait for the clocks to stabilize. */
911 udelay(150);
912
913 if (IS_I965G(dev)) {
914 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
915 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
916 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
917 } else {
918 /* write it again -- the BIOS does, after all */
919 I915_WRITE(dpll_reg, dpll);
920 }
921 I915_READ(dpll_reg);
922 /* Wait for the clocks to stabilize. */
923 udelay(150);
924
925 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
926 ((adjusted_mode->crtc_htotal - 1) << 16));
927 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
928 ((adjusted_mode->crtc_hblank_end - 1) << 16));
929 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
930 ((adjusted_mode->crtc_hsync_end - 1) << 16));
931 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
932 ((adjusted_mode->crtc_vtotal - 1) << 16));
933 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
934 ((adjusted_mode->crtc_vblank_end - 1) << 16));
935 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
936 ((adjusted_mode->crtc_vsync_end - 1) << 16));
937 /* pipesrc and dspsize control the size that is scaled from, which should
938 * always be the user's requested size.
939 */
940 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
941 I915_WRITE(dsppos_reg, 0);
942 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
943 I915_WRITE(pipeconf_reg, pipeconf);
944 I915_READ(pipeconf_reg);
945
946 intel_wait_for_vblank(dev);
947
948 I915_WRITE(dspcntr_reg, dspcntr);
949
950 /* Flush the plane changes */
951 intel_pipe_set_base(crtc, x, y, old_fb);
952
953 drm_vblank_post_modeset(dev, pipe);
954 }
955
956 /** Loads the palette/gamma unit for the CRTC with the prepared values */
957 void intel_crtc_load_lut(struct drm_crtc *crtc)
958 {
959 struct drm_device *dev = crtc->dev;
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
962 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
963 int i;
964
965 /* The clocks have to be on to load the palette. */
966 if (!crtc->enabled)
967 return;
968
969 for (i = 0; i < 256; i++) {
970 I915_WRITE(palreg + 4 * i,
971 (intel_crtc->lut_r[i] << 16) |
972 (intel_crtc->lut_g[i] << 8) |
973 intel_crtc->lut_b[i]);
974 }
975 }
976
977 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
978 struct drm_file *file_priv,
979 uint32_t handle,
980 uint32_t width, uint32_t height)
981 {
982 struct drm_device *dev = crtc->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
985 struct drm_gem_object *bo;
986 struct drm_i915_gem_object *obj_priv;
987 int pipe = intel_crtc->pipe;
988 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
989 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
990 uint32_t temp;
991 size_t addr;
992 int ret;
993
994 DRM_DEBUG("\n");
995
996 /* if we want to turn off the cursor ignore width and height */
997 if (!handle) {
998 DRM_DEBUG("cursor off\n");
999 temp = CURSOR_MODE_DISABLE;
1000 addr = 0;
1001 bo = NULL;
1002 goto finish;
1003 }
1004
1005 /* Currently we only support 64x64 cursors */
1006 if (width != 64 || height != 64) {
1007 DRM_ERROR("we currently only support 64x64 cursors\n");
1008 return -EINVAL;
1009 }
1010
1011 bo = drm_gem_object_lookup(dev, file_priv, handle);
1012 if (!bo)
1013 return -ENOENT;
1014
1015 obj_priv = bo->driver_private;
1016
1017 if (bo->size < width * height * 4) {
1018 DRM_ERROR("buffer is to small\n");
1019 drm_gem_object_unreference(bo);
1020 return -ENOMEM;
1021 }
1022
1023 if (dev_priv->cursor_needs_physical) {
1024 addr = dev->agp->base + obj_priv->gtt_offset;
1025 } else {
1026 addr = obj_priv->gtt_offset;
1027 }
1028
1029 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1030 if (ret) {
1031 DRM_ERROR("failed to pin cursor bo\n");
1032 drm_gem_object_unreference(bo);
1033 return ret;
1034 }
1035
1036 temp = 0;
1037 /* set the pipe for the cursor */
1038 temp |= (pipe << 28);
1039 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1040
1041 finish:
1042 I915_WRITE(control, temp);
1043 I915_WRITE(base, addr);
1044
1045 if (intel_crtc->cursor_bo) {
1046 i915_gem_object_unpin(intel_crtc->cursor_bo);
1047 drm_gem_object_unreference(intel_crtc->cursor_bo);
1048 }
1049
1050 intel_crtc->cursor_addr = addr;
1051 intel_crtc->cursor_bo = bo;
1052
1053 return 0;
1054 }
1055
1056 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1057 {
1058 struct drm_device *dev = crtc->dev;
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1061 int pipe = intel_crtc->pipe;
1062 uint32_t temp = 0;
1063 uint32_t adder;
1064
1065 if (x < 0) {
1066 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1067 x = -x;
1068 }
1069 if (y < 0) {
1070 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1071 y = -y;
1072 }
1073
1074 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1075 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1076
1077 adder = intel_crtc->cursor_addr;
1078 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1079 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1080
1081 return 0;
1082 }
1083
1084 /** Sets the color ramps on behalf of RandR */
1085 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1086 u16 blue, int regno)
1087 {
1088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1089
1090 intel_crtc->lut_r[regno] = red >> 8;
1091 intel_crtc->lut_g[regno] = green >> 8;
1092 intel_crtc->lut_b[regno] = blue >> 8;
1093 }
1094
1095 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1096 u16 *blue, uint32_t size)
1097 {
1098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1099 int i;
1100
1101 if (size != 256)
1102 return;
1103
1104 for (i = 0; i < 256; i++) {
1105 intel_crtc->lut_r[i] = red[i] >> 8;
1106 intel_crtc->lut_g[i] = green[i] >> 8;
1107 intel_crtc->lut_b[i] = blue[i] >> 8;
1108 }
1109
1110 intel_crtc_load_lut(crtc);
1111 }
1112
1113 /**
1114 * Get a pipe with a simple mode set on it for doing load-based monitor
1115 * detection.
1116 *
1117 * It will be up to the load-detect code to adjust the pipe as appropriate for
1118 * its requirements. The pipe will be connected to no other outputs.
1119 *
1120 * Currently this code will only succeed if there is a pipe with no outputs
1121 * configured for it. In the future, it could choose to temporarily disable
1122 * some outputs to free up a pipe for its use.
1123 *
1124 * \return crtc, or NULL if no pipes are available.
1125 */
1126
1127 /* VESA 640x480x72Hz mode to set on the pipe */
1128 static struct drm_display_mode load_detect_mode = {
1129 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
1130 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1131 };
1132
1133 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1134 struct drm_display_mode *mode,
1135 int *dpms_mode)
1136 {
1137 struct intel_crtc *intel_crtc;
1138 struct drm_crtc *possible_crtc;
1139 struct drm_crtc *supported_crtc =NULL;
1140 struct drm_encoder *encoder = &intel_output->enc;
1141 struct drm_crtc *crtc = NULL;
1142 struct drm_device *dev = encoder->dev;
1143 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1144 struct drm_crtc_helper_funcs *crtc_funcs;
1145 int i = -1;
1146
1147 /*
1148 * Algorithm gets a little messy:
1149 * - if the connector already has an assigned crtc, use it (but make
1150 * sure it's on first)
1151 * - try to find the first unused crtc that can drive this connector,
1152 * and use that if we find one
1153 * - if there are no unused crtcs available, try to use the first
1154 * one we found that supports the connector
1155 */
1156
1157 /* See if we already have a CRTC for this connector */
1158 if (encoder->crtc) {
1159 crtc = encoder->crtc;
1160 /* Make sure the crtc and connector are running */
1161 intel_crtc = to_intel_crtc(crtc);
1162 *dpms_mode = intel_crtc->dpms_mode;
1163 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1164 crtc_funcs = crtc->helper_private;
1165 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1166 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1167 }
1168 return crtc;
1169 }
1170
1171 /* Find an unused one (if possible) */
1172 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
1173 i++;
1174 if (!(encoder->possible_crtcs & (1 << i)))
1175 continue;
1176 if (!possible_crtc->enabled) {
1177 crtc = possible_crtc;
1178 break;
1179 }
1180 if (!supported_crtc)
1181 supported_crtc = possible_crtc;
1182 }
1183
1184 /*
1185 * If we didn't find an unused CRTC, don't use any.
1186 */
1187 if (!crtc) {
1188 return NULL;
1189 }
1190
1191 encoder->crtc = crtc;
1192 intel_output->load_detect_temp = true;
1193
1194 intel_crtc = to_intel_crtc(crtc);
1195 *dpms_mode = intel_crtc->dpms_mode;
1196
1197 if (!crtc->enabled) {
1198 if (!mode)
1199 mode = &load_detect_mode;
1200 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
1201 } else {
1202 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1203 crtc_funcs = crtc->helper_private;
1204 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1205 }
1206
1207 /* Add this connector to the crtc */
1208 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
1209 encoder_funcs->commit(encoder);
1210 }
1211 /* let the connector get through one full cycle before testing */
1212 intel_wait_for_vblank(dev);
1213
1214 return crtc;
1215 }
1216
1217 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
1218 {
1219 struct drm_encoder *encoder = &intel_output->enc;
1220 struct drm_device *dev = encoder->dev;
1221 struct drm_crtc *crtc = encoder->crtc;
1222 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1223 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1224
1225 if (intel_output->load_detect_temp) {
1226 encoder->crtc = NULL;
1227 intel_output->load_detect_temp = false;
1228 crtc->enabled = drm_helper_crtc_in_use(crtc);
1229 drm_helper_disable_unused_functions(dev);
1230 }
1231
1232 /* Switch crtc and output back off if necessary */
1233 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
1234 if (encoder->crtc == crtc)
1235 encoder_funcs->dpms(encoder, dpms_mode);
1236 crtc_funcs->dpms(crtc, dpms_mode);
1237 }
1238 }
1239
1240 /* Returns the clock of the currently programmed mode of the given pipe. */
1241 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1242 {
1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1245 int pipe = intel_crtc->pipe;
1246 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
1247 u32 fp;
1248 intel_clock_t clock;
1249
1250 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1251 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
1252 else
1253 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1254
1255 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1256 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1257 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1258 if (IS_I9XX(dev)) {
1259 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1260 DPLL_FPA01_P1_POST_DIV_SHIFT);
1261
1262 switch (dpll & DPLL_MODE_MASK) {
1263 case DPLLB_MODE_DAC_SERIAL:
1264 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
1265 5 : 10;
1266 break;
1267 case DPLLB_MODE_LVDS:
1268 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
1269 7 : 14;
1270 break;
1271 default:
1272 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1273 "mode\n", (int)(dpll & DPLL_MODE_MASK));
1274 return 0;
1275 }
1276
1277 /* XXX: Handle the 100Mhz refclk */
1278 i9xx_clock(96000, &clock);
1279 } else {
1280 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1281
1282 if (is_lvds) {
1283 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1284 DPLL_FPA01_P1_POST_DIV_SHIFT);
1285 clock.p2 = 14;
1286
1287 if ((dpll & PLL_REF_INPUT_MASK) ==
1288 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1289 /* XXX: might not be 66MHz */
1290 i8xx_clock(66000, &clock);
1291 } else
1292 i8xx_clock(48000, &clock);
1293 } else {
1294 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1295 clock.p1 = 2;
1296 else {
1297 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1298 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1299 }
1300 if (dpll & PLL_P2_DIVIDE_BY_4)
1301 clock.p2 = 4;
1302 else
1303 clock.p2 = 2;
1304
1305 i8xx_clock(48000, &clock);
1306 }
1307 }
1308
1309 /* XXX: It would be nice to validate the clocks, but we can't reuse
1310 * i830PllIsValid() because it relies on the xf86_config connector
1311 * configuration being accurate, which it isn't necessarily.
1312 */
1313
1314 return clock.dot;
1315 }
1316
1317 /** Returns the currently programmed mode of the given pipe. */
1318 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1319 struct drm_crtc *crtc)
1320 {
1321 struct drm_i915_private *dev_priv = dev->dev_private;
1322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1323 int pipe = intel_crtc->pipe;
1324 struct drm_display_mode *mode;
1325 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1326 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1327 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1328 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1329
1330 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1331 if (!mode)
1332 return NULL;
1333
1334 mode->clock = intel_crtc_clock_get(dev, crtc);
1335 mode->hdisplay = (htot & 0xffff) + 1;
1336 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1337 mode->hsync_start = (hsync & 0xffff) + 1;
1338 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1339 mode->vdisplay = (vtot & 0xffff) + 1;
1340 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1341 mode->vsync_start = (vsync & 0xffff) + 1;
1342 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1343
1344 drm_mode_set_name(mode);
1345 drm_mode_set_crtcinfo(mode, 0);
1346
1347 return mode;
1348 }
1349
1350 static void intel_crtc_destroy(struct drm_crtc *crtc)
1351 {
1352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1353
1354 drm_crtc_cleanup(crtc);
1355 kfree(intel_crtc);
1356 }
1357
1358 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
1359 .dpms = intel_crtc_dpms,
1360 .mode_fixup = intel_crtc_mode_fixup,
1361 .mode_set = intel_crtc_mode_set,
1362 .mode_set_base = intel_pipe_set_base,
1363 .prepare = intel_crtc_prepare,
1364 .commit = intel_crtc_commit,
1365 };
1366
1367 static const struct drm_crtc_funcs intel_crtc_funcs = {
1368 .cursor_set = intel_crtc_cursor_set,
1369 .cursor_move = intel_crtc_cursor_move,
1370 .gamma_set = intel_crtc_gamma_set,
1371 .set_config = drm_crtc_helper_set_config,
1372 .destroy = intel_crtc_destroy,
1373 };
1374
1375
1376 static void intel_crtc_init(struct drm_device *dev, int pipe)
1377 {
1378 struct intel_crtc *intel_crtc;
1379 int i;
1380
1381 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
1382 if (intel_crtc == NULL)
1383 return;
1384
1385 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
1386
1387 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
1388 intel_crtc->pipe = pipe;
1389 for (i = 0; i < 256; i++) {
1390 intel_crtc->lut_r[i] = i;
1391 intel_crtc->lut_g[i] = i;
1392 intel_crtc->lut_b[i] = i;
1393 }
1394
1395 intel_crtc->cursor_addr = 0;
1396 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
1397 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1398
1399 intel_crtc->mode_set.crtc = &intel_crtc->base;
1400 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
1401 intel_crtc->mode_set.num_connectors = 0;
1402
1403 if (i915_fbpercrtc) {
1404
1405
1406
1407 }
1408 }
1409
1410 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1411 {
1412 struct drm_crtc *crtc = NULL;
1413
1414 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1416 if (intel_crtc->pipe == pipe)
1417 break;
1418 }
1419 return crtc;
1420 }
1421
1422 static int intel_connector_clones(struct drm_device *dev, int type_mask)
1423 {
1424 int index_mask = 0;
1425 struct drm_connector *connector;
1426 int entry = 0;
1427
1428 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1429 struct intel_output *intel_output = to_intel_output(connector);
1430 if (type_mask & (1 << intel_output->type))
1431 index_mask |= (1 << entry);
1432 entry++;
1433 }
1434 return index_mask;
1435 }
1436
1437
1438 static void intel_setup_outputs(struct drm_device *dev)
1439 {
1440 struct drm_connector *connector;
1441
1442 intel_crt_init(dev);
1443
1444 /* Set up integrated LVDS */
1445 if (IS_MOBILE(dev) && !IS_I830(dev))
1446 intel_lvds_init(dev);
1447
1448 if (IS_I9XX(dev)) {
1449 int found;
1450
1451 found = intel_sdvo_init(dev, SDVOB);
1452 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1453 intel_hdmi_init(dev, SDVOB);
1454
1455 found = intel_sdvo_init(dev, SDVOC);
1456 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1457 intel_hdmi_init(dev, SDVOC);
1458 } else
1459 intel_dvo_init(dev);
1460
1461 if (IS_I9XX(dev) && IS_MOBILE(dev))
1462 intel_tv_init(dev);
1463
1464 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1465 struct intel_output *intel_output = to_intel_output(connector);
1466 struct drm_encoder *encoder = &intel_output->enc;
1467 int crtc_mask = 0, clone_mask = 0;
1468
1469 /* valid crtcs */
1470 switch(intel_output->type) {
1471 case INTEL_OUTPUT_HDMI:
1472 crtc_mask = ((1 << 0)|
1473 (1 << 1));
1474 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
1475 break;
1476 case INTEL_OUTPUT_DVO:
1477 case INTEL_OUTPUT_SDVO:
1478 crtc_mask = ((1 << 0)|
1479 (1 << 1));
1480 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1481 (1 << INTEL_OUTPUT_DVO) |
1482 (1 << INTEL_OUTPUT_SDVO));
1483 break;
1484 case INTEL_OUTPUT_ANALOG:
1485 crtc_mask = ((1 << 0)|
1486 (1 << 1));
1487 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1488 (1 << INTEL_OUTPUT_DVO) |
1489 (1 << INTEL_OUTPUT_SDVO));
1490 break;
1491 case INTEL_OUTPUT_LVDS:
1492 crtc_mask = (1 << 1);
1493 clone_mask = (1 << INTEL_OUTPUT_LVDS);
1494 break;
1495 case INTEL_OUTPUT_TVOUT:
1496 crtc_mask = ((1 << 0) |
1497 (1 << 1));
1498 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
1499 break;
1500 }
1501 encoder->possible_crtcs = crtc_mask;
1502 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
1503 }
1504 }
1505
1506 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1507 {
1508 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1509 struct drm_device *dev = fb->dev;
1510
1511 if (fb->fbdev)
1512 intelfb_remove(dev, fb);
1513
1514 drm_framebuffer_cleanup(fb);
1515 mutex_lock(&dev->struct_mutex);
1516 drm_gem_object_unreference(intel_fb->obj);
1517 mutex_unlock(&dev->struct_mutex);
1518
1519 kfree(intel_fb);
1520 }
1521
1522 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1523 struct drm_file *file_priv,
1524 unsigned int *handle)
1525 {
1526 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1527 struct drm_gem_object *object = intel_fb->obj;
1528
1529 return drm_gem_handle_create(file_priv, object, handle);
1530 }
1531
1532 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1533 .destroy = intel_user_framebuffer_destroy,
1534 .create_handle = intel_user_framebuffer_create_handle,
1535 };
1536
1537 int intel_framebuffer_create(struct drm_device *dev,
1538 struct drm_mode_fb_cmd *mode_cmd,
1539 struct drm_framebuffer **fb,
1540 struct drm_gem_object *obj)
1541 {
1542 struct intel_framebuffer *intel_fb;
1543 int ret;
1544
1545 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1546 if (!intel_fb)
1547 return -ENOMEM;
1548
1549 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
1550 if (ret) {
1551 DRM_ERROR("framebuffer init failed %d\n", ret);
1552 return ret;
1553 }
1554
1555 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
1556
1557 intel_fb->obj = obj;
1558
1559 *fb = &intel_fb->base;
1560
1561 return 0;
1562 }
1563
1564
1565 static struct drm_framebuffer *
1566 intel_user_framebuffer_create(struct drm_device *dev,
1567 struct drm_file *filp,
1568 struct drm_mode_fb_cmd *mode_cmd)
1569 {
1570 struct drm_gem_object *obj;
1571 struct drm_framebuffer *fb;
1572 int ret;
1573
1574 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
1575 if (!obj)
1576 return NULL;
1577
1578 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
1579 if (ret) {
1580 drm_gem_object_unreference(obj);
1581 return NULL;
1582 }
1583
1584 return fb;
1585 }
1586
1587 static const struct drm_mode_config_funcs intel_mode_funcs = {
1588 .fb_create = intel_user_framebuffer_create,
1589 .fb_changed = intelfb_probe,
1590 };
1591
1592 void intel_modeset_init(struct drm_device *dev)
1593 {
1594 int num_pipe;
1595 int i;
1596
1597 drm_mode_config_init(dev);
1598
1599 dev->mode_config.min_width = 0;
1600 dev->mode_config.min_height = 0;
1601
1602 dev->mode_config.funcs = (void *)&intel_mode_funcs;
1603
1604 if (IS_I965G(dev)) {
1605 dev->mode_config.max_width = 8192;
1606 dev->mode_config.max_height = 8192;
1607 } else {
1608 dev->mode_config.max_width = 2048;
1609 dev->mode_config.max_height = 2048;
1610 }
1611
1612 /* set memory base */
1613 if (IS_I9XX(dev))
1614 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
1615 else
1616 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
1617
1618 if (IS_MOBILE(dev) || IS_I9XX(dev))
1619 num_pipe = 2;
1620 else
1621 num_pipe = 1;
1622 DRM_DEBUG("%d display pipe%s available.\n",
1623 num_pipe, num_pipe > 1 ? "s" : "");
1624
1625 for (i = 0; i < num_pipe; i++) {
1626 intel_crtc_init(dev, i);
1627 }
1628
1629 intel_setup_outputs(dev);
1630 }
1631
1632 void intel_modeset_cleanup(struct drm_device *dev)
1633 {
1634 drm_mode_config_cleanup(dev);
1635 }
1636
1637
1638 /* current intel driver doesn't take advantage of encoders
1639 always give back the encoder for the connector
1640 */
1641 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
1642 {
1643 struct intel_output *intel_output = to_intel_output(connector);
1644
1645 return &intel_output->enc;
1646 }
Support for the Chinese Samsung S3C2440 based development boards