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net: net_assign_generic() fix
[linux-2.6/mini2440.git] / drivers / ata / pdc_adma.c
blob6c65b0776a2cc900c6b97dd437a458cc7fd125ed
1 /*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "pdc_adma"
47 #define DRV_VERSION "1.0"
48
49 /* macro to calculate base address for ATA regs */
50 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
51
52 /* macro to calculate base address for ADMA regs */
53 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
54
55 /* macro to obtain addresses from ata_port */
56 #define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
58
59 enum {
60 ADMA_MMIO_BAR = 4,
61
62 ADMA_PORTS = 2,
63 ADMA_CPB_BYTES = 40,
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
67 ADMA_DMA_BOUNDARY = 0xffffffff,
68
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
71
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
81
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
86 aPIOMD4 = 0x0003, /* PIO mode 4 */
87
88 /* ADMA_STATUS register bits */
89 aPSD = (1 << 6),
90 aUIRQ = (1 << 4),
91 aPERR = (1 << 0),
92
93 /* CPB bits */
94 cDONE = (1 << 0),
95 cATERR = (1 << 3),
96
97 cVLD = (1 << 0),
98 cDAT = (1 << 2),
99 cIEN = (1 << 3),
100
101 /* PRD bits */
102 pORD = (1 << 4),
103 pDIRO = (1 << 5),
104 pEND = (1 << 7),
105
106 /* ATA register flags */
107 rIGN = (1 << 5),
108 rEND = (1 << 7),
109
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
118
119 /* PCI device IDs */
120 board_1841_idx = 0, /* ADMA 2-port controller */
121 };
122
123 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
125 struct adma_port_priv {
126 u8 *pkt;
127 dma_addr_t pkt_dma;
128 adma_state_t state;
129 };
130
131 static int adma_ata_init_one(struct pci_dev *pdev,
132 const struct pci_device_id *ent);
133 static int adma_port_start(struct ata_port *ap);
134 static void adma_port_stop(struct ata_port *ap);
135 static void adma_qc_prep(struct ata_queued_cmd *qc);
136 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
137 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
138 static void adma_freeze(struct ata_port *ap);
139 static void adma_thaw(struct ata_port *ap);
140 static int adma_prereset(struct ata_link *link, unsigned long deadline);
141
142 static struct scsi_host_template adma_ata_sht = {
143 ATA_BASE_SHT(DRV_NAME),
144 .sg_tablesize = LIBATA_MAX_PRD,
145 .dma_boundary = ADMA_DMA_BOUNDARY,
146 };
147
148 static struct ata_port_operations adma_ata_ops = {
149 .inherits = &ata_sff_port_ops,
150
151 .lost_interrupt = ATA_OP_NULL,
152
153 .check_atapi_dma = adma_check_atapi_dma,
154 .qc_prep = adma_qc_prep,
155 .qc_issue = adma_qc_issue,
156
157 .freeze = adma_freeze,
158 .thaw = adma_thaw,
159 .prereset = adma_prereset,
160
161 .port_start = adma_port_start,
162 .port_stop = adma_port_stop,
163 };
164
165 static struct ata_port_info adma_port_info[] = {
166 /* board_1841_idx */
167 {
168 .flags = ATA_FLAG_SLAVE_POSS |
169 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
170 ATA_FLAG_PIO_POLLING,
171 .pio_mask = ATA_PIO4_ONLY,
172 .udma_mask = ATA_UDMA4,
173 .port_ops = &adma_ata_ops,
174 },
175 };
176
177 static const struct pci_device_id adma_ata_pci_tbl[] = {
178 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
179
180 { } /* terminate list */
181 };
182
183 static struct pci_driver adma_ata_pci_driver = {
184 .name = DRV_NAME,
185 .id_table = adma_ata_pci_tbl,
186 .probe = adma_ata_init_one,
187 .remove = ata_pci_remove_one,
188 };
189
190 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
191 {
192 return 1; /* ATAPI DMA not yet supported */
193 }
194
195 static void adma_reset_engine(struct ata_port *ap)
196 {
197 void __iomem *chan = ADMA_PORT_REGS(ap);
198
199 /* reset ADMA to idle state */
200 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
201 udelay(2);
202 writew(aPIOMD4, chan + ADMA_CONTROL);
203 udelay(2);
204 }
205
206 static void adma_reinit_engine(struct ata_port *ap)
207 {
208 struct adma_port_priv *pp = ap->private_data;
209 void __iomem *chan = ADMA_PORT_REGS(ap);
210
211 /* mask/clear ATA interrupts */
212 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
213 ata_sff_check_status(ap);
214
215 /* reset the ADMA engine */
216 adma_reset_engine(ap);
217
218 /* set in-FIFO threshold to 0x100 */
219 writew(0x100, chan + ADMA_FIFO_IN);
220
221 /* set CPB pointer */
222 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
223
224 /* set out-FIFO threshold to 0x100 */
225 writew(0x100, chan + ADMA_FIFO_OUT);
226
227 /* set CPB count */
228 writew(1, chan + ADMA_CPB_COUNT);
229
230 /* read/discard ADMA status */
231 readb(chan + ADMA_STATUS);
232 }
233
234 static inline void adma_enter_reg_mode(struct ata_port *ap)
235 {
236 void __iomem *chan = ADMA_PORT_REGS(ap);
237
238 writew(aPIOMD4, chan + ADMA_CONTROL);
239 readb(chan + ADMA_STATUS); /* flush */
240 }
241
242 static void adma_freeze(struct ata_port *ap)
243 {
244 void __iomem *chan = ADMA_PORT_REGS(ap);
245
246 /* mask/clear ATA interrupts */
247 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
248 ata_sff_check_status(ap);
249
250 /* reset ADMA to idle state */
251 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
252 udelay(2);
253 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
254 udelay(2);
255 }
256
257 static void adma_thaw(struct ata_port *ap)
258 {
259 adma_reinit_engine(ap);
260 }
261
262 static int adma_prereset(struct ata_link *link, unsigned long deadline)
263 {
264 struct ata_port *ap = link->ap;
265 struct adma_port_priv *pp = ap->private_data;
266
267 if (pp->state != adma_state_idle) /* healthy paranoia */
268 pp->state = adma_state_mmio;
269 adma_reinit_engine(ap);
270
271 return ata_sff_prereset(link, deadline);
272 }
273
274 static int adma_fill_sg(struct ata_queued_cmd *qc)
275 {
276 struct scatterlist *sg;
277 struct ata_port *ap = qc->ap;
278 struct adma_port_priv *pp = ap->private_data;
279 u8 *buf = pp->pkt, *last_buf = NULL;
280 int i = (2 + buf[3]) * 8;
281 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
282 unsigned int si;
283
284 for_each_sg(qc->sg, sg, qc->n_elem, si) {
285 u32 addr;
286 u32 len;
287
288 addr = (u32)sg_dma_address(sg);
289 *(__le32 *)(buf + i) = cpu_to_le32(addr);
290 i += 4;
291
292 len = sg_dma_len(sg) >> 3;
293 *(__le32 *)(buf + i) = cpu_to_le32(len);
294 i += 4;
295
296 last_buf = &buf[i];
297 buf[i++] = pFLAGS;
298 buf[i++] = qc->dev->dma_mode & 0xf;
299 buf[i++] = 0; /* pPKLW */
300 buf[i++] = 0; /* reserved */
301
302 *(__le32 *)(buf + i) =
303 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
304 i += 4;
305
306 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
307 (unsigned long)addr, len);
308 }
309
310 if (likely(last_buf))
311 *last_buf |= pEND;
312
313 return i;
314 }
315
316 static void adma_qc_prep(struct ata_queued_cmd *qc)
317 {
318 struct adma_port_priv *pp = qc->ap->private_data;
319 u8 *buf = pp->pkt;
320 u32 pkt_dma = (u32)pp->pkt_dma;
321 int i = 0;
322
323 VPRINTK("ENTER\n");
324
325 adma_enter_reg_mode(qc->ap);
326 if (qc->tf.protocol != ATA_PROT_DMA) {
327 ata_sff_qc_prep(qc);
328 return;
329 }
330
331 buf[i++] = 0; /* Response flags */
332 buf[i++] = 0; /* reserved */
333 buf[i++] = cVLD | cDAT | cIEN;
334 i++; /* cLEN, gets filled in below */
335
336 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
337 i += 4; /* cNCPB */
338 i += 4; /* cPRD, gets filled in below */
339
340 buf[i++] = 0; /* reserved */
341 buf[i++] = 0; /* reserved */
342 buf[i++] = 0; /* reserved */
343 buf[i++] = 0; /* reserved */
344
345 /* ATA registers; must be a multiple of 4 */
346 buf[i++] = qc->tf.device;
347 buf[i++] = ADMA_REGS_DEVICE;
348 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
349 buf[i++] = qc->tf.hob_nsect;
350 buf[i++] = ADMA_REGS_SECTOR_COUNT;
351 buf[i++] = qc->tf.hob_lbal;
352 buf[i++] = ADMA_REGS_LBA_LOW;
353 buf[i++] = qc->tf.hob_lbam;
354 buf[i++] = ADMA_REGS_LBA_MID;
355 buf[i++] = qc->tf.hob_lbah;
356 buf[i++] = ADMA_REGS_LBA_HIGH;
357 }
358 buf[i++] = qc->tf.nsect;
359 buf[i++] = ADMA_REGS_SECTOR_COUNT;
360 buf[i++] = qc->tf.lbal;
361 buf[i++] = ADMA_REGS_LBA_LOW;
362 buf[i++] = qc->tf.lbam;
363 buf[i++] = ADMA_REGS_LBA_MID;
364 buf[i++] = qc->tf.lbah;
365 buf[i++] = ADMA_REGS_LBA_HIGH;
366 buf[i++] = 0;
367 buf[i++] = ADMA_REGS_CONTROL;
368 buf[i++] = rIGN;
369 buf[i++] = 0;
370 buf[i++] = qc->tf.command;
371 buf[i++] = ADMA_REGS_COMMAND | rEND;
372
373 buf[3] = (i >> 3) - 2; /* cLEN */
374 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
375
376 i = adma_fill_sg(qc);
377 wmb(); /* flush PRDs and pkt to memory */
378 #if 0
379 /* dump out CPB + PRDs for debug */
380 {
381 int j, len = 0;
382 static char obuf[2048];
383 for (j = 0; j < i; ++j) {
384 len += sprintf(obuf+len, "%02x ", buf[j]);
385 if ((j & 7) == 7) {
386 printk("%s\n", obuf);
387 len = 0;
388 }
389 }
390 if (len)
391 printk("%s\n", obuf);
392 }
393 #endif
394 }
395
396 static inline void adma_packet_start(struct ata_queued_cmd *qc)
397 {
398 struct ata_port *ap = qc->ap;
399 void __iomem *chan = ADMA_PORT_REGS(ap);
400
401 VPRINTK("ENTER, ap %p\n", ap);
402
403 /* fire up the ADMA engine */
404 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
405 }
406
407 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
408 {
409 struct adma_port_priv *pp = qc->ap->private_data;
410
411 switch (qc->tf.protocol) {
412 case ATA_PROT_DMA:
413 pp->state = adma_state_pkt;
414 adma_packet_start(qc);
415 return 0;
416
417 case ATAPI_PROT_DMA:
418 BUG();
419 break;
420
421 default:
422 break;
423 }
424
425 pp->state = adma_state_mmio;
426 return ata_sff_qc_issue(qc);
427 }
428
429 static inline unsigned int adma_intr_pkt(struct ata_host *host)
430 {
431 unsigned int handled = 0, port_no;
432
433 for (port_no = 0; port_no < host->n_ports; ++port_no) {
434 struct ata_port *ap = host->ports[port_no];
435 struct adma_port_priv *pp;
436 struct ata_queued_cmd *qc;
437 void __iomem *chan = ADMA_PORT_REGS(ap);
438 u8 status = readb(chan + ADMA_STATUS);
439
440 if (status == 0)
441 continue;
442 handled = 1;
443 adma_enter_reg_mode(ap);
444 if (ap->flags & ATA_FLAG_DISABLED)
445 continue;
446 pp = ap->private_data;
447 if (!pp || pp->state != adma_state_pkt)
448 continue;
449 qc = ata_qc_from_tag(ap, ap->link.active_tag);
450 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
451 if (status & aPERR)
452 qc->err_mask |= AC_ERR_HOST_BUS;
453 else if ((status & (aPSD | aUIRQ)))
454 qc->err_mask |= AC_ERR_OTHER;
455
456 if (pp->pkt[0] & cATERR)
457 qc->err_mask |= AC_ERR_DEV;
458 else if (pp->pkt[0] != cDONE)
459 qc->err_mask |= AC_ERR_OTHER;
460
461 if (!qc->err_mask)
462 ata_qc_complete(qc);
463 else {
464 struct ata_eh_info *ehi = &ap->link.eh_info;
465 ata_ehi_clear_desc(ehi);
466 ata_ehi_push_desc(ehi,
467 "ADMA-status 0x%02X", status);
468 ata_ehi_push_desc(ehi,
469 "pkt[0] 0x%02X", pp->pkt[0]);
470
471 if (qc->err_mask == AC_ERR_DEV)
472 ata_port_abort(ap);
473 else
474 ata_port_freeze(ap);
475 }
476 }
477 }
478 return handled;
479 }
480
481 static inline unsigned int adma_intr_mmio(struct ata_host *host)
482 {
483 unsigned int handled = 0, port_no;
484
485 for (port_no = 0; port_no < host->n_ports; ++port_no) {
486 struct ata_port *ap;
487 ap = host->ports[port_no];
488 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
489 struct ata_queued_cmd *qc;
490 struct adma_port_priv *pp = ap->private_data;
491 if (!pp || pp->state != adma_state_mmio)
492 continue;
493 qc = ata_qc_from_tag(ap, ap->link.active_tag);
494 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
495
496 /* check main status, clearing INTRQ */
497 u8 status = ata_sff_check_status(ap);
498 if ((status & ATA_BUSY))
499 continue;
500 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
501 ap->print_id, qc->tf.protocol, status);
502
503 /* complete taskfile transaction */
504 pp->state = adma_state_idle;
505 qc->err_mask |= ac_err_mask(status);
506 if (!qc->err_mask)
507 ata_qc_complete(qc);
508 else {
509 struct ata_eh_info *ehi =
510 &ap->link.eh_info;
511 ata_ehi_clear_desc(ehi);
512 ata_ehi_push_desc(ehi,
513 "status 0x%02X", status);
514
515 if (qc->err_mask == AC_ERR_DEV)
516 ata_port_abort(ap);
517 else
518 ata_port_freeze(ap);
519 }
520 handled = 1;
521 }
522 }
523 }
524 return handled;
525 }
526
527 static irqreturn_t adma_intr(int irq, void *dev_instance)
528 {
529 struct ata_host *host = dev_instance;
530 unsigned int handled = 0;
531
532 VPRINTK("ENTER\n");
533
534 spin_lock(&host->lock);
535 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
536 spin_unlock(&host->lock);
537
538 VPRINTK("EXIT\n");
539
540 return IRQ_RETVAL(handled);
541 }
542
543 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
544 {
545 port->cmd_addr =
546 port->data_addr = base + 0x000;
547 port->error_addr =
548 port->feature_addr = base + 0x004;
549 port->nsect_addr = base + 0x008;
550 port->lbal_addr = base + 0x00c;
551 port->lbam_addr = base + 0x010;
552 port->lbah_addr = base + 0x014;
553 port->device_addr = base + 0x018;
554 port->status_addr =
555 port->command_addr = base + 0x01c;
556 port->altstatus_addr =
557 port->ctl_addr = base + 0x038;
558 }
559
560 static int adma_port_start(struct ata_port *ap)
561 {
562 struct device *dev = ap->host->dev;
563 struct adma_port_priv *pp;
564 int rc;
565
566 rc = ata_port_start(ap);
567 if (rc)
568 return rc;
569 adma_enter_reg_mode(ap);
570 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
571 if (!pp)
572 return -ENOMEM;
573 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
574 GFP_KERNEL);
575 if (!pp->pkt)
576 return -ENOMEM;
577 /* paranoia? */
578 if ((pp->pkt_dma & 7) != 0) {
579 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
580 (u32)pp->pkt_dma);
581 return -ENOMEM;
582 }
583 memset(pp->pkt, 0, ADMA_PKT_BYTES);
584 ap->private_data = pp;
585 adma_reinit_engine(ap);
586 return 0;
587 }
588
589 static void adma_port_stop(struct ata_port *ap)
590 {
591 adma_reset_engine(ap);
592 }
593
594 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
595 {
596 unsigned int port_no;
597
598 /* enable/lock aGO operation */
599 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
600
601 /* reset the ADMA logic */
602 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
603 adma_reset_engine(host->ports[port_no]);
604 }
605
606 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
607 {
608 int rc;
609
610 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
611 if (rc) {
612 dev_printk(KERN_ERR, &pdev->dev,
613 "32-bit DMA enable failed\n");
614 return rc;
615 }
616 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
617 if (rc) {
618 dev_printk(KERN_ERR, &pdev->dev,
619 "32-bit consistent DMA enable failed\n");
620 return rc;
621 }
622 return 0;
623 }
624
625 static int adma_ata_init_one(struct pci_dev *pdev,
626 const struct pci_device_id *ent)
627 {
628 static int printed_version;
629 unsigned int board_idx = (unsigned int) ent->driver_data;
630 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
631 struct ata_host *host;
632 void __iomem *mmio_base;
633 int rc, port_no;
634
635 if (!printed_version++)
636 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
637
638 /* alloc host */
639 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
640 if (!host)
641 return -ENOMEM;
642
643 /* acquire resources and fill host */
644 rc = pcim_enable_device(pdev);
645 if (rc)
646 return rc;
647
648 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
649 return -ENODEV;
650
651 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
652 if (rc)
653 return rc;
654 host->iomap = pcim_iomap_table(pdev);
655 mmio_base = host->iomap[ADMA_MMIO_BAR];
656
657 rc = adma_set_dma_masks(pdev, mmio_base);
658 if (rc)
659 return rc;
660
661 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
662 struct ata_port *ap = host->ports[port_no];
663 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
664 unsigned int offset = port_base - mmio_base;
665
666 adma_ata_setup_port(&ap->ioaddr, port_base);
667
668 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
669 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
670 }
671
672 /* initialize adapter */
673 adma_host_init(host, board_idx);
674
675 pci_set_master(pdev);
676 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
677 &adma_ata_sht);
678 }
679
680 static int __init adma_ata_init(void)
681 {
682 return pci_register_driver(&adma_ata_pci_driver);
683 }
684
685 static void __exit adma_ata_exit(void)
686 {
687 pci_unregister_driver(&adma_ata_pci_driver);
688 }
689
690 MODULE_AUTHOR("Mark Lord");
691 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
692 MODULE_LICENSE("GPL");
693 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
694 MODULE_VERSION(DRV_VERSION);
695
696 module_init(adma_ata_init);
697 module_exit(adma_ata_exit);
Support for the Chinese Samsung S3C2440 based development boards