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net: net_assign_generic() fix
[linux-2.6/mini2440.git] / drivers / ata / ata_piix.c
blob1aeb7082b0c4e34faecfb1d9f92ae14fbec766ca
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <scsi/scsi_host.h>
94 #include <linux/libata.h>
95 #include <linux/dmi.h>
96
97 #define DRV_NAME "ata_piix"
98 #define DRV_VERSION "2.13"
99
100 enum {
101 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
102 ICH5_PMR = 0x90, /* port mapping register */
103 ICH5_PCS = 0x92, /* port control and status */
104 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4,
108
109 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
110 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
111
112 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
113 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* constants for mapping table */
119 P0 = 0, /* port 0 */
120 P1 = 1, /* port 1 */
121 P2 = 2, /* port 2 */
122 P3 = 3, /* port 3 */
123 IDE = -1, /* IDE */
124 NA = -2, /* not avaliable */
125 RV = -3, /* reserved */
126
127 PIIX_AHCI_DEVICE = 6,
128
129 /* host->flags bits */
130 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
131 };
132
133 enum piix_controller_ids {
134 /* controller IDs */
135 piix_pata_mwdma, /* PIIX3 MWDMA only */
136 piix_pata_33, /* PIIX4 at 33Mhz */
137 ich_pata_33, /* ICH up to UDMA 33 only */
138 ich_pata_66, /* ICH up to 66 Mhz */
139 ich_pata_100, /* ICH up to UDMA 100 */
140 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
141 ich5_sata,
142 ich6_sata,
143 ich6m_sata,
144 ich8_sata,
145 ich8_2port_sata,
146 ich8m_apple_sata, /* locks up on second port enable */
147 tolapai_sata,
148 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
149 };
150
151 struct piix_map_db {
152 const u32 mask;
153 const u16 port_enable;
154 const int map[][4];
155 };
156
157 struct piix_host_priv {
158 const int *map;
159 u32 saved_iocfg;
160 void __iomem *sidpr;
161 };
162
163 static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent);
165 static void piix_remove_one(struct pci_dev *pdev);
166 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
167 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
168 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
169 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
170 static int ich_pata_cable_detect(struct ata_port *ap);
171 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
172 static int piix_sidpr_scr_read(struct ata_link *link,
173 unsigned int reg, u32 *val);
174 static int piix_sidpr_scr_write(struct ata_link *link,
175 unsigned int reg, u32 val);
176 #ifdef CONFIG_PM
177 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
178 static int piix_pci_device_resume(struct pci_dev *pdev);
179 #endif
180
181 static unsigned int in_module_init = 1;
182
183 static const struct pci_device_id piix_pci_tbl[] = {
184 /* Intel PIIX3 for the 430HX etc */
185 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
186 /* VMware ICH4 */
187 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
188 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
189 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
190 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX4 */
192 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel PIIX4 */
194 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel PIIX */
196 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
197 /* Intel ICH (i810, i815, i840) UDMA 66*/
198 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
199 /* Intel ICH0 : UDMA 33*/
200 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
201 /* Intel ICH2M */
202 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
204 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH3M */
206 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH3 (E7500/1) UDMA 100 */
208 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
210 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* Intel ICH5 */
213 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* C-ICH (i810E2) */
215 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
217 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ICH6 (and 6) (i915) UDMA 100 */
219 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 /* ICH7/7-R (i945, i975) UDMA 100*/
221 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
222 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
223 /* ICH8 Mobile PATA Controller */
224 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
225
226 /* NOTE: The following PCI ids must be kept in sync with the
227 * list in drivers/pci/quirks.c.
228 */
229
230 /* 82801EB (ICH5) */
231 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 82801EB (ICH5) */
233 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 6300ESB (ICH5 variant with broken PCS present bits) */
235 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
236 /* 6300ESB pretending RAID */
237 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
238 /* 82801FB/FW (ICH6/ICH6W) */
239 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
240 /* 82801FR/FRW (ICH6R/ICH6RW) */
241 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
242 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
243 * Attach iff the controller is in IDE mode. */
244 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
245 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
246 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
247 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
249 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
250 /* Enterprise Southbridge 2 (631xESB/632xESB) */
251 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
252 /* SATA Controller 1 IDE (ICH8) */
253 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
254 /* SATA Controller 2 IDE (ICH8) */
255 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* Mobile SATA Controller IDE (ICH8M), Apple */
257 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
258 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
259 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
260 /* Mobile SATA Controller IDE (ICH8M) */
261 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
262 /* SATA Controller IDE (ICH9) */
263 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller IDE (ICH9) */
265 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9) */
267 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
268 /* SATA Controller IDE (ICH9M) */
269 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
270 /* SATA Controller IDE (ICH9M) */
271 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
272 /* SATA Controller IDE (ICH9M) */
273 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
274 /* SATA Controller IDE (Tolapai) */
275 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
278 /* SATA Controller IDE (ICH10) */
279 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (ICH10) */
281 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (ICH10) */
283 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
284 /* SATA Controller IDE (PCH) */
285 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
286 /* SATA Controller IDE (PCH) */
287 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (PCH) */
289 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (PCH) */
291 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
296 { } /* terminate list */
297 };
298
299 static struct pci_driver piix_pci_driver = {
300 .name = DRV_NAME,
301 .id_table = piix_pci_tbl,
302 .probe = piix_init_one,
303 .remove = piix_remove_one,
304 #ifdef CONFIG_PM
305 .suspend = piix_pci_device_suspend,
306 .resume = piix_pci_device_resume,
307 #endif
308 };
309
310 static struct scsi_host_template piix_sht = {
311 ATA_BMDMA_SHT(DRV_NAME),
312 };
313
314 static struct ata_port_operations piix_pata_ops = {
315 .inherits = &ata_bmdma32_port_ops,
316 .cable_detect = ata_cable_40wire,
317 .set_piomode = piix_set_piomode,
318 .set_dmamode = piix_set_dmamode,
319 .prereset = piix_pata_prereset,
320 };
321
322 static struct ata_port_operations piix_vmw_ops = {
323 .inherits = &piix_pata_ops,
324 .bmdma_status = piix_vmw_bmdma_status,
325 };
326
327 static struct ata_port_operations ich_pata_ops = {
328 .inherits = &piix_pata_ops,
329 .cable_detect = ich_pata_cable_detect,
330 .set_dmamode = ich_set_dmamode,
331 };
332
333 static struct ata_port_operations piix_sata_ops = {
334 .inherits = &ata_bmdma_port_ops,
335 };
336
337 static struct ata_port_operations piix_sidpr_sata_ops = {
338 .inherits = &piix_sata_ops,
339 .hardreset = sata_std_hardreset,
340 .scr_read = piix_sidpr_scr_read,
341 .scr_write = piix_sidpr_scr_write,
342 };
343
344 static const struct piix_map_db ich5_map_db = {
345 .mask = 0x7,
346 .port_enable = 0x3,
347 .map = {
348 /* PM PS SM SS MAP */
349 { P0, NA, P1, NA }, /* 000b */
350 { P1, NA, P0, NA }, /* 001b */
351 { RV, RV, RV, RV },
352 { RV, RV, RV, RV },
353 { P0, P1, IDE, IDE }, /* 100b */
354 { P1, P0, IDE, IDE }, /* 101b */
355 { IDE, IDE, P0, P1 }, /* 110b */
356 { IDE, IDE, P1, P0 }, /* 111b */
357 },
358 };
359
360 static const struct piix_map_db ich6_map_db = {
361 .mask = 0x3,
362 .port_enable = 0xf,
363 .map = {
364 /* PM PS SM SS MAP */
365 { P0, P2, P1, P3 }, /* 00b */
366 { IDE, IDE, P1, P3 }, /* 01b */
367 { P0, P2, IDE, IDE }, /* 10b */
368 { RV, RV, RV, RV },
369 },
370 };
371
372 static const struct piix_map_db ich6m_map_db = {
373 .mask = 0x3,
374 .port_enable = 0x5,
375
376 /* Map 01b isn't specified in the doc but some notebooks use
377 * it anyway. MAP 01b have been spotted on both ICH6M and
378 * ICH7M.
379 */
380 .map = {
381 /* PM PS SM SS MAP */
382 { P0, P2, NA, NA }, /* 00b */
383 { IDE, IDE, P1, P3 }, /* 01b */
384 { P0, P2, IDE, IDE }, /* 10b */
385 { RV, RV, RV, RV },
386 },
387 };
388
389 static const struct piix_map_db ich8_map_db = {
390 .mask = 0x3,
391 .port_enable = 0xf,
392 .map = {
393 /* PM PS SM SS MAP */
394 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
395 { RV, RV, RV, RV },
396 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
397 { RV, RV, RV, RV },
398 },
399 };
400
401 static const struct piix_map_db ich8_2port_map_db = {
402 .mask = 0x3,
403 .port_enable = 0x3,
404 .map = {
405 /* PM PS SM SS MAP */
406 { P0, NA, P1, NA }, /* 00b */
407 { RV, RV, RV, RV }, /* 01b */
408 { RV, RV, RV, RV }, /* 10b */
409 { RV, RV, RV, RV },
410 },
411 };
412
413 static const struct piix_map_db ich8m_apple_map_db = {
414 .mask = 0x3,
415 .port_enable = 0x1,
416 .map = {
417 /* PM PS SM SS MAP */
418 { P0, NA, NA, NA }, /* 00b */
419 { RV, RV, RV, RV },
420 { P0, P2, IDE, IDE }, /* 10b */
421 { RV, RV, RV, RV },
422 },
423 };
424
425 static const struct piix_map_db tolapai_map_db = {
426 .mask = 0x3,
427 .port_enable = 0x3,
428 .map = {
429 /* PM PS SM SS MAP */
430 { P0, NA, P1, NA }, /* 00b */
431 { RV, RV, RV, RV }, /* 01b */
432 { RV, RV, RV, RV }, /* 10b */
433 { RV, RV, RV, RV },
434 },
435 };
436
437 static const struct piix_map_db *piix_map_db_table[] = {
438 [ich5_sata] = &ich5_map_db,
439 [ich6_sata] = &ich6_map_db,
440 [ich6m_sata] = &ich6m_map_db,
441 [ich8_sata] = &ich8_map_db,
442 [ich8_2port_sata] = &ich8_2port_map_db,
443 [ich8m_apple_sata] = &ich8m_apple_map_db,
444 [tolapai_sata] = &tolapai_map_db,
445 };
446
447 static struct ata_port_info piix_port_info[] = {
448 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
449 {
450 .flags = PIIX_PATA_FLAGS,
451 .pio_mask = ATA_PIO4,
452 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
453 .port_ops = &piix_pata_ops,
454 },
455
456 [piix_pata_33] = /* PIIX4 at 33MHz */
457 {
458 .flags = PIIX_PATA_FLAGS,
459 .pio_mask = ATA_PIO4,
460 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
461 .udma_mask = ATA_UDMA2,
462 .port_ops = &piix_pata_ops,
463 },
464
465 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
466 {
467 .flags = PIIX_PATA_FLAGS,
468 .pio_mask = ATA_PIO4,
469 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
470 .udma_mask = ATA_UDMA2,
471 .port_ops = &ich_pata_ops,
472 },
473
474 [ich_pata_66] = /* ICH controllers up to 66MHz */
475 {
476 .flags = PIIX_PATA_FLAGS,
477 .pio_mask = ATA_PIO4,
478 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
479 .udma_mask = ATA_UDMA4,
480 .port_ops = &ich_pata_ops,
481 },
482
483 [ich_pata_100] =
484 {
485 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
486 .pio_mask = ATA_PIO4,
487 .mwdma_mask = ATA_MWDMA12_ONLY,
488 .udma_mask = ATA_UDMA5,
489 .port_ops = &ich_pata_ops,
490 },
491
492 [ich_pata_100_nomwdma1] =
493 {
494 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
495 .pio_mask = ATA_PIO4,
496 .mwdma_mask = ATA_MWDMA2_ONLY,
497 .udma_mask = ATA_UDMA5,
498 .port_ops = &ich_pata_ops,
499 },
500
501 [ich5_sata] =
502 {
503 .flags = PIIX_SATA_FLAGS,
504 .pio_mask = ATA_PIO4,
505 .mwdma_mask = ATA_MWDMA2,
506 .udma_mask = ATA_UDMA6,
507 .port_ops = &piix_sata_ops,
508 },
509
510 [ich6_sata] =
511 {
512 .flags = PIIX_SATA_FLAGS,
513 .pio_mask = ATA_PIO4,
514 .mwdma_mask = ATA_MWDMA2,
515 .udma_mask = ATA_UDMA6,
516 .port_ops = &piix_sata_ops,
517 },
518
519 [ich6m_sata] =
520 {
521 .flags = PIIX_SATA_FLAGS,
522 .pio_mask = ATA_PIO4,
523 .mwdma_mask = ATA_MWDMA2,
524 .udma_mask = ATA_UDMA6,
525 .port_ops = &piix_sata_ops,
526 },
527
528 [ich8_sata] =
529 {
530 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
531 .pio_mask = ATA_PIO4,
532 .mwdma_mask = ATA_MWDMA2,
533 .udma_mask = ATA_UDMA6,
534 .port_ops = &piix_sata_ops,
535 },
536
537 [ich8_2port_sata] =
538 {
539 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
540 .pio_mask = ATA_PIO4,
541 .mwdma_mask = ATA_MWDMA2,
542 .udma_mask = ATA_UDMA6,
543 .port_ops = &piix_sata_ops,
544 },
545
546 [tolapai_sata] =
547 {
548 .flags = PIIX_SATA_FLAGS,
549 .pio_mask = ATA_PIO4,
550 .mwdma_mask = ATA_MWDMA2,
551 .udma_mask = ATA_UDMA6,
552 .port_ops = &piix_sata_ops,
553 },
554
555 [ich8m_apple_sata] =
556 {
557 .flags = PIIX_SATA_FLAGS,
558 .pio_mask = ATA_PIO4,
559 .mwdma_mask = ATA_MWDMA2,
560 .udma_mask = ATA_UDMA6,
561 .port_ops = &piix_sata_ops,
562 },
563
564 [piix_pata_vmw] =
565 {
566 .flags = PIIX_PATA_FLAGS,
567 .pio_mask = ATA_PIO4,
568 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
569 .udma_mask = ATA_UDMA2,
570 .port_ops = &piix_vmw_ops,
571 },
572
573 };
574
575 static struct pci_bits piix_enable_bits[] = {
576 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
577 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
578 };
579
580 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
581 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
582 MODULE_LICENSE("GPL");
583 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
584 MODULE_VERSION(DRV_VERSION);
585
586 struct ich_laptop {
587 u16 device;
588 u16 subvendor;
589 u16 subdevice;
590 };
591
592 /*
593 * List of laptops that use short cables rather than 80 wire
594 */
595
596 static const struct ich_laptop ich_laptop[] = {
597 /* devid, subvendor, subdev */
598 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
599 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
600 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
601 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
602 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
603 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
604 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
605 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
606 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
607 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
608 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
609 /* end marker */
610 { 0, }
611 };
612
613 /**
614 * ich_pata_cable_detect - Probe host controller cable detect info
615 * @ap: Port for which cable detect info is desired
616 *
617 * Read 80c cable indicator from ATA PCI device's PCI config
618 * register. This register is normally set by firmware (BIOS).
619 *
620 * LOCKING:
621 * None (inherited from caller).
622 */
623
624 static int ich_pata_cable_detect(struct ata_port *ap)
625 {
626 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
627 struct piix_host_priv *hpriv = ap->host->private_data;
628 const struct ich_laptop *lap = &ich_laptop[0];
629 u8 mask;
630
631 /* Check for specials - Acer Aspire 5602WLMi */
632 while (lap->device) {
633 if (lap->device == pdev->device &&
634 lap->subvendor == pdev->subsystem_vendor &&
635 lap->subdevice == pdev->subsystem_device)
636 return ATA_CBL_PATA40_SHORT;
637
638 lap++;
639 }
640
641 /* check BIOS cable detect results */
642 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
643 if ((hpriv->saved_iocfg & mask) == 0)
644 return ATA_CBL_PATA40;
645 return ATA_CBL_PATA80;
646 }
647
648 /**
649 * piix_pata_prereset - prereset for PATA host controller
650 * @link: Target link
651 * @deadline: deadline jiffies for the operation
652 *
653 * LOCKING:
654 * None (inherited from caller).
655 */
656 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
657 {
658 struct ata_port *ap = link->ap;
659 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
660
661 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
662 return -ENOENT;
663 return ata_sff_prereset(link, deadline);
664 }
665
666 /**
667 * piix_set_piomode - Initialize host controller PATA PIO timings
668 * @ap: Port whose timings we are configuring
669 * @adev: um
670 *
671 * Set PIO mode for device, in host controller PCI config space.
672 *
673 * LOCKING:
674 * None (inherited from caller).
675 */
676
677 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
678 {
679 unsigned int pio = adev->pio_mode - XFER_PIO_0;
680 struct pci_dev *dev = to_pci_dev(ap->host->dev);
681 unsigned int is_slave = (adev->devno != 0);
682 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
683 unsigned int slave_port = 0x44;
684 u16 master_data;
685 u8 slave_data;
686 u8 udma_enable;
687 int control = 0;
688
689 /*
690 * See Intel Document 298600-004 for the timing programing rules
691 * for ICH controllers.
692 */
693
694 static const /* ISP RTC */
695 u8 timings[][2] = { { 0, 0 },
696 { 0, 0 },
697 { 1, 0 },
698 { 2, 1 },
699 { 2, 3 }, };
700
701 if (pio >= 2)
702 control |= 1; /* TIME1 enable */
703 if (ata_pio_need_iordy(adev))
704 control |= 2; /* IE enable */
705
706 /* Intel specifies that the PPE functionality is for disk only */
707 if (adev->class == ATA_DEV_ATA)
708 control |= 4; /* PPE enable */
709
710 /* PIO configuration clears DTE unconditionally. It will be
711 * programmed in set_dmamode which is guaranteed to be called
712 * after set_piomode if any DMA mode is available.
713 */
714 pci_read_config_word(dev, master_port, &master_data);
715 if (is_slave) {
716 /* clear TIME1|IE1|PPE1|DTE1 */
717 master_data &= 0xff0f;
718 /* Enable SITRE (separate slave timing register) */
719 master_data |= 0x4000;
720 /* enable PPE1, IE1 and TIME1 as needed */
721 master_data |= (control << 4);
722 pci_read_config_byte(dev, slave_port, &slave_data);
723 slave_data &= (ap->port_no ? 0x0f : 0xf0);
724 /* Load the timing nibble for this slave */
725 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
726 << (ap->port_no ? 4 : 0);
727 } else {
728 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
729 master_data &= 0xccf0;
730 /* Enable PPE, IE and TIME as appropriate */
731 master_data |= control;
732 /* load ISP and RCT */
733 master_data |=
734 (timings[pio][0] << 12) |
735 (timings[pio][1] << 8);
736 }
737 pci_write_config_word(dev, master_port, master_data);
738 if (is_slave)
739 pci_write_config_byte(dev, slave_port, slave_data);
740
741 /* Ensure the UDMA bit is off - it will be turned back on if
742 UDMA is selected */
743
744 if (ap->udma_mask) {
745 pci_read_config_byte(dev, 0x48, &udma_enable);
746 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
747 pci_write_config_byte(dev, 0x48, udma_enable);
748 }
749 }
750
751 /**
752 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
753 * @ap: Port whose timings we are configuring
754 * @adev: Drive in question
755 * @isich: set if the chip is an ICH device
756 *
757 * Set UDMA mode for device, in host controller PCI config space.
758 *
759 * LOCKING:
760 * None (inherited from caller).
761 */
762
763 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
764 {
765 struct pci_dev *dev = to_pci_dev(ap->host->dev);
766 u8 master_port = ap->port_no ? 0x42 : 0x40;
767 u16 master_data;
768 u8 speed = adev->dma_mode;
769 int devid = adev->devno + 2 * ap->port_no;
770 u8 udma_enable = 0;
771
772 static const /* ISP RTC */
773 u8 timings[][2] = { { 0, 0 },
774 { 0, 0 },
775 { 1, 0 },
776 { 2, 1 },
777 { 2, 3 }, };
778
779 pci_read_config_word(dev, master_port, &master_data);
780 if (ap->udma_mask)
781 pci_read_config_byte(dev, 0x48, &udma_enable);
782
783 if (speed >= XFER_UDMA_0) {
784 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
785 u16 udma_timing;
786 u16 ideconf;
787 int u_clock, u_speed;
788
789 /*
790 * UDMA is handled by a combination of clock switching and
791 * selection of dividers
792 *
793 * Handy rule: Odd modes are UDMATIMx 01, even are 02
794 * except UDMA0 which is 00
795 */
796 u_speed = min(2 - (udma & 1), udma);
797 if (udma == 5)
798 u_clock = 0x1000; /* 100Mhz */
799 else if (udma > 2)
800 u_clock = 1; /* 66Mhz */
801 else
802 u_clock = 0; /* 33Mhz */
803
804 udma_enable |= (1 << devid);
805
806 /* Load the CT/RP selection */
807 pci_read_config_word(dev, 0x4A, &udma_timing);
808 udma_timing &= ~(3 << (4 * devid));
809 udma_timing |= u_speed << (4 * devid);
810 pci_write_config_word(dev, 0x4A, udma_timing);
811
812 if (isich) {
813 /* Select a 33/66/100Mhz clock */
814 pci_read_config_word(dev, 0x54, &ideconf);
815 ideconf &= ~(0x1001 << devid);
816 ideconf |= u_clock << devid;
817 /* For ICH or later we should set bit 10 for better
818 performance (WR_PingPong_En) */
819 pci_write_config_word(dev, 0x54, ideconf);
820 }
821 } else {
822 /*
823 * MWDMA is driven by the PIO timings. We must also enable
824 * IORDY unconditionally along with TIME1. PPE has already
825 * been set when the PIO timing was set.
826 */
827 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
828 unsigned int control;
829 u8 slave_data;
830 const unsigned int needed_pio[3] = {
831 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
832 };
833 int pio = needed_pio[mwdma] - XFER_PIO_0;
834
835 control = 3; /* IORDY|TIME1 */
836
837 /* If the drive MWDMA is faster than it can do PIO then
838 we must force PIO into PIO0 */
839
840 if (adev->pio_mode < needed_pio[mwdma])
841 /* Enable DMA timing only */
842 control |= 8; /* PIO cycles in PIO0 */
843
844 if (adev->devno) { /* Slave */
845 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
846 master_data |= control << 4;
847 pci_read_config_byte(dev, 0x44, &slave_data);
848 slave_data &= (ap->port_no ? 0x0f : 0xf0);
849 /* Load the matching timing */
850 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
851 pci_write_config_byte(dev, 0x44, slave_data);
852 } else { /* Master */
853 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
854 and master timing bits */
855 master_data |= control;
856 master_data |=
857 (timings[pio][0] << 12) |
858 (timings[pio][1] << 8);
859 }
860
861 if (ap->udma_mask) {
862 udma_enable &= ~(1 << devid);
863 pci_write_config_word(dev, master_port, master_data);
864 }
865 }
866 /* Don't scribble on 0x48 if the controller does not support UDMA */
867 if (ap->udma_mask)
868 pci_write_config_byte(dev, 0x48, udma_enable);
869 }
870
871 /**
872 * piix_set_dmamode - Initialize host controller PATA DMA timings
873 * @ap: Port whose timings we are configuring
874 * @adev: um
875 *
876 * Set MW/UDMA mode for device, in host controller PCI config space.
877 *
878 * LOCKING:
879 * None (inherited from caller).
880 */
881
882 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
883 {
884 do_pata_set_dmamode(ap, adev, 0);
885 }
886
887 /**
888 * ich_set_dmamode - Initialize host controller PATA DMA timings
889 * @ap: Port whose timings we are configuring
890 * @adev: um
891 *
892 * Set MW/UDMA mode for device, in host controller PCI config space.
893 *
894 * LOCKING:
895 * None (inherited from caller).
896 */
897
898 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
899 {
900 do_pata_set_dmamode(ap, adev, 1);
901 }
902
903 /*
904 * Serial ATA Index/Data Pair Superset Registers access
905 *
906 * Beginning from ICH8, there's a sane way to access SCRs using index
907 * and data register pair located at BAR5 which means that we have
908 * separate SCRs for master and slave. This is handled using libata
909 * slave_link facility.
910 */
911 static const int piix_sidx_map[] = {
912 [SCR_STATUS] = 0,
913 [SCR_ERROR] = 2,
914 [SCR_CONTROL] = 1,
915 };
916
917 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
918 {
919 struct ata_port *ap = link->ap;
920 struct piix_host_priv *hpriv = ap->host->private_data;
921
922 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
923 hpriv->sidpr + PIIX_SIDPR_IDX);
924 }
925
926 static int piix_sidpr_scr_read(struct ata_link *link,
927 unsigned int reg, u32 *val)
928 {
929 struct piix_host_priv *hpriv = link->ap->host->private_data;
930
931 if (reg >= ARRAY_SIZE(piix_sidx_map))
932 return -EINVAL;
933
934 piix_sidpr_sel(link, reg);
935 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
936 return 0;
937 }
938
939 static int piix_sidpr_scr_write(struct ata_link *link,
940 unsigned int reg, u32 val)
941 {
942 struct piix_host_priv *hpriv = link->ap->host->private_data;
943
944 if (reg >= ARRAY_SIZE(piix_sidx_map))
945 return -EINVAL;
946
947 piix_sidpr_sel(link, reg);
948 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
949 return 0;
950 }
951
952 #ifdef CONFIG_PM
953 static int piix_broken_suspend(void)
954 {
955 static const struct dmi_system_id sysids[] = {
956 {
957 .ident = "TECRA M3",
958 .matches = {
959 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
960 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
961 },
962 },
963 {
964 .ident = "TECRA M3",
965 .matches = {
966 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
967 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
968 },
969 },
970 {
971 .ident = "TECRA M4",
972 .matches = {
973 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
974 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
975 },
976 },
977 {
978 .ident = "TECRA M4",
979 .matches = {
980 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
981 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
982 },
983 },
984 {
985 .ident = "TECRA M5",
986 .matches = {
987 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
988 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
989 },
990 },
991 {
992 .ident = "TECRA M6",
993 .matches = {
994 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
995 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
996 },
997 },
998 {
999 .ident = "TECRA M7",
1000 .matches = {
1001 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1002 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1003 },
1004 },
1005 {
1006 .ident = "TECRA A8",
1007 .matches = {
1008 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1009 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1010 },
1011 },
1012 {
1013 .ident = "Satellite R20",
1014 .matches = {
1015 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1016 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1017 },
1018 },
1019 {
1020 .ident = "Satellite R25",
1021 .matches = {
1022 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1023 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1024 },
1025 },
1026 {
1027 .ident = "Satellite U200",
1028 .matches = {
1029 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1030 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1031 },
1032 },
1033 {
1034 .ident = "Satellite U200",
1035 .matches = {
1036 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1037 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1038 },
1039 },
1040 {
1041 .ident = "Satellite Pro U200",
1042 .matches = {
1043 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1044 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1045 },
1046 },
1047 {
1048 .ident = "Satellite U205",
1049 .matches = {
1050 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1051 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1052 },
1053 },
1054 {
1055 .ident = "SATELLITE U205",
1056 .matches = {
1057 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1058 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1059 },
1060 },
1061 {
1062 .ident = "Portege M500",
1063 .matches = {
1064 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1065 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1066 },
1067 },
1068 {
1069 .ident = "VGN-BX297XP",
1070 .matches = {
1071 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1072 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1073 },
1074 },
1075
1076 { } /* terminate list */
1077 };
1078 static const char *oemstrs[] = {
1079 "Tecra M3,",
1080 };
1081 int i;
1082
1083 if (dmi_check_system(sysids))
1084 return 1;
1085
1086 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1087 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1088 return 1;
1089
1090 /* TECRA M4 sometimes forgets its identify and reports bogus
1091 * DMI information. As the bogus information is a bit
1092 * generic, match as many entries as possible. This manual
1093 * matching is necessary because dmi_system_id.matches is
1094 * limited to four entries.
1095 */
1096 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1097 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1098 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1099 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1100 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1101 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1102 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1103 return 1;
1104
1105 return 0;
1106 }
1107
1108 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1109 {
1110 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1111 unsigned long flags;
1112 int rc = 0;
1113
1114 rc = ata_host_suspend(host, mesg);
1115 if (rc)
1116 return rc;
1117
1118 /* Some braindamaged ACPI suspend implementations expect the
1119 * controller to be awake on entry; otherwise, it burns cpu
1120 * cycles and power trying to do something to the sleeping
1121 * beauty.
1122 */
1123 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1124 pci_save_state(pdev);
1125
1126 /* mark its power state as "unknown", since we don't
1127 * know if e.g. the BIOS will change its device state
1128 * when we suspend.
1129 */
1130 if (pdev->current_state == PCI_D0)
1131 pdev->current_state = PCI_UNKNOWN;
1132
1133 /* tell resume that it's waking up from broken suspend */
1134 spin_lock_irqsave(&host->lock, flags);
1135 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1136 spin_unlock_irqrestore(&host->lock, flags);
1137 } else
1138 ata_pci_device_do_suspend(pdev, mesg);
1139
1140 return 0;
1141 }
1142
1143 static int piix_pci_device_resume(struct pci_dev *pdev)
1144 {
1145 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1146 unsigned long flags;
1147 int rc;
1148
1149 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1150 spin_lock_irqsave(&host->lock, flags);
1151 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1152 spin_unlock_irqrestore(&host->lock, flags);
1153
1154 pci_set_power_state(pdev, PCI_D0);
1155 pci_restore_state(pdev);
1156
1157 /* PCI device wasn't disabled during suspend. Use
1158 * pci_reenable_device() to avoid affecting the enable
1159 * count.
1160 */
1161 rc = pci_reenable_device(pdev);
1162 if (rc)
1163 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1164 "device after resume (%d)\n", rc);
1165 } else
1166 rc = ata_pci_device_do_resume(pdev);
1167
1168 if (rc == 0)
1169 ata_host_resume(host);
1170
1171 return rc;
1172 }
1173 #endif
1174
1175 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1176 {
1177 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1178 }
1179
1180 #define AHCI_PCI_BAR 5
1181 #define AHCI_GLOBAL_CTL 0x04
1182 #define AHCI_ENABLE (1 << 31)
1183 static int piix_disable_ahci(struct pci_dev *pdev)
1184 {
1185 void __iomem *mmio;
1186 u32 tmp;
1187 int rc = 0;
1188
1189 /* BUG: pci_enable_device has not yet been called. This
1190 * works because this device is usually set up by BIOS.
1191 */
1192
1193 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1194 !pci_resource_len(pdev, AHCI_PCI_BAR))
1195 return 0;
1196
1197 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1198 if (!mmio)
1199 return -ENOMEM;
1200
1201 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1202 if (tmp & AHCI_ENABLE) {
1203 tmp &= ~AHCI_ENABLE;
1204 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1205
1206 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1207 if (tmp & AHCI_ENABLE)
1208 rc = -EIO;
1209 }
1210
1211 pci_iounmap(pdev, mmio);
1212 return rc;
1213 }
1214
1215 /**
1216 * piix_check_450nx_errata - Check for problem 450NX setup
1217 * @ata_dev: the PCI device to check
1218 *
1219 * Check for the present of 450NX errata #19 and errata #25. If
1220 * they are found return an error code so we can turn off DMA
1221 */
1222
1223 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1224 {
1225 struct pci_dev *pdev = NULL;
1226 u16 cfg;
1227 int no_piix_dma = 0;
1228
1229 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1230 /* Look for 450NX PXB. Check for problem configurations
1231 A PCI quirk checks bit 6 already */
1232 pci_read_config_word(pdev, 0x41, &cfg);
1233 /* Only on the original revision: IDE DMA can hang */
1234 if (pdev->revision == 0x00)
1235 no_piix_dma = 1;
1236 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1237 else if (cfg & (1<<14) && pdev->revision < 5)
1238 no_piix_dma = 2;
1239 }
1240 if (no_piix_dma)
1241 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1242 if (no_piix_dma == 2)
1243 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1244 return no_piix_dma;
1245 }
1246
1247 static void __devinit piix_init_pcs(struct ata_host *host,
1248 const struct piix_map_db *map_db)
1249 {
1250 struct pci_dev *pdev = to_pci_dev(host->dev);
1251 u16 pcs, new_pcs;
1252
1253 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1254
1255 new_pcs = pcs | map_db->port_enable;
1256
1257 if (new_pcs != pcs) {
1258 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1259 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1260 msleep(150);
1261 }
1262 }
1263
1264 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1265 struct ata_port_info *pinfo,
1266 const struct piix_map_db *map_db)
1267 {
1268 const int *map;
1269 int i, invalid_map = 0;
1270 u8 map_value;
1271
1272 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1273
1274 map = map_db->map[map_value & map_db->mask];
1275
1276 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1277 for (i = 0; i < 4; i++) {
1278 switch (map[i]) {
1279 case RV:
1280 invalid_map = 1;
1281 printk(" XX");
1282 break;
1283
1284 case NA:
1285 printk(" --");
1286 break;
1287
1288 case IDE:
1289 WARN_ON((i & 1) || map[i + 1] != IDE);
1290 pinfo[i / 2] = piix_port_info[ich_pata_100];
1291 i++;
1292 printk(" IDE IDE");
1293 break;
1294
1295 default:
1296 printk(" P%d", map[i]);
1297 if (i & 1)
1298 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1299 break;
1300 }
1301 }
1302 printk(" ]\n");
1303
1304 if (invalid_map)
1305 dev_printk(KERN_ERR, &pdev->dev,
1306 "invalid MAP value %u\n", map_value);
1307
1308 return map;
1309 }
1310
1311 static bool piix_no_sidpr(struct ata_host *host)
1312 {
1313 struct pci_dev *pdev = to_pci_dev(host->dev);
1314
1315 /*
1316 * Samsung DB-P70 only has three ATA ports exposed and
1317 * curiously the unconnected first port reports link online
1318 * while not responding to SRST protocol causing excessive
1319 * detection delay.
1320 *
1321 * Unfortunately, the system doesn't carry enough DMI
1322 * information to identify the machine but does have subsystem
1323 * vendor and device set. As it's unclear whether the
1324 * subsystem vendor/device is used only for this specific
1325 * board, the port can't be disabled solely with the
1326 * information; however, turning off SIDPR access works around
1327 * the problem. Turn it off.
1328 *
1329 * This problem is reported in bnc#441240.
1330 *
1331 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1332 */
1333 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1334 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1335 pdev->subsystem_device == 0xb049) {
1336 dev_printk(KERN_WARNING, host->dev,
1337 "Samsung DB-P70 detected, disabling SIDPR\n");
1338 return true;
1339 }
1340
1341 return false;
1342 }
1343
1344 static int __devinit piix_init_sidpr(struct ata_host *host)
1345 {
1346 struct pci_dev *pdev = to_pci_dev(host->dev);
1347 struct piix_host_priv *hpriv = host->private_data;
1348 struct ata_link *link0 = &host->ports[0]->link;
1349 u32 scontrol;
1350 int i, rc;
1351
1352 /* check for availability */
1353 for (i = 0; i < 4; i++)
1354 if (hpriv->map[i] == IDE)
1355 return 0;
1356
1357 /* is it blacklisted? */
1358 if (piix_no_sidpr(host))
1359 return 0;
1360
1361 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1362 return 0;
1363
1364 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1365 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1366 return 0;
1367
1368 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1369 return 0;
1370
1371 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1372
1373 /* SCR access via SIDPR doesn't work on some configurations.
1374 * Give it a test drive by inhibiting power save modes which
1375 * we'll do anyway.
1376 */
1377 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1378
1379 /* if IPM is already 3, SCR access is probably working. Don't
1380 * un-inhibit power save modes as BIOS might have inhibited
1381 * them for a reason.
1382 */
1383 if ((scontrol & 0xf00) != 0x300) {
1384 scontrol |= 0x300;
1385 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1386 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1387
1388 if ((scontrol & 0xf00) != 0x300) {
1389 dev_printk(KERN_INFO, host->dev, "SCR access via "
1390 "SIDPR is available but doesn't work\n");
1391 return 0;
1392 }
1393 }
1394
1395 /* okay, SCRs available, set ops and ask libata for slave_link */
1396 for (i = 0; i < 2; i++) {
1397 struct ata_port *ap = host->ports[i];
1398
1399 ap->ops = &piix_sidpr_sata_ops;
1400
1401 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1402 rc = ata_slave_link_init(ap);
1403 if (rc)
1404 return rc;
1405 }
1406 }
1407
1408 return 0;
1409 }
1410
1411 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1412 {
1413 static const struct dmi_system_id sysids[] = {
1414 {
1415 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1416 * isn't used to boot the system which
1417 * disables the channel.
1418 */
1419 .ident = "M570U",
1420 .matches = {
1421 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1422 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1423 },
1424 },
1425
1426 { } /* terminate list */
1427 };
1428 struct pci_dev *pdev = to_pci_dev(host->dev);
1429 struct piix_host_priv *hpriv = host->private_data;
1430
1431 if (!dmi_check_system(sysids))
1432 return;
1433
1434 /* The datasheet says that bit 18 is NOOP but certain systems
1435 * seem to use it to disable a channel. Clear the bit on the
1436 * affected systems.
1437 */
1438 if (hpriv->saved_iocfg & (1 << 18)) {
1439 dev_printk(KERN_INFO, &pdev->dev,
1440 "applying IOCFG bit18 quirk\n");
1441 pci_write_config_dword(pdev, PIIX_IOCFG,
1442 hpriv->saved_iocfg & ~(1 << 18));
1443 }
1444 }
1445
1446 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1447 {
1448 static const struct dmi_system_id broken_systems[] = {
1449 {
1450 .ident = "HP Compaq 2510p",
1451 .matches = {
1452 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1453 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1454 },
1455 /* PCI slot number of the controller */
1456 .driver_data = (void *)0x1FUL,
1457 },
1458 {
1459 .ident = "HP Compaq nc6000",
1460 .matches = {
1461 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1462 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1463 },
1464 /* PCI slot number of the controller */
1465 .driver_data = (void *)0x1FUL,
1466 },
1467
1468 { } /* terminate list */
1469 };
1470 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1471
1472 if (dmi) {
1473 unsigned long slot = (unsigned long)dmi->driver_data;
1474 /* apply the quirk only to on-board controllers */
1475 return slot == PCI_SLOT(pdev->devfn);
1476 }
1477
1478 return false;
1479 }
1480
1481 /**
1482 * piix_init_one - Register PIIX ATA PCI device with kernel services
1483 * @pdev: PCI device to register
1484 * @ent: Entry in piix_pci_tbl matching with @pdev
1485 *
1486 * Called from kernel PCI layer. We probe for combined mode (sigh),
1487 * and then hand over control to libata, for it to do the rest.
1488 *
1489 * LOCKING:
1490 * Inherited from PCI layer (may sleep).
1491 *
1492 * RETURNS:
1493 * Zero on success, or -ERRNO value.
1494 */
1495
1496 static int __devinit piix_init_one(struct pci_dev *pdev,
1497 const struct pci_device_id *ent)
1498 {
1499 static int printed_version;
1500 struct device *dev = &pdev->dev;
1501 struct ata_port_info port_info[2];
1502 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1503 unsigned long port_flags;
1504 struct ata_host *host;
1505 struct piix_host_priv *hpriv;
1506 int rc;
1507
1508 if (!printed_version++)
1509 dev_printk(KERN_DEBUG, &pdev->dev,
1510 "version " DRV_VERSION "\n");
1511
1512 /* no hotplugging support (FIXME) */
1513 if (!in_module_init)
1514 return -ENODEV;
1515
1516 if (piix_broken_system_poweroff(pdev)) {
1517 piix_port_info[ent->driver_data].flags |=
1518 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1519 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1520 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1521 "on poweroff and hibernation\n");
1522 }
1523
1524 port_info[0] = piix_port_info[ent->driver_data];
1525 port_info[1] = piix_port_info[ent->driver_data];
1526
1527 port_flags = port_info[0].flags;
1528
1529 /* enable device and prepare host */
1530 rc = pcim_enable_device(pdev);
1531 if (rc)
1532 return rc;
1533
1534 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1535 if (!hpriv)
1536 return -ENOMEM;
1537
1538 /* Save IOCFG, this will be used for cable detection, quirk
1539 * detection and restoration on detach. This is necessary
1540 * because some ACPI implementations mess up cable related
1541 * bits on _STM. Reported on kernel bz#11879.
1542 */
1543 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1544
1545 /* ICH6R may be driven by either ata_piix or ahci driver
1546 * regardless of BIOS configuration. Make sure AHCI mode is
1547 * off.
1548 */
1549 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1550 rc = piix_disable_ahci(pdev);
1551 if (rc)
1552 return rc;
1553 }
1554
1555 /* SATA map init can change port_info, do it before prepping host */
1556 if (port_flags & ATA_FLAG_SATA)
1557 hpriv->map = piix_init_sata_map(pdev, port_info,
1558 piix_map_db_table[ent->driver_data]);
1559
1560 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1561 if (rc)
1562 return rc;
1563 host->private_data = hpriv;
1564
1565 /* initialize controller */
1566 if (port_flags & ATA_FLAG_SATA) {
1567 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1568 rc = piix_init_sidpr(host);
1569 if (rc)
1570 return rc;
1571 }
1572
1573 /* apply IOCFG bit18 quirk */
1574 piix_iocfg_bit18_quirk(host);
1575
1576 /* On ICH5, some BIOSen disable the interrupt using the
1577 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1578 * On ICH6, this bit has the same effect, but only when
1579 * MSI is disabled (and it is disabled, as we don't use
1580 * message-signalled interrupts currently).
1581 */
1582 if (port_flags & PIIX_FLAG_CHECKINTR)
1583 pci_intx(pdev, 1);
1584
1585 if (piix_check_450nx_errata(pdev)) {
1586 /* This writes into the master table but it does not
1587 really matter for this errata as we will apply it to
1588 all the PIIX devices on the board */
1589 host->ports[0]->mwdma_mask = 0;
1590 host->ports[0]->udma_mask = 0;
1591 host->ports[1]->mwdma_mask = 0;
1592 host->ports[1]->udma_mask = 0;
1593 }
1594
1595 pci_set_master(pdev);
1596 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1597 }
1598
1599 static void piix_remove_one(struct pci_dev *pdev)
1600 {
1601 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1602 struct piix_host_priv *hpriv = host->private_data;
1603
1604 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1605
1606 ata_pci_remove_one(pdev);
1607 }
1608
1609 static int __init piix_init(void)
1610 {
1611 int rc;
1612
1613 DPRINTK("pci_register_driver\n");
1614 rc = pci_register_driver(&piix_pci_driver);
1615 if (rc)
1616 return rc;
1617
1618 in_module_init = 0;
1619
1620 DPRINTK("done\n");
1621 return 0;
1622 }
1623
1624 static void __exit piix_exit(void)
1625 {
1626 pci_unregister_driver(&piix_pci_driver);
1627 }
1628
1629 module_init(piix_init);
1630 module_exit(piix_exit);
Support for the Chinese Samsung S3C2440 based development boards