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V4L/DVB (12506): soc-camera: convert to platform device
[linux-2.6/mini2440.git] / drivers / media / video / ov772x.c
blob3ea650d55b17242c9fb9c012a3717481caaa0396
1 /*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/videodev2.h>
24 #include <media/v4l2-chip-ident.h>
25 #include <media/v4l2-common.h>
26 #include <media/soc_camera.h>
27 #include <media/ov772x.h>
28
29 /*
30 * register offset
31 */
32 #define GAIN 0x00 /* AGC - Gain control gain setting */
33 #define BLUE 0x01 /* AWB - Blue channel gain setting */
34 #define RED 0x02 /* AWB - Red channel gain setting */
35 #define GREEN 0x03 /* AWB - Green channel gain setting */
36 #define COM1 0x04 /* Common control 1 */
37 #define BAVG 0x05 /* U/B Average Level */
38 #define GAVG 0x06 /* Y/Gb Average Level */
39 #define RAVG 0x07 /* V/R Average Level */
40 #define AECH 0x08 /* Exposure Value - AEC MSBs */
41 #define COM2 0x09 /* Common control 2 */
42 #define PID 0x0A /* Product ID Number MSB */
43 #define VER 0x0B /* Product ID Number LSB */
44 #define COM3 0x0C /* Common control 3 */
45 #define COM4 0x0D /* Common control 4 */
46 #define COM5 0x0E /* Common control 5 */
47 #define COM6 0x0F /* Common control 6 */
48 #define AEC 0x10 /* Exposure Value */
49 #define CLKRC 0x11 /* Internal clock */
50 #define COM7 0x12 /* Common control 7 */
51 #define COM8 0x13 /* Common control 8 */
52 #define COM9 0x14 /* Common control 9 */
53 #define COM10 0x15 /* Common control 10 */
54 #define REG16 0x16 /* Register 16 */
55 #define HSTART 0x17 /* Horizontal sensor size */
56 #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
57 #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
58 #define VSIZE 0x1A /* Vertical sensor size */
59 #define PSHFT 0x1B /* Data format - pixel delay select */
60 #define MIDH 0x1C /* Manufacturer ID byte - high */
61 #define MIDL 0x1D /* Manufacturer ID byte - low */
62 #define LAEC 0x1F /* Fine AEC value */
63 #define COM11 0x20 /* Common control 11 */
64 #define BDBASE 0x22 /* Banding filter Minimum AEC value */
65 #define DBSTEP 0x23 /* Banding filter Maximum Setp */
66 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
67 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
68 #define VPT 0x26 /* AGC/AEC Fast mode operating region */
69 #define REG28 0x28 /* Register 28 */
70 #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
71 #define EXHCH 0x2A /* Dummy pixel insert MSB */
72 #define EXHCL 0x2B /* Dummy pixel insert LSB */
73 #define VOUTSIZE 0x2C /* Vertical data output size MSBs */
74 #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
75 #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
76 #define YAVE 0x2F /* Y/G Channel Average value */
77 #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
78 #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
79 #define HREF 0x32 /* Image start and size control */
80 #define DM_LNL 0x33 /* Dummy line low 8 bits */
81 #define DM_LNH 0x34 /* Dummy line high 8 bits */
82 #define ADOFF_B 0x35 /* AD offset compensation value for B channel */
83 #define ADOFF_R 0x36 /* AD offset compensation value for R channel */
84 #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
85 #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
86 #define OFF_B 0x39 /* Analog process B channel offset value */
87 #define OFF_R 0x3A /* Analog process R channel offset value */
88 #define OFF_GB 0x3B /* Analog process Gb channel offset value */
89 #define OFF_GR 0x3C /* Analog process Gr channel offset value */
90 #define COM12 0x3D /* Common control 12 */
91 #define COM13 0x3E /* Common control 13 */
92 #define COM14 0x3F /* Common control 14 */
93 #define COM15 0x40 /* Common control 15*/
94 #define COM16 0x41 /* Common control 16 */
95 #define TGT_B 0x42 /* BLC blue channel target value */
96 #define TGT_R 0x43 /* BLC red channel target value */
97 #define TGT_GB 0x44 /* BLC Gb channel target value */
98 #define TGT_GR 0x45 /* BLC Gr channel target value */
99 /* for ov7720 */
100 #define LCC0 0x46 /* Lens correction control 0 */
101 #define LCC1 0x47 /* Lens correction option 1 - X coordinate */
102 #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
103 #define LCC3 0x49 /* Lens correction option 3 */
104 #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
105 #define LCC5 0x4B /* Lens correction option 5 */
106 #define LCC6 0x4C /* Lens correction option 6 */
107 /* for ov7725 */
108 #define LC_CTR 0x46 /* Lens correction control */
109 #define LC_XC 0x47 /* X coordinate of lens correction center relative */
110 #define LC_YC 0x48 /* Y coordinate of lens correction center relative */
111 #define LC_COEF 0x49 /* Lens correction coefficient */
112 #define LC_RADI 0x4A /* Lens correction radius */
113 #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
114 #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
115
116 #define FIXGAIN 0x4D /* Analog fix gain amplifer */
117 #define AREF0 0x4E /* Sensor reference control */
118 #define AREF1 0x4F /* Sensor reference current control */
119 #define AREF2 0x50 /* Analog reference control */
120 #define AREF3 0x51 /* ADC reference control */
121 #define AREF4 0x52 /* ADC reference control */
122 #define AREF5 0x53 /* ADC reference control */
123 #define AREF6 0x54 /* Analog reference control */
124 #define AREF7 0x55 /* Analog reference control */
125 #define UFIX 0x60 /* U channel fixed value output */
126 #define VFIX 0x61 /* V channel fixed value output */
127 #define AWBB_BLK 0x62 /* AWB option for advanced AWB */
128 #define AWB_CTRL0 0x63 /* AWB control byte 0 */
129 #define DSP_CTRL1 0x64 /* DSP control byte 1 */
130 #define DSP_CTRL2 0x65 /* DSP control byte 2 */
131 #define DSP_CTRL3 0x66 /* DSP control byte 3 */
132 #define DSP_CTRL4 0x67 /* DSP control byte 4 */
133 #define AWB_BIAS 0x68 /* AWB BLC level clip */
134 #define AWB_CTRL1 0x69 /* AWB control 1 */
135 #define AWB_CTRL2 0x6A /* AWB control 2 */
136 #define AWB_CTRL3 0x6B /* AWB control 3 */
137 #define AWB_CTRL4 0x6C /* AWB control 4 */
138 #define AWB_CTRL5 0x6D /* AWB control 5 */
139 #define AWB_CTRL6 0x6E /* AWB control 6 */
140 #define AWB_CTRL7 0x6F /* AWB control 7 */
141 #define AWB_CTRL8 0x70 /* AWB control 8 */
142 #define AWB_CTRL9 0x71 /* AWB control 9 */
143 #define AWB_CTRL10 0x72 /* AWB control 10 */
144 #define AWB_CTRL11 0x73 /* AWB control 11 */
145 #define AWB_CTRL12 0x74 /* AWB control 12 */
146 #define AWB_CTRL13 0x75 /* AWB control 13 */
147 #define AWB_CTRL14 0x76 /* AWB control 14 */
148 #define AWB_CTRL15 0x77 /* AWB control 15 */
149 #define AWB_CTRL16 0x78 /* AWB control 16 */
150 #define AWB_CTRL17 0x79 /* AWB control 17 */
151 #define AWB_CTRL18 0x7A /* AWB control 18 */
152 #define AWB_CTRL19 0x7B /* AWB control 19 */
153 #define AWB_CTRL20 0x7C /* AWB control 20 */
154 #define AWB_CTRL21 0x7D /* AWB control 21 */
155 #define GAM1 0x7E /* Gamma Curve 1st segment input end point */
156 #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
157 #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
158 #define GAM4 0x81 /* Gamma Curve 4th segment input end point */
159 #define GAM5 0x82 /* Gamma Curve 5th segment input end point */
160 #define GAM6 0x83 /* Gamma Curve 6th segment input end point */
161 #define GAM7 0x84 /* Gamma Curve 7th segment input end point */
162 #define GAM8 0x85 /* Gamma Curve 8th segment input end point */
163 #define GAM9 0x86 /* Gamma Curve 9th segment input end point */
164 #define GAM10 0x87 /* Gamma Curve 10th segment input end point */
165 #define GAM11 0x88 /* Gamma Curve 11th segment input end point */
166 #define GAM12 0x89 /* Gamma Curve 12th segment input end point */
167 #define GAM13 0x8A /* Gamma Curve 13th segment input end point */
168 #define GAM14 0x8B /* Gamma Curve 14th segment input end point */
169 #define GAM15 0x8C /* Gamma Curve 15th segment input end point */
170 #define SLOP 0x8D /* Gamma curve highest segment slope */
171 #define DNSTH 0x8E /* De-noise threshold */
172 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
173 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
174 #define DNSOFF 0x91 /* Auto De-noise threshold control */
175 #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
176 #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
177 #define MTX1 0x94 /* Matrix coefficient 1 */
178 #define MTX2 0x95 /* Matrix coefficient 2 */
179 #define MTX3 0x96 /* Matrix coefficient 3 */
180 #define MTX4 0x97 /* Matrix coefficient 4 */
181 #define MTX5 0x98 /* Matrix coefficient 5 */
182 #define MTX6 0x99 /* Matrix coefficient 6 */
183 #define MTX_CTRL 0x9A /* Matrix control */
184 #define BRIGHT 0x9B /* Brightness control */
185 #define CNTRST 0x9C /* Contrast contrast */
186 #define CNTRST_CTRL 0x9D /* Contrast contrast center */
187 #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
188 #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
189 #define SCAL0 0xA0 /* Scaling control 0 */
190 #define SCAL1 0xA1 /* Scaling control 1 */
191 #define SCAL2 0xA2 /* Scaling control 2 */
192 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
193 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
194 #define SDE 0xA6 /* Special digital effect control */
195 #define USAT 0xA7 /* U component saturation control */
196 #define VSAT 0xA8 /* V component saturation control */
197 /* for ov7720 */
198 #define HUE0 0xA9 /* Hue control 0 */
199 #define HUE1 0xAA /* Hue control 1 */
200 /* for ov7725 */
201 #define HUECOS 0xA9 /* Cosine value */
202 #define HUESIN 0xAA /* Sine value */
203
204 #define SIGN 0xAB /* Sign bit for Hue and contrast */
205 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
206
207 /*
208 * register detail
209 */
210
211 /* COM2 */
212 #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
213 /* Output drive capability */
214 #define OCAP_1x 0x00 /* 1x */
215 #define OCAP_2x 0x01 /* 2x */
216 #define OCAP_3x 0x02 /* 3x */
217 #define OCAP_4x 0x03 /* 4x */
218
219 /* COM3 */
220 #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
221 #define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
222
223 #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
224 #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
225 #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
226 #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
227 #define SWAP_ML 0x08 /* Swap output MSB/LSB */
228 /* Tri-state option for output clock */
229 #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
230 /* 1: No tri-state at this period */
231 /* Tri-state option for output data */
232 #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
233 /* 1: No tri-state at this period */
234 #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
235
236 /* COM4 */
237 /* PLL frequency control */
238 #define PLL_BYPASS 0x00 /* 00: Bypass PLL */
239 #define PLL_4x 0x40 /* 01: PLL 4x */
240 #define PLL_6x 0x80 /* 10: PLL 6x */
241 #define PLL_8x 0xc0 /* 11: PLL 8x */
242 /* AEC evaluate window */
243 #define AEC_FULL 0x00 /* 00: Full window */
244 #define AEC_1p2 0x10 /* 01: 1/2 window */
245 #define AEC_1p4 0x20 /* 10: 1/4 window */
246 #define AEC_2p3 0x30 /* 11: Low 2/3 window */
247
248 /* COM5 */
249 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
250 #define AFR_SPPED 0x40 /* Auto frame rate control speed slection */
251 /* Auto frame rate max rate control */
252 #define AFR_NO_RATE 0x00 /* No reduction of frame rate */
253 #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
254 #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
255 #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
256 /* Auto frame rate active point control */
257 #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
258 #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
259 #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
260 #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
261 /* AEC max step control */
262 #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
263 /* 1 : No limit to AEC increase step */
264
265 /* COM7 */
266 /* SCCB Register Reset */
267 #define SCCB_RESET 0x80 /* 0 : No change */
268 /* 1 : Resets all registers to default */
269 /* Resolution selection */
270 #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
271 #define SLCT_VGA 0x00 /* 0 : VGA */
272 #define SLCT_QVGA 0x40 /* 1 : QVGA */
273 #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
274 /* RGB output format control */
275 #define FMT_MASK 0x0c /* Mask of color format */
276 #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
277 #define FMT_RGB565 0x04 /* 01 : RGB 565 */
278 #define FMT_RGB555 0x08 /* 10 : RGB 555 */
279 #define FMT_RGB444 0x0c /* 11 : RGB 444 */
280 /* Output format control */
281 #define OFMT_MASK 0x03 /* Mask of output format */
282 #define OFMT_YUV 0x00 /* 00 : YUV */
283 #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
284 #define OFMT_RGB 0x02 /* 10 : RGB */
285 #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
286
287 /* COM8 */
288 #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
289 /* AEC Setp size limit */
290 #define UNLMT_STEP 0x40 /* 0 : Step size is limited */
291 /* 1 : Unlimited step size */
292 #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
293 #define AEC_BND 0x10 /* Enable AEC below banding value */
294 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
295 #define AGC_ON 0x04 /* AGC Enable */
296 #define AWB_ON 0x02 /* AWB Enable */
297 #define AEC_ON 0x01 /* AEC Enable */
298
299 /* COM9 */
300 #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
301 /* Automatic gain ceiling - maximum AGC value */
302 #define GAIN_2x 0x00 /* 000 : 2x */
303 #define GAIN_4x 0x10 /* 001 : 4x */
304 #define GAIN_8x 0x20 /* 010 : 8x */
305 #define GAIN_16x 0x30 /* 011 : 16x */
306 #define GAIN_32x 0x40 /* 100 : 32x */
307 #define GAIN_64x 0x50 /* 101 : 64x */
308 #define GAIN_128x 0x60 /* 110 : 128x */
309 #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
310 #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
311
312 /* COM11 */
313 #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
314 #define SGLF_TRIG 0x01 /* Single frame transfer trigger */
315
316 /* EXHCH */
317 #define VSIZE_LSB 0x04 /* Vertical data output size LSB */
318
319 /* DSP_CTRL1 */
320 #define FIFO_ON 0x80 /* FIFO enable/disable selection */
321 #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
322 #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
323 #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
324 #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
325 #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
326 #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
327 #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
328
329 /* DSP_CTRL3 */
330 #define UV_MASK 0x80 /* UV output sequence option */
331 #define UV_ON 0x80 /* ON */
332 #define UV_OFF 0x00 /* OFF */
333 #define CBAR_MASK 0x20 /* DSP Color bar mask */
334 #define CBAR_ON 0x20 /* ON */
335 #define CBAR_OFF 0x00 /* OFF */
336
337 /* HSTART */
338 #define HST_VGA 0x23
339 #define HST_QVGA 0x3F
340
341 /* HSIZE */
342 #define HSZ_VGA 0xA0
343 #define HSZ_QVGA 0x50
344
345 /* VSTART */
346 #define VST_VGA 0x07
347 #define VST_QVGA 0x03
348
349 /* VSIZE */
350 #define VSZ_VGA 0xF0
351 #define VSZ_QVGA 0x78
352
353 /* HOUTSIZE */
354 #define HOSZ_VGA 0xA0
355 #define HOSZ_QVGA 0x50
356
357 /* VOUTSIZE */
358 #define VOSZ_VGA 0xF0
359 #define VOSZ_QVGA 0x78
360
361 /* DSPAUTO (DSP Auto Function ON/OFF Control) */
362 #define AWB_ACTRL 0x80 /* AWB auto threshold control */
363 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
364 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
365 #define UV_ACTRL 0x10 /* UV adjust auto slope control */
366 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
367 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
368
369 /*
370 * ID
371 */
372 #define OV7720 0x7720
373 #define OV7725 0x7721
374 #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
375
376 /*
377 * struct
378 */
379 struct regval_list {
380 unsigned char reg_num;
381 unsigned char value;
382 };
383
384 struct ov772x_color_format {
385 char *name;
386 __u32 fourcc;
387 u8 dsp3;
388 u8 com3;
389 u8 com7;
390 };
391
392 struct ov772x_win_size {
393 char *name;
394 __u32 width;
395 __u32 height;
396 unsigned char com7_bit;
397 const struct regval_list *regs;
398 };
399
400 struct ov772x_priv {
401 struct ov772x_camera_info *info;
402 const struct ov772x_color_format *fmt;
403 const struct ov772x_win_size *win;
404 int model;
405 unsigned int flag_vflip:1;
406 unsigned int flag_hflip:1;
407 };
408
409 #define ENDMARKER { 0xff, 0xff }
410
411 /*
412 * register setting for window size
413 */
414 static const struct regval_list ov772x_qvga_regs[] = {
415 { HSTART, HST_QVGA },
416 { HSIZE, HSZ_QVGA },
417 { VSTART, VST_QVGA },
418 { VSIZE, VSZ_QVGA },
419 { HOUTSIZE, HOSZ_QVGA },
420 { VOUTSIZE, VOSZ_QVGA },
421 ENDMARKER,
422 };
423
424 static const struct regval_list ov772x_vga_regs[] = {
425 { HSTART, HST_VGA },
426 { HSIZE, HSZ_VGA },
427 { VSTART, VST_VGA },
428 { VSIZE, VSZ_VGA },
429 { HOUTSIZE, HOSZ_VGA },
430 { VOUTSIZE, VOSZ_VGA },
431 ENDMARKER,
432 };
433
434 /*
435 * supported format list
436 */
437
438 #define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type)
439 static const struct soc_camera_data_format ov772x_fmt_lists[] = {
440 {
441 SETFOURCC(YUYV),
442 .depth = 16,
443 .colorspace = V4L2_COLORSPACE_JPEG,
444 },
445 {
446 SETFOURCC(YVYU),
447 .depth = 16,
448 .colorspace = V4L2_COLORSPACE_JPEG,
449 },
450 {
451 SETFOURCC(UYVY),
452 .depth = 16,
453 .colorspace = V4L2_COLORSPACE_JPEG,
454 },
455 {
456 SETFOURCC(RGB555),
457 .depth = 16,
458 .colorspace = V4L2_COLORSPACE_SRGB,
459 },
460 {
461 SETFOURCC(RGB555X),
462 .depth = 16,
463 .colorspace = V4L2_COLORSPACE_SRGB,
464 },
465 {
466 SETFOURCC(RGB565),
467 .depth = 16,
468 .colorspace = V4L2_COLORSPACE_SRGB,
469 },
470 {
471 SETFOURCC(RGB565X),
472 .depth = 16,
473 .colorspace = V4L2_COLORSPACE_SRGB,
474 },
475 };
476
477 /*
478 * color format list
479 */
480 static const struct ov772x_color_format ov772x_cfmts[] = {
481 {
482 SETFOURCC(YUYV),
483 .dsp3 = 0x0,
484 .com3 = SWAP_YUV,
485 .com7 = OFMT_YUV,
486 },
487 {
488 SETFOURCC(YVYU),
489 .dsp3 = UV_ON,
490 .com3 = SWAP_YUV,
491 .com7 = OFMT_YUV,
492 },
493 {
494 SETFOURCC(UYVY),
495 .dsp3 = 0x0,
496 .com3 = 0x0,
497 .com7 = OFMT_YUV,
498 },
499 {
500 SETFOURCC(RGB555),
501 .dsp3 = 0x0,
502 .com3 = SWAP_RGB,
503 .com7 = FMT_RGB555 | OFMT_RGB,
504 },
505 {
506 SETFOURCC(RGB555X),
507 .dsp3 = 0x0,
508 .com3 = 0x0,
509 .com7 = FMT_RGB555 | OFMT_RGB,
510 },
511 {
512 SETFOURCC(RGB565),
513 .dsp3 = 0x0,
514 .com3 = SWAP_RGB,
515 .com7 = FMT_RGB565 | OFMT_RGB,
516 },
517 {
518 SETFOURCC(RGB565X),
519 .dsp3 = 0x0,
520 .com3 = 0x0,
521 .com7 = FMT_RGB565 | OFMT_RGB,
522 },
523 };
524
525
526 /*
527 * window size list
528 */
529 #define VGA_WIDTH 640
530 #define VGA_HEIGHT 480
531 #define QVGA_WIDTH 320
532 #define QVGA_HEIGHT 240
533 #define MAX_WIDTH VGA_WIDTH
534 #define MAX_HEIGHT VGA_HEIGHT
535
536 static const struct ov772x_win_size ov772x_win_vga = {
537 .name = "VGA",
538 .width = VGA_WIDTH,
539 .height = VGA_HEIGHT,
540 .com7_bit = SLCT_VGA,
541 .regs = ov772x_vga_regs,
542 };
543
544 static const struct ov772x_win_size ov772x_win_qvga = {
545 .name = "QVGA",
546 .width = QVGA_WIDTH,
547 .height = QVGA_HEIGHT,
548 .com7_bit = SLCT_QVGA,
549 .regs = ov772x_qvga_regs,
550 };
551
552 static const struct v4l2_queryctrl ov772x_controls[] = {
553 {
554 .id = V4L2_CID_VFLIP,
555 .type = V4L2_CTRL_TYPE_BOOLEAN,
556 .name = "Flip Vertically",
557 .minimum = 0,
558 .maximum = 1,
559 .step = 1,
560 .default_value = 0,
561 },
562 {
563 .id = V4L2_CID_HFLIP,
564 .type = V4L2_CTRL_TYPE_BOOLEAN,
565 .name = "Flip Horizontally",
566 .minimum = 0,
567 .maximum = 1,
568 .step = 1,
569 .default_value = 0,
570 },
571 };
572
573
574 /*
575 * general function
576 */
577
578 static int ov772x_write_array(struct i2c_client *client,
579 const struct regval_list *vals)
580 {
581 while (vals->reg_num != 0xff) {
582 int ret = i2c_smbus_write_byte_data(client,
583 vals->reg_num,
584 vals->value);
585 if (ret < 0)
586 return ret;
587 vals++;
588 }
589 return 0;
590 }
591
592 static int ov772x_mask_set(struct i2c_client *client,
593 u8 command,
594 u8 mask,
595 u8 set)
596 {
597 s32 val = i2c_smbus_read_byte_data(client, command);
598 if (val < 0)
599 return val;
600
601 val &= ~mask;
602 val |= set & mask;
603
604 return i2c_smbus_write_byte_data(client, command, val);
605 }
606
607 static int ov772x_reset(struct i2c_client *client)
608 {
609 int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
610 msleep(1);
611 return ret;
612 }
613
614 /*
615 * soc_camera_ops function
616 */
617
618 static int ov772x_init(struct soc_camera_device *icd)
619 {
620 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
621 struct soc_camera_link *icl = to_soc_camera_link(icd);
622 int ret = 0;
623
624 if (icl->power) {
625 ret = icl->power(&client->dev, 1);
626 if (ret < 0)
627 return ret;
628 }
629
630 if (icl->reset)
631 ret = icl->reset(&client->dev);
632
633 return ret;
634 }
635
636 static int ov772x_release(struct soc_camera_device *icd)
637 {
638 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
639 struct soc_camera_link *icl = to_soc_camera_link(icd);
640 int ret = 0;
641
642 if (icl->power)
643 ret = icl->power(&client->dev, 0);
644
645 return ret;
646 }
647
648 static int ov772x_start_capture(struct soc_camera_device *icd)
649 {
650 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
651 struct ov772x_priv *priv = i2c_get_clientdata(client);
652
653 if (!priv->win || !priv->fmt) {
654 dev_err(&icd->dev, "norm or win select error\n");
655 return -EPERM;
656 }
657
658 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
659
660 dev_dbg(&icd->dev,
661 "format %s, win %s\n", priv->fmt->name, priv->win->name);
662
663 return 0;
664 }
665
666 static int ov772x_stop_capture(struct soc_camera_device *icd)
667 {
668 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
669 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
670 return 0;
671 }
672
673 static int ov772x_set_bus_param(struct soc_camera_device *icd,
674 unsigned long flags)
675 {
676 return 0;
677 }
678
679 static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd)
680 {
681 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
682 struct ov772x_priv *priv = i2c_get_clientdata(client);
683 struct soc_camera_link *icl = to_soc_camera_link(icd);
684 unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
685 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
686 SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth;
687
688 return soc_camera_apply_sensor_flags(icl, flags);
689 }
690
691 static int ov772x_get_control(struct soc_camera_device *icd,
692 struct v4l2_control *ctrl)
693 {
694 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
695 struct ov772x_priv *priv = i2c_get_clientdata(client);
696
697 switch (ctrl->id) {
698 case V4L2_CID_VFLIP:
699 ctrl->value = priv->flag_vflip;
700 break;
701 case V4L2_CID_HFLIP:
702 ctrl->value = priv->flag_hflip;
703 break;
704 }
705 return 0;
706 }
707
708 static int ov772x_set_control(struct soc_camera_device *icd,
709 struct v4l2_control *ctrl)
710 {
711 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
712 struct ov772x_priv *priv = i2c_get_clientdata(client);
713 int ret = 0;
714 u8 val;
715
716 switch (ctrl->id) {
717 case V4L2_CID_VFLIP:
718 val = ctrl->value ? VFLIP_IMG : 0x00;
719 priv->flag_vflip = ctrl->value;
720 if (priv->info->flags & OV772X_FLAG_VFLIP)
721 val ^= VFLIP_IMG;
722 ret = ov772x_mask_set(client, COM3, VFLIP_IMG, val);
723 break;
724 case V4L2_CID_HFLIP:
725 val = ctrl->value ? HFLIP_IMG : 0x00;
726 priv->flag_hflip = ctrl->value;
727 if (priv->info->flags & OV772X_FLAG_HFLIP)
728 val ^= HFLIP_IMG;
729 ret = ov772x_mask_set(client, COM3, HFLIP_IMG, val);
730 break;
731 }
732
733 return ret;
734 }
735
736 static int ov772x_get_chip_id(struct soc_camera_device *icd,
737 struct v4l2_dbg_chip_ident *id)
738 {
739 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
740 struct ov772x_priv *priv = i2c_get_clientdata(client);
741
742 id->ident = priv->model;
743 id->revision = 0;
744
745 return 0;
746 }
747
748 #ifdef CONFIG_VIDEO_ADV_DEBUG
749 static int ov772x_get_register(struct soc_camera_device *icd,
750 struct v4l2_dbg_register *reg)
751 {
752 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
753 int ret;
754
755 reg->size = 1;
756 if (reg->reg > 0xff)
757 return -EINVAL;
758
759 ret = i2c_smbus_read_byte_data(client, reg->reg);
760 if (ret < 0)
761 return ret;
762
763 reg->val = (__u64)ret;
764
765 return 0;
766 }
767
768 static int ov772x_set_register(struct soc_camera_device *icd,
769 struct v4l2_dbg_register *reg)
770 {
771 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
772
773 if (reg->reg > 0xff ||
774 reg->val > 0xff)
775 return -EINVAL;
776
777 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
778 }
779 #endif
780
781 static const struct ov772x_win_size*
782 ov772x_select_win(u32 width, u32 height)
783 {
784 __u32 diff;
785 const struct ov772x_win_size *win;
786
787 /* default is QVGA */
788 diff = abs(width - ov772x_win_qvga.width) +
789 abs(height - ov772x_win_qvga.height);
790 win = &ov772x_win_qvga;
791
792 /* VGA */
793 if (diff >
794 abs(width - ov772x_win_vga.width) +
795 abs(height - ov772x_win_vga.height))
796 win = &ov772x_win_vga;
797
798 return win;
799 }
800
801 static int ov772x_set_params(struct soc_camera_device *icd,
802 u32 width, u32 height, u32 pixfmt)
803 {
804 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
805 struct ov772x_priv *priv = i2c_get_clientdata(client);
806 int ret = -EINVAL;
807 u8 val;
808 int i;
809
810 /*
811 * select format
812 */
813 priv->fmt = NULL;
814 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
815 if (pixfmt == ov772x_cfmts[i].fourcc) {
816 priv->fmt = ov772x_cfmts + i;
817 break;
818 }
819 }
820 dev_dbg(&icd->dev, "Using fmt %x #%d\n", pixfmt, i);
821 if (!priv->fmt)
822 goto ov772x_set_fmt_error;
823
824 /*
825 * select win
826 */
827 priv->win = ov772x_select_win(width, height);
828
829 /*
830 * reset hardware
831 */
832 ov772x_reset(client);
833
834 /*
835 * Edge Ctrl
836 */
837 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
838
839 /*
840 * Manual Edge Control Mode
841 *
842 * Edge auto strength bit is set by default.
843 * Remove it when manual mode.
844 */
845
846 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
847 if (ret < 0)
848 goto ov772x_set_fmt_error;
849
850 ret = ov772x_mask_set(client,
851 EDGE_TRSHLD, EDGE_THRESHOLD_MASK,
852 priv->info->edgectrl.threshold);
853 if (ret < 0)
854 goto ov772x_set_fmt_error;
855
856 ret = ov772x_mask_set(client,
857 EDGE_STRNGT, EDGE_STRENGTH_MASK,
858 priv->info->edgectrl.strength);
859 if (ret < 0)
860 goto ov772x_set_fmt_error;
861
862 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
863 /*
864 * Auto Edge Control Mode
865 *
866 * set upper and lower limit
867 */
868 ret = ov772x_mask_set(client,
869 EDGE_UPPER, EDGE_UPPER_MASK,
870 priv->info->edgectrl.upper);
871 if (ret < 0)
872 goto ov772x_set_fmt_error;
873
874 ret = ov772x_mask_set(client,
875 EDGE_LOWER, EDGE_LOWER_MASK,
876 priv->info->edgectrl.lower);
877 if (ret < 0)
878 goto ov772x_set_fmt_error;
879 }
880
881 /*
882 * set size format
883 */
884 ret = ov772x_write_array(client, priv->win->regs);
885 if (ret < 0)
886 goto ov772x_set_fmt_error;
887
888 /*
889 * set DSP_CTRL3
890 */
891 val = priv->fmt->dsp3;
892 if (val) {
893 ret = ov772x_mask_set(client,
894 DSP_CTRL3, UV_MASK, val);
895 if (ret < 0)
896 goto ov772x_set_fmt_error;
897 }
898
899 /*
900 * set COM3
901 */
902 val = priv->fmt->com3;
903 if (priv->info->flags & OV772X_FLAG_VFLIP)
904 val |= VFLIP_IMG;
905 if (priv->info->flags & OV772X_FLAG_HFLIP)
906 val |= HFLIP_IMG;
907 if (priv->flag_vflip)
908 val ^= VFLIP_IMG;
909 if (priv->flag_hflip)
910 val ^= HFLIP_IMG;
911
912 ret = ov772x_mask_set(client,
913 COM3, SWAP_MASK | IMG_MASK, val);
914 if (ret < 0)
915 goto ov772x_set_fmt_error;
916
917 /*
918 * set COM7
919 */
920 val = priv->win->com7_bit | priv->fmt->com7;
921 ret = ov772x_mask_set(client,
922 COM7, (SLCT_MASK | FMT_MASK | OFMT_MASK),
923 val);
924 if (ret < 0)
925 goto ov772x_set_fmt_error;
926
927 return ret;
928
929 ov772x_set_fmt_error:
930
931 ov772x_reset(client);
932 priv->win = NULL;
933 priv->fmt = NULL;
934
935 return ret;
936 }
937
938 static int ov772x_set_crop(struct soc_camera_device *icd,
939 struct v4l2_rect *rect)
940 {
941 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
942 struct ov772x_priv *priv = i2c_get_clientdata(client);
943
944 if (!priv->fmt)
945 return -EINVAL;
946
947 return ov772x_set_params(icd, rect->width, rect->height,
948 priv->fmt->fourcc);
949 }
950
951 static int ov772x_set_fmt(struct soc_camera_device *icd,
952 struct v4l2_format *f)
953 {
954 struct v4l2_pix_format *pix = &f->fmt.pix;
955
956 return ov772x_set_params(icd, pix->width, pix->height,
957 pix->pixelformat);
958 }
959
960 static int ov772x_try_fmt(struct soc_camera_device *icd,
961 struct v4l2_format *f)
962 {
963 struct v4l2_pix_format *pix = &f->fmt.pix;
964 const struct ov772x_win_size *win;
965
966 /*
967 * select suitable win
968 */
969 win = ov772x_select_win(pix->width, pix->height);
970
971 pix->width = win->width;
972 pix->height = win->height;
973 pix->field = V4L2_FIELD_NONE;
974
975 return 0;
976 }
977
978 static int ov772x_video_probe(struct soc_camera_device *icd,
979 struct i2c_client *client)
980 {
981 struct ov772x_priv *priv = i2c_get_clientdata(client);
982 u8 pid, ver;
983 const char *devname;
984 int ret;
985
986 /*
987 * We must have a parent by now. And it cannot be a wrong one.
988 * So this entire test is completely redundant.
989 */
990 if (!icd->dev.parent ||
991 to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
992 return -ENODEV;
993
994 /*
995 * ov772x only use 8 or 10 bit bus width
996 */
997 if (SOCAM_DATAWIDTH_10 != priv->info->buswidth &&
998 SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
999 dev_err(&icd->dev, "bus width error\n");
1000 return -ENODEV;
1001 }
1002
1003 icd->formats = ov772x_fmt_lists;
1004 icd->num_formats = ARRAY_SIZE(ov772x_fmt_lists);
1005
1006 /* Switch master clock on */
1007 ret = soc_camera_video_start(icd, &client->dev);
1008 if (ret)
1009 return ret;
1010
1011 /*
1012 * check and show product ID and manufacturer ID
1013 */
1014 pid = i2c_smbus_read_byte_data(client, PID);
1015 ver = i2c_smbus_read_byte_data(client, VER);
1016
1017 switch (VERSION(pid, ver)) {
1018 case OV7720:
1019 devname = "ov7720";
1020 priv->model = V4L2_IDENT_OV7720;
1021 break;
1022 case OV7725:
1023 devname = "ov7725";
1024 priv->model = V4L2_IDENT_OV7725;
1025 break;
1026 default:
1027 dev_err(&icd->dev,
1028 "Product ID error %x:%x\n", pid, ver);
1029 ret = -ENODEV;
1030 goto ever;
1031 }
1032
1033 dev_info(&icd->dev,
1034 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1035 devname,
1036 pid,
1037 ver,
1038 i2c_smbus_read_byte_data(client, MIDH),
1039 i2c_smbus_read_byte_data(client, MIDL));
1040
1041 soc_camera_video_stop(icd);
1042
1043 ever:
1044 return ret;
1045 }
1046
1047 static struct soc_camera_ops ov772x_ops = {
1048 .owner = THIS_MODULE,
1049 .init = ov772x_init,
1050 .release = ov772x_release,
1051 .start_capture = ov772x_start_capture,
1052 .stop_capture = ov772x_stop_capture,
1053 .set_crop = ov772x_set_crop,
1054 .set_fmt = ov772x_set_fmt,
1055 .try_fmt = ov772x_try_fmt,
1056 .set_bus_param = ov772x_set_bus_param,
1057 .query_bus_param = ov772x_query_bus_param,
1058 .controls = ov772x_controls,
1059 .num_controls = ARRAY_SIZE(ov772x_controls),
1060 .get_control = ov772x_get_control,
1061 .set_control = ov772x_set_control,
1062 .get_chip_id = ov772x_get_chip_id,
1063 #ifdef CONFIG_VIDEO_ADV_DEBUG
1064 .get_register = ov772x_get_register,
1065 .set_register = ov772x_set_register,
1066 #endif
1067 };
1068
1069 /*
1070 * i2c_driver function
1071 */
1072
1073 static int ov772x_probe(struct i2c_client *client,
1074 const struct i2c_device_id *did)
1075 {
1076 struct ov772x_priv *priv;
1077 struct ov772x_camera_info *info;
1078 struct soc_camera_device *icd = client->dev.platform_data;
1079 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1080 struct soc_camera_link *icl;
1081 int ret;
1082
1083 if (!icd) {
1084 dev_err(&client->dev, "MT9M001: missing soc-camera data!\n");
1085 return -EINVAL;
1086 }
1087
1088 icl = to_soc_camera_link(icd);
1089 if (!icl)
1090 return -EINVAL;
1091
1092 info = container_of(icl, struct ov772x_camera_info, link);
1093
1094 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1095 dev_err(&adapter->dev,
1096 "I2C-Adapter doesn't support "
1097 "I2C_FUNC_SMBUS_BYTE_DATA\n");
1098 return -EIO;
1099 }
1100
1101 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1102 if (!priv)
1103 return -ENOMEM;
1104
1105 priv->info = info;
1106 i2c_set_clientdata(client, priv);
1107
1108 icd->ops = &ov772x_ops;
1109 icd->width_max = MAX_WIDTH;
1110 icd->height_max = MAX_HEIGHT;
1111
1112 ret = ov772x_video_probe(icd, client);
1113 if (ret) {
1114 icd->ops = NULL;
1115 i2c_set_clientdata(client, NULL);
1116 kfree(priv);
1117 }
1118
1119 return ret;
1120 }
1121
1122 static int ov772x_remove(struct i2c_client *client)
1123 {
1124 struct ov772x_priv *priv = i2c_get_clientdata(client);
1125 struct soc_camera_device *icd = client->dev.platform_data;
1126
1127 icd->ops = NULL;
1128 i2c_set_clientdata(client, NULL);
1129 kfree(priv);
1130 return 0;
1131 }
1132
1133 static const struct i2c_device_id ov772x_id[] = {
1134 { "ov772x", 0 },
1135 { }
1136 };
1137 MODULE_DEVICE_TABLE(i2c, ov772x_id);
1138
1139 static struct i2c_driver ov772x_i2c_driver = {
1140 .driver = {
1141 .name = "ov772x",
1142 },
1143 .probe = ov772x_probe,
1144 .remove = ov772x_remove,
1145 .id_table = ov772x_id,
1146 };
1147
1148 /*
1149 * module function
1150 */
1151
1152 static int __init ov772x_module_init(void)
1153 {
1154 return i2c_add_driver(&ov772x_i2c_driver);
1155 }
1156
1157 static void __exit ov772x_module_exit(void)
1158 {
1159 i2c_del_driver(&ov772x_i2c_driver);
1160 }
1161
1162 module_init(ov772x_module_init);
1163 module_exit(ov772x_module_exit);
1164
1165 MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1166 MODULE_AUTHOR("Kuninori Morimoto");
1167 MODULE_LICENSE("GPL v2");
Support for the Chinese Samsung S3C2440 based development boards