drivers/pci/quirks.c

   1 /*
   2  *  This file contains work-arounds for many known PCI hardware
   3  *  bugs.  Devices present only on certain architectures (host
   4  *  bridges et cetera) should be handled in arch-specific code.
   5  *
   6  *  Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
   7  *
   8  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   9  *
  10  *  Init/reset quirks for USB host controllers should be in the
  11  *  USB quirks file, where their drivers can access reuse it.
  12  *
  13  *  The bridge optimization stuff has been removed. If you really
  14  *  have a silly BIOS which is unable to set your host bridge right,
  15  *  use the PowerTweak utility (see http://powertweak.sourceforge.net).
  16  */
  17
  18 #include <linux/types.h>
  19 #include <linux/kernel.h>
  20 #include <linux/pci.h>
  21 #include <linux/init.h>
  22 #include <linux/delay.h>
  23 #include <linux/acpi.h>
  24 #include <linux/kallsyms.h>
  25 #include "pci.h"
  26
  27 int isa_dma_bridge_buggy;
  28 EXPORT_SYMBOL(isa_dma_bridge_buggy);
  29 int pci_pci_problems;
  30 EXPORT_SYMBOL(pci_pci_problems);
  31 int pcie_mch_quirk;
  32 EXPORT_SYMBOL(pcie_mch_quirk);
  33
  34 #ifdef CONFIG_PCI_QUIRKS
  35 /* The Mellanox Tavor device gives false positive parity errors
  36  * Mark this device with a broken_parity_status, to allow
  37  * PCI scanning code to "skip" this now blacklisted device.
  38  */
  39 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
  40 {
  41         dev->broken_parity_status = 1;  /* This device gives false positives */
  42 }
  43 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
  44 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
  45
  46 /* Deal with broken BIOS'es that neglect to enable passive release,
  47    which can cause problems in combination with the 82441FX/PPro MTRRs */
  48 static void quirk_passive_release(struct pci_dev *dev)
  49 {
  50         struct pci_dev *d = NULL;
  51         unsigned char dlc;
  52
  53         /* We have to make sure a particular bit is set in the PIIX3
  54            ISA bridge, so we have to go out and find it. */
  55         while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  56                 pci_read_config_byte(d, 0x82, &dlc);
  57                 if (!(dlc & 1<<1)) {
  58                         dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
  59                         dlc |= 1<<1;
  60                         pci_write_config_byte(d, 0x82, dlc);
  61                 }
  62         }
  63 }
  64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
  65 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
  66
  67 /*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
  68     but VIA don't answer queries. If you happen to have good contacts at VIA
  69     ask them for me please -- Alan
  70
  71     This appears to be BIOS not version dependent. So presumably there is a
  72     chipset level fix */
  73
  74 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
  75 {
  76         if (!isa_dma_bridge_buggy) {
  77                 isa_dma_bridge_buggy=1;
  78                 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
  79         }
  80 }
  81         /*
  82          * Its not totally clear which chipsets are the problematic ones
  83          * We know 82C586 and 82C596 variants are affected.
  84          */
  85 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs);
  86 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs);
  87 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
  88 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1533,         quirk_isa_dma_hangs);
  89 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_1,       quirk_isa_dma_hangs);
  90 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_2,       quirk_isa_dma_hangs);
  91 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_3,       quirk_isa_dma_hangs);
  92
  93 /*
  94  *      Chipsets where PCI->PCI transfers vanish or hang
  95  */
  96 static void __devinit quirk_nopcipci(struct pci_dev *dev)
  97 {
  98         if ((pci_pci_problems & PCIPCI_FAIL)==0) {
  99                 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
 100                 pci_pci_problems |= PCIPCI_FAIL;
 101         }
 102 }
 103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci);
 104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci);
 105
 106 static void __devinit quirk_nopciamd(struct pci_dev *dev)
 107 {
 108         u8 rev;
 109         pci_read_config_byte(dev, 0x08, &rev);
 110         if (rev == 0x13) {
 111                 /* Erratum 24 */
 112                 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
 113                 pci_pci_problems |= PCIAGP_FAIL;
 114         }
 115 }
 116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8151_0,       quirk_nopciamd);
 117
 118 /*
 119  *      Triton requires workarounds to be used by the drivers
 120  */
 121 static void __devinit quirk_triton(struct pci_dev *dev)
 122 {
 123         if ((pci_pci_problems&PCIPCI_TRITON)==0) {
 124                 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 125                 pci_pci_problems |= PCIPCI_TRITON;
 126         }
 127 }
 128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton);
 129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437VX,    quirk_triton);
 130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439,      quirk_triton);
 131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439TX,    quirk_triton);
 132
 133 /*
 134  *      VIA Apollo KT133 needs PCI latency patch
 135  *      Made according to a windows driver based patch by George E. Breese
 136  *      see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
 137  *      Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
 138  *      the info on which Mr Breese based his work.
 139  *
 140  *      Updated based on further information from the site and also on
 141  *      information provided by VIA
 142  */
 143 static void quirk_vialatency(struct pci_dev *dev)
 144 {
 145         struct pci_dev *p;
 146         u8 busarb;
 147         /* Ok we have a potential problem chipset here. Now see if we have
 148            a buggy southbridge */
 149
 150         p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
 151         if (p!=NULL) {
 152                 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
 153                 /* Check for buggy part revisions */
 154                 if (p->revision < 0x40 || p->revision > 0x42)
 155                         goto exit;
 156         } else {
 157                 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
 158                 if (p==NULL)    /* No problem parts */
 159                         goto exit;
 160                 /* Check for buggy part revisions */
 161                 if (p->revision < 0x10 || p->revision > 0x12)
 162                         goto exit;
 163         }
 164
 165         /*
 166          *      Ok we have the problem. Now set the PCI master grant to
 167          *      occur every master grant. The apparent bug is that under high
 168          *      PCI load (quite common in Linux of course) you can get data
 169          *      loss when the CPU is held off the bus for 3 bus master requests
 170          *      This happens to include the IDE controllers....
 171          *
 172          *      VIA only apply this fix when an SB Live! is present but under
 173          *      both Linux and Windows this isnt enough, and we have seen
 174          *      corruption without SB Live! but with things like 3 UDMA IDE
 175          *      controllers. So we ignore that bit of the VIA recommendation..
 176          */
 177
 178         pci_read_config_byte(dev, 0x76, &busarb);
 179         /* Set bit 4 and bi 5 of byte 76 to 0x01
 180            "Master priority rotation on every PCI master grant */
 181         busarb &= ~(1<<5);
 182         busarb |= (1<<4);
 183         pci_write_config_byte(dev, 0x76, busarb);
 184         dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
 185 exit:
 186         pci_dev_put(p);
 187 }
 188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 191 /* Must restore this on a resume from RAM */
 192 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 193 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 194 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 195
 196 /*
 197  *      VIA Apollo VP3 needs ETBF on BT848/878
 198  */
 199 static void __devinit quirk_viaetbf(struct pci_dev *dev)
 200 {
 201         if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
 202                 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 203                 pci_pci_problems |= PCIPCI_VIAETBF;
 204         }
 205 }
 206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_viaetbf);
 207
 208 static void __devinit quirk_vsfx(struct pci_dev *dev)
 209 {
 210         if ((pci_pci_problems&PCIPCI_VSFX)==0) {
 211                 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 212                 pci_pci_problems |= PCIPCI_VSFX;
 213         }
 214 }
 215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C576,       quirk_vsfx);
 216
 217 /*
 218  *      Ali Magik requires workarounds to be used by the drivers
 219  *      that DMA to AGP space. Latency must be set to 0xA and triton
 220  *      workaround applied too
 221  *      [Info kindly provided by ALi]
 222  */
 223 static void __init quirk_alimagik(struct pci_dev *dev)
 224 {
 225         if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
 226                 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 227                 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
 228         }
 229 }
 230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1647,         quirk_alimagik);
 231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1651,         quirk_alimagik);
 232
 233 /*
 234  *      Natoma has some interesting boundary conditions with Zoran stuff
 235  *      at least
 236  */
 237 static void __devinit quirk_natoma(struct pci_dev *dev)
 238 {
 239         if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
 240                 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 241                 pci_pci_problems |= PCIPCI_NATOMA;
 242         }
 243 }
 244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_natoma);
 245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_0,  quirk_natoma);
 246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_1,  quirk_natoma);
 247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_0,  quirk_natoma);
 248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_1,  quirk_natoma);
 249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma);
 250
 251 /*
 252  *  This chip can cause PCI parity errors if config register 0xA0 is read
 253  *  while DMAs are occurring.
 254  */
 255 static void __devinit quirk_citrine(struct pci_dev *dev)
 256 {
 257         dev->cfg_size = 0xA0;
 258 }
 259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CITRINE,      quirk_citrine);
 260
 261 /*
 262  *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 263  *  If it's needed, re-allocate the region.
 264  */
 265 static void __devinit quirk_s3_64M(struct pci_dev *dev)
 266 {
 267         struct resource *r = &dev->resource[0];
 268
 269         if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
 270                 r->start = 0;
 271                 r->end = 0x3ffffff;
 272         }
 273 }
 274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_868,           quirk_s3_64M);
 275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_968,           quirk_s3_64M);
 276
 277 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
 278         unsigned size, int nr, const char *name)
 279 {
 280         region &= ~(size-1);
 281         if (region) {
 282                 struct pci_bus_region bus_region;
 283                 struct resource *res = dev->resource + nr;
 284
 285                 res->name = pci_name(dev);
 286                 res->start = region;
 287                 res->end = region + size - 1;
 288                 res->flags = IORESOURCE_IO;
 289
 290                 /* Convert from PCI bus to resource space.  */
 291                 bus_region.start = res->start;
 292                 bus_region.end = res->end;
 293                 pcibios_bus_to_resource(dev, res, &bus_region);
 294
 295                 pci_claim_resource(dev, nr);
 296                 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
 297         }
 298 }
 299
 300 /*
 301  *      ATI Northbridge setups MCE the processor if you even
 302  *      read somewhere between 0x3b0->0x3bb or read 0x3d3
 303  */
 304 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
 305 {
 306         dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
 307         /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
 308         request_region(0x3b0, 0x0C, "RadeonIGP");
 309         request_region(0x3d3, 0x01, "RadeonIGP");
 310 }
 311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
 312
 313 /*
 314  * Let's make the southbridge information explicit instead
 315  * of having to worry about people probing the ACPI areas,
 316  * for example.. (Yes, it happens, and if you read the wrong
 317  * ACPI register it will put the machine to sleep with no
 318  * way of waking it up again. Bummer).
 319  *
 320  * ALI M7101: Two IO regions pointed to by words at
 321  *      0xE0 (64 bytes of ACPI registers)
 322  *      0xE2 (32 bytes of SMB registers)
 323  */
 324 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
 325 {
 326         u16 region;
 327
 328         pci_read_config_word(dev, 0xE0, &region);
 329         quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
 330         pci_read_config_word(dev, 0xE2, &region);
 331         quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
 332 }
 333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,      PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi);
 334
 335 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 336 {
 337         u32 devres;
 338         u32 mask, size, base;
 339
 340         pci_read_config_dword(dev, port, &devres);
 341         if ((devres & enable) != enable)
 342                 return;
 343         mask = (devres >> 16) & 15;
 344         base = devres & 0xffff;
 345         size = 16;
 346         for (;;) {
 347                 unsigned bit = size >> 1;
 348                 if ((bit & mask) == bit)
 349                         break;
 350                 size = bit;
 351         }
 352         /*
 353          * For now we only print it out. Eventually we'll want to
 354          * reserve it (at least if it's in the 0x1000+ range), but
 355          * let's get enough confirmation reports first.
 356          */
 357         base &= -size;
 358         dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
 359 }
 360
 361 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 362 {
 363         u32 devres;
 364         u32 mask, size, base;
 365
 366         pci_read_config_dword(dev, port, &devres);
 367         if ((devres & enable) != enable)
 368                 return;
 369         base = devres & 0xffff0000;
 370         mask = (devres & 0x3f) << 16;
 371         size = 128 << 16;
 372         for (;;) {
 373                 unsigned bit = size >> 1;
 374                 if ((bit & mask) == bit)
 375                         break;
 376                 size = bit;
 377         }
 378         /*
 379          * For now we only print it out. Eventually we'll want to
 380          * reserve it, but let's get enough confirmation reports first.
 381          */
 382         base &= -size;
 383         dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
 384 }
 385
 386 /*
 387  * PIIX4 ACPI: Two IO regions pointed to by longwords at
 388  *      0x40 (64 bytes of ACPI registers)
 389  *      0x90 (16 bytes of SMB registers)
 390  * and a few strange programmable PIIX4 device resources.
 391  */
 392 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
 393 {
 394         u32 region, res_a;
 395
 396         pci_read_config_dword(dev, 0x40, &region);
 397         quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
 398         pci_read_config_dword(dev, 0x90, &region);
 399         quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
 400
 401         /* Device resource A has enables for some of the other ones */
 402         pci_read_config_dword(dev, 0x5c, &res_a);
 403
 404         piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
 405         piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
 406
 407         /* Device resource D is just bitfields for static resources */
 408
 409         /* Device 12 enabled? */
 410         if (res_a & (1 << 29)) {
 411                 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
 412                 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
 413         }
 414         /* Device 13 enabled? */
 415         if (res_a & (1 << 30)) {
 416                 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
 417                 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
 418         }
 419         piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
 420         piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
 421 }
 422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi);
 423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82443MX_3,  quirk_piix4_acpi);
 424
 425 /*
 426  * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
 427  *      0x40 (128 bytes of ACPI, GPIO & TCO registers)
 428  *      0x58 (64 bytes of GPIO I/O space)
 429  */
 430 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
 431 {
 432         u32 region;
 433
 434         pci_read_config_dword(dev, 0x40, &region);
 435         quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
 436
 437         pci_read_config_dword(dev, 0x58, &region);
 438         quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
 439 }
 440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,         quirk_ich4_lpc_acpi);
 441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,         quirk_ich4_lpc_acpi);
 442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,         quirk_ich4_lpc_acpi);
 443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,        quirk_ich4_lpc_acpi);
 444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,         quirk_ich4_lpc_acpi);
 445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,        quirk_ich4_lpc_acpi);
 446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,         quirk_ich4_lpc_acpi);
 447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,        quirk_ich4_lpc_acpi);
 448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,         quirk_ich4_lpc_acpi);
 449 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,             quirk_ich4_lpc_acpi);
 450
 451 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
 452 {
 453         u32 region;
 454
 455         pci_read_config_dword(dev, 0x40, &region);
 456         quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
 457
 458         pci_read_config_dword(dev, 0x48, &region);
 459         quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
 460 }
 461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
 462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
 463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
 464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
 465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
 466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
 467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
 468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
 469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
 471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
 472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
 473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
 474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
 475
 476 /*
 477  * VIA ACPI: One IO region pointed to by longword at
 478  *      0x48 or 0x20 (256 bytes of ACPI registers)
 479  */
 480 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
 481 {
 482         u32 region;
 483
 484         if (dev->revision & 0x10) {
 485                 pci_read_config_dword(dev, 0x48, &region);
 486                 region &= PCI_BASE_ADDRESS_IO_MASK;
 487                 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
 488         }
 489 }
 490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_vt82c586_acpi);
 491
 492 /*
 493  * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 494  *      0x48 (256 bytes of ACPI registers)
 495  *      0x70 (128 bytes of hardware monitoring register)
 496  *      0x90 (16 bytes of SMB registers)
 497  */
 498 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
 499 {
 500         u16 hm;
 501         u32 smb;
 502
 503         quirk_vt82c586_acpi(dev);
 504
 505         pci_read_config_word(dev, 0x70, &hm);
 506         hm &= PCI_BASE_ADDRESS_IO_MASK;
 507         quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
 508
 509         pci_read_config_dword(dev, 0x90, &smb);
 510         smb &= PCI_BASE_ADDRESS_IO_MASK;
 511         quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
 512 }
 513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_vt82c686_acpi);
 514
 515 /*
 516  * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
 517  *      0x88 (128 bytes of power management registers)
 518  *      0xd0 (16 bytes of SMB registers)
 519  */
 520 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
 521 {
 522         u16 pm, smb;
 523
 524         pci_read_config_word(dev, 0x88, &pm);
 525         pm &= PCI_BASE_ADDRESS_IO_MASK;
 526         quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
 527
 528         pci_read_config_word(dev, 0xd0, &smb);
 529         smb &= PCI_BASE_ADDRESS_IO_MASK;
 530         quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
 531 }
 532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
 533
 534
 535 #ifdef CONFIG_X86_IO_APIC
 536
 537 #include <asm/io_apic.h>
 538
 539 /*
 540  * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
 541  * devices to the external APIC.
 542  *
 543  * TODO: When we have device-specific interrupt routers,
 544  * this code will go away from quirks.
 545  */
 546 static void quirk_via_ioapic(struct pci_dev *dev)
 547 {
 548         u8 tmp;
 549
 550         if (nr_ioapics < 1)
 551                 tmp = 0;    /* nothing routed to external APIC */
 552         else
 553                 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
 554
 555         dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
 556                tmp == 0 ? "Disa" : "Ena");
 557
 558         /* Offset 0x58: External APIC IRQ output control */
 559         pci_write_config_byte (dev, 0x58, tmp);
 560 }
 561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 562 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 563
 564 /*
 565  * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
 566  * This leads to doubled level interrupt rates.
 567  * Set this bit to get rid of cycle wastage.
 568  * Otherwise uncritical.
 569  */
 570 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
 571 {
 572         u8 misc_control2;
 573 #define BYPASS_APIC_DEASSERT 8
 574
 575         pci_read_config_byte(dev, 0x5B, &misc_control2);
 576         if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
 577                 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
 578                 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
 579         }
 580 }
 581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
 582 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
 583
 584 /*
 585  * The AMD io apic can hang the box when an apic irq is masked.
 586  * We check all revs >= B0 (yet not in the pre production!) as the bug
 587  * is currently marked NoFix
 588  *
 589  * We have multiple reports of hangs with this chipset that went away with
 590  * noapic specified. For the moment we assume it's the erratum. We may be wrong
 591  * of course. However the advice is demonstrably good even if so..
 592  */
 593 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
 594 {
 595         if (dev->revision >= 0x02) {
 596                 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
 597                 dev_warn(&dev->dev, "        : booting with the \"noapic\" option\n");
 598         }
 599 }
 600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic);
 601
 602 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
 603 {
 604         if (dev->devfn == 0 && dev->bus->number == 0)
 605                 sis_apic_bug = 1;
 606 }
 607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_ANY_ID,                     quirk_ioapic_rmw);
 608
 609 #define AMD8131_revA0        0x01
 610 #define AMD8131_revB0        0x11
 611 #define AMD8131_MISC         0x40
 612 #define AMD8131_NIOAMODE_BIT 0
 613 static void quirk_amd_8131_ioapic(struct pci_dev *dev)
 614 {
 615         unsigned char tmp;
 616
 617         if (nr_ioapics == 0)
 618                 return;
 619
 620         if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
 621                 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
 622                 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
 623                 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
 624                 pci_write_config_byte( dev, AMD8131_MISC, tmp);
 625         }
 626 }
 627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
 628 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
 629 #endif /* CONFIG_X86_IO_APIC */
 630
 631 /*
 632  * Some settings of MMRBC can lead to data corruption so block changes.
 633  * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
 634  */
 635 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
 636 {
 637         if (dev->subordinate && dev->revision <= 0x12) {
 638                 dev_info(&dev->dev, "AMD8131 rev %x detected; "
 639                         "disabling PCI-X MMRBC\n", dev->revision);
 640                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
 641         }
 642 }
 643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
 644
 645 /*
 646  * FIXME: it is questionable that quirk_via_acpi
 647  * is needed.  It shows up as an ISA bridge, and does not
 648  * support the PCI_INTERRUPT_LINE register at all.  Therefore
 649  * it seems like setting the pci_dev's 'irq' to the
 650  * value of the ACPI SCI interrupt is only done for convenience.
 651  *      -jgarzik
 652  */
 653 static void __devinit quirk_via_acpi(struct pci_dev *d)
 654 {
 655         /*
 656          * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
 657          */
 658         u8 irq;
 659         pci_read_config_byte(d, 0x42, &irq);
 660         irq &= 0xf;
 661         if (irq && (irq != 2))
 662                 d->irq = irq;
 663 }
 664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_via_acpi);
 665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_via_acpi);
 666
 667
 668 /*
 669  *      VIA bridges which have VLink
 670  */
 671
 672 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
 673
 674 static void quirk_via_bridge(struct pci_dev *dev)
 675 {
 676         /* See what bridge we have and find the device ranges */
 677         switch (dev->device) {
 678         case PCI_DEVICE_ID_VIA_82C686:
 679                 /* The VT82C686 is special, it attaches to PCI and can have
 680                    any device number. All its subdevices are functions of
 681                    that single device. */
 682                 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
 683                 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
 684                 break;
 685         case PCI_DEVICE_ID_VIA_8237:
 686         case PCI_DEVICE_ID_VIA_8237A:
 687                 via_vlink_dev_lo = 15;
 688                 break;
 689         case PCI_DEVICE_ID_VIA_8235:
 690                 via_vlink_dev_lo = 16;
 691                 break;
 692         case PCI_DEVICE_ID_VIA_8231:
 693         case PCI_DEVICE_ID_VIA_8233_0:
 694         case PCI_DEVICE_ID_VIA_8233A:
 695         case PCI_DEVICE_ID_VIA_8233C_0:
 696                 via_vlink_dev_lo = 17;
 697                 break;
 698         }
 699 }
 700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686,       quirk_via_bridge);
 701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8231,         quirk_via_bridge);
 702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233_0,       quirk_via_bridge);
 703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233A,        quirk_via_bridge);
 704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233C_0,      quirk_via_bridge);
 705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235,         quirk_via_bridge);
 706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237,         quirk_via_bridge);
 707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237A,        quirk_via_bridge);
 708
 709 /**
 710  *      quirk_via_vlink         -       VIA VLink IRQ number update
 711  *      @dev: PCI device
 712  *
 713  *      If the device we are dealing with is on a PIC IRQ we need to
 714  *      ensure that the IRQ line register which usually is not relevant
 715  *      for PCI cards, is actually written so that interrupts get sent
 716  *      to the right place.
 717  *      We only do this on systems where a VIA south bridge was detected,
 718  *      and only for VIA devices on the motherboard (see quirk_via_bridge
 719  *      above).
 720  */
 721
 722 static void quirk_via_vlink(struct pci_dev *dev)
 723 {
 724         u8 irq, new_irq;
 725
 726         /* Check if we have VLink at all */
 727         if (via_vlink_dev_lo == -1)
 728                 return;
 729
 730         new_irq = dev->irq;
 731
 732         /* Don't quirk interrupts outside the legacy IRQ range */
 733         if (!new_irq || new_irq > 15)
 734                 return;
 735
 736         /* Internal device ? */
 737         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
 738             PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
 739                 return;
 740
 741         /* This is an internal VLink device on a PIC interrupt. The BIOS
 742            ought to have set this but may not have, so we redo it */
 743
 744         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 745         if (new_irq != irq) {
 746                 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
 747                         irq, new_irq);
 748                 udelay(15);     /* unknown if delay really needed */
 749                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
 750         }
 751 }
 752 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
 753
 754 /*
 755  * VIA VT82C598 has its device ID settable and many BIOSes
 756  * set it to the ID of VT82C597 for backward compatibility.
 757  * We need to switch it off to be able to recognize the real
 758  * type of the chip.
 759  */
 760 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
 761 {
 762         pci_write_config_byte(dev, 0xfc, 0);
 763         pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
 764 }
 765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C597_0,     quirk_vt82c598_id);
 766
 767 /*
 768  * CardBus controllers have a legacy base address that enables them
 769  * to respond as i82365 pcmcia controllers.  We don't want them to
 770  * do this even if the Linux CardBus driver is not loaded, because
 771  * the Linux i82365 driver does not (and should not) handle CardBus.
 772  */
 773 static void quirk_cardbus_legacy(struct pci_dev *dev)
 774 {
 775         if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
 776                 return;
 777         pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
 778 }
 779 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
 780 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
 781
 782 /*
 783  * Following the PCI ordering rules is optional on the AMD762. I'm not
 784  * sure what the designers were smoking but let's not inhale...
 785  *
 786  * To be fair to AMD, it follows the spec by default, its BIOS people
 787  * who turn it off!
 788  */
 789 static void quirk_amd_ordering(struct pci_dev *dev)
 790 {
 791         u32 pcic;
 792         pci_read_config_dword(dev, 0x4C, &pcic);
 793         if ((pcic&6)!=6) {
 794                 pcic |= 6;
 795                 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
 796                 pci_write_config_dword(dev, 0x4C, pcic);
 797                 pci_read_config_dword(dev, 0x84, &pcic);
 798                 pcic |= (1<<23);        /* Required in this mode */
 799                 pci_write_config_dword(dev, 0x84, pcic);
 800         }
 801 }
 802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
 803 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,       PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
 804
 805 /*
 806  *      DreamWorks provided workaround for Dunord I-3000 problem
 807  *
 808  *      This card decodes and responds to addresses not apparently
 809  *      assigned to it. We force a larger allocation to ensure that
 810  *      nothing gets put too close to it.
 811  */
 812 static void __devinit quirk_dunord ( struct pci_dev * dev )
 813 {
 814         struct resource *r = &dev->resource [1];
 815         r->start = 0;
 816         r->end = 0xffffff;
 817 }
 818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,  PCI_DEVICE_ID_DUNORD_I3000,     quirk_dunord);
 819
 820 /*
 821  * i82380FB mobile docking controller: its PCI-to-PCI bridge
 822  * is subtractive decoding (transparent), and does indicate this
 823  * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
 824  * instead of 0x01.
 825  */
 826 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
 827 {
 828         dev->transparent = 1;
 829 }
 830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82380FB,    quirk_transparent_bridge);
 831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605,  quirk_transparent_bridge);
 832
 833 /*
 834  * Common misconfiguration of the MediaGX/Geode PCI master that will
 835  * reduce PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1
 836  * datasheets found at http://www.national.com/ds/GX for info on what
 837  * these bits do.  <christer@weinigel.se>
 838  */
 839 static void quirk_mediagx_master(struct pci_dev *dev)
 840 {
 841         u8 reg;
 842         pci_read_config_byte(dev, 0x41, &reg);
 843         if (reg & 2) {
 844                 reg &= ~2;
 845                 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
 846                 pci_write_config_byte(dev, 0x41, reg);
 847         }
 848 }
 849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,    PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
 850 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,   PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
 851
 852 /*
 853  *      Ensure C0 rev restreaming is off. This is normally done by
 854  *      the BIOS but in the odd case it is not the results are corruption
 855  *      hence the presence of a Linux check
 856  */
 857 static void quirk_disable_pxb(struct pci_dev *pdev)
 858 {
 859         u16 config;
 860
 861         if (pdev->revision != 0x04)             /* Only C0 requires this */
 862                 return;
 863         pci_read_config_word(pdev, 0x40, &config);
 864         if (config & (1<<6)) {
 865                 config &= ~(1<<6);
 866                 pci_write_config_word(pdev, 0x40, config);
 867                 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
 868         }
 869 }
 870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
 871 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
 872
 873 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
 874 {
 875         /* set sb600/sb700/sb800 sata to ahci mode */
 876         u8 tmp;
 877
 878         pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
 879         if (tmp == 0x01) {
 880                 pci_read_config_byte(pdev, 0x40, &tmp);
 881                 pci_write_config_byte(pdev, 0x40, tmp|1);
 882                 pci_write_config_byte(pdev, 0x9, 1);
 883                 pci_write_config_byte(pdev, 0xa, 6);
 884                 pci_write_config_byte(pdev, 0x40, tmp);
 885
 886                 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
 887                 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
 888         }
 889 }
 890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
 891 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
 892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
 893 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
 894
 895 /*
 896  *      Serverworks CSB5 IDE does not fully support native mode
 897  */
 898 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
 899 {
 900         u8 prog;
 901         pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
 902         if (prog & 5) {
 903                 prog &= ~5;
 904                 pdev->class &= ~5;
 905                 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
 906                 /* PCI layer will sort out resources */
 907         }
 908 }
 909 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
 910
 911 /*
 912  *      Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
 913  */
 914 static void __init quirk_ide_samemode(struct pci_dev *pdev)
 915 {
 916         u8 prog;
 917
 918         pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
 919
 920         if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
 921                 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
 922                 prog &= ~5;
 923                 pdev->class &= ~5;
 924                 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
 925         }
 926 }
 927 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
 928
 929 /*
 930  * Some ATA devices break if put into D3
 931  */
 932
 933 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
 934 {
 935         /* Quirk the legacy ATA devices only. The AHCI ones are ok */
 936         if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 937                 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
 938 }
 939 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
 940 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
 941
 942 /* This was originally an Alpha specific thing, but it really fits here.
 943  * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
 944  */
 945 static void __init quirk_eisa_bridge(struct pci_dev *dev)
 946 {
 947         dev->class = PCI_CLASS_BRIDGE_EISA << 8;
 948 }
 949 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82375,      quirk_eisa_bridge);
 950
 951
 952 /*
 953  * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
 954  * is not activated. The myth is that Asus said that they do not want the
 955  * users to be irritated by just another PCI Device in the Win98 device
 956  * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
 957  * package 2.7.0 for details)
 958  *
 959  * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
 960  * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
 961  * becomes necessary to do this tweak in two steps -- the chosen trigger
 962  * is either the Host bridge (preferred) or on-board VGA controller.
 963  *
 964  * Note that we used to unhide the SMBus that way on Toshiba laptops
 965  * (Satellite A40 and Tecra M2) but then found that the thermal management
 966  * was done by SMM code, which could cause unsynchronized concurrent
 967  * accesses to the SMBus registers, with potentially bad effects. Thus you
 968  * should be very careful when adding new entries: if SMM is accessing the
 969  * Intel SMBus, this is a very good reason to leave it hidden.
 970  *
 971  * Likewise, many recent laptops use ACPI for thermal management. If the
 972  * ACPI DSDT code accesses the SMBus, then Linux should not access it
 973  * natively, and keeping the SMBus hidden is the right thing to do. If you
 974  * are about to add an entry in the table below, please first disassemble
 975  * the DSDT and double-check that there is no code accessing the SMBus.
 976  */
 977 static int asus_hides_smbus;
 978
 979 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
 980 {
 981         if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
 982                 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
 983                         switch(dev->subsystem_device) {
 984                         case 0x8025: /* P4B-LX */
 985                         case 0x8070: /* P4B */
 986                         case 0x8088: /* P4B533 */
 987                         case 0x1626: /* L3C notebook */
 988                                 asus_hides_smbus = 1;
 989                         }
 990                 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
 991                         switch(dev->subsystem_device) {
 992                         case 0x80b1: /* P4GE-V */
 993                         case 0x80b2: /* P4PE */
 994                         case 0x8093: /* P4B533-V */
 995                                 asus_hides_smbus = 1;
 996                         }
 997                 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
 998                         switch(dev->subsystem_device) {
 999                         case 0x8030: /* P4T533 */
1000                                 asus_hides_smbus = 1;
1001                         }
1002                 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1003                         switch (dev->subsystem_device) {
1004                         case 0x8070: /* P4G8X Deluxe */
1005                                 asus_hides_smbus = 1;
1006                         }
1007                 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1008                         switch (dev->subsystem_device) {
1009                         case 0x80c9: /* PU-DLS */
1010                                 asus_hides_smbus = 1;
1011                         }
1012                 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1013                         switch (dev->subsystem_device) {
1014                         case 0x1751: /* M2N notebook */
1015                         case 0x1821: /* M5N notebook */
1016                                 asus_hides_smbus = 1;
1017                         }
1018                 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1019                         switch (dev->subsystem_device) {
1020                         case 0x184b: /* W1N notebook */
1021                         case 0x186a: /* M6Ne notebook */
1022                                 asus_hides_smbus = 1;
1023                         }
1024                 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1025                         switch (dev->subsystem_device) {
1026                         case 0x80f2: /* P4P800-X */
1027                                 asus_hides_smbus = 1;
1028                         }
1029                 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1030                         switch (dev->subsystem_device) {
1031                         case 0x1882: /* M6V notebook */
1032                         case 0x1977: /* A6VA notebook */
1033                                 asus_hides_smbus = 1;
1034                         }
1035         } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1036                 if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1037                         switch(dev->subsystem_device) {
1038                         case 0x088C: /* HP Compaq nc8000 */
1039                         case 0x0890: /* HP Compaq nc6000 */
1040                                 asus_hides_smbus = 1;
1041                         }
1042                 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1043                         switch (dev->subsystem_device) {
1044                         case 0x12bc: /* HP D330L */
1045                         case 0x12bd: /* HP D530 */
1046                                 asus_hides_smbus = 1;
1047                         }
1048                 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1049                         switch (dev->subsystem_device) {
1050                         case 0x12bf: /* HP xw4100 */
1051                                 asus_hides_smbus = 1;
1052                         }
1053        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1054                if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1055                        switch(dev->subsystem_device) {
1056                        case 0xC00C: /* Samsung P35 notebook */
1057                                asus_hides_smbus = 1;
1058                        }
1059         } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1060                 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1061                         switch(dev->subsystem_device) {
1062                         case 0x0058: /* Compaq Evo N620c */
1063                                 asus_hides_smbus = 1;
1064                         }
1065                 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1066                         switch(dev->subsystem_device) {
1067                         case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1068                                 /* Motherboard doesn't have Host bridge
1069                                  * subvendor/subdevice IDs, therefore checking
1070                                  * its on-board VGA controller */
1071                                 asus_hides_smbus = 1;
1072                         }
1073                 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1074                         switch(dev->subsystem_device) {
1075                         case 0x00b8: /* Compaq Evo D510 CMT */
1076                         case 0x00b9: /* Compaq Evo D510 SFF */
1077                                 asus_hides_smbus = 1;
1078                         }
1079                 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1080                         switch (dev->subsystem_device) {
1081                         case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1082                                 /* Motherboard doesn't have host bridge
1083                                  * subvendor/subdevice IDs, therefore checking
1084                                  * its on-board VGA controller */
1085                                 asus_hides_smbus = 1;
1086                         }
1087         }
1088 }
1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845_HB,   asus_hides_smbus_hostbridge);
1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845G_HB,  asus_hides_smbus_hostbridge);
1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82850_HB,   asus_hides_smbus_hostbridge);
1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82865_HB,   asus_hides_smbus_hostbridge);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82875_HB,   asus_hides_smbus_hostbridge);
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_7205_0,     asus_hides_smbus_hostbridge);
1095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_E7501_MCH,  asus_hides_smbus_hostbridge);
1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1099
1100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82810_IG3,  asus_hides_smbus_hostbridge);
1101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845G_IG,  asus_hides_smbus_hostbridge);
1102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82815_CGC,  asus_hides_smbus_hostbridge);
1103
1104 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1105 {
1106         u16 val;
1107
1108         if (likely(!asus_hides_smbus))
1109                 return;
1110
1111         pci_read_config_word(dev, 0xF2, &val);
1112         if (val & 0x8) {
1113                 pci_write_config_word(dev, 0xF2, val & (~0x8));
1114                 pci_read_config_word(dev, 0xF2, &val);
1115                 if (val & 0x8)
1116                         dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1117                 else
1118                         dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1119         }
1120 }
1121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1128 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1129 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1130 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1131 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1132 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1133 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1134 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1135
1136 /* It appears we just have one such device. If not, we have a warning */
1137 static void __iomem *asus_rcba_base;
1138 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1139 {
1140         u32 rcba;
1141
1142         if (likely(!asus_hides_smbus))
1143                 return;
1144         WARN_ON(asus_rcba_base);
1145
1146         pci_read_config_dword(dev, 0xF0, &rcba);
1147         /* use bits 31:14, 16 kB aligned */
1148         asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1149         if (asus_rcba_base == NULL)
1150                 return;
1151 }
1152
1153 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1154 {
1155         u32 val;
1156
1157         if (likely(!asus_hides_smbus || !asus_rcba_base))
1158                 return;
1159         /* read the Function Disable register, dword mode only */
1160         val = readl(asus_rcba_base + 0x3418);
1161         writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1162 }
1163
1164 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1165 {
1166         if (likely(!asus_hides_smbus || !asus_rcba_base))
1167                 return;
1168         iounmap(asus_rcba_base);
1169         asus_rcba_base = NULL;
1170         dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1171 }
1172
1173 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1174 {
1175         asus_hides_smbus_lpc_ich6_suspend(dev);
1176         asus_hides_smbus_lpc_ich6_resume_early(dev);
1177         asus_hides_smbus_lpc_ich6_resume(dev);
1178 }
1179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6);
1180 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_suspend);
1181 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume);
1182 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume_early);
1183
1184 /*
1185  * SiS 96x south bridge: BIOS typically hides SMBus device...
1186  */
1187 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1188 {
1189         u8 val = 0;
1190         pci_read_config_byte(dev, 0x77, &val);
1191         if (val & 0x10) {
1192                 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1193                 pci_write_config_byte(dev, 0x77, val & ~0x10);
1194         }
1195 }
1196 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1200 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1201 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1202 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1203 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1204
1205 /*
1206  * ... This is further complicated by the fact that some SiS96x south
1207  * bridges pretend to be 85C503/5513 instead.  In that case see if we
1208  * spotted a compatible north bridge to make sure.
1209  * (pci_find_device doesn't work yet)
1210  *
1211  * We can also enable the sis96x bit in the discovery register..
1212  */
1213 #define SIS_DETECT_REGISTER 0x40
1214
1215 static void quirk_sis_503(struct pci_dev *dev)
1216 {
1217         u8 reg;
1218         u16 devid;
1219
1220         pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1221         pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1222         pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1223         if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1224                 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1225                 return;
1226         }
1227
1228         /*
1229          * Ok, it now shows up as a 96x.. run the 96x quirk by
1230          * hand in case it has already been processed.
1231          * (depends on link order, which is apparently not guaranteed)
1232          */
1233         dev->device = devid;
1234         quirk_sis_96x_smbus(dev);
1235 }
1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1237 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1238
1239
1240 /*
1241  * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1242  * and MC97 modem controller are disabled when a second PCI soundcard is
1243  * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1244  * -- bjd
1245  */
1246 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1247 {
1248         u8 val;
1249         int asus_hides_ac97 = 0;
1250
1251         if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1252                 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1253                         asus_hides_ac97 = 1;
1254         }
1255
1256         if (!asus_hides_ac97)
1257                 return;
1258
1259         pci_read_config_byte(dev, 0x50, &val);
1260         if (val & 0xc0) {
1261                 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1262                 pci_read_config_byte(dev, 0x50, &val);
1263                 if (val & 0xc0)
1264                         dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1265                 else
1266                         dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1267         }
1268 }
1269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1270 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1271
1272 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1273
1274 /*
1275  *      If we are using libata we can drive this chip properly but must
1276  *      do this early on to make the additional device appear during
1277  *      the PCI scanning.
1278  */
1279 static void quirk_jmicron_ata(struct pci_dev *pdev)
1280 {
1281         u32 conf1, conf5, class;
1282         u8 hdr;
1283
1284         /* Only poke fn 0 */
1285         if (PCI_FUNC(pdev->devfn))
1286                 return;
1287
1288         pci_read_config_dword(pdev, 0x40, &conf1);
1289         pci_read_config_dword(pdev, 0x80, &conf5);
1290
1291         conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1292         conf5 &= ~(1 << 24);  /* Clear bit 24 */
1293
1294         switch (pdev->device) {
1295         case PCI_DEVICE_ID_JMICRON_JMB360:
1296                 /* The controller should be in single function ahci mode */
1297                 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1298                 break;
1299
1300         case PCI_DEVICE_ID_JMICRON_JMB365:
1301         case PCI_DEVICE_ID_JMICRON_JMB366:
1302                 /* Redirect IDE second PATA port to the right spot */
1303                 conf5 |= (1 << 24);
1304                 /* Fall through */
1305         case PCI_DEVICE_ID_JMICRON_JMB361:
1306         case PCI_DEVICE_ID_JMICRON_JMB363:
1307                 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1308                 /* Set the class codes correctly and then direct IDE 0 */
1309                 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1310                 break;
1311
1312         case PCI_DEVICE_ID_JMICRON_JMB368:
1313                 /* The controller should be in single function IDE mode */
1314                 conf1 |= 0x00C00000; /* Set 22, 23 */
1315                 break;
1316         }
1317
1318         pci_write_config_dword(pdev, 0x40, conf1);
1319         pci_write_config_dword(pdev, 0x80, conf5);
1320
1321         /* Update pdev accordingly */
1322         pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1323         pdev->hdr_type = hdr & 0x7f;
1324         pdev->multifunction = !!(hdr & 0x80);
1325
1326         pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1327         pdev->class = class >> 8;
1328 }
1329 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1330 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1331 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1332 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1333 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1334 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1335 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1336 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1337 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1338 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1339 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1340 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1341
1342 #endif
1343
1344 #ifdef CONFIG_X86_IO_APIC
1345 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1346 {
1347         int i;
1348
1349         if ((pdev->class >> 8) != 0xff00)
1350                 return;
1351
1352         /* the first BAR is the location of the IO APIC...we must
1353          * not touch this (and it's already covered by the fixmap), so
1354          * forcibly insert it into the resource tree */
1355         if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1356                 insert_resource(&iomem_resource, &pdev->resource[0]);
1357
1358         /* The next five BARs all seem to be rubbish, so just clean
1359          * them out */
1360         for (i=1; i < 6; i++) {
1361                 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1362         }
1363
1364 }
1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_EESSC,      quirk_alder_ioapic);
1366 #endif
1367
1368 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1369 {
1370         pcie_mch_quirk = 1;
1371 }
1372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7520_MCH,  quirk_pcie_mch);
1373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7320_MCH,  quirk_pcie_mch);
1374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7525_MCH,  quirk_pcie_mch);
1375
1376
1377 /*
1378  * It's possible for the MSI to get corrupted if shpc and acpi
1379  * are used together on certain PXH-based systems.
1380  */
1381 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1382 {
1383         pci_msi_off(dev);
1384         dev->no_msi = 1;
1385         dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1386 }
1387 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_0,     quirk_pcie_pxh);
1388 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_1,     quirk_pcie_pxh);
1389 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_pcie_pxh);
1390 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_pcie_pxh);
1391 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_pcie_pxh);
1392
1393 /*
1394  * Some Intel PCI Express chipsets have trouble with downstream
1395  * device power management.
1396  */
1397 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1398 {
1399         pci_pm_d3_delay = 120;
1400         dev->no_d1d2 = 1;
1401 }
1402
1403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e2, quirk_intel_pcie_pm);
1404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e3, quirk_intel_pcie_pm);
1405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e4, quirk_intel_pcie_pm);
1406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e5, quirk_intel_pcie_pm);
1407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e6, quirk_intel_pcie_pm);
1408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e7, quirk_intel_pcie_pm);
1409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f7, quirk_intel_pcie_pm);
1410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f8, quirk_intel_pcie_pm);
1411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f9, quirk_intel_pcie_pm);
1412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25fa, quirk_intel_pcie_pm);
1413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2601, quirk_intel_pcie_pm);
1414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2602, quirk_intel_pcie_pm);
1415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2603, quirk_intel_pcie_pm);
1416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2604, quirk_intel_pcie_pm);
1417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2605, quirk_intel_pcie_pm);
1418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2606, quirk_intel_pcie_pm);
1419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2607, quirk_intel_pcie_pm);
1420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2608, quirk_intel_pcie_pm);
1421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2609, quirk_intel_pcie_pm);
1422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260a, quirk_intel_pcie_pm);
1423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260b, quirk_intel_pcie_pm);
1424
1425 /*
1426  * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1427  * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1428  * Re-allocate the region if needed...
1429  */
1430 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1431 {
1432         struct resource *r = &dev->resource[0];
1433
1434         if (r->start & 0x8) {
1435                 r->start = 0;
1436                 r->end = 0xf;
1437         }
1438 }
1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1440                          PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1441                          quirk_tc86c001_ide);
1442
1443 static void __devinit quirk_netmos(struct pci_dev *dev)
1444 {
1445         unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1446         unsigned int num_serial = dev->subsystem_device & 0xf;
1447
1448         /*
1449          * These Netmos parts are multiport serial devices with optional
1450          * parallel ports.  Even when parallel ports are present, they
1451          * are identified as class SERIAL, which means the serial driver
1452          * will claim them.  To prevent this, mark them as class OTHER.
1453          * These combo devices should be claimed by parport_serial.
1454          *
1455          * The subdevice ID is of the form 0x00PS, where <P> is the number
1456          * of parallel ports and <S> is the number of serial ports.
1457          */
1458         switch (dev->device) {
1459         case PCI_DEVICE_ID_NETMOS_9735:
1460         case PCI_DEVICE_ID_NETMOS_9745:
1461         case PCI_DEVICE_ID_NETMOS_9835:
1462         case PCI_DEVICE_ID_NETMOS_9845:
1463         case PCI_DEVICE_ID_NETMOS_9855:
1464                 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1465                     num_parallel) {
1466                         dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1467                                 "%u serial); changing class SERIAL to OTHER "
1468                                 "(use parport_serial)\n",
1469                                 dev->device, num_parallel, num_serial);
1470                         dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1471                             (dev->class & 0xff);
1472                 }
1473         }
1474 }
1475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1476
1477 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1478 {
1479         u16 command, pmcsr;
1480         u8 __iomem *csr;
1481         u8 cmd_hi;
1482         int pm;
1483
1484         switch (dev->device) {
1485         /* PCI IDs taken from drivers/net/e100.c */
1486         case 0x1029:
1487         case 0x1030 ... 0x1034:
1488         case 0x1038 ... 0x103E:
1489         case 0x1050 ... 0x1057:
1490         case 0x1059:
1491         case 0x1064 ... 0x106B:
1492         case 0x1091 ... 0x1095:
1493         case 0x1209:
1494         case 0x1229:
1495         case 0x2449:
1496         case 0x2459:
1497         case 0x245D:
1498         case 0x27DC:
1499                 break;
1500         default:
1501                 return;
1502         }
1503
1504         /*
1505          * Some firmware hands off the e100 with interrupts enabled,
1506          * which can cause a flood of interrupts if packets are
1507          * received before the driver attaches to the device.  So
1508          * disable all e100 interrupts here.  The driver will
1509          * re-enable them when it's ready.
1510          */
1511         pci_read_config_word(dev, PCI_COMMAND, &command);
1512
1513         if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1514                 return;
1515
1516         /*
1517          * Check that the device is in the D0 power state. If it's not,
1518          * there is no point to look any further.
1519          */
1520         pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1521         if (pm) {
1522                 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1523                 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1524                         return;
1525         }
1526
1527         /* Convert from PCI bus to resource space.  */
1528         csr = ioremap(pci_resource_start(dev, 0), 8);
1529         if (!csr) {
1530                 dev_warn(&dev->dev, "Can't map e100 registers\n");
1531                 return;
1532         }
1533
1534         cmd_hi = readb(csr + 3);
1535         if (cmd_hi == 0) {
1536                 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1537                         "disabling\n");
1538                 writeb(1, csr + 3);
1539         }
1540
1541         iounmap(csr);
1542 }
1543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1544
1545 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1546 {
1547         /* rev 1 ncr53c810 chips don't set the class at all which means
1548          * they don't get their resources remapped. Fix that here.
1549          */
1550
1551         if (dev->class == PCI_CLASS_NOT_DEFINED) {
1552                 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1553                 dev->class = PCI_CLASS_STORAGE_SCSI;
1554         }
1555 }
1556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1557
1558 /* Enable 1k I/O space granularity on the Intel P64H2 */
1559 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1560 {
1561         u16 en1k;
1562         u8 io_base_lo, io_limit_lo;
1563         unsigned long base, limit;
1564         struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1565
1566         pci_read_config_word(dev, 0x40, &en1k);
1567
1568         if (en1k & 0x200) {
1569                 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1570
1571                 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1572                 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1573                 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1574                 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1575
1576                 if (base <= limit) {
1577                         res->start = base;
1578                         res->end = limit + 0x3ff;
1579                 }
1580         }
1581 }
1582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   0x1460,         quirk_p64h2_1k_io);
1583
1584 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1585  * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1586  * in drivers/pci/setup-bus.c
1587  */
1588 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1589 {
1590         u16 en1k, iobl_adr, iobl_adr_1k;
1591         struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1592
1593         pci_read_config_word(dev, 0x40, &en1k);
1594
1595         if (en1k & 0x200) {
1596                 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1597
1598                 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1599
1600                 if (iobl_adr != iobl_adr_1k) {
1601                         dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1602                                 iobl_adr,iobl_adr_1k);
1603                         pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1604                 }
1605         }
1606 }
1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x1460,         quirk_p64h2_1k_io_fix_iobl);
1608
1609 /* Under some circumstances, AER is not linked with extended capabilities.
1610  * Force it to be linked by setting the corresponding control bit in the
1611  * config space.
1612  */
1613 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1614 {
1615         uint8_t b;
1616         if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1617                 if (!(b & 0x20)) {
1618                         pci_write_config_byte(dev, 0xf41, b | 0x20);
1619                         dev_info(&dev->dev,
1620                                "Linking AER extended capability\n");
1621                 }
1622         }
1623 }
1624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1625                         quirk_nvidia_ck804_pcie_aer_ext_cap);
1626 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1627                         quirk_nvidia_ck804_pcie_aer_ext_cap);
1628
1629 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1630 {
1631         /*
1632          * Disable PCI Bus Parking and PCI Master read caching on CX700
1633          * which causes unspecified timing errors with a VT6212L on the PCI
1634          * bus leading to USB2.0 packet loss. The defaults are that these
1635          * features are turned off but some BIOSes turn them on.
1636          */
1637
1638         uint8_t b;
1639         if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1640                 if (b & 0x40) {
1641                         /* Turn off PCI Bus Parking */
1642                         pci_write_config_byte(dev, 0x76, b ^ 0x40);
1643
1644                         dev_info(&dev->dev,
1645                                 "Disabling VIA CX700 PCI parking\n");
1646                 }
1647         }
1648
1649         if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1650                 if (b != 0) {
1651                         /* Turn off PCI Master read caching */
1652                         pci_write_config_byte(dev, 0x72, 0x0);
1653
1654                         /* Set PCI Master Bus time-out to "1x16 PCLK" */
1655                         pci_write_config_byte(dev, 0x75, 0x1);
1656
1657                         /* Disable "Read FIFO Timer" */
1658                         pci_write_config_byte(dev, 0x77, 0x0);
1659
1660                         dev_info(&dev->dev,
1661                                 "Disabling VIA CX700 PCI caching\n");
1662                 }
1663         }
1664 }
1665 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1666
1667 /*
1668  * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1669  * VPD end tag will hang the device.  This problem was initially
1670  * observed when a vpd entry was created in sysfs
1671  * ('/sys/bus/pci/devices/<id>/vpd').   A read to this sysfs entry
1672  * will dump 32k of data.  Reading a full 32k will cause an access
1673  * beyond the VPD end tag causing the device to hang.  Once the device
1674  * is hung, the bnx2 driver will not be able to reset the device.
1675  * We believe that it is legal to read beyond the end tag and
1676  * therefore the solution is to limit the read/write length.
1677  */
1678 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1679 {
1680         /*
1681          * Only disable the VPD capability for 5706, 5706S, 5708,
1682          * 5708S and 5709 rev. A
1683          */
1684         if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
1685             (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
1686             (dev->device == PCI_DEVICE_ID_NX2_5708) ||
1687             (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
1688             ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1689              (dev->revision & 0xf0) == 0x0)) {
1690                 if (dev->vpd)
1691                         dev->vpd->len = 0x80;
1692         }
1693 }
1694
1695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1696                          PCI_DEVICE_ID_NX2_5706,
1697                          quirk_brcm_570x_limit_vpd);
1698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1699                          PCI_DEVICE_ID_NX2_5706S,
1700                          quirk_brcm_570x_limit_vpd);
1701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1702                          PCI_DEVICE_ID_NX2_5708,
1703                          quirk_brcm_570x_limit_vpd);
1704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1705                          PCI_DEVICE_ID_NX2_5708S,
1706                          quirk_brcm_570x_limit_vpd);
1707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1708                          PCI_DEVICE_ID_NX2_5709,
1709                          quirk_brcm_570x_limit_vpd);
1710 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM,
1711                          PCI_DEVICE_ID_NX2_5709S,
1712                          quirk_brcm_570x_limit_vpd);
1713
1714 #ifdef CONFIG_PCI_MSI
1715 /* Some chipsets do not support MSI. We cannot easily rely on setting
1716  * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1717  * some other busses controlled by the chipset even if Linux is not
1718  * aware of it.  Instead of setting the flag on all busses in the
1719  * machine, simply disable MSI globally.
1720  */
1721 static void __init quirk_disable_all_msi(struct pci_dev *dev)
1722 {
1723         pci_no_msi();
1724         dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
1725 }
1726 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1728 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
1729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
1730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
1731
1732 /* Disable MSI on chipsets that are known to not support it */
1733 static void __devinit quirk_disable_msi(struct pci_dev *dev)
1734 {
1735         if (dev->subordinate) {
1736                 dev_warn(&dev->dev, "MSI quirk detected; "
1737                         "subordinate MSI disabled\n");
1738                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1739         }
1740 }
1741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1742
1743 /* Go through the list of Hypertransport capabilities and
1744  * return 1 if a HT MSI capability is found and enabled */
1745 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1746 {
1747         int pos, ttl = 48;
1748
1749         pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1750         while (pos && ttl--) {
1751                 u8 flags;
1752
1753                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1754                                          &flags) == 0)
1755                 {
1756                         dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
1757                                 flags & HT_MSI_FLAGS_ENABLE ?
1758                                 "enabled" : "disabled");
1759                         return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1760                 }
1761
1762                 pos = pci_find_next_ht_capability(dev, pos,
1763                                                   HT_CAPTYPE_MSI_MAPPING);
1764         }
1765         return 0;
1766 }
1767
1768 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1769 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1770 {
1771         if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1772                 dev_warn(&dev->dev, "MSI quirk detected; "
1773                         "subordinate MSI disabled\n");
1774                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1775         }
1776 }
1777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1778                         quirk_msi_ht_cap);
1779
1780
1781 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1782  * MSI are supported if the MSI capability set in any of these mappings.
1783  */
1784 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1785 {
1786         struct pci_dev *pdev;
1787
1788         if (!dev->subordinate)
1789                 return;
1790
1791         /* check HT MSI cap on this chipset and the root one.
1792          * a single one having MSI is enough to be sure that MSI are supported.
1793          */
1794         pdev = pci_get_slot(dev->bus, 0);
1795         if (!pdev)
1796                 return;
1797         if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1798                 dev_warn(&dev->dev, "MSI quirk detected; "
1799                         "subordinate MSI disabled\n");
1800                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1801         }
1802         pci_dev_put(pdev);
1803 }
1804 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1805                         quirk_nvidia_ck804_msi_ht_cap);
1806
1807 /* Force enable MSI mapping capability on HT bridges */
1808 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
1809 {
1810         int pos, ttl = 48;
1811
1812         pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1813         while (pos && ttl--) {
1814                 u8 flags;
1815
1816                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1817                                          &flags) == 0) {
1818                         dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
1819
1820                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1821                                               flags | HT_MSI_FLAGS_ENABLE);
1822                 }
1823                 pos = pci_find_next_ht_capability(dev, pos,
1824                                                   HT_CAPTYPE_MSI_MAPPING);
1825         }
1826 }
1827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1828                          PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1829                          ht_enable_msi_mapping);
1830
1831 static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
1832 {
1833         struct pci_dev *host_bridge;
1834         int pos, ttl = 48;
1835
1836         /*
1837          * HT MSI mapping should be disabled on devices that are below
1838          * a non-Hypertransport host bridge. Locate the host bridge...
1839          */
1840         host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1841         if (host_bridge == NULL) {
1842                 dev_warn(&dev->dev,
1843                          "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1844                 return;
1845         }
1846
1847         pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
1848         if (pos != 0) {
1849                 /* Host bridge is to HT */
1850                 ht_enable_msi_mapping(dev);
1851                 return;
1852         }
1853
1854         /* Host bridge is not to HT, disable HT MSI mapping on this device */
1855         pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1856         while (pos && ttl--) {
1857                 u8 flags;
1858
1859                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1860                                          &flags) == 0) {
1861                         dev_info(&dev->dev, "Disabling HT MSI mapping");
1862                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1863                                               flags & ~HT_MSI_FLAGS_ENABLE);
1864                 }
1865                 pos = pci_find_next_ht_capability(dev, pos,
1866                                                   HT_CAPTYPE_MSI_MAPPING);
1867         }
1868 }
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
1871
1872 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1873 {
1874         dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1875 }
1876 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1877 {
1878         struct pci_dev *p;
1879
1880         /* SB700 MSI issue will be fixed at HW level from revision A21,
1881          * we need check PCI REVISION ID of SMBus controller to get SB700
1882          * revision.
1883          */
1884         p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1885                            NULL);
1886         if (!p)
1887                 return;
1888
1889         if ((p->revision < 0x3B) && (p->revision >= 0x30))
1890                 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1891         pci_dev_put(p);
1892 }
1893 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1894                         PCI_DEVICE_ID_TIGON3_5780,
1895                         quirk_msi_intx_disable_bug);
1896 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1897                         PCI_DEVICE_ID_TIGON3_5780S,
1898                         quirk_msi_intx_disable_bug);
1899 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1900                         PCI_DEVICE_ID_TIGON3_5714,
1901                         quirk_msi_intx_disable_bug);
1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1903                         PCI_DEVICE_ID_TIGON3_5714S,
1904                         quirk_msi_intx_disable_bug);
1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1906                         PCI_DEVICE_ID_TIGON3_5715,
1907                         quirk_msi_intx_disable_bug);
1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1909                         PCI_DEVICE_ID_TIGON3_5715S,
1910                         quirk_msi_intx_disable_bug);
1911
1912 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
1913                         quirk_msi_intx_disable_ati_bug);
1914 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
1915                         quirk_msi_intx_disable_ati_bug);
1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
1917                         quirk_msi_intx_disable_ati_bug);
1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
1919                         quirk_msi_intx_disable_ati_bug);
1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
1921                         quirk_msi_intx_disable_ati_bug);
1922
1923 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1924                         quirk_msi_intx_disable_bug);
1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
1926                         quirk_msi_intx_disable_bug);
1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
1928                         quirk_msi_intx_disable_bug);
1929
1930 #endif /* CONFIG_PCI_MSI */
1931
1932 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1933 {
1934         while (f < end) {
1935                 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1936                     (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1937                         dev_dbg(&dev->dev, "calling %pF\n", f->hook);
1938                         f->hook(dev);
1939                 }
1940                 f++;
1941         }
1942 }
1943
1944 extern struct pci_fixup __start_pci_fixups_early[];
1945 extern struct pci_fixup __end_pci_fixups_early[];
1946 extern struct pci_fixup __start_pci_fixups_header[];
1947 extern struct pci_fixup __end_pci_fixups_header[];
1948 extern struct pci_fixup __start_pci_fixups_final[];
1949 extern struct pci_fixup __end_pci_fixups_final[];
1950 extern struct pci_fixup __start_pci_fixups_enable[];
1951 extern struct pci_fixup __end_pci_fixups_enable[];
1952 extern struct pci_fixup __start_pci_fixups_resume[];
1953 extern struct pci_fixup __end_pci_fixups_resume[];
1954 extern struct pci_fixup __start_pci_fixups_resume_early[];
1955 extern struct pci_fixup __end_pci_fixups_resume_early[];
1956 extern struct pci_fixup __start_pci_fixups_suspend[];
1957 extern struct pci_fixup __end_pci_fixups_suspend[];
1958
1959
1960 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1961 {
1962         struct pci_fixup *start, *end;
1963
1964         switch(pass) {
1965         case pci_fixup_early:
1966                 start = __start_pci_fixups_early;
1967                 end = __end_pci_fixups_early;
1968                 break;
1969
1970         case pci_fixup_header:
1971                 start = __start_pci_fixups_header;
1972                 end = __end_pci_fixups_header;
1973                 break;
1974
1975         case pci_fixup_final:
1976                 start = __start_pci_fixups_final;
1977                 end = __end_pci_fixups_final;
1978                 break;
1979
1980         case pci_fixup_enable:
1981                 start = __start_pci_fixups_enable;
1982                 end = __end_pci_fixups_enable;
1983                 break;
1984
1985         case pci_fixup_resume:
1986                 start = __start_pci_fixups_resume;
1987                 end = __end_pci_fixups_resume;
1988                 break;
1989
1990         case pci_fixup_resume_early:
1991                 start = __start_pci_fixups_resume_early;
1992                 end = __end_pci_fixups_resume_early;
1993                 break;
1994
1995         case pci_fixup_suspend:
1996                 start = __start_pci_fixups_suspend;
1997                 end = __end_pci_fixups_suspend;
1998                 break;
1999
2000         default:
2001                 /* stupid compiler warning, you would think with an enum... */
2002                 return;
2003         }
2004         pci_do_fixups(dev, start, end);
2005 }
2006 #else
2007 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2008 #endif
2009 EXPORT_SYMBOL(pci_fixup_device);