2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
16 #include <asm/processor.h>
17 #include <asm/tlbflush.h>
18 #include <asm/sections.h>
19 #include <asm/setup.h>
20 #include <asm/uaccess.h>
21 #include <asm/pgalloc.h>
22 #include <asm/proto.h>
26 * The current flushing context - we pass it instead of 5 arguments:
35 unsigned force_split
: 1;
41 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
42 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
43 * entries change the page attribute in parallel to some other cpu
44 * splitting a large page entry along with changing the attribute.
46 static DEFINE_SPINLOCK(cpa_lock
);
48 #define CPA_FLUSHTLB 1
50 #define CPA_PAGES_ARRAY 4
53 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
55 void update_page_count(int level
, unsigned long pages
)
59 /* Protect against CPA */
60 spin_lock_irqsave(&pgd_lock
, flags
);
61 direct_pages_count
[level
] += pages
;
62 spin_unlock_irqrestore(&pgd_lock
, flags
);
65 static void split_page_count(int level
)
67 direct_pages_count
[level
]--;
68 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
71 void arch_report_meminfo(struct seq_file
*m
)
73 seq_printf(m
, "DirectMap4k: %8lu kB\n",
74 direct_pages_count
[PG_LEVEL_4K
] << 2);
75 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
76 seq_printf(m
, "DirectMap2M: %8lu kB\n",
77 direct_pages_count
[PG_LEVEL_2M
] << 11);
79 seq_printf(m
, "DirectMap4M: %8lu kB\n",
80 direct_pages_count
[PG_LEVEL_2M
] << 12);
84 seq_printf(m
, "DirectMap1G: %8lu kB\n",
85 direct_pages_count
[PG_LEVEL_1G
] << 20);
89 static inline void split_page_count(int level
) { }
94 static inline unsigned long highmap_start_pfn(void)
96 return __pa(_text
) >> PAGE_SHIFT
;
99 static inline unsigned long highmap_end_pfn(void)
101 return __pa(roundup(_brk_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
106 #ifdef CONFIG_DEBUG_PAGEALLOC
107 # define debug_pagealloc 1
109 # define debug_pagealloc 0
113 within(unsigned long addr
, unsigned long start
, unsigned long end
)
115 return addr
>= start
&& addr
< end
;
123 * clflush_cache_range - flush a cache range with clflush
124 * @addr: virtual start address
125 * @size: number of bytes to flush
127 * clflush is an unordered instruction which needs fencing with mfence
128 * to avoid ordering issues.
130 void clflush_cache_range(void *vaddr
, unsigned int size
)
132 void *vend
= vaddr
+ size
- 1;
136 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
139 * Flush any possible final partial cacheline:
146 static void __cpa_flush_all(void *arg
)
148 unsigned long cache
= (unsigned long)arg
;
151 * Flush all to work around Errata in early athlons regarding
152 * large page flushing.
156 if (cache
&& boot_cpu_data
.x86
>= 4)
160 static void cpa_flush_all(unsigned long cache
)
162 BUG_ON(irqs_disabled());
164 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
167 static void __cpa_flush_range(void *arg
)
170 * We could optimize that further and do individual per page
171 * tlb invalidates for a low number of pages. Caveat: we must
172 * flush the high aliases on 64bit as well.
177 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
179 unsigned int i
, level
;
182 BUG_ON(irqs_disabled());
183 WARN_ON(PAGE_ALIGN(start
) != start
);
185 on_each_cpu(__cpa_flush_range
, NULL
, 1);
191 * We only need to flush on one CPU,
192 * clflush is a MESI-coherent instruction that
193 * will cause all other CPUs to flush the same
196 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
197 pte_t
*pte
= lookup_address(addr
, &level
);
200 * Only flush present addresses:
202 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
203 clflush_cache_range((void *) addr
, PAGE_SIZE
);
207 static void wbinvd_local(void *unused
)
212 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
,
213 int in_flags
, struct page
**pages
)
215 unsigned int i
, level
;
217 BUG_ON(irqs_disabled());
219 on_each_cpu(__cpa_flush_range
, NULL
, 1);
225 if (numpages
>= 1024) {
226 if (boot_cpu_data
.x86
>= 4)
227 on_each_cpu(wbinvd_local
, NULL
, 1);
232 * We only need to flush on one CPU,
233 * clflush is a MESI-coherent instruction that
234 * will cause all other CPUs to flush the same
237 for (i
= 0; i
< numpages
; i
++) {
241 if (in_flags
& CPA_PAGES_ARRAY
)
242 addr
= (unsigned long)page_address(pages
[i
]);
246 pte
= lookup_address(addr
, &level
);
249 * Only flush present addresses:
251 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
252 clflush_cache_range((void *)addr
, PAGE_SIZE
);
257 * Certain areas of memory on x86 require very specific protection flags,
258 * for example the BIOS area or kernel text. Callers don't always get this
259 * right (again, ioremap() on BIOS memory is not uncommon) so this function
260 * checks and fixes these known static required protection bits.
262 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
265 pgprot_t forbidden
= __pgprot(0);
268 * The BIOS area between 640k and 1Mb needs to be executable for
269 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
271 if (within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
272 pgprot_val(forbidden
) |= _PAGE_NX
;
275 * The kernel text needs to be executable for obvious reasons
276 * Does not cover __inittext since that is gone later on. On
277 * 64bit we do not enforce !NX on the low mapping
279 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
280 pgprot_val(forbidden
) |= _PAGE_NX
;
283 * The .rodata section needs to be read-only. Using the pfn
284 * catches all aliases.
286 if (within(pfn
, __pa((unsigned long)__start_rodata
) >> PAGE_SHIFT
,
287 __pa((unsigned long)__end_rodata
) >> PAGE_SHIFT
))
288 pgprot_val(forbidden
) |= _PAGE_RW
;
290 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
296 * Lookup the page table entry for a virtual address. Return a pointer
297 * to the entry and the level of the mapping.
299 * Note: We return pud and pmd either when the entry is marked large
300 * or when the present bit is not set. Otherwise we would return a
301 * pointer to a nonexisting mapping.
303 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
305 pgd_t
*pgd
= pgd_offset_k(address
);
309 *level
= PG_LEVEL_NONE
;
314 pud
= pud_offset(pgd
, address
);
318 *level
= PG_LEVEL_1G
;
319 if (pud_large(*pud
) || !pud_present(*pud
))
322 pmd
= pmd_offset(pud
, address
);
326 *level
= PG_LEVEL_2M
;
327 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
330 *level
= PG_LEVEL_4K
;
332 return pte_offset_kernel(pmd
, address
);
334 EXPORT_SYMBOL_GPL(lookup_address
);
337 * Set the new pmd in all the pgds we know about:
339 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
342 set_pte_atomic(kpte
, pte
);
344 if (!SHARED_KERNEL_PMD
) {
347 list_for_each_entry(page
, &pgd_list
, lru
) {
352 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
353 pud
= pud_offset(pgd
, address
);
354 pmd
= pmd_offset(pud
, address
);
355 set_pte_atomic((pte_t
*)pmd
, pte
);
362 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
363 struct cpa_data
*cpa
)
365 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
, addr
, pfn
;
366 pte_t new_pte
, old_pte
, *tmp
;
367 pgprot_t old_prot
, new_prot
;
371 if (cpa
->force_split
)
374 spin_lock_irqsave(&pgd_lock
, flags
);
376 * Check for races, another CPU might have split this page
379 tmp
= lookup_address(address
, &level
);
385 psize
= PMD_PAGE_SIZE
;
386 pmask
= PMD_PAGE_MASK
;
390 psize
= PUD_PAGE_SIZE
;
391 pmask
= PUD_PAGE_MASK
;
400 * Calculate the number of pages, which fit into this large
401 * page starting at address:
403 nextpage_addr
= (address
+ psize
) & pmask
;
404 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
405 if (numpages
< cpa
->numpages
)
406 cpa
->numpages
= numpages
;
409 * We are safe now. Check whether the new pgprot is the same:
412 old_prot
= new_prot
= pte_pgprot(old_pte
);
414 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
415 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
418 * old_pte points to the large page base address. So we need
419 * to add the offset of the virtual address:
421 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
424 new_prot
= static_protections(new_prot
, address
, pfn
);
427 * We need to check the full range, whether
428 * static_protection() requires a different pgprot for one of
429 * the pages in the range we try to preserve:
431 addr
= address
+ PAGE_SIZE
;
433 for (i
= 1; i
< cpa
->numpages
; i
++, addr
+= PAGE_SIZE
, pfn
++) {
434 pgprot_t chk_prot
= static_protections(new_prot
, addr
, pfn
);
436 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
441 * If there are no changes, return. maxpages has been updated
444 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
450 * We need to change the attributes. Check, whether we can
451 * change the large page in one go. We request a split, when
452 * the address is not aligned and the number of pages is
453 * smaller than the number of pages in the large page. Note
454 * that we limited the number of possible pages already to
455 * the number of pages in the large page.
457 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
459 * The address is aligned and the number of pages
460 * covers the full page.
462 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
463 __set_pmd_pte(kpte
, address
, new_pte
);
464 cpa
->flags
|= CPA_FLUSHTLB
;
469 spin_unlock_irqrestore(&pgd_lock
, flags
);
474 static int split_large_page(pte_t
*kpte
, unsigned long address
)
476 unsigned long flags
, pfn
, pfninc
= 1;
477 unsigned int i
, level
;
482 if (!debug_pagealloc
)
483 spin_unlock(&cpa_lock
);
484 base
= alloc_pages(GFP_KERNEL
, 0);
485 if (!debug_pagealloc
)
486 spin_lock(&cpa_lock
);
490 spin_lock_irqsave(&pgd_lock
, flags
);
492 * Check for races, another CPU might have split this page
495 tmp
= lookup_address(address
, &level
);
499 pbase
= (pte_t
*)page_address(base
);
500 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
501 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
503 * If we ever want to utilize the PAT bit, we need to
504 * update this function to make sure it's converted from
505 * bit 12 to bit 7 when we cross from the 2MB level to
508 WARN_ON_ONCE(pgprot_val(ref_prot
) & _PAGE_PAT_LARGE
);
511 if (level
== PG_LEVEL_1G
) {
512 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
513 pgprot_val(ref_prot
) |= _PAGE_PSE
;
518 * Get the target pfn from the original entry:
520 pfn
= pte_pfn(*kpte
);
521 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
522 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
524 if (address
>= (unsigned long)__va(0) &&
525 address
< (unsigned long)__va(max_low_pfn_mapped
<< PAGE_SHIFT
))
526 split_page_count(level
);
529 if (address
>= (unsigned long)__va(1UL<<32) &&
530 address
< (unsigned long)__va(max_pfn_mapped
<< PAGE_SHIFT
))
531 split_page_count(level
);
535 * Install the new, split up pagetable.
537 * We use the standard kernel pagetable protections for the new
538 * pagetable protections, the actual ptes set above control the
539 * primary protection behavior:
541 __set_pmd_pte(kpte
, address
, mk_pte(base
, __pgprot(_KERNPG_TABLE
)));
544 * Intel Atom errata AAH41 workaround.
546 * The real fix should be in hw or in a microcode update, but
547 * we also probabilistically try to reduce the window of having
548 * a large TLB mixed with 4K TLBs while instruction fetches are
557 * If we dropped out via the lookup_address check under
558 * pgd_lock then stick the page back into the pool:
562 spin_unlock_irqrestore(&pgd_lock
, flags
);
567 static int __cpa_process_fault(struct cpa_data
*cpa
, unsigned long vaddr
,
571 * Ignore all non primary paths.
577 * Ignore the NULL PTE for kernel identity mapping, as it is expected
579 * Also set numpages to '1' indicating that we processed cpa req for
580 * one virtual address page and its pfn. TBD: numpages can be set based
581 * on the initial value and the level returned by lookup_address().
583 if (within(vaddr
, PAGE_OFFSET
,
584 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))) {
586 cpa
->pfn
= __pa(vaddr
) >> PAGE_SHIFT
;
589 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
590 "vaddr = %lx cpa->vaddr = %lx\n", vaddr
,
597 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
599 unsigned long address
;
602 pte_t
*kpte
, old_pte
;
604 if (cpa
->flags
& CPA_PAGES_ARRAY
)
605 address
= (unsigned long)page_address(cpa
->pages
[cpa
->curpage
]);
606 else if (cpa
->flags
& CPA_ARRAY
)
607 address
= cpa
->vaddr
[cpa
->curpage
];
609 address
= *cpa
->vaddr
;
611 kpte
= lookup_address(address
, &level
);
613 return __cpa_process_fault(cpa
, address
, primary
);
616 if (!pte_val(old_pte
))
617 return __cpa_process_fault(cpa
, address
, primary
);
619 if (level
== PG_LEVEL_4K
) {
621 pgprot_t new_prot
= pte_pgprot(old_pte
);
622 unsigned long pfn
= pte_pfn(old_pte
);
624 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
625 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
627 new_prot
= static_protections(new_prot
, address
, pfn
);
630 * We need to keep the pfn from the existing PTE,
631 * after all we're only going to change it's attributes
632 * not the memory it points to
634 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
637 * Do we really change anything ?
639 if (pte_val(old_pte
) != pte_val(new_pte
)) {
640 set_pte_atomic(kpte
, new_pte
);
641 cpa
->flags
|= CPA_FLUSHTLB
;
648 * Check, whether we can keep the large page intact
649 * and just change the pte:
651 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
653 * When the range fits into the existing large page,
654 * return. cp->numpages and cpa->tlbflush have been updated in
661 * We have to split the large page:
663 err
= split_large_page(kpte
, address
);
666 * Do a global flush tlb after splitting the large page
667 * and before we do the actual change page attribute in the PTE.
669 * With out this, we violate the TLB application note, that says
670 * "The TLBs may contain both ordinary and large-page
671 * translations for a 4-KByte range of linear addresses. This
672 * may occur if software modifies the paging structures so that
673 * the page size used for the address range changes. If the two
674 * translations differ with respect to page frame or attributes
675 * (e.g., permissions), processor behavior is undefined and may
676 * be implementation-specific."
678 * We do this global tlb flush inside the cpa_lock, so that we
679 * don't allow any other cpu, with stale tlb entries change the
680 * page attribute in parallel, that also falls into the
681 * just split large page entry.
690 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
692 static int cpa_process_alias(struct cpa_data
*cpa
)
694 struct cpa_data alias_cpa
;
696 unsigned long temp_cpa_vaddr
, vaddr
;
698 if (cpa
->pfn
>= max_pfn_mapped
)
702 if (cpa
->pfn
>= max_low_pfn_mapped
&& cpa
->pfn
< (1UL<<(32-PAGE_SHIFT
)))
706 * No need to redo, when the primary call touched the direct
709 if (cpa
->flags
& CPA_PAGES_ARRAY
)
710 vaddr
= (unsigned long)page_address(cpa
->pages
[cpa
->curpage
]);
711 else if (cpa
->flags
& CPA_ARRAY
)
712 vaddr
= cpa
->vaddr
[cpa
->curpage
];
716 if (!(within(vaddr
, PAGE_OFFSET
,
717 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
)))) {
720 temp_cpa_vaddr
= (unsigned long) __va(cpa
->pfn
<< PAGE_SHIFT
);
721 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
722 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
725 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
732 * No need to redo, when the primary call touched the high
735 if (within(vaddr
, (unsigned long) _text
, _brk_end
))
739 * If the physical address is inside the kernel map, we need
740 * to touch the high mapped kernel as well:
742 if (!within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn()))
746 temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) + __START_KERNEL_map
- phys_base
;
747 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
748 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
751 * The high mapping range is imprecise, so ignore the return value.
753 __change_page_attr_set_clr(&alias_cpa
, 0);
758 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
760 int ret
, numpages
= cpa
->numpages
;
764 * Store the remaining nr of pages for the large page
765 * preservation check.
767 cpa
->numpages
= numpages
;
768 /* for array changes, we can't use large page */
769 if (cpa
->flags
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
772 if (!debug_pagealloc
)
773 spin_lock(&cpa_lock
);
774 ret
= __change_page_attr(cpa
, checkalias
);
775 if (!debug_pagealloc
)
776 spin_unlock(&cpa_lock
);
781 ret
= cpa_process_alias(cpa
);
787 * Adjust the number of pages with the result of the
788 * CPA operation. Either a large page has been
789 * preserved or a single page update happened.
791 BUG_ON(cpa
->numpages
> numpages
);
792 numpages
-= cpa
->numpages
;
793 if (cpa
->flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
))
796 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
802 static inline int cache_attr(pgprot_t attr
)
804 return pgprot_val(attr
) &
805 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
808 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
809 pgprot_t mask_set
, pgprot_t mask_clr
,
810 int force_split
, int in_flag
,
814 int ret
, cache
, checkalias
;
817 * Check, if we are requested to change a not supported
820 mask_set
= canon_pgprot(mask_set
);
821 mask_clr
= canon_pgprot(mask_clr
);
822 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
825 /* Ensure we are PAGE_SIZE aligned */
826 if (in_flag
& CPA_ARRAY
) {
828 for (i
= 0; i
< numpages
; i
++) {
829 if (addr
[i
] & ~PAGE_MASK
) {
830 addr
[i
] &= PAGE_MASK
;
834 } else if (!(in_flag
& CPA_PAGES_ARRAY
)) {
836 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
837 * No need to cehck in that case
839 if (*addr
& ~PAGE_MASK
) {
842 * People should not be passing in unaligned addresses:
848 /* Must avoid aliasing mappings in the highmem code */
854 * If we're called with lazy mmu updates enabled, the
855 * in-memory pte state may be stale. Flush pending updates to
856 * bring them up to date.
858 arch_flush_lazy_mmu_mode();
862 cpa
.numpages
= numpages
;
863 cpa
.mask_set
= mask_set
;
864 cpa
.mask_clr
= mask_clr
;
867 cpa
.force_split
= force_split
;
869 if (in_flag
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
870 cpa
.flags
|= in_flag
;
872 /* No alias checking for _NX bit modifications */
873 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
875 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
878 * Check whether we really changed something:
880 if (!(cpa
.flags
& CPA_FLUSHTLB
))
884 * No need to flush, when we did not set any of the caching
887 cache
= cache_attr(mask_set
);
890 * On success we use clflush, when the CPU supports it to
891 * avoid the wbindv. If the CPU does not support it and in the
892 * error case we fall back to cpa_flush_all (which uses
895 if (!ret
&& cpu_has_clflush
) {
896 if (cpa
.flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
)) {
897 cpa_flush_array(addr
, numpages
, cache
,
900 cpa_flush_range(*addr
, numpages
, cache
);
902 cpa_flush_all(cache
);
905 * If we've been called with lazy mmu updates enabled, then
906 * make sure that everything gets flushed out before we
909 arch_flush_lazy_mmu_mode();
915 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
916 pgprot_t mask
, int array
)
918 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
919 (array
? CPA_ARRAY
: 0), NULL
);
922 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
923 pgprot_t mask
, int array
)
925 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
926 (array
? CPA_ARRAY
: 0), NULL
);
929 static inline int cpa_set_pages_array(struct page
**pages
, int numpages
,
932 return change_page_attr_set_clr(NULL
, numpages
, mask
, __pgprot(0), 0,
933 CPA_PAGES_ARRAY
, pages
);
936 static inline int cpa_clear_pages_array(struct page
**pages
, int numpages
,
939 return change_page_attr_set_clr(NULL
, numpages
, __pgprot(0), mask
, 0,
940 CPA_PAGES_ARRAY
, pages
);
943 int _set_memory_uc(unsigned long addr
, int numpages
)
946 * for now UC MINUS. see comments in ioremap_nocache()
948 return change_page_attr_set(&addr
, numpages
,
949 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
952 int set_memory_uc(unsigned long addr
, int numpages
)
957 * for now UC MINUS. see comments in ioremap_nocache()
959 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
960 _PAGE_CACHE_UC_MINUS
, NULL
);
964 ret
= _set_memory_uc(addr
, numpages
);
971 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
975 EXPORT_SYMBOL(set_memory_uc
);
977 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
983 * for now UC MINUS. see comments in ioremap_nocache()
985 for (i
= 0; i
< addrinarray
; i
++) {
986 ret
= reserve_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
,
987 _PAGE_CACHE_UC_MINUS
, NULL
);
992 ret
= change_page_attr_set(addr
, addrinarray
,
993 __pgprot(_PAGE_CACHE_UC_MINUS
), 1);
1000 for (j
= 0; j
< i
; j
++)
1001 free_memtype(__pa(addr
[j
]), __pa(addr
[j
]) + PAGE_SIZE
);
1005 EXPORT_SYMBOL(set_memory_array_uc
);
1007 int _set_memory_wc(unsigned long addr
, int numpages
)
1010 ret
= change_page_attr_set(&addr
, numpages
,
1011 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
1014 ret
= change_page_attr_set(&addr
, numpages
,
1015 __pgprot(_PAGE_CACHE_WC
), 0);
1020 int set_memory_wc(unsigned long addr
, int numpages
)
1025 return set_memory_uc(addr
, numpages
);
1027 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
1028 _PAGE_CACHE_WC
, NULL
);
1032 ret
= _set_memory_wc(addr
, numpages
);
1039 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1043 EXPORT_SYMBOL(set_memory_wc
);
1045 int _set_memory_wb(unsigned long addr
, int numpages
)
1047 return change_page_attr_clear(&addr
, numpages
,
1048 __pgprot(_PAGE_CACHE_MASK
), 0);
1051 int set_memory_wb(unsigned long addr
, int numpages
)
1055 ret
= _set_memory_wb(addr
, numpages
);
1059 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1062 EXPORT_SYMBOL(set_memory_wb
);
1064 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
1069 ret
= change_page_attr_clear(addr
, addrinarray
,
1070 __pgprot(_PAGE_CACHE_MASK
), 1);
1074 for (i
= 0; i
< addrinarray
; i
++)
1075 free_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
);
1079 EXPORT_SYMBOL(set_memory_array_wb
);
1081 int set_memory_x(unsigned long addr
, int numpages
)
1083 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1085 EXPORT_SYMBOL(set_memory_x
);
1087 int set_memory_nx(unsigned long addr
, int numpages
)
1089 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1091 EXPORT_SYMBOL(set_memory_nx
);
1093 int set_memory_ro(unsigned long addr
, int numpages
)
1095 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1097 EXPORT_SYMBOL_GPL(set_memory_ro
);
1099 int set_memory_rw(unsigned long addr
, int numpages
)
1101 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1103 EXPORT_SYMBOL_GPL(set_memory_rw
);
1105 int set_memory_np(unsigned long addr
, int numpages
)
1107 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
1110 int set_memory_4k(unsigned long addr
, int numpages
)
1112 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
1113 __pgprot(0), 1, 0, NULL
);
1116 int set_pages_uc(struct page
*page
, int numpages
)
1118 unsigned long addr
= (unsigned long)page_address(page
);
1120 return set_memory_uc(addr
, numpages
);
1122 EXPORT_SYMBOL(set_pages_uc
);
1124 int set_pages_array_uc(struct page
**pages
, int addrinarray
)
1126 unsigned long start
;
1131 for (i
= 0; i
< addrinarray
; i
++) {
1132 start
= (unsigned long)page_address(pages
[i
]);
1133 end
= start
+ PAGE_SIZE
;
1134 if (reserve_memtype(start
, end
, _PAGE_CACHE_UC_MINUS
, NULL
))
1138 if (cpa_set_pages_array(pages
, addrinarray
,
1139 __pgprot(_PAGE_CACHE_UC_MINUS
)) == 0) {
1140 return 0; /* Success */
1144 for (i
= 0; i
< free_idx
; i
++) {
1145 start
= (unsigned long)page_address(pages
[i
]);
1146 end
= start
+ PAGE_SIZE
;
1147 free_memtype(start
, end
);
1151 EXPORT_SYMBOL(set_pages_array_uc
);
1153 int set_pages_wb(struct page
*page
, int numpages
)
1155 unsigned long addr
= (unsigned long)page_address(page
);
1157 return set_memory_wb(addr
, numpages
);
1159 EXPORT_SYMBOL(set_pages_wb
);
1161 int set_pages_array_wb(struct page
**pages
, int addrinarray
)
1164 unsigned long start
;
1168 retval
= cpa_clear_pages_array(pages
, addrinarray
,
1169 __pgprot(_PAGE_CACHE_MASK
));
1173 for (i
= 0; i
< addrinarray
; i
++) {
1174 start
= (unsigned long)page_address(pages
[i
]);
1175 end
= start
+ PAGE_SIZE
;
1176 free_memtype(start
, end
);
1181 EXPORT_SYMBOL(set_pages_array_wb
);
1183 int set_pages_x(struct page
*page
, int numpages
)
1185 unsigned long addr
= (unsigned long)page_address(page
);
1187 return set_memory_x(addr
, numpages
);
1189 EXPORT_SYMBOL(set_pages_x
);
1191 int set_pages_nx(struct page
*page
, int numpages
)
1193 unsigned long addr
= (unsigned long)page_address(page
);
1195 return set_memory_nx(addr
, numpages
);
1197 EXPORT_SYMBOL(set_pages_nx
);
1199 int set_pages_ro(struct page
*page
, int numpages
)
1201 unsigned long addr
= (unsigned long)page_address(page
);
1203 return set_memory_ro(addr
, numpages
);
1206 int set_pages_rw(struct page
*page
, int numpages
)
1208 unsigned long addr
= (unsigned long)page_address(page
);
1210 return set_memory_rw(addr
, numpages
);
1213 #ifdef CONFIG_DEBUG_PAGEALLOC
1215 static int __set_pages_p(struct page
*page
, int numpages
)
1217 unsigned long tempaddr
= (unsigned long) page_address(page
);
1218 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1219 .numpages
= numpages
,
1220 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1221 .mask_clr
= __pgprot(0),
1225 * No alias checking needed for setting present flag. otherwise,
1226 * we may need to break large pages for 64-bit kernel text
1227 * mappings (this adds to complexity if we want to do this from
1228 * atomic context especially). Let's keep it simple!
1230 return __change_page_attr_set_clr(&cpa
, 0);
1233 static int __set_pages_np(struct page
*page
, int numpages
)
1235 unsigned long tempaddr
= (unsigned long) page_address(page
);
1236 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1237 .numpages
= numpages
,
1238 .mask_set
= __pgprot(0),
1239 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1243 * No alias checking needed for setting not present flag. otherwise,
1244 * we may need to break large pages for 64-bit kernel text
1245 * mappings (this adds to complexity if we want to do this from
1246 * atomic context especially). Let's keep it simple!
1248 return __change_page_attr_set_clr(&cpa
, 0);
1251 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1253 if (PageHighMem(page
))
1256 debug_check_no_locks_freed(page_address(page
),
1257 numpages
* PAGE_SIZE
);
1261 * If page allocator is not up yet then do not call c_p_a():
1263 if (!debug_pagealloc_enabled
)
1267 * The return value is ignored as the calls cannot fail.
1268 * Large pages for identity mappings are not used at boot time
1269 * and hence no memory allocations during large page split.
1272 __set_pages_p(page
, numpages
);
1274 __set_pages_np(page
, numpages
);
1277 * We should perform an IPI and flush all tlbs,
1278 * but that can deadlock->flush only current cpu:
1283 #ifdef CONFIG_HIBERNATION
1285 bool kernel_page_present(struct page
*page
)
1290 if (PageHighMem(page
))
1293 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1294 return (pte_val(*pte
) & _PAGE_PRESENT
);
1297 #endif /* CONFIG_HIBERNATION */
1299 #endif /* CONFIG_DEBUG_PAGEALLOC */
1302 * The testcases use internal knowledge of the implementation that shouldn't
1303 * be exposed to the rest of the kernel. Include these directly here.
1305 #ifdef CONFIG_CPA_DEBUG
1306 #include "pageattr-test.c"