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V4L/DVB (10663): soc-camera: fix S_CROP breakage on PXA and SuperH
[linux-2.6/mini2440.git] / drivers / media / video / pxa_camera.c
blob07c334f25aae69bf257a2a0cff91465bd5e784b9
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <mach/dma.h>
38 #include <mach/pxa-regs.h>
39 #include <mach/camera.h>
40
41 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43
44 /* Camera Interface */
45 #define CICR0 0x0000
46 #define CICR1 0x0004
47 #define CICR2 0x0008
48 #define CICR3 0x000C
49 #define CICR4 0x0010
50 #define CISR 0x0014
51 #define CIFR 0x0018
52 #define CITOR 0x001C
53 #define CIBR0 0x0028
54 #define CIBR1 0x0030
55 #define CIBR2 0x0038
56
57 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
58 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
59 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
60 #define CICR0_ENB (1 << 28) /* Camera interface enable */
61 #define CICR0_DIS (1 << 27) /* Camera interface disable */
62 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
63 #define CICR0_TOM (1 << 9) /* Time-out mask */
64 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
65 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
66 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
67 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
68 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
69 #define CICR0_CDM (1 << 3) /* Disable-done mask */
70 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
71 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
72 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
73
74 #define CICR1_TBIT (1 << 31) /* Transparency bit */
75 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
76 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
77 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
78 #define CICR1_RGB_F (1 << 11) /* RGB format */
79 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
80 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
81 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
82 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
83 #define CICR1_DW (0x7 << 0) /* Data width mask */
84
85 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
86 wait count mask */
87 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
88 wait count mask */
89 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
90 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
91 wait count mask */
92 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
93 wait count mask */
94
95 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
96 wait count mask */
97 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
98 wait count mask */
99 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
100 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 wait count mask */
102 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
103
104 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
105 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
106 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
107 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
108 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
109 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
110 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
111 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
112
113 #define CISR_FTO (1 << 15) /* FIFO time-out */
114 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
115 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
116 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
117 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
118 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
119 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
120 #define CISR_EOL (1 << 8) /* End of line */
121 #define CISR_PAR_ERR (1 << 7) /* Parity error */
122 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
123 #define CISR_CDD (1 << 5) /* Camera interface disable done */
124 #define CISR_SOF (1 << 4) /* Start of frame */
125 #define CISR_EOF (1 << 3) /* End of frame */
126 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
127 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
128 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
129
130 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
131 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
132 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
133 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
134 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
135 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
136 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
137 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
138
139 #define CICR0_SIM_MP (0 << 24)
140 #define CICR0_SIM_SP (1 << 24)
141 #define CICR0_SIM_MS (2 << 24)
142 #define CICR0_SIM_EP (3 << 24)
143 #define CICR0_SIM_ES (4 << 24)
144
145 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
146 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
147 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
148 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
149 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
150
151 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
152 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
153 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
154 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
155 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
156
157 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
158 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
159 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
160 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
161
162 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
163 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
164 CICR0_EOFM | CICR0_FOM)
165
166 /*
167 * Structures
168 */
169 enum pxa_camera_active_dma {
170 DMA_Y = 0x1,
171 DMA_U = 0x2,
172 DMA_V = 0x4,
173 };
174
175 /* descriptor needed for the PXA DMA engine */
176 struct pxa_cam_dma {
177 dma_addr_t sg_dma;
178 struct pxa_dma_desc *sg_cpu;
179 size_t sg_size;
180 int sglen;
181 };
182
183 /* buffer for one video frame */
184 struct pxa_buffer {
185 /* common v4l buffer stuff -- must be first */
186 struct videobuf_buffer vb;
187
188 const struct soc_camera_data_format *fmt;
189
190 /* our descriptor lists for Y, U and V channels */
191 struct pxa_cam_dma dmas[3];
192
193 int inwork;
194
195 enum pxa_camera_active_dma active_dma;
196 };
197
198 struct pxa_camera_dev {
199 struct device *dev;
200 /* PXA27x is only supposed to handle one camera on its Quick Capture
201 * interface. If anyone ever builds hardware to enable more than
202 * one camera, they will have to modify this driver too */
203 struct soc_camera_device *icd;
204 struct clk *clk;
205
206 unsigned int irq;
207 void __iomem *base;
208
209 int channels;
210 unsigned int dma_chans[3];
211
212 struct pxacamera_platform_data *pdata;
213 struct resource *res;
214 unsigned long platform_flags;
215 unsigned long ciclk;
216 unsigned long mclk;
217 u32 mclk_divisor;
218
219 struct list_head capture;
220
221 spinlock_t lock;
222
223 struct pxa_buffer *active;
224 struct pxa_dma_desc *sg_tail[3];
225
226 u32 save_cicr[5];
227 };
228
229 static const char *pxa_cam_driver_description = "PXA_Camera";
230
231 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
232
233 /*
234 * Videobuf operations
235 */
236 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
237 unsigned int *size)
238 {
239 struct soc_camera_device *icd = vq->priv_data;
240 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
241 struct pxa_camera_dev *pcdev = ici->priv;
242
243 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
244
245 /* planar capture requires Y, U and V buffers to be page aligned */
246 if (pcdev->channels == 3) {
247 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
248 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
249 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
250 } else {
251 *size = icd->width * icd->height *
252 ((icd->current_fmt->depth + 7) >> 3);
253 }
254
255 if (0 == *count)
256 *count = 32;
257 while (*size * *count > vid_limit * 1024 * 1024)
258 (*count)--;
259
260 return 0;
261 }
262
263 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
264 {
265 struct soc_camera_device *icd = vq->priv_data;
266 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
267 struct pxa_camera_dev *pcdev = ici->priv;
268 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
269 int i;
270
271 BUG_ON(in_interrupt());
272
273 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
274 &buf->vb, buf->vb.baddr, buf->vb.bsize);
275
276 /* This waits until this buffer is out of danger, i.e., until it is no
277 * longer in STATE_QUEUED or STATE_ACTIVE */
278 videobuf_waiton(&buf->vb, 0, 0);
279 videobuf_dma_unmap(vq, dma);
280 videobuf_dma_free(dma);
281
282 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
283 if (buf->dmas[i].sg_cpu)
284 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
285 buf->dmas[i].sg_cpu,
286 buf->dmas[i].sg_dma);
287 buf->dmas[i].sg_cpu = NULL;
288 }
289
290 buf->vb.state = VIDEOBUF_NEEDS_INIT;
291 }
292
293 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
294 struct pxa_buffer *buf,
295 struct videobuf_dmabuf *dma, int channel,
296 int sglen, int sg_start, int cibr,
297 unsigned int size)
298 {
299 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
300 int i;
301
302 if (pxa_dma->sg_cpu)
303 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
304 pxa_dma->sg_cpu, pxa_dma->sg_dma);
305
306 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
307 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
308 &pxa_dma->sg_dma, GFP_KERNEL);
309 if (!pxa_dma->sg_cpu)
310 return -ENOMEM;
311
312 pxa_dma->sglen = sglen;
313
314 for (i = 0; i < sglen; i++) {
315 int sg_i = sg_start + i;
316 struct scatterlist *sg = dma->sglist;
317 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
318
319 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
320 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
321
322 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
323 xfer_len = (min(dma_len, size) + 7) & ~7;
324
325 pxa_dma->sg_cpu[i].dcmd =
326 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
327 size -= dma_len;
328 pxa_dma->sg_cpu[i].ddadr =
329 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
330 }
331
332 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
333 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
334
335 return 0;
336 }
337
338 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
339 struct videobuf_buffer *vb, enum v4l2_field field)
340 {
341 struct soc_camera_device *icd = vq->priv_data;
342 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
343 struct pxa_camera_dev *pcdev = ici->priv;
344 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
345 int ret;
346 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
347 int size_y, size_u = 0, size_v = 0;
348
349 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
350 vb, vb->baddr, vb->bsize);
351
352 /* Added list head initialization on alloc */
353 WARN_ON(!list_empty(&vb->queue));
354
355 #ifdef DEBUG
356 /* This can be useful if you want to see if we actually fill
357 * the buffer with something */
358 memset((void *)vb->baddr, 0xaa, vb->bsize);
359 #endif
360
361 BUG_ON(NULL == icd->current_fmt);
362
363 /* I think, in buf_prepare you only have to protect global data,
364 * the actual buffer is yours */
365 buf->inwork = 1;
366
367 if (buf->fmt != icd->current_fmt ||
368 vb->width != icd->width ||
369 vb->height != icd->height ||
370 vb->field != field) {
371 buf->fmt = icd->current_fmt;
372 vb->width = icd->width;
373 vb->height = icd->height;
374 vb->field = field;
375 vb->state = VIDEOBUF_NEEDS_INIT;
376 }
377
378 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
379 if (0 != vb->baddr && vb->bsize < vb->size) {
380 ret = -EINVAL;
381 goto out;
382 }
383
384 if (vb->state == VIDEOBUF_NEEDS_INIT) {
385 unsigned int size = vb->size;
386 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
387
388 ret = videobuf_iolock(vq, vb, NULL);
389 if (ret)
390 goto fail;
391
392 if (pcdev->channels == 3) {
393 /* FIXME the calculations should be more precise */
394 sglen_y = dma->sglen / 2;
395 sglen_u = sglen_v = dma->sglen / 4 + 1;
396 sglen_yu = sglen_y + sglen_u;
397 size_y = size / 2;
398 size_u = size_v = size / 4;
399 } else {
400 sglen_y = dma->sglen;
401 size_y = size;
402 }
403
404 /* init DMA for Y channel */
405 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
406 0, 0x28, size_y);
407
408 if (ret) {
409 dev_err(pcdev->dev,
410 "DMA initialization for Y/RGB failed\n");
411 goto fail;
412 }
413
414 if (pcdev->channels == 3) {
415 /* init DMA for U channel */
416 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
417 sglen_y, 0x30, size_u);
418 if (ret) {
419 dev_err(pcdev->dev,
420 "DMA initialization for U failed\n");
421 goto fail_u;
422 }
423
424 /* init DMA for V channel */
425 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
426 sglen_yu, 0x38, size_v);
427 if (ret) {
428 dev_err(pcdev->dev,
429 "DMA initialization for V failed\n");
430 goto fail_v;
431 }
432 }
433
434 vb->state = VIDEOBUF_PREPARED;
435 }
436
437 buf->inwork = 0;
438 buf->active_dma = DMA_Y;
439 if (pcdev->channels == 3)
440 buf->active_dma |= DMA_U | DMA_V;
441
442 return 0;
443
444 fail_v:
445 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
446 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
447 fail_u:
448 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
449 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
450 fail:
451 free_buffer(vq, buf);
452 out:
453 buf->inwork = 0;
454 return ret;
455 }
456
457 static void pxa_videobuf_queue(struct videobuf_queue *vq,
458 struct videobuf_buffer *vb)
459 {
460 struct soc_camera_device *icd = vq->priv_data;
461 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
462 struct pxa_camera_dev *pcdev = ici->priv;
463 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
464 struct pxa_buffer *active;
465 unsigned long flags;
466 int i;
467
468 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
469 vb, vb->baddr, vb->bsize);
470 spin_lock_irqsave(&pcdev->lock, flags);
471
472 list_add_tail(&vb->queue, &pcdev->capture);
473
474 vb->state = VIDEOBUF_ACTIVE;
475 active = pcdev->active;
476
477 if (!active) {
478 unsigned long cifr, cicr0;
479
480 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
481 __raw_writel(cifr, pcdev->base + CIFR);
482
483 for (i = 0; i < pcdev->channels; i++) {
484 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
485 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
486 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
487 }
488
489 pcdev->active = buf;
490
491 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
492 __raw_writel(cicr0, pcdev->base + CICR0);
493 } else {
494 struct pxa_cam_dma *buf_dma;
495 struct pxa_cam_dma *act_dma;
496 int nents;
497
498 for (i = 0; i < pcdev->channels; i++) {
499 buf_dma = &buf->dmas[i];
500 act_dma = &active->dmas[i];
501 nents = buf_dma->sglen;
502
503 /* Stop DMA engine */
504 DCSR(pcdev->dma_chans[i]) = 0;
505
506 /* Add the descriptors we just initialized to
507 the currently running chain */
508 pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
509 pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
510
511 /* Setup a dummy descriptor with the DMA engines current
512 * state
513 */
514 buf_dma->sg_cpu[nents].dsadr =
515 pcdev->res->start + 0x28 + i*8; /* CIBRx */
516 buf_dma->sg_cpu[nents].dtadr =
517 DTADR(pcdev->dma_chans[i]);
518 buf_dma->sg_cpu[nents].dcmd =
519 DCMD(pcdev->dma_chans[i]);
520
521 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
522 /* The DMA engine is on the last
523 descriptor, set the next descriptors
524 address to the descriptors we just
525 initialized */
526 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
527 } else {
528 buf_dma->sg_cpu[nents].ddadr =
529 DDADR(pcdev->dma_chans[i]);
530 }
531
532 /* The next descriptor is the dummy descriptor */
533 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
534 sizeof(struct pxa_dma_desc);
535
536 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
537 }
538 }
539
540 spin_unlock_irqrestore(&pcdev->lock, flags);
541 }
542
543 static void pxa_videobuf_release(struct videobuf_queue *vq,
544 struct videobuf_buffer *vb)
545 {
546 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
547 #ifdef DEBUG
548 struct soc_camera_device *icd = vq->priv_data;
549
550 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
551 vb, vb->baddr, vb->bsize);
552
553 switch (vb->state) {
554 case VIDEOBUF_ACTIVE:
555 dev_dbg(&icd->dev, "%s (active)\n", __func__);
556 break;
557 case VIDEOBUF_QUEUED:
558 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
559 break;
560 case VIDEOBUF_PREPARED:
561 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
562 break;
563 default:
564 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
565 break;
566 }
567 #endif
568
569 free_buffer(vq, buf);
570 }
571
572 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
573 struct videobuf_buffer *vb,
574 struct pxa_buffer *buf)
575 {
576 unsigned long cicr0;
577
578 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
579 list_del_init(&vb->queue);
580 vb->state = VIDEOBUF_DONE;
581 do_gettimeofday(&vb->ts);
582 vb->field_count++;
583 wake_up(&vb->done);
584
585 if (list_empty(&pcdev->capture)) {
586 pcdev->active = NULL;
587 DCSR(pcdev->dma_chans[0]) = 0;
588 DCSR(pcdev->dma_chans[1]) = 0;
589 DCSR(pcdev->dma_chans[2]) = 0;
590
591 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
592 __raw_writel(cicr0, pcdev->base + CICR0);
593 return;
594 }
595
596 pcdev->active = list_entry(pcdev->capture.next,
597 struct pxa_buffer, vb.queue);
598 }
599
600 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
601 enum pxa_camera_active_dma act_dma)
602 {
603 struct pxa_buffer *buf;
604 unsigned long flags;
605 u32 status, camera_status, overrun;
606 struct videobuf_buffer *vb;
607 unsigned long cifr, cicr0;
608
609 spin_lock_irqsave(&pcdev->lock, flags);
610
611 status = DCSR(channel);
612 DCSR(channel) = status | DCSR_ENDINTR;
613
614 if (status & DCSR_BUSERR) {
615 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
616 goto out;
617 }
618
619 if (!(status & DCSR_ENDINTR)) {
620 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
621 "status: 0x%08x\n", status);
622 goto out;
623 }
624
625 if (!pcdev->active) {
626 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
627 goto out;
628 }
629
630 camera_status = __raw_readl(pcdev->base + CISR);
631 overrun = CISR_IFO_0;
632 if (pcdev->channels == 3)
633 overrun |= CISR_IFO_1 | CISR_IFO_2;
634 if (camera_status & overrun) {
635 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
636 /* Stop the Capture Interface */
637 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
638 __raw_writel(cicr0, pcdev->base + CICR0);
639
640 /* Stop DMA */
641 DCSR(channel) = 0;
642 /* Reset the FIFOs */
643 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
644 __raw_writel(cifr, pcdev->base + CIFR);
645 /* Enable End-Of-Frame Interrupt */
646 cicr0 &= ~CICR0_EOFM;
647 __raw_writel(cicr0, pcdev->base + CICR0);
648 /* Restart the Capture Interface */
649 __raw_writel(cicr0 | CICR0_ENB, pcdev->base + CICR0);
650 goto out;
651 }
652
653 vb = &pcdev->active->vb;
654 buf = container_of(vb, struct pxa_buffer, vb);
655 WARN_ON(buf->inwork || list_empty(&vb->queue));
656 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
657 vb, vb->baddr, vb->bsize);
658
659 buf->active_dma &= ~act_dma;
660 if (!buf->active_dma)
661 pxa_camera_wakeup(pcdev, vb, buf);
662
663 out:
664 spin_unlock_irqrestore(&pcdev->lock, flags);
665 }
666
667 static void pxa_camera_dma_irq_y(int channel, void *data)
668 {
669 struct pxa_camera_dev *pcdev = data;
670 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
671 }
672
673 static void pxa_camera_dma_irq_u(int channel, void *data)
674 {
675 struct pxa_camera_dev *pcdev = data;
676 pxa_camera_dma_irq(channel, pcdev, DMA_U);
677 }
678
679 static void pxa_camera_dma_irq_v(int channel, void *data)
680 {
681 struct pxa_camera_dev *pcdev = data;
682 pxa_camera_dma_irq(channel, pcdev, DMA_V);
683 }
684
685 static struct videobuf_queue_ops pxa_videobuf_ops = {
686 .buf_setup = pxa_videobuf_setup,
687 .buf_prepare = pxa_videobuf_prepare,
688 .buf_queue = pxa_videobuf_queue,
689 .buf_release = pxa_videobuf_release,
690 };
691
692 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
693 struct soc_camera_device *icd)
694 {
695 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
696 struct pxa_camera_dev *pcdev = ici->priv;
697
698 /* We must pass NULL as dev pointer, then all pci_* dma operations
699 * transform to normal dma_* ones. */
700 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
701 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
702 sizeof(struct pxa_buffer), icd);
703 }
704
705 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
706 {
707 unsigned long mclk = pcdev->mclk;
708 u32 div;
709 unsigned long lcdclk;
710
711 lcdclk = clk_get_rate(pcdev->clk);
712 pcdev->ciclk = lcdclk;
713
714 /* mclk <= ciclk / 4 (27.4.2) */
715 if (mclk > lcdclk / 4) {
716 mclk = lcdclk / 4;
717 dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
718 }
719
720 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
721 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
722
723 /* If we're not supplying MCLK, leave it at 0 */
724 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
725 pcdev->mclk = lcdclk / (2 * (div + 1));
726
727 dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
728 "divisor %u\n", lcdclk, mclk, div);
729
730 return div;
731 }
732
733 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
734 unsigned long pclk)
735 {
736 /* We want a timeout > 1 pixel time, not ">=" */
737 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
738
739 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
740 }
741
742 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
743 {
744 struct pxacamera_platform_data *pdata = pcdev->pdata;
745 u32 cicr4 = 0;
746
747 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
748 pcdev, pdata);
749
750 if (pdata && pdata->init) {
751 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
752 pdata->init(pcdev->dev);
753 }
754
755 /* disable all interrupts */
756 __raw_writel(0x3ff, pcdev->base + CICR0);
757
758 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
759 cicr4 |= CICR4_PCLK_EN;
760 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
761 cicr4 |= CICR4_MCLK_EN;
762 if (pcdev->platform_flags & PXA_CAMERA_PCP)
763 cicr4 |= CICR4_PCP;
764 if (pcdev->platform_flags & PXA_CAMERA_HSP)
765 cicr4 |= CICR4_HSP;
766 if (pcdev->platform_flags & PXA_CAMERA_VSP)
767 cicr4 |= CICR4_VSP;
768
769 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
770
771 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
772 /* Initialise the timeout under the assumption pclk = mclk */
773 recalculate_fifo_timeout(pcdev, pcdev->mclk);
774 else
775 /* "Safe default" - 13MHz */
776 recalculate_fifo_timeout(pcdev, 13000000);
777
778 clk_enable(pcdev->clk);
779 }
780
781 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
782 {
783 clk_disable(pcdev->clk);
784 }
785
786 static irqreturn_t pxa_camera_irq(int irq, void *data)
787 {
788 struct pxa_camera_dev *pcdev = data;
789 unsigned long status, cicr0;
790
791 status = __raw_readl(pcdev->base + CISR);
792 dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
793
794 if (!status)
795 return IRQ_NONE;
796
797 __raw_writel(status, pcdev->base + CISR);
798
799 if (status & CISR_EOF) {
800 int i;
801 for (i = 0; i < pcdev->channels; i++) {
802 DDADR(pcdev->dma_chans[i]) =
803 pcdev->active->dmas[i].sg_dma;
804 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
805 }
806 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
807 __raw_writel(cicr0, pcdev->base + CICR0);
808 }
809
810 return IRQ_HANDLED;
811 }
812
813 /*
814 * The following two functions absolutely depend on the fact, that
815 * there can be only one camera on PXA quick capture interface
816 * Called with .video_lock held
817 */
818 static int pxa_camera_add_device(struct soc_camera_device *icd)
819 {
820 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
821 struct pxa_camera_dev *pcdev = ici->priv;
822 int ret;
823
824 if (pcdev->icd) {
825 ret = -EBUSY;
826 goto ebusy;
827 }
828
829 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
830 icd->devnum);
831
832 pxa_camera_activate(pcdev);
833 ret = icd->ops->init(icd);
834
835 if (!ret)
836 pcdev->icd = icd;
837
838 ebusy:
839 return ret;
840 }
841
842 /* Called with .video_lock held */
843 static void pxa_camera_remove_device(struct soc_camera_device *icd)
844 {
845 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
846 struct pxa_camera_dev *pcdev = ici->priv;
847
848 BUG_ON(icd != pcdev->icd);
849
850 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
851 icd->devnum);
852
853 /* disable capture, disable interrupts */
854 __raw_writel(0x3ff, pcdev->base + CICR0);
855
856 /* Stop DMA engine */
857 DCSR(pcdev->dma_chans[0]) = 0;
858 DCSR(pcdev->dma_chans[1]) = 0;
859 DCSR(pcdev->dma_chans[2]) = 0;
860
861 icd->ops->release(icd);
862
863 pxa_camera_deactivate(pcdev);
864
865 pcdev->icd = NULL;
866 }
867
868 static int test_platform_param(struct pxa_camera_dev *pcdev,
869 unsigned char buswidth, unsigned long *flags)
870 {
871 /*
872 * Platform specified synchronization and pixel clock polarities are
873 * only a recommendation and are only used during probing. The PXA270
874 * quick capture interface supports both.
875 */
876 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
877 SOCAM_MASTER : SOCAM_SLAVE) |
878 SOCAM_HSYNC_ACTIVE_HIGH |
879 SOCAM_HSYNC_ACTIVE_LOW |
880 SOCAM_VSYNC_ACTIVE_HIGH |
881 SOCAM_VSYNC_ACTIVE_LOW |
882 SOCAM_PCLK_SAMPLE_RISING |
883 SOCAM_PCLK_SAMPLE_FALLING;
884
885 /* If requested data width is supported by the platform, use it */
886 switch (buswidth) {
887 case 10:
888 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
889 return -EINVAL;
890 *flags |= SOCAM_DATAWIDTH_10;
891 break;
892 case 9:
893 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
894 return -EINVAL;
895 *flags |= SOCAM_DATAWIDTH_9;
896 break;
897 case 8:
898 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
899 return -EINVAL;
900 *flags |= SOCAM_DATAWIDTH_8;
901 break;
902 default:
903 return -EINVAL;
904 }
905
906 return 0;
907 }
908
909 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
910 {
911 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
912 struct pxa_camera_dev *pcdev = ici->priv;
913 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
914 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
915 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
916
917 if (ret < 0)
918 return ret;
919
920 camera_flags = icd->ops->query_bus_param(icd);
921
922 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
923 if (!common_flags)
924 return -EINVAL;
925
926 pcdev->channels = 1;
927
928 /* Make choises, based on platform preferences */
929 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
930 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
931 if (pcdev->platform_flags & PXA_CAMERA_HSP)
932 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
933 else
934 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
935 }
936
937 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
938 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
939 if (pcdev->platform_flags & PXA_CAMERA_VSP)
940 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
941 else
942 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
943 }
944
945 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
946 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
947 if (pcdev->platform_flags & PXA_CAMERA_PCP)
948 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
949 else
950 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
951 }
952
953 ret = icd->ops->set_bus_param(icd, common_flags);
954 if (ret < 0)
955 return ret;
956
957 /* Datawidth is now guaranteed to be equal to one of the three values.
958 * We fix bit-per-pixel equal to data-width... */
959 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
960 case SOCAM_DATAWIDTH_10:
961 dw = 4;
962 bpp = 0x40;
963 break;
964 case SOCAM_DATAWIDTH_9:
965 dw = 3;
966 bpp = 0x20;
967 break;
968 default:
969 /* Actually it can only be 8 now,
970 * default is just to silence compiler warnings */
971 case SOCAM_DATAWIDTH_8:
972 dw = 2;
973 bpp = 0;
974 }
975
976 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
977 cicr4 |= CICR4_PCLK_EN;
978 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
979 cicr4 |= CICR4_MCLK_EN;
980 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
981 cicr4 |= CICR4_PCP;
982 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
983 cicr4 |= CICR4_HSP;
984 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
985 cicr4 |= CICR4_VSP;
986
987 cicr0 = __raw_readl(pcdev->base + CICR0);
988 if (cicr0 & CICR0_ENB)
989 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
990
991 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
992
993 switch (pixfmt) {
994 case V4L2_PIX_FMT_YUV422P:
995 pcdev->channels = 3;
996 cicr1 |= CICR1_YCBCR_F;
997 /*
998 * Normally, pxa bus wants as input UYVY format. We allow all
999 * reorderings of the YUV422 format, as no processing is done,
1000 * and the YUV stream is just passed through without any
1001 * transformation. Note that UYVY is the only format that
1002 * should be used if pxa framebuffer Overlay2 is used.
1003 */
1004 case V4L2_PIX_FMT_UYVY:
1005 case V4L2_PIX_FMT_VYUY:
1006 case V4L2_PIX_FMT_YUYV:
1007 case V4L2_PIX_FMT_YVYU:
1008 cicr1 |= CICR1_COLOR_SP_VAL(2);
1009 break;
1010 case V4L2_PIX_FMT_RGB555:
1011 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1012 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1013 break;
1014 case V4L2_PIX_FMT_RGB565:
1015 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1016 break;
1017 }
1018
1019 cicr2 = 0;
1020 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1021 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1022 cicr4 |= pcdev->mclk_divisor;
1023
1024 __raw_writel(cicr1, pcdev->base + CICR1);
1025 __raw_writel(cicr2, pcdev->base + CICR2);
1026 __raw_writel(cicr3, pcdev->base + CICR3);
1027 __raw_writel(cicr4, pcdev->base + CICR4);
1028
1029 /* CIF interrupts are not used, only DMA */
1030 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1031 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1032 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1033 __raw_writel(cicr0, pcdev->base + CICR0);
1034
1035 return 0;
1036 }
1037
1038 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1039 unsigned char buswidth)
1040 {
1041 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1042 struct pxa_camera_dev *pcdev = ici->priv;
1043 unsigned long bus_flags, camera_flags;
1044 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1045
1046 if (ret < 0)
1047 return ret;
1048
1049 camera_flags = icd->ops->query_bus_param(icd);
1050
1051 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1052 }
1053
1054 static const struct soc_camera_data_format pxa_camera_formats[] = {
1055 {
1056 .name = "Planar YUV422 16 bit",
1057 .depth = 16,
1058 .fourcc = V4L2_PIX_FMT_YUV422P,
1059 .colorspace = V4L2_COLORSPACE_JPEG,
1060 },
1061 };
1062
1063 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1064 {
1065 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1066 struct pxa_camera_dev *pcdev = ici->priv;
1067
1068 switch (depth) {
1069 case 8:
1070 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1071 case 9:
1072 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1073 case 10:
1074 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1075 }
1076 return false;
1077 }
1078
1079 static int required_buswidth(const struct soc_camera_data_format *fmt)
1080 {
1081 switch (fmt->fourcc) {
1082 case V4L2_PIX_FMT_UYVY:
1083 case V4L2_PIX_FMT_VYUY:
1084 case V4L2_PIX_FMT_YUYV:
1085 case V4L2_PIX_FMT_YVYU:
1086 case V4L2_PIX_FMT_RGB565:
1087 case V4L2_PIX_FMT_RGB555:
1088 return 8;
1089 default:
1090 return fmt->depth;
1091 }
1092 }
1093
1094 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1095 struct soc_camera_format_xlate *xlate)
1096 {
1097 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1098 int formats = 0, buswidth, ret;
1099
1100 buswidth = required_buswidth(icd->formats + idx);
1101
1102 if (!buswidth_supported(icd, buswidth))
1103 return 0;
1104
1105 ret = pxa_camera_try_bus_param(icd, buswidth);
1106 if (ret < 0)
1107 return 0;
1108
1109 switch (icd->formats[idx].fourcc) {
1110 case V4L2_PIX_FMT_UYVY:
1111 formats++;
1112 if (xlate) {
1113 xlate->host_fmt = &pxa_camera_formats[0];
1114 xlate->cam_fmt = icd->formats + idx;
1115 xlate->buswidth = buswidth;
1116 xlate++;
1117 dev_dbg(&ici->dev, "Providing format %s using %s\n",
1118 pxa_camera_formats[0].name,
1119 icd->formats[idx].name);
1120 }
1121 case V4L2_PIX_FMT_VYUY:
1122 case V4L2_PIX_FMT_YUYV:
1123 case V4L2_PIX_FMT_YVYU:
1124 case V4L2_PIX_FMT_RGB565:
1125 case V4L2_PIX_FMT_RGB555:
1126 formats++;
1127 if (xlate) {
1128 xlate->host_fmt = icd->formats + idx;
1129 xlate->cam_fmt = icd->formats + idx;
1130 xlate->buswidth = buswidth;
1131 xlate++;
1132 dev_dbg(&ici->dev, "Providing format %s packed\n",
1133 icd->formats[idx].name);
1134 }
1135 break;
1136 default:
1137 /* Generic pass-through */
1138 formats++;
1139 if (xlate) {
1140 xlate->host_fmt = icd->formats + idx;
1141 xlate->cam_fmt = icd->formats + idx;
1142 xlate->buswidth = icd->formats[idx].depth;
1143 xlate++;
1144 dev_dbg(&ici->dev,
1145 "Providing format %s in pass-through mode\n",
1146 icd->formats[idx].name);
1147 }
1148 }
1149
1150 return formats;
1151 }
1152
1153 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1154 __u32 pixfmt, struct v4l2_rect *rect)
1155 {
1156 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1157 struct pxa_camera_dev *pcdev = ici->priv;
1158 const struct soc_camera_data_format *cam_fmt = NULL;
1159 const struct soc_camera_format_xlate *xlate = NULL;
1160 struct soc_camera_sense sense = {
1161 .master_clock = pcdev->mclk,
1162 .pixel_clock_max = pcdev->ciclk / 4,
1163 };
1164 int ret;
1165
1166 if (pixfmt) {
1167 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1168 if (!xlate) {
1169 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1170 return -EINVAL;
1171 }
1172
1173 cam_fmt = xlate->cam_fmt;
1174 }
1175
1176 /* If PCLK is used to latch data from the sensor, check sense */
1177 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1178 icd->sense = &sense;
1179
1180 switch (pixfmt) {
1181 case 0: /* Only geometry change */
1182 ret = icd->ops->set_fmt(icd, pixfmt, rect);
1183 break;
1184 default:
1185 ret = icd->ops->set_fmt(icd, cam_fmt->fourcc, rect);
1186 }
1187
1188 icd->sense = NULL;
1189
1190 if (ret < 0) {
1191 dev_warn(&ici->dev, "Failed to configure for format %x\n",
1192 pixfmt);
1193 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1194 if (sense.pixel_clock > sense.pixel_clock_max) {
1195 dev_err(&ici->dev,
1196 "pixel clock %lu set by the camera too high!",
1197 sense.pixel_clock);
1198 return -EIO;
1199 }
1200 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1201 }
1202
1203 if (pixfmt && !ret) {
1204 icd->buswidth = xlate->buswidth;
1205 icd->current_fmt = xlate->host_fmt;
1206 }
1207
1208 return ret;
1209 }
1210
1211 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1212 struct v4l2_format *f)
1213 {
1214 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1215 const struct soc_camera_format_xlate *xlate;
1216 struct v4l2_pix_format *pix = &f->fmt.pix;
1217 __u32 pixfmt = pix->pixelformat;
1218 enum v4l2_field field;
1219 int ret;
1220
1221 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1222 if (!xlate) {
1223 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1224 return -EINVAL;
1225 }
1226
1227 /* limit to pxa hardware capabilities */
1228 if (pix->height < 32)
1229 pix->height = 32;
1230 if (pix->height > 2048)
1231 pix->height = 2048;
1232 if (pix->width < 48)
1233 pix->width = 48;
1234 if (pix->width > 2048)
1235 pix->width = 2048;
1236 pix->width &= ~0x01;
1237
1238 pix->bytesperline = pix->width *
1239 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1240 pix->sizeimage = pix->height * pix->bytesperline;
1241
1242 /* camera has to see its format, but the user the original one */
1243 pix->pixelformat = xlate->cam_fmt->fourcc;
1244 /* limit to sensor capabilities */
1245 ret = icd->ops->try_fmt(icd, f);
1246 pix->pixelformat = xlate->host_fmt->fourcc;
1247
1248 field = pix->field;
1249
1250 if (field == V4L2_FIELD_ANY) {
1251 pix->field = V4L2_FIELD_NONE;
1252 } else if (field != V4L2_FIELD_NONE) {
1253 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1254 return -EINVAL;
1255 }
1256
1257 return ret;
1258 }
1259
1260 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1261 struct v4l2_requestbuffers *p)
1262 {
1263 int i;
1264
1265 /* This is for locking debugging only. I removed spinlocks and now I
1266 * check whether .prepare is ever called on a linked buffer, or whether
1267 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1268 * it hadn't triggered */
1269 for (i = 0; i < p->count; i++) {
1270 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1271 struct pxa_buffer, vb);
1272 buf->inwork = 0;
1273 INIT_LIST_HEAD(&buf->vb.queue);
1274 }
1275
1276 return 0;
1277 }
1278
1279 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1280 {
1281 struct soc_camera_file *icf = file->private_data;
1282 struct pxa_buffer *buf;
1283
1284 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1285 vb.stream);
1286
1287 poll_wait(file, &buf->vb.done, pt);
1288
1289 if (buf->vb.state == VIDEOBUF_DONE ||
1290 buf->vb.state == VIDEOBUF_ERROR)
1291 return POLLIN|POLLRDNORM;
1292
1293 return 0;
1294 }
1295
1296 static int pxa_camera_querycap(struct soc_camera_host *ici,
1297 struct v4l2_capability *cap)
1298 {
1299 /* cap->name is set by the firendly caller:-> */
1300 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1301 cap->version = PXA_CAM_VERSION_CODE;
1302 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1303
1304 return 0;
1305 }
1306
1307 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1308 {
1309 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1310 struct pxa_camera_dev *pcdev = ici->priv;
1311 int i = 0, ret = 0;
1312
1313 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1314 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1315 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1316 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1317 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1318
1319 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1320 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1321
1322 return ret;
1323 }
1324
1325 static int pxa_camera_resume(struct soc_camera_device *icd)
1326 {
1327 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1328 struct pxa_camera_dev *pcdev = ici->priv;
1329 int i = 0, ret = 0;
1330
1331 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1332 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1333 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1334
1335 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1336 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1337 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1338 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1339 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1340
1341 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1342 ret = pcdev->icd->ops->resume(pcdev->icd);
1343
1344 /* Restart frame capture if active buffer exists */
1345 if (!ret && pcdev->active) {
1346 unsigned long cifr, cicr0;
1347
1348 /* Reset the FIFOs */
1349 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1350 __raw_writel(cifr, pcdev->base + CIFR);
1351
1352 cicr0 = __raw_readl(pcdev->base + CICR0);
1353 cicr0 &= ~CICR0_EOFM; /* Enable End-Of-Frame Interrupt */
1354 cicr0 |= CICR0_ENB; /* Restart the Capture Interface */
1355 __raw_writel(cicr0, pcdev->base + CICR0);
1356 }
1357
1358 return ret;
1359 }
1360
1361 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1362 .owner = THIS_MODULE,
1363 .add = pxa_camera_add_device,
1364 .remove = pxa_camera_remove_device,
1365 .suspend = pxa_camera_suspend,
1366 .resume = pxa_camera_resume,
1367 .get_formats = pxa_camera_get_formats,
1368 .set_fmt = pxa_camera_set_fmt,
1369 .try_fmt = pxa_camera_try_fmt,
1370 .init_videobuf = pxa_camera_init_videobuf,
1371 .reqbufs = pxa_camera_reqbufs,
1372 .poll = pxa_camera_poll,
1373 .querycap = pxa_camera_querycap,
1374 .set_bus_param = pxa_camera_set_bus_param,
1375 };
1376
1377 /* Should be allocated dynamically too, but we have only one. */
1378 static struct soc_camera_host pxa_soc_camera_host = {
1379 .drv_name = PXA_CAM_DRV_NAME,
1380 .ops = &pxa_soc_camera_host_ops,
1381 };
1382
1383 static int pxa_camera_probe(struct platform_device *pdev)
1384 {
1385 struct pxa_camera_dev *pcdev;
1386 struct resource *res;
1387 void __iomem *base;
1388 int irq;
1389 int err = 0;
1390
1391 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1392 irq = platform_get_irq(pdev, 0);
1393 if (!res || irq < 0) {
1394 err = -ENODEV;
1395 goto exit;
1396 }
1397
1398 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1399 if (!pcdev) {
1400 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1401 err = -ENOMEM;
1402 goto exit;
1403 }
1404
1405 pcdev->clk = clk_get(&pdev->dev, NULL);
1406 if (IS_ERR(pcdev->clk)) {
1407 err = PTR_ERR(pcdev->clk);
1408 goto exit_kfree;
1409 }
1410
1411 dev_set_drvdata(&pdev->dev, pcdev);
1412 pcdev->res = res;
1413
1414 pcdev->pdata = pdev->dev.platform_data;
1415 pcdev->platform_flags = pcdev->pdata->flags;
1416 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1417 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1418 /* Platform hasn't set available data widths. This is bad.
1419 * Warn and use a default. */
1420 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1421 "data widths, using default 10 bit\n");
1422 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1423 }
1424 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1425 if (!pcdev->mclk) {
1426 dev_warn(&pdev->dev,
1427 "mclk == 0! Please, fix your platform data. "
1428 "Using default 20MHz\n");
1429 pcdev->mclk = 20000000;
1430 }
1431
1432 pcdev->dev = &pdev->dev;
1433 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1434
1435 INIT_LIST_HEAD(&pcdev->capture);
1436 spin_lock_init(&pcdev->lock);
1437
1438 /*
1439 * Request the regions.
1440 */
1441 if (!request_mem_region(res->start, res->end - res->start + 1,
1442 PXA_CAM_DRV_NAME)) {
1443 err = -EBUSY;
1444 goto exit_clk;
1445 }
1446
1447 base = ioremap(res->start, res->end - res->start + 1);
1448 if (!base) {
1449 err = -ENOMEM;
1450 goto exit_release;
1451 }
1452 pcdev->irq = irq;
1453 pcdev->base = base;
1454
1455 /* request dma */
1456 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1457 pxa_camera_dma_irq_y, pcdev);
1458 if (err < 0) {
1459 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1460 goto exit_iounmap;
1461 }
1462 pcdev->dma_chans[0] = err;
1463 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1464
1465 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1466 pxa_camera_dma_irq_u, pcdev);
1467 if (err < 0) {
1468 dev_err(pcdev->dev, "Can't request DMA for U\n");
1469 goto exit_free_dma_y;
1470 }
1471 pcdev->dma_chans[1] = err;
1472 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1473
1474 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1475 pxa_camera_dma_irq_v, pcdev);
1476 if (err < 0) {
1477 dev_err(pcdev->dev, "Can't request DMA for V\n");
1478 goto exit_free_dma_u;
1479 }
1480 pcdev->dma_chans[2] = err;
1481 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1482
1483 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1484 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1485 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1486
1487 /* request irq */
1488 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1489 pcdev);
1490 if (err) {
1491 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1492 goto exit_free_dma;
1493 }
1494
1495 pxa_soc_camera_host.priv = pcdev;
1496 pxa_soc_camera_host.dev.parent = &pdev->dev;
1497 pxa_soc_camera_host.nr = pdev->id;
1498 err = soc_camera_host_register(&pxa_soc_camera_host);
1499 if (err)
1500 goto exit_free_irq;
1501
1502 return 0;
1503
1504 exit_free_irq:
1505 free_irq(pcdev->irq, pcdev);
1506 exit_free_dma:
1507 pxa_free_dma(pcdev->dma_chans[2]);
1508 exit_free_dma_u:
1509 pxa_free_dma(pcdev->dma_chans[1]);
1510 exit_free_dma_y:
1511 pxa_free_dma(pcdev->dma_chans[0]);
1512 exit_iounmap:
1513 iounmap(base);
1514 exit_release:
1515 release_mem_region(res->start, res->end - res->start + 1);
1516 exit_clk:
1517 clk_put(pcdev->clk);
1518 exit_kfree:
1519 kfree(pcdev);
1520 exit:
1521 return err;
1522 }
1523
1524 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1525 {
1526 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1527 struct resource *res;
1528
1529 clk_put(pcdev->clk);
1530
1531 pxa_free_dma(pcdev->dma_chans[0]);
1532 pxa_free_dma(pcdev->dma_chans[1]);
1533 pxa_free_dma(pcdev->dma_chans[2]);
1534 free_irq(pcdev->irq, pcdev);
1535
1536 soc_camera_host_unregister(&pxa_soc_camera_host);
1537
1538 iounmap(pcdev->base);
1539
1540 res = pcdev->res;
1541 release_mem_region(res->start, res->end - res->start + 1);
1542
1543 kfree(pcdev);
1544
1545 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1546
1547 return 0;
1548 }
1549
1550 static struct platform_driver pxa_camera_driver = {
1551 .driver = {
1552 .name = PXA_CAM_DRV_NAME,
1553 },
1554 .probe = pxa_camera_probe,
1555 .remove = __exit_p(pxa_camera_remove),
1556 };
1557
1558
1559 static int __devinit pxa_camera_init(void)
1560 {
1561 return platform_driver_register(&pxa_camera_driver);
1562 }
1563
1564 static void __exit pxa_camera_exit(void)
1565 {
1566 platform_driver_unregister(&pxa_camera_driver);
1567 }
1568
1569 module_init(pxa_camera_init);
1570 module_exit(pxa_camera_exit);
1571
1572 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1573 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1574 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards