?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable
[linux-2.6/mini2440.git] / drivers / net / ucc_geth.c
blob44f8392da11729522a5e809e13f3a782ee03df71
1 /*
2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_platform.h>
31
32 #include <asm/uaccess.h>
33 #include <asm/irq.h>
34 #include <asm/io.h>
35 #include <asm/immap_qe.h>
36 #include <asm/qe.h>
37 #include <asm/ucc.h>
38 #include <asm/ucc_fast.h>
39
40 #include "ucc_geth.h"
41 #include "fsl_pq_mdio.h"
42
43 #undef DEBUG
44
45 #define ugeth_printk(level, format, arg...) \
46 printk(level format "\n", ## arg)
47
48 #define ugeth_dbg(format, arg...) \
49 ugeth_printk(KERN_DEBUG , format , ## arg)
50 #define ugeth_err(format, arg...) \
51 ugeth_printk(KERN_ERR , format , ## arg)
52 #define ugeth_info(format, arg...) \
53 ugeth_printk(KERN_INFO , format , ## arg)
54 #define ugeth_warn(format, arg...) \
55 ugeth_printk(KERN_WARNING , format , ## arg)
56
57 #ifdef UGETH_VERBOSE_DEBUG
58 #define ugeth_vdbg ugeth_dbg
59 #else
60 #define ugeth_vdbg(fmt, args...) do { } while (0)
61 #endif /* UGETH_VERBOSE_DEBUG */
62 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
63
64
65 static DEFINE_SPINLOCK(ugeth_lock);
66
67 static struct {
68 u32 msg_enable;
69 } debug = { -1 };
70
71 module_param_named(debug, debug.msg_enable, int, 0);
72 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
73
74 static struct ucc_geth_info ugeth_primary_info = {
75 .uf_info = {
76 .bd_mem_part = MEM_PART_SYSTEM,
77 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
78 .max_rx_buf_length = 1536,
79 /* adjusted at startup if max-speed 1000 */
80 .urfs = UCC_GETH_URFS_INIT,
81 .urfet = UCC_GETH_URFET_INIT,
82 .urfset = UCC_GETH_URFSET_INIT,
83 .utfs = UCC_GETH_UTFS_INIT,
84 .utfet = UCC_GETH_UTFET_INIT,
85 .utftt = UCC_GETH_UTFTT_INIT,
86 .ufpt = 256,
87 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
88 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
89 .tenc = UCC_FAST_TX_ENCODING_NRZ,
90 .renc = UCC_FAST_RX_ENCODING_NRZ,
91 .tcrc = UCC_FAST_16_BIT_CRC,
92 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
93 },
94 .numQueuesTx = 1,
95 .numQueuesRx = 1,
96 .extendedFilteringChainPointer = ((uint32_t) NULL),
97 .typeorlen = 3072 /*1536 */ ,
98 .nonBackToBackIfgPart1 = 0x40,
99 .nonBackToBackIfgPart2 = 0x60,
100 .miminumInterFrameGapEnforcement = 0x50,
101 .backToBackInterFrameGap = 0x60,
102 .mblinterval = 128,
103 .nortsrbytetime = 5,
104 .fracsiz = 1,
105 .strictpriorityq = 0xff,
106 .altBebTruncation = 0xa,
107 .excessDefer = 1,
108 .maxRetransmission = 0xf,
109 .collisionWindow = 0x37,
110 .receiveFlowControl = 1,
111 .transmitFlowControl = 1,
112 .maxGroupAddrInHash = 4,
113 .maxIndAddrInHash = 4,
114 .prel = 7,
115 .maxFrameLength = 1518,
116 .minFrameLength = 64,
117 .maxD1Length = 1520,
118 .maxD2Length = 1520,
119 .vlantype = 0x8100,
120 .ecamptr = ((uint32_t) NULL),
121 .eventRegMask = UCCE_OTHER,
122 .pausePeriod = 0xf000,
123 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
124 .bdRingLenTx = {
125 TX_BD_RING_LEN,
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN},
133
134 .bdRingLenRx = {
135 RX_BD_RING_LEN,
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN},
143
144 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
145 .largestexternallookupkeysize =
146 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
147 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
148 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
150 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
151 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
152 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
153 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
154 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
155 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
156 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
157 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
158 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 };
160
161 static struct ucc_geth_info ugeth_info[8];
162
163 #ifdef DEBUG
164 static void mem_disp(u8 *addr, int size)
165 {
166 u8 *i;
167 int size16Aling = (size >> 4) << 4;
168 int size4Aling = (size >> 2) << 2;
169 int notAlign = 0;
170 if (size % 16)
171 notAlign = 1;
172
173 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
174 printk("0x%08x: %08x %08x %08x %08x\r\n",
175 (u32) i,
176 *((u32 *) (i)),
177 *((u32 *) (i + 4)),
178 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
179 if (notAlign == 1)
180 printk("0x%08x: ", (u32) i);
181 for (; (u32) i < (u32) addr + size4Aling; i += 4)
182 printk("%08x ", *((u32 *) (i)));
183 for (; (u32) i < (u32) addr + size; i++)
184 printk("%02x", *((u8 *) (i)));
185 if (notAlign == 1)
186 printk("\r\n");
187 }
188 #endif /* DEBUG */
189
190 static struct list_head *dequeue(struct list_head *lh)
191 {
192 unsigned long flags;
193
194 spin_lock_irqsave(&ugeth_lock, flags);
195 if (!list_empty(lh)) {
196 struct list_head *node = lh->next;
197 list_del(node);
198 spin_unlock_irqrestore(&ugeth_lock, flags);
199 return node;
200 } else {
201 spin_unlock_irqrestore(&ugeth_lock, flags);
202 return NULL;
203 }
204 }
205
206 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
207 u8 __iomem *bd)
208 {
209 struct sk_buff *skb = NULL;
210
211 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
212 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
213
214 if (skb == NULL)
215 return NULL;
216
217 /* We need the data buffer to be aligned properly. We will reserve
218 * as many bytes as needed to align the data properly
219 */
220 skb_reserve(skb,
221 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
222 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
223 1)));
224
225 skb->dev = ugeth->ndev;
226
227 out_be32(&((struct qe_bd __iomem *)bd)->buf,
228 dma_map_single(ugeth->dev,
229 skb->data,
230 ugeth->ug_info->uf_info.max_rx_buf_length +
231 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
232 DMA_FROM_DEVICE));
233
234 out_be32((u32 __iomem *)bd,
235 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
236
237 return skb;
238 }
239
240 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
241 {
242 u8 __iomem *bd;
243 u32 bd_status;
244 struct sk_buff *skb;
245 int i;
246
247 bd = ugeth->p_rx_bd_ring[rxQ];
248 i = 0;
249
250 do {
251 bd_status = in_be32((u32 __iomem *)bd);
252 skb = get_new_skb(ugeth, bd);
253
254 if (!skb) /* If can not allocate data buffer,
255 abort. Cleanup will be elsewhere */
256 return -ENOMEM;
257
258 ugeth->rx_skbuff[rxQ][i] = skb;
259
260 /* advance the BD pointer */
261 bd += sizeof(struct qe_bd);
262 i++;
263 } while (!(bd_status & R_W));
264
265 return 0;
266 }
267
268 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
269 u32 *p_start,
270 u8 num_entries,
271 u32 thread_size,
272 u32 thread_alignment,
273 enum qe_risc_allocation risc,
274 int skip_page_for_first_entry)
275 {
276 u32 init_enet_offset;
277 u8 i;
278 int snum;
279
280 for (i = 0; i < num_entries; i++) {
281 if ((snum = qe_get_snum()) < 0) {
282 if (netif_msg_ifup(ugeth))
283 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
284 return snum;
285 }
286 if ((i == 0) && skip_page_for_first_entry)
287 /* First entry of Rx does not have page */
288 init_enet_offset = 0;
289 else {
290 init_enet_offset =
291 qe_muram_alloc(thread_size, thread_alignment);
292 if (IS_ERR_VALUE(init_enet_offset)) {
293 if (netif_msg_ifup(ugeth))
294 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
295 qe_put_snum((u8) snum);
296 return -ENOMEM;
297 }
298 }
299 *(p_start++) =
300 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
301 | risc;
302 }
303
304 return 0;
305 }
306
307 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
308 u32 *p_start,
309 u8 num_entries,
310 enum qe_risc_allocation risc,
311 int skip_page_for_first_entry)
312 {
313 u32 init_enet_offset;
314 u8 i;
315 int snum;
316
317 for (i = 0; i < num_entries; i++) {
318 u32 val = *p_start;
319
320 /* Check that this entry was actually valid --
321 needed in case failed in allocations */
322 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
323 snum =
324 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
325 ENET_INIT_PARAM_SNUM_SHIFT;
326 qe_put_snum((u8) snum);
327 if (!((i == 0) && skip_page_for_first_entry)) {
328 /* First entry of Rx does not have page */
329 init_enet_offset =
330 (val & ENET_INIT_PARAM_PTR_MASK);
331 qe_muram_free(init_enet_offset);
332 }
333 *p_start++ = 0;
334 }
335 }
336
337 return 0;
338 }
339
340 #ifdef DEBUG
341 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
342 u32 __iomem *p_start,
343 u8 num_entries,
344 u32 thread_size,
345 enum qe_risc_allocation risc,
346 int skip_page_for_first_entry)
347 {
348 u32 init_enet_offset;
349 u8 i;
350 int snum;
351
352 for (i = 0; i < num_entries; i++) {
353 u32 val = in_be32(p_start);
354
355 /* Check that this entry was actually valid --
356 needed in case failed in allocations */
357 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
358 snum =
359 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
360 ENET_INIT_PARAM_SNUM_SHIFT;
361 qe_put_snum((u8) snum);
362 if (!((i == 0) && skip_page_for_first_entry)) {
363 /* First entry of Rx does not have page */
364 init_enet_offset =
365 (in_be32(p_start) &
366 ENET_INIT_PARAM_PTR_MASK);
367 ugeth_info("Init enet entry %d:", i);
368 ugeth_info("Base address: 0x%08x",
369 (u32)
370 qe_muram_addr(init_enet_offset));
371 mem_disp(qe_muram_addr(init_enet_offset),
372 thread_size);
373 }
374 p_start++;
375 }
376 }
377
378 return 0;
379 }
380 #endif
381
382 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
383 {
384 kfree(enet_addr_cont);
385 }
386
387 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
388 {
389 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
390 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
391 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
392 }
393
394 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
395 {
396 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
397
398 if (!(paddr_num < NUM_OF_PADDRS)) {
399 ugeth_warn("%s: Illagel paddr_num.", __func__);
400 return -EINVAL;
401 }
402
403 p_82xx_addr_filt =
404 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
405 addressfiltering;
406
407 /* Writing address ff.ff.ff.ff.ff.ff disables address
408 recognition for this register */
409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
412
413 return 0;
414 }
415
416 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
417 u8 *p_enet_addr)
418 {
419 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
420 u32 cecr_subblock;
421
422 p_82xx_addr_filt =
423 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
424 addressfiltering;
425
426 cecr_subblock =
427 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
428
429 /* Ethernet frames are defined in Little Endian mode,
430 therefor to insert */
431 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
432
433 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
434
435 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
436 QE_CR_PROTOCOL_ETHERNET, 0);
437 }
438
439 #ifdef CONFIG_UGETH_MAGIC_PACKET
440 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
441 {
442 struct ucc_fast_private *uccf;
443 struct ucc_geth __iomem *ug_regs;
444
445 uccf = ugeth->uccf;
446 ug_regs = ugeth->ug_regs;
447
448 /* Enable interrupts for magic packet detection */
449 setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
450
451 /* Enable magic packet detection */
452 setbits32(&ug_regs->maccfg2, MACCFG2_MPE);
453 }
454
455 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
456 {
457 struct ucc_fast_private *uccf;
458 struct ucc_geth __iomem *ug_regs;
459
460 uccf = ugeth->uccf;
461 ug_regs = ugeth->ug_regs;
462
463 /* Disable interrupts for magic packet detection */
464 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
465
466 /* Disable magic packet detection */
467 clrbits32(&ug_regs->maccfg2, MACCFG2_MPE);
468 }
469 #endif /* MAGIC_PACKET */
470
471 static inline int compare_addr(u8 **addr1, u8 **addr2)
472 {
473 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
474 }
475
476 #ifdef DEBUG
477 static void get_statistics(struct ucc_geth_private *ugeth,
478 struct ucc_geth_tx_firmware_statistics *
479 tx_firmware_statistics,
480 struct ucc_geth_rx_firmware_statistics *
481 rx_firmware_statistics,
482 struct ucc_geth_hardware_statistics *hardware_statistics)
483 {
484 struct ucc_fast __iomem *uf_regs;
485 struct ucc_geth __iomem *ug_regs;
486 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
487 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
488
489 ug_regs = ugeth->ug_regs;
490 uf_regs = (struct ucc_fast __iomem *) ug_regs;
491 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
492 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
493
494 /* Tx firmware only if user handed pointer and driver actually
495 gathers Tx firmware statistics */
496 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
497 tx_firmware_statistics->sicoltx =
498 in_be32(&p_tx_fw_statistics_pram->sicoltx);
499 tx_firmware_statistics->mulcoltx =
500 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
501 tx_firmware_statistics->latecoltxfr =
502 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
503 tx_firmware_statistics->frabortduecol =
504 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
505 tx_firmware_statistics->frlostinmactxer =
506 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
507 tx_firmware_statistics->carriersenseertx =
508 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
509 tx_firmware_statistics->frtxok =
510 in_be32(&p_tx_fw_statistics_pram->frtxok);
511 tx_firmware_statistics->txfrexcessivedefer =
512 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
513 tx_firmware_statistics->txpkts256 =
514 in_be32(&p_tx_fw_statistics_pram->txpkts256);
515 tx_firmware_statistics->txpkts512 =
516 in_be32(&p_tx_fw_statistics_pram->txpkts512);
517 tx_firmware_statistics->txpkts1024 =
518 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
519 tx_firmware_statistics->txpktsjumbo =
520 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
521 }
522
523 /* Rx firmware only if user handed pointer and driver actually
524 * gathers Rx firmware statistics */
525 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
526 int i;
527 rx_firmware_statistics->frrxfcser =
528 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
529 rx_firmware_statistics->fraligner =
530 in_be32(&p_rx_fw_statistics_pram->fraligner);
531 rx_firmware_statistics->inrangelenrxer =
532 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
533 rx_firmware_statistics->outrangelenrxer =
534 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
535 rx_firmware_statistics->frtoolong =
536 in_be32(&p_rx_fw_statistics_pram->frtoolong);
537 rx_firmware_statistics->runt =
538 in_be32(&p_rx_fw_statistics_pram->runt);
539 rx_firmware_statistics->verylongevent =
540 in_be32(&p_rx_fw_statistics_pram->verylongevent);
541 rx_firmware_statistics->symbolerror =
542 in_be32(&p_rx_fw_statistics_pram->symbolerror);
543 rx_firmware_statistics->dropbsy =
544 in_be32(&p_rx_fw_statistics_pram->dropbsy);
545 for (i = 0; i < 0x8; i++)
546 rx_firmware_statistics->res0[i] =
547 p_rx_fw_statistics_pram->res0[i];
548 rx_firmware_statistics->mismatchdrop =
549 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
550 rx_firmware_statistics->underpkts =
551 in_be32(&p_rx_fw_statistics_pram->underpkts);
552 rx_firmware_statistics->pkts256 =
553 in_be32(&p_rx_fw_statistics_pram->pkts256);
554 rx_firmware_statistics->pkts512 =
555 in_be32(&p_rx_fw_statistics_pram->pkts512);
556 rx_firmware_statistics->pkts1024 =
557 in_be32(&p_rx_fw_statistics_pram->pkts1024);
558 rx_firmware_statistics->pktsjumbo =
559 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
560 rx_firmware_statistics->frlossinmacer =
561 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
562 rx_firmware_statistics->pausefr =
563 in_be32(&p_rx_fw_statistics_pram->pausefr);
564 for (i = 0; i < 0x4; i++)
565 rx_firmware_statistics->res1[i] =
566 p_rx_fw_statistics_pram->res1[i];
567 rx_firmware_statistics->removevlan =
568 in_be32(&p_rx_fw_statistics_pram->removevlan);
569 rx_firmware_statistics->replacevlan =
570 in_be32(&p_rx_fw_statistics_pram->replacevlan);
571 rx_firmware_statistics->insertvlan =
572 in_be32(&p_rx_fw_statistics_pram->insertvlan);
573 }
574
575 /* Hardware only if user handed pointer and driver actually
576 gathers hardware statistics */
577 if (hardware_statistics &&
578 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
579 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
580 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
581 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
582 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
583 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
584 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
585 hardware_statistics->txok = in_be32(&ug_regs->txok);
586 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
587 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
588 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
589 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
590 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
591 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
592 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
593 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
594 }
595 }
596
597 static void dump_bds(struct ucc_geth_private *ugeth)
598 {
599 int i;
600 int length;
601
602 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
603 if (ugeth->p_tx_bd_ring[i]) {
604 length =
605 (ugeth->ug_info->bdRingLenTx[i] *
606 sizeof(struct qe_bd));
607 ugeth_info("TX BDs[%d]", i);
608 mem_disp(ugeth->p_tx_bd_ring[i], length);
609 }
610 }
611 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
612 if (ugeth->p_rx_bd_ring[i]) {
613 length =
614 (ugeth->ug_info->bdRingLenRx[i] *
615 sizeof(struct qe_bd));
616 ugeth_info("RX BDs[%d]", i);
617 mem_disp(ugeth->p_rx_bd_ring[i], length);
618 }
619 }
620 }
621
622 static void dump_regs(struct ucc_geth_private *ugeth)
623 {
624 int i;
625
626 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
627 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
628
629 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
630 (u32) & ugeth->ug_regs->maccfg1,
631 in_be32(&ugeth->ug_regs->maccfg1));
632 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
633 (u32) & ugeth->ug_regs->maccfg2,
634 in_be32(&ugeth->ug_regs->maccfg2));
635 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
636 (u32) & ugeth->ug_regs->ipgifg,
637 in_be32(&ugeth->ug_regs->ipgifg));
638 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
639 (u32) & ugeth->ug_regs->hafdup,
640 in_be32(&ugeth->ug_regs->hafdup));
641 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
642 (u32) & ugeth->ug_regs->ifctl,
643 in_be32(&ugeth->ug_regs->ifctl));
644 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
645 (u32) & ugeth->ug_regs->ifstat,
646 in_be32(&ugeth->ug_regs->ifstat));
647 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
648 (u32) & ugeth->ug_regs->macstnaddr1,
649 in_be32(&ugeth->ug_regs->macstnaddr1));
650 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
651 (u32) & ugeth->ug_regs->macstnaddr2,
652 in_be32(&ugeth->ug_regs->macstnaddr2));
653 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
654 (u32) & ugeth->ug_regs->uempr,
655 in_be32(&ugeth->ug_regs->uempr));
656 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
657 (u32) & ugeth->ug_regs->utbipar,
658 in_be32(&ugeth->ug_regs->utbipar));
659 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
660 (u32) & ugeth->ug_regs->uescr,
661 in_be16(&ugeth->ug_regs->uescr));
662 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
663 (u32) & ugeth->ug_regs->tx64,
664 in_be32(&ugeth->ug_regs->tx64));
665 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
666 (u32) & ugeth->ug_regs->tx127,
667 in_be32(&ugeth->ug_regs->tx127));
668 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
669 (u32) & ugeth->ug_regs->tx255,
670 in_be32(&ugeth->ug_regs->tx255));
671 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
672 (u32) & ugeth->ug_regs->rx64,
673 in_be32(&ugeth->ug_regs->rx64));
674 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
675 (u32) & ugeth->ug_regs->rx127,
676 in_be32(&ugeth->ug_regs->rx127));
677 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
678 (u32) & ugeth->ug_regs->rx255,
679 in_be32(&ugeth->ug_regs->rx255));
680 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
681 (u32) & ugeth->ug_regs->txok,
682 in_be32(&ugeth->ug_regs->txok));
683 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
684 (u32) & ugeth->ug_regs->txcf,
685 in_be16(&ugeth->ug_regs->txcf));
686 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
687 (u32) & ugeth->ug_regs->tmca,
688 in_be32(&ugeth->ug_regs->tmca));
689 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
690 (u32) & ugeth->ug_regs->tbca,
691 in_be32(&ugeth->ug_regs->tbca));
692 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
693 (u32) & ugeth->ug_regs->rxfok,
694 in_be32(&ugeth->ug_regs->rxfok));
695 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
696 (u32) & ugeth->ug_regs->rxbok,
697 in_be32(&ugeth->ug_regs->rxbok));
698 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
699 (u32) & ugeth->ug_regs->rbyt,
700 in_be32(&ugeth->ug_regs->rbyt));
701 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
702 (u32) & ugeth->ug_regs->rmca,
703 in_be32(&ugeth->ug_regs->rmca));
704 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
705 (u32) & ugeth->ug_regs->rbca,
706 in_be32(&ugeth->ug_regs->rbca));
707 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
708 (u32) & ugeth->ug_regs->scar,
709 in_be32(&ugeth->ug_regs->scar));
710 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
711 (u32) & ugeth->ug_regs->scam,
712 in_be32(&ugeth->ug_regs->scam));
713
714 if (ugeth->p_thread_data_tx) {
715 int numThreadsTxNumerical;
716 switch (ugeth->ug_info->numThreadsTx) {
717 case UCC_GETH_NUM_OF_THREADS_1:
718 numThreadsTxNumerical = 1;
719 break;
720 case UCC_GETH_NUM_OF_THREADS_2:
721 numThreadsTxNumerical = 2;
722 break;
723 case UCC_GETH_NUM_OF_THREADS_4:
724 numThreadsTxNumerical = 4;
725 break;
726 case UCC_GETH_NUM_OF_THREADS_6:
727 numThreadsTxNumerical = 6;
728 break;
729 case UCC_GETH_NUM_OF_THREADS_8:
730 numThreadsTxNumerical = 8;
731 break;
732 default:
733 numThreadsTxNumerical = 0;
734 break;
735 }
736
737 ugeth_info("Thread data TXs:");
738 ugeth_info("Base address: 0x%08x",
739 (u32) ugeth->p_thread_data_tx);
740 for (i = 0; i < numThreadsTxNumerical; i++) {
741 ugeth_info("Thread data TX[%d]:", i);
742 ugeth_info("Base address: 0x%08x",
743 (u32) & ugeth->p_thread_data_tx[i]);
744 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
745 sizeof(struct ucc_geth_thread_data_tx));
746 }
747 }
748 if (ugeth->p_thread_data_rx) {
749 int numThreadsRxNumerical;
750 switch (ugeth->ug_info->numThreadsRx) {
751 case UCC_GETH_NUM_OF_THREADS_1:
752 numThreadsRxNumerical = 1;
753 break;
754 case UCC_GETH_NUM_OF_THREADS_2:
755 numThreadsRxNumerical = 2;
756 break;
757 case UCC_GETH_NUM_OF_THREADS_4:
758 numThreadsRxNumerical = 4;
759 break;
760 case UCC_GETH_NUM_OF_THREADS_6:
761 numThreadsRxNumerical = 6;
762 break;
763 case UCC_GETH_NUM_OF_THREADS_8:
764 numThreadsRxNumerical = 8;
765 break;
766 default:
767 numThreadsRxNumerical = 0;
768 break;
769 }
770
771 ugeth_info("Thread data RX:");
772 ugeth_info("Base address: 0x%08x",
773 (u32) ugeth->p_thread_data_rx);
774 for (i = 0; i < numThreadsRxNumerical; i++) {
775 ugeth_info("Thread data RX[%d]:", i);
776 ugeth_info("Base address: 0x%08x",
777 (u32) & ugeth->p_thread_data_rx[i]);
778 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
779 sizeof(struct ucc_geth_thread_data_rx));
780 }
781 }
782 if (ugeth->p_exf_glbl_param) {
783 ugeth_info("EXF global param:");
784 ugeth_info("Base address: 0x%08x",
785 (u32) ugeth->p_exf_glbl_param);
786 mem_disp((u8 *) ugeth->p_exf_glbl_param,
787 sizeof(*ugeth->p_exf_glbl_param));
788 }
789 if (ugeth->p_tx_glbl_pram) {
790 ugeth_info("TX global param:");
791 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
792 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
793 (u32) & ugeth->p_tx_glbl_pram->temoder,
794 in_be16(&ugeth->p_tx_glbl_pram->temoder));
795 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
796 (u32) & ugeth->p_tx_glbl_pram->sqptr,
797 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
798 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
799 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
800 in_be32(&ugeth->p_tx_glbl_pram->
801 schedulerbasepointer));
802 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
803 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
804 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
805 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
806 (u32) & ugeth->p_tx_glbl_pram->tstate,
807 in_be32(&ugeth->p_tx_glbl_pram->tstate));
808 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
809 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
810 ugeth->p_tx_glbl_pram->iphoffset[0]);
811 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
812 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
813 ugeth->p_tx_glbl_pram->iphoffset[1]);
814 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
815 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
816 ugeth->p_tx_glbl_pram->iphoffset[2]);
817 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
818 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
819 ugeth->p_tx_glbl_pram->iphoffset[3]);
820 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
821 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
822 ugeth->p_tx_glbl_pram->iphoffset[4]);
823 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
824 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
825 ugeth->p_tx_glbl_pram->iphoffset[5]);
826 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
827 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
828 ugeth->p_tx_glbl_pram->iphoffset[6]);
829 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
830 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
831 ugeth->p_tx_glbl_pram->iphoffset[7]);
832 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
833 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
834 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
835 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
836 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
837 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
838 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
839 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
840 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
841 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
842 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
843 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
844 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
845 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
846 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
847 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
848 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
849 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
850 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
851 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
852 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
853 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
854 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
855 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
856 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
857 (u32) & ugeth->p_tx_glbl_pram->tqptr,
858 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
859 }
860 if (ugeth->p_rx_glbl_pram) {
861 ugeth_info("RX global param:");
862 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
863 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
864 (u32) & ugeth->p_rx_glbl_pram->remoder,
865 in_be32(&ugeth->p_rx_glbl_pram->remoder));
866 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
867 (u32) & ugeth->p_rx_glbl_pram->rqptr,
868 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
869 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
870 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
871 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
872 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
873 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
874 ugeth->p_rx_glbl_pram->rxgstpack);
875 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
876 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
877 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
878 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
879 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
880 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
881 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
882 (u32) & ugeth->p_rx_glbl_pram->rstate,
883 ugeth->p_rx_glbl_pram->rstate);
884 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
885 (u32) & ugeth->p_rx_glbl_pram->mrblr,
886 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
887 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
888 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
889 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
890 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
891 (u32) & ugeth->p_rx_glbl_pram->mflr,
892 in_be16(&ugeth->p_rx_glbl_pram->mflr));
893 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
894 (u32) & ugeth->p_rx_glbl_pram->minflr,
895 in_be16(&ugeth->p_rx_glbl_pram->minflr));
896 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
897 (u32) & ugeth->p_rx_glbl_pram->maxd1,
898 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
899 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
900 (u32) & ugeth->p_rx_glbl_pram->maxd2,
901 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
902 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
903 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
904 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
905 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
906 (u32) & ugeth->p_rx_glbl_pram->l2qt,
907 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
908 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
909 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
910 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
911 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
912 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
913 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
914 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
915 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
916 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
917 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
918 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
919 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
920 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
921 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
922 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
923 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
924 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
925 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
926 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
927 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
928 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
929 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
930 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
931 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
932 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
933 (u32) & ugeth->p_rx_glbl_pram->vlantype,
934 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
935 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
936 (u32) & ugeth->p_rx_glbl_pram->vlantci,
937 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
938 for (i = 0; i < 64; i++)
939 ugeth_info
940 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
941 i,
942 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
943 ugeth->p_rx_glbl_pram->addressfiltering[i]);
944 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
945 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
946 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
947 }
948 if (ugeth->p_send_q_mem_reg) {
949 ugeth_info("Send Q memory registers:");
950 ugeth_info("Base address: 0x%08x",
951 (u32) ugeth->p_send_q_mem_reg);
952 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
953 ugeth_info("SQQD[%d]:", i);
954 ugeth_info("Base address: 0x%08x",
955 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
956 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
957 sizeof(struct ucc_geth_send_queue_qd));
958 }
959 }
960 if (ugeth->p_scheduler) {
961 ugeth_info("Scheduler:");
962 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
963 mem_disp((u8 *) ugeth->p_scheduler,
964 sizeof(*ugeth->p_scheduler));
965 }
966 if (ugeth->p_tx_fw_statistics_pram) {
967 ugeth_info("TX FW statistics pram:");
968 ugeth_info("Base address: 0x%08x",
969 (u32) ugeth->p_tx_fw_statistics_pram);
970 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
971 sizeof(*ugeth->p_tx_fw_statistics_pram));
972 }
973 if (ugeth->p_rx_fw_statistics_pram) {
974 ugeth_info("RX FW statistics pram:");
975 ugeth_info("Base address: 0x%08x",
976 (u32) ugeth->p_rx_fw_statistics_pram);
977 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
978 sizeof(*ugeth->p_rx_fw_statistics_pram));
979 }
980 if (ugeth->p_rx_irq_coalescing_tbl) {
981 ugeth_info("RX IRQ coalescing tables:");
982 ugeth_info("Base address: 0x%08x",
983 (u32) ugeth->p_rx_irq_coalescing_tbl);
984 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
985 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
986 ugeth_info("Base address: 0x%08x",
987 (u32) & ugeth->p_rx_irq_coalescing_tbl->
988 coalescingentry[i]);
989 ugeth_info
990 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
991 (u32) & ugeth->p_rx_irq_coalescing_tbl->
992 coalescingentry[i].interruptcoalescingmaxvalue,
993 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
994 coalescingentry[i].
995 interruptcoalescingmaxvalue));
996 ugeth_info
997 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
998 (u32) & ugeth->p_rx_irq_coalescing_tbl->
999 coalescingentry[i].interruptcoalescingcounter,
1000 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1001 coalescingentry[i].
1002 interruptcoalescingcounter));
1003 }
1004 }
1005 if (ugeth->p_rx_bd_qs_tbl) {
1006 ugeth_info("RX BD QS tables:");
1007 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1008 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1009 ugeth_info("RX BD QS table[%d]:", i);
1010 ugeth_info("Base address: 0x%08x",
1011 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1012 ugeth_info
1013 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1014 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1015 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1016 ugeth_info
1017 ("bdptr : addr - 0x%08x, val - 0x%08x",
1018 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1019 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1020 ugeth_info
1021 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1022 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1023 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1024 externalbdbaseptr));
1025 ugeth_info
1026 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1027 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1028 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1029 ugeth_info("ucode RX Prefetched BDs:");
1030 ugeth_info("Base address: 0x%08x",
1031 (u32)
1032 qe_muram_addr(in_be32
1033 (&ugeth->p_rx_bd_qs_tbl[i].
1034 bdbaseptr)));
1035 mem_disp((u8 *)
1036 qe_muram_addr(in_be32
1037 (&ugeth->p_rx_bd_qs_tbl[i].
1038 bdbaseptr)),
1039 sizeof(struct ucc_geth_rx_prefetched_bds));
1040 }
1041 }
1042 if (ugeth->p_init_enet_param_shadow) {
1043 int size;
1044 ugeth_info("Init enet param shadow:");
1045 ugeth_info("Base address: 0x%08x",
1046 (u32) ugeth->p_init_enet_param_shadow);
1047 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1048 sizeof(*ugeth->p_init_enet_param_shadow));
1049
1050 size = sizeof(struct ucc_geth_thread_rx_pram);
1051 if (ugeth->ug_info->rxExtendedFiltering) {
1052 size +=
1053 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1054 if (ugeth->ug_info->largestexternallookupkeysize ==
1055 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1056 size +=
1057 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1058 if (ugeth->ug_info->largestexternallookupkeysize ==
1059 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1060 size +=
1061 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1062 }
1063
1064 dump_init_enet_entries(ugeth,
1065 &(ugeth->p_init_enet_param_shadow->
1066 txthread[0]),
1067 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1068 sizeof(struct ucc_geth_thread_tx_pram),
1069 ugeth->ug_info->riscTx, 0);
1070 dump_init_enet_entries(ugeth,
1071 &(ugeth->p_init_enet_param_shadow->
1072 rxthread[0]),
1073 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1074 ugeth->ug_info->riscRx, 1);
1075 }
1076 }
1077 #endif /* DEBUG */
1078
1079 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1080 u32 __iomem *maccfg1_register,
1081 u32 __iomem *maccfg2_register)
1082 {
1083 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1084 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1085 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1086 }
1087
1088 static int init_half_duplex_params(int alt_beb,
1089 int back_pressure_no_backoff,
1090 int no_backoff,
1091 int excess_defer,
1092 u8 alt_beb_truncation,
1093 u8 max_retransmissions,
1094 u8 collision_window,
1095 u32 __iomem *hafdup_register)
1096 {
1097 u32 value = 0;
1098
1099 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1100 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1101 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1102 return -EINVAL;
1103
1104 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1105
1106 if (alt_beb)
1107 value |= HALFDUP_ALT_BEB;
1108 if (back_pressure_no_backoff)
1109 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1110 if (no_backoff)
1111 value |= HALFDUP_NO_BACKOFF;
1112 if (excess_defer)
1113 value |= HALFDUP_EXCESSIVE_DEFER;
1114
1115 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1116
1117 value |= collision_window;
1118
1119 out_be32(hafdup_register, value);
1120 return 0;
1121 }
1122
1123 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1124 u8 non_btb_ipg,
1125 u8 min_ifg,
1126 u8 btb_ipg,
1127 u32 __iomem *ipgifg_register)
1128 {
1129 u32 value = 0;
1130
1131 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1132 IPG part 2 */
1133 if (non_btb_cs_ipg > non_btb_ipg)
1134 return -EINVAL;
1135
1136 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1137 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1138 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1139 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1140 return -EINVAL;
1141
1142 value |=
1143 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1144 IPGIFG_NBTB_CS_IPG_MASK);
1145 value |=
1146 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1147 IPGIFG_NBTB_IPG_MASK);
1148 value |=
1149 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1150 IPGIFG_MIN_IFG_MASK);
1151 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1152
1153 out_be32(ipgifg_register, value);
1154 return 0;
1155 }
1156
1157 int init_flow_control_params(u32 automatic_flow_control_mode,
1158 int rx_flow_control_enable,
1159 int tx_flow_control_enable,
1160 u16 pause_period,
1161 u16 extension_field,
1162 u32 __iomem *upsmr_register,
1163 u32 __iomem *uempr_register,
1164 u32 __iomem *maccfg1_register)
1165 {
1166 u32 value = 0;
1167
1168 /* Set UEMPR register */
1169 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1170 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1171 out_be32(uempr_register, value);
1172
1173 /* Set UPSMR register */
1174 setbits32(upsmr_register, automatic_flow_control_mode);
1175
1176 value = in_be32(maccfg1_register);
1177 if (rx_flow_control_enable)
1178 value |= MACCFG1_FLOW_RX;
1179 if (tx_flow_control_enable)
1180 value |= MACCFG1_FLOW_TX;
1181 out_be32(maccfg1_register, value);
1182
1183 return 0;
1184 }
1185
1186 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1187 int auto_zero_hardware_statistics,
1188 u32 __iomem *upsmr_register,
1189 u16 __iomem *uescr_register)
1190 {
1191 u16 uescr_value = 0;
1192
1193 /* Enable hardware statistics gathering if requested */
1194 if (enable_hardware_statistics)
1195 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1196
1197 /* Clear hardware statistics counters */
1198 uescr_value = in_be16(uescr_register);
1199 uescr_value |= UESCR_CLRCNT;
1200 /* Automatically zero hardware statistics counters on read,
1201 if requested */
1202 if (auto_zero_hardware_statistics)
1203 uescr_value |= UESCR_AUTOZ;
1204 out_be16(uescr_register, uescr_value);
1205
1206 return 0;
1207 }
1208
1209 static int init_firmware_statistics_gathering_mode(int
1210 enable_tx_firmware_statistics,
1211 int enable_rx_firmware_statistics,
1212 u32 __iomem *tx_rmon_base_ptr,
1213 u32 tx_firmware_statistics_structure_address,
1214 u32 __iomem *rx_rmon_base_ptr,
1215 u32 rx_firmware_statistics_structure_address,
1216 u16 __iomem *temoder_register,
1217 u32 __iomem *remoder_register)
1218 {
1219 /* Note: this function does not check if */
1220 /* the parameters it receives are NULL */
1221
1222 if (enable_tx_firmware_statistics) {
1223 out_be32(tx_rmon_base_ptr,
1224 tx_firmware_statistics_structure_address);
1225 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1226 }
1227
1228 if (enable_rx_firmware_statistics) {
1229 out_be32(rx_rmon_base_ptr,
1230 rx_firmware_statistics_structure_address);
1231 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int init_mac_station_addr_regs(u8 address_byte_0,
1238 u8 address_byte_1,
1239 u8 address_byte_2,
1240 u8 address_byte_3,
1241 u8 address_byte_4,
1242 u8 address_byte_5,
1243 u32 __iomem *macstnaddr1_register,
1244 u32 __iomem *macstnaddr2_register)
1245 {
1246 u32 value = 0;
1247
1248 /* Example: for a station address of 0x12345678ABCD, */
1249 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1250
1251 /* MACSTNADDR1 Register: */
1252
1253 /* 0 7 8 15 */
1254 /* station address byte 5 station address byte 4 */
1255 /* 16 23 24 31 */
1256 /* station address byte 3 station address byte 2 */
1257 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1258 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1259 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1260 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1261
1262 out_be32(macstnaddr1_register, value);
1263
1264 /* MACSTNADDR2 Register: */
1265
1266 /* 0 7 8 15 */
1267 /* station address byte 1 station address byte 0 */
1268 /* 16 23 24 31 */
1269 /* reserved reserved */
1270 value = 0;
1271 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1272 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1273
1274 out_be32(macstnaddr2_register, value);
1275
1276 return 0;
1277 }
1278
1279 static int init_check_frame_length_mode(int length_check,
1280 u32 __iomem *maccfg2_register)
1281 {
1282 u32 value = 0;
1283
1284 value = in_be32(maccfg2_register);
1285
1286 if (length_check)
1287 value |= MACCFG2_LC;
1288 else
1289 value &= ~MACCFG2_LC;
1290
1291 out_be32(maccfg2_register, value);
1292 return 0;
1293 }
1294
1295 static int init_preamble_length(u8 preamble_length,
1296 u32 __iomem *maccfg2_register)
1297 {
1298 if ((preamble_length < 3) || (preamble_length > 7))
1299 return -EINVAL;
1300
1301 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1302 preamble_length << MACCFG2_PREL_SHIFT);
1303
1304 return 0;
1305 }
1306
1307 static int init_rx_parameters(int reject_broadcast,
1308 int receive_short_frames,
1309 int promiscuous, u32 __iomem *upsmr_register)
1310 {
1311 u32 value = 0;
1312
1313 value = in_be32(upsmr_register);
1314
1315 if (reject_broadcast)
1316 value |= UCC_GETH_UPSMR_BRO;
1317 else
1318 value &= ~UCC_GETH_UPSMR_BRO;
1319
1320 if (receive_short_frames)
1321 value |= UCC_GETH_UPSMR_RSH;
1322 else
1323 value &= ~UCC_GETH_UPSMR_RSH;
1324
1325 if (promiscuous)
1326 value |= UCC_GETH_UPSMR_PRO;
1327 else
1328 value &= ~UCC_GETH_UPSMR_PRO;
1329
1330 out_be32(upsmr_register, value);
1331
1332 return 0;
1333 }
1334
1335 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1336 u16 __iomem *mrblr_register)
1337 {
1338 /* max_rx_buf_len value must be a multiple of 128 */
1339 if ((max_rx_buf_len == 0)
1340 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1341 return -EINVAL;
1342
1343 out_be16(mrblr_register, max_rx_buf_len);
1344 return 0;
1345 }
1346
1347 static int init_min_frame_len(u16 min_frame_length,
1348 u16 __iomem *minflr_register,
1349 u16 __iomem *mrblr_register)
1350 {
1351 u16 mrblr_value = 0;
1352
1353 mrblr_value = in_be16(mrblr_register);
1354 if (min_frame_length >= (mrblr_value - 4))
1355 return -EINVAL;
1356
1357 out_be16(minflr_register, min_frame_length);
1358 return 0;
1359 }
1360
1361 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1362 {
1363 struct ucc_geth_info *ug_info;
1364 struct ucc_geth __iomem *ug_regs;
1365 struct ucc_fast __iomem *uf_regs;
1366 int ret_val;
1367 u32 upsmr, maccfg2, tbiBaseAddress;
1368 u16 value;
1369
1370 ugeth_vdbg("%s: IN", __func__);
1371
1372 ug_info = ugeth->ug_info;
1373 ug_regs = ugeth->ug_regs;
1374 uf_regs = ugeth->uccf->uf_regs;
1375
1376 /* Set MACCFG2 */
1377 maccfg2 = in_be32(&ug_regs->maccfg2);
1378 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1379 if ((ugeth->max_speed == SPEED_10) ||
1380 (ugeth->max_speed == SPEED_100))
1381 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1382 else if (ugeth->max_speed == SPEED_1000)
1383 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1384 maccfg2 |= ug_info->padAndCrc;
1385 out_be32(&ug_regs->maccfg2, maccfg2);
1386
1387 /* Set UPSMR */
1388 upsmr = in_be32(&uf_regs->upsmr);
1389 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1390 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1391 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1392 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1393 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1394 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1395 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1396 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1397 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1398 upsmr |= UCC_GETH_UPSMR_RPM;
1399 switch (ugeth->max_speed) {
1400 case SPEED_10:
1401 upsmr |= UCC_GETH_UPSMR_R10M;
1402 /* FALLTHROUGH */
1403 case SPEED_100:
1404 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1405 upsmr |= UCC_GETH_UPSMR_RMM;
1406 }
1407 }
1408 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1409 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1410 upsmr |= UCC_GETH_UPSMR_TBIM;
1411 }
1412 out_be32(&uf_regs->upsmr, upsmr);
1413
1414 /* Disable autonegotiation in tbi mode, because by default it
1415 comes up in autonegotiation mode. */
1416 /* Note that this depends on proper setting in utbipar register. */
1417 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1418 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1419 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1420 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1421 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1422 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1423 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1424 value &= ~0x1000; /* Turn off autonegotiation */
1425 ugeth->phydev->bus->write(ugeth->phydev->bus,
1426 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1427 }
1428
1429 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1430
1431 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1432 if (ret_val != 0) {
1433 if (netif_msg_probe(ugeth))
1434 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1435 __func__);
1436 return ret_val;
1437 }
1438
1439 return 0;
1440 }
1441
1442 /* Called every time the controller might need to be made
1443 * aware of new link state. The PHY code conveys this
1444 * information through variables in the ugeth structure, and this
1445 * function converts those variables into the appropriate
1446 * register values, and can bring down the device if needed.
1447 */
1448
1449 static void adjust_link(struct net_device *dev)
1450 {
1451 struct ucc_geth_private *ugeth = netdev_priv(dev);
1452 struct ucc_geth __iomem *ug_regs;
1453 struct ucc_fast __iomem *uf_regs;
1454 struct phy_device *phydev = ugeth->phydev;
1455 unsigned long flags;
1456 int new_state = 0;
1457
1458 ug_regs = ugeth->ug_regs;
1459 uf_regs = ugeth->uccf->uf_regs;
1460
1461 spin_lock_irqsave(&ugeth->lock, flags);
1462
1463 if (phydev->link) {
1464 u32 tempval = in_be32(&ug_regs->maccfg2);
1465 u32 upsmr = in_be32(&uf_regs->upsmr);
1466 /* Now we make sure that we can be in full duplex mode.
1467 * If not, we operate in half-duplex mode. */
1468 if (phydev->duplex != ugeth->oldduplex) {
1469 new_state = 1;
1470 if (!(phydev->duplex))
1471 tempval &= ~(MACCFG2_FDX);
1472 else
1473 tempval |= MACCFG2_FDX;
1474 ugeth->oldduplex = phydev->duplex;
1475 }
1476
1477 if (phydev->speed != ugeth->oldspeed) {
1478 new_state = 1;
1479 switch (phydev->speed) {
1480 case SPEED_1000:
1481 tempval = ((tempval &
1482 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1483 MACCFG2_INTERFACE_MODE_BYTE);
1484 break;
1485 case SPEED_100:
1486 case SPEED_10:
1487 tempval = ((tempval &
1488 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1489 MACCFG2_INTERFACE_MODE_NIBBLE);
1490 /* if reduced mode, re-set UPSMR.R10M */
1491 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1492 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1493 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1494 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1495 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1496 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1497 if (phydev->speed == SPEED_10)
1498 upsmr |= UCC_GETH_UPSMR_R10M;
1499 else
1500 upsmr &= ~UCC_GETH_UPSMR_R10M;
1501 }
1502 break;
1503 default:
1504 if (netif_msg_link(ugeth))
1505 ugeth_warn(
1506 "%s: Ack! Speed (%d) is not 10/100/1000!",
1507 dev->name, phydev->speed);
1508 break;
1509 }
1510 ugeth->oldspeed = phydev->speed;
1511 }
1512
1513 out_be32(&ug_regs->maccfg2, tempval);
1514 out_be32(&uf_regs->upsmr, upsmr);
1515
1516 if (!ugeth->oldlink) {
1517 new_state = 1;
1518 ugeth->oldlink = 1;
1519 }
1520 } else if (ugeth->oldlink) {
1521 new_state = 1;
1522 ugeth->oldlink = 0;
1523 ugeth->oldspeed = 0;
1524 ugeth->oldduplex = -1;
1525 }
1526
1527 if (new_state && netif_msg_link(ugeth))
1528 phy_print_status(phydev);
1529
1530 spin_unlock_irqrestore(&ugeth->lock, flags);
1531 }
1532
1533 /* Configure the PHY for dev.
1534 * returns 0 if success. -1 if failure
1535 */
1536 static int init_phy(struct net_device *dev)
1537 {
1538 struct ucc_geth_private *priv = netdev_priv(dev);
1539 struct ucc_geth_info *ug_info = priv->ug_info;
1540 struct phy_device *phydev;
1541
1542 priv->oldlink = 0;
1543 priv->oldspeed = 0;
1544 priv->oldduplex = -1;
1545
1546 phydev = phy_connect(dev, ug_info->phy_bus_id, &adjust_link, 0,
1547 priv->phy_interface);
1548
1549 if (IS_ERR(phydev)) {
1550 printk("%s: Could not attach to PHY\n", dev->name);
1551 return PTR_ERR(phydev);
1552 }
1553
1554 phydev->supported &= (ADVERTISED_10baseT_Half |
1555 ADVERTISED_10baseT_Full |
1556 ADVERTISED_100baseT_Half |
1557 ADVERTISED_100baseT_Full);
1558
1559 if (priv->max_speed == SPEED_1000)
1560 phydev->supported |= ADVERTISED_1000baseT_Full;
1561
1562 phydev->advertising = phydev->supported;
1563
1564 priv->phydev = phydev;
1565
1566 return 0;
1567 }
1568
1569
1570
1571 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1572 {
1573 struct ucc_fast_private *uccf;
1574 u32 cecr_subblock;
1575 u32 temp;
1576 int i = 10;
1577
1578 uccf = ugeth->uccf;
1579
1580 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1581 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1582 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1583
1584 /* Issue host command */
1585 cecr_subblock =
1586 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1587 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1588 QE_CR_PROTOCOL_ETHERNET, 0);
1589
1590 /* Wait for command to complete */
1591 do {
1592 msleep(10);
1593 temp = in_be32(uccf->p_ucce);
1594 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1595
1596 uccf->stopped_tx = 1;
1597
1598 return 0;
1599 }
1600
1601 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1602 {
1603 struct ucc_fast_private *uccf;
1604 u32 cecr_subblock;
1605 u8 temp;
1606 int i = 10;
1607
1608 uccf = ugeth->uccf;
1609
1610 /* Clear acknowledge bit */
1611 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1612 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1613 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1614
1615 /* Keep issuing command and checking acknowledge bit until
1616 it is asserted, according to spec */
1617 do {
1618 /* Issue host command */
1619 cecr_subblock =
1620 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1621 ucc_num);
1622 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1623 QE_CR_PROTOCOL_ETHERNET, 0);
1624 msleep(10);
1625 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1626 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1627
1628 uccf->stopped_rx = 1;
1629
1630 return 0;
1631 }
1632
1633 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1634 {
1635 struct ucc_fast_private *uccf;
1636 u32 cecr_subblock;
1637
1638 uccf = ugeth->uccf;
1639
1640 cecr_subblock =
1641 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1642 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1643 uccf->stopped_tx = 0;
1644
1645 return 0;
1646 }
1647
1648 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1649 {
1650 struct ucc_fast_private *uccf;
1651 u32 cecr_subblock;
1652
1653 uccf = ugeth->uccf;
1654
1655 cecr_subblock =
1656 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1657 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1658 0);
1659 uccf->stopped_rx = 0;
1660
1661 return 0;
1662 }
1663
1664 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1665 {
1666 struct ucc_fast_private *uccf;
1667 int enabled_tx, enabled_rx;
1668
1669 uccf = ugeth->uccf;
1670
1671 /* check if the UCC number is in range. */
1672 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1673 if (netif_msg_probe(ugeth))
1674 ugeth_err("%s: ucc_num out of range.", __func__);
1675 return -EINVAL;
1676 }
1677
1678 enabled_tx = uccf->enabled_tx;
1679 enabled_rx = uccf->enabled_rx;
1680
1681 /* Get Tx and Rx going again, in case this channel was actively
1682 disabled. */
1683 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1684 ugeth_restart_tx(ugeth);
1685 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1686 ugeth_restart_rx(ugeth);
1687
1688 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1689
1690 return 0;
1691
1692 }
1693
1694 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1695 {
1696 struct ucc_fast_private *uccf;
1697
1698 uccf = ugeth->uccf;
1699
1700 /* check if the UCC number is in range. */
1701 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1702 if (netif_msg_probe(ugeth))
1703 ugeth_err("%s: ucc_num out of range.", __func__);
1704 return -EINVAL;
1705 }
1706
1707 /* Stop any transmissions */
1708 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1709 ugeth_graceful_stop_tx(ugeth);
1710
1711 /* Stop any receptions */
1712 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1713 ugeth_graceful_stop_rx(ugeth);
1714
1715 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1716
1717 return 0;
1718 }
1719
1720 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1721 {
1722 #ifdef DEBUG
1723 ucc_fast_dump_regs(ugeth->uccf);
1724 dump_regs(ugeth);
1725 dump_bds(ugeth);
1726 #endif
1727 }
1728
1729 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1730 ugeth,
1731 enum enet_addr_type
1732 enet_addr_type)
1733 {
1734 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1735 struct ucc_fast_private *uccf;
1736 enum comm_dir comm_dir;
1737 struct list_head *p_lh;
1738 u16 i, num;
1739 u32 __iomem *addr_h;
1740 u32 __iomem *addr_l;
1741 u8 *p_counter;
1742
1743 uccf = ugeth->uccf;
1744
1745 p_82xx_addr_filt =
1746 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1747 ugeth->p_rx_glbl_pram->addressfiltering;
1748
1749 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1750 addr_h = &(p_82xx_addr_filt->gaddr_h);
1751 addr_l = &(p_82xx_addr_filt->gaddr_l);
1752 p_lh = &ugeth->group_hash_q;
1753 p_counter = &(ugeth->numGroupAddrInHash);
1754 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1755 addr_h = &(p_82xx_addr_filt->iaddr_h);
1756 addr_l = &(p_82xx_addr_filt->iaddr_l);
1757 p_lh = &ugeth->ind_hash_q;
1758 p_counter = &(ugeth->numIndAddrInHash);
1759 } else
1760 return -EINVAL;
1761
1762 comm_dir = 0;
1763 if (uccf->enabled_tx)
1764 comm_dir |= COMM_DIR_TX;
1765 if (uccf->enabled_rx)
1766 comm_dir |= COMM_DIR_RX;
1767 if (comm_dir)
1768 ugeth_disable(ugeth, comm_dir);
1769
1770 /* Clear the hash table. */
1771 out_be32(addr_h, 0x00000000);
1772 out_be32(addr_l, 0x00000000);
1773
1774 if (!p_lh)
1775 return 0;
1776
1777 num = *p_counter;
1778
1779 /* Delete all remaining CQ elements */
1780 for (i = 0; i < num; i++)
1781 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1782
1783 *p_counter = 0;
1784
1785 if (comm_dir)
1786 ugeth_enable(ugeth, comm_dir);
1787
1788 return 0;
1789 }
1790
1791 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1792 u8 paddr_num)
1793 {
1794 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1795 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1796 }
1797
1798 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1799 {
1800 u16 i, j;
1801 u8 __iomem *bd;
1802
1803 if (!ugeth)
1804 return;
1805
1806 if (ugeth->uccf) {
1807 ucc_fast_free(ugeth->uccf);
1808 ugeth->uccf = NULL;
1809 }
1810
1811 if (ugeth->p_thread_data_tx) {
1812 qe_muram_free(ugeth->thread_dat_tx_offset);
1813 ugeth->p_thread_data_tx = NULL;
1814 }
1815 if (ugeth->p_thread_data_rx) {
1816 qe_muram_free(ugeth->thread_dat_rx_offset);
1817 ugeth->p_thread_data_rx = NULL;
1818 }
1819 if (ugeth->p_exf_glbl_param) {
1820 qe_muram_free(ugeth->exf_glbl_param_offset);
1821 ugeth->p_exf_glbl_param = NULL;
1822 }
1823 if (ugeth->p_rx_glbl_pram) {
1824 qe_muram_free(ugeth->rx_glbl_pram_offset);
1825 ugeth->p_rx_glbl_pram = NULL;
1826 }
1827 if (ugeth->p_tx_glbl_pram) {
1828 qe_muram_free(ugeth->tx_glbl_pram_offset);
1829 ugeth->p_tx_glbl_pram = NULL;
1830 }
1831 if (ugeth->p_send_q_mem_reg) {
1832 qe_muram_free(ugeth->send_q_mem_reg_offset);
1833 ugeth->p_send_q_mem_reg = NULL;
1834 }
1835 if (ugeth->p_scheduler) {
1836 qe_muram_free(ugeth->scheduler_offset);
1837 ugeth->p_scheduler = NULL;
1838 }
1839 if (ugeth->p_tx_fw_statistics_pram) {
1840 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1841 ugeth->p_tx_fw_statistics_pram = NULL;
1842 }
1843 if (ugeth->p_rx_fw_statistics_pram) {
1844 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1845 ugeth->p_rx_fw_statistics_pram = NULL;
1846 }
1847 if (ugeth->p_rx_irq_coalescing_tbl) {
1848 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1849 ugeth->p_rx_irq_coalescing_tbl = NULL;
1850 }
1851 if (ugeth->p_rx_bd_qs_tbl) {
1852 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1853 ugeth->p_rx_bd_qs_tbl = NULL;
1854 }
1855 if (ugeth->p_init_enet_param_shadow) {
1856 return_init_enet_entries(ugeth,
1857 &(ugeth->p_init_enet_param_shadow->
1858 rxthread[0]),
1859 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1860 ugeth->ug_info->riscRx, 1);
1861 return_init_enet_entries(ugeth,
1862 &(ugeth->p_init_enet_param_shadow->
1863 txthread[0]),
1864 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1865 ugeth->ug_info->riscTx, 0);
1866 kfree(ugeth->p_init_enet_param_shadow);
1867 ugeth->p_init_enet_param_shadow = NULL;
1868 }
1869 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1870 bd = ugeth->p_tx_bd_ring[i];
1871 if (!bd)
1872 continue;
1873 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1874 if (ugeth->tx_skbuff[i][j]) {
1875 dma_unmap_single(ugeth->dev,
1876 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1877 (in_be32((u32 __iomem *)bd) &
1878 BD_LENGTH_MASK),
1879 DMA_TO_DEVICE);
1880 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1881 ugeth->tx_skbuff[i][j] = NULL;
1882 }
1883 }
1884
1885 kfree(ugeth->tx_skbuff[i]);
1886
1887 if (ugeth->p_tx_bd_ring[i]) {
1888 if (ugeth->ug_info->uf_info.bd_mem_part ==
1889 MEM_PART_SYSTEM)
1890 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1891 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1892 MEM_PART_MURAM)
1893 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1894 ugeth->p_tx_bd_ring[i] = NULL;
1895 }
1896 }
1897 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1898 if (ugeth->p_rx_bd_ring[i]) {
1899 /* Return existing data buffers in ring */
1900 bd = ugeth->p_rx_bd_ring[i];
1901 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1902 if (ugeth->rx_skbuff[i][j]) {
1903 dma_unmap_single(ugeth->dev,
1904 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1905 ugeth->ug_info->
1906 uf_info.max_rx_buf_length +
1907 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1908 DMA_FROM_DEVICE);
1909 dev_kfree_skb_any(
1910 ugeth->rx_skbuff[i][j]);
1911 ugeth->rx_skbuff[i][j] = NULL;
1912 }
1913 bd += sizeof(struct qe_bd);
1914 }
1915
1916 kfree(ugeth->rx_skbuff[i]);
1917
1918 if (ugeth->ug_info->uf_info.bd_mem_part ==
1919 MEM_PART_SYSTEM)
1920 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1921 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1922 MEM_PART_MURAM)
1923 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1924 ugeth->p_rx_bd_ring[i] = NULL;
1925 }
1926 }
1927 while (!list_empty(&ugeth->group_hash_q))
1928 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1929 (dequeue(&ugeth->group_hash_q)));
1930 while (!list_empty(&ugeth->ind_hash_q))
1931 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1932 (dequeue(&ugeth->ind_hash_q)));
1933 if (ugeth->ug_regs) {
1934 iounmap(ugeth->ug_regs);
1935 ugeth->ug_regs = NULL;
1936 }
1937 }
1938
1939 static void ucc_geth_set_multi(struct net_device *dev)
1940 {
1941 struct ucc_geth_private *ugeth;
1942 struct dev_mc_list *dmi;
1943 struct ucc_fast __iomem *uf_regs;
1944 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1945 int i;
1946
1947 ugeth = netdev_priv(dev);
1948
1949 uf_regs = ugeth->uccf->uf_regs;
1950
1951 if (dev->flags & IFF_PROMISC) {
1952 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1953 } else {
1954 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1955
1956 p_82xx_addr_filt =
1957 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
1958 p_rx_glbl_pram->addressfiltering;
1959
1960 if (dev->flags & IFF_ALLMULTI) {
1961 /* Catch all multicast addresses, so set the
1962 * filter to all 1's.
1963 */
1964 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
1965 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
1966 } else {
1967 /* Clear filter and add the addresses in the list.
1968 */
1969 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
1970 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
1971
1972 dmi = dev->mc_list;
1973
1974 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
1975
1976 /* Only support group multicast for now.
1977 */
1978 if (!(dmi->dmi_addr[0] & 1))
1979 continue;
1980
1981 /* Ask CPM to run CRC and set bit in
1982 * filter mask.
1983 */
1984 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
1985 }
1986 }
1987 }
1988 }
1989
1990 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
1991 {
1992 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
1993 struct phy_device *phydev = ugeth->phydev;
1994
1995 ugeth_vdbg("%s: IN", __func__);
1996
1997 /* Disable the controller */
1998 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1999
2000 /* Tell the kernel the link is down */
2001 phy_stop(phydev);
2002
2003 /* Mask all interrupts */
2004 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2005
2006 /* Clear all interrupts */
2007 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2008
2009 /* Disable Rx and Tx */
2010 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2011
2012 phy_disconnect(ugeth->phydev);
2013 ugeth->phydev = NULL;
2014
2015 ucc_geth_memclean(ugeth);
2016 }
2017
2018 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2019 {
2020 struct ucc_geth_info *ug_info;
2021 struct ucc_fast_info *uf_info;
2022 int i;
2023
2024 ug_info = ugeth->ug_info;
2025 uf_info = &ug_info->uf_info;
2026
2027 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2028 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2029 if (netif_msg_probe(ugeth))
2030 ugeth_err("%s: Bad memory partition value.",
2031 __func__);
2032 return -EINVAL;
2033 }
2034
2035 /* Rx BD lengths */
2036 for (i = 0; i < ug_info->numQueuesRx; i++) {
2037 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2038 (ug_info->bdRingLenRx[i] %
2039 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2040 if (netif_msg_probe(ugeth))
2041 ugeth_err
2042 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2043 __func__);
2044 return -EINVAL;
2045 }
2046 }
2047
2048 /* Tx BD lengths */
2049 for (i = 0; i < ug_info->numQueuesTx; i++) {
2050 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2051 if (netif_msg_probe(ugeth))
2052 ugeth_err
2053 ("%s: Tx BD ring length must be no smaller than 2.",
2054 __func__);
2055 return -EINVAL;
2056 }
2057 }
2058
2059 /* mrblr */
2060 if ((uf_info->max_rx_buf_length == 0) ||
2061 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2062 if (netif_msg_probe(ugeth))
2063 ugeth_err
2064 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2065 __func__);
2066 return -EINVAL;
2067 }
2068
2069 /* num Tx queues */
2070 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2071 if (netif_msg_probe(ugeth))
2072 ugeth_err("%s: number of tx queues too large.", __func__);
2073 return -EINVAL;
2074 }
2075
2076 /* num Rx queues */
2077 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2078 if (netif_msg_probe(ugeth))
2079 ugeth_err("%s: number of rx queues too large.", __func__);
2080 return -EINVAL;
2081 }
2082
2083 /* l2qt */
2084 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2085 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2086 if (netif_msg_probe(ugeth))
2087 ugeth_err
2088 ("%s: VLAN priority table entry must not be"
2089 " larger than number of Rx queues.",
2090 __func__);
2091 return -EINVAL;
2092 }
2093 }
2094
2095 /* l3qt */
2096 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2097 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2098 if (netif_msg_probe(ugeth))
2099 ugeth_err
2100 ("%s: IP priority table entry must not be"
2101 " larger than number of Rx queues.",
2102 __func__);
2103 return -EINVAL;
2104 }
2105 }
2106
2107 if (ug_info->cam && !ug_info->ecamptr) {
2108 if (netif_msg_probe(ugeth))
2109 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2110 __func__);
2111 return -EINVAL;
2112 }
2113
2114 if ((ug_info->numStationAddresses !=
2115 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2116 && ug_info->rxExtendedFiltering) {
2117 if (netif_msg_probe(ugeth))
2118 ugeth_err("%s: Number of station addresses greater than 1 "
2119 "not allowed in extended parsing mode.",
2120 __func__);
2121 return -EINVAL;
2122 }
2123
2124 /* Generate uccm_mask for receive */
2125 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2126 for (i = 0; i < ug_info->numQueuesRx; i++)
2127 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2128
2129 for (i = 0; i < ug_info->numQueuesTx; i++)
2130 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2131 /* Initialize the general fast UCC block. */
2132 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2133 if (netif_msg_probe(ugeth))
2134 ugeth_err("%s: Failed to init uccf.", __func__);
2135 return -ENOMEM;
2136 }
2137
2138 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2139 if (!ugeth->ug_regs) {
2140 if (netif_msg_probe(ugeth))
2141 ugeth_err("%s: Failed to ioremap regs.", __func__);
2142 return -ENOMEM;
2143 }
2144
2145 return 0;
2146 }
2147
2148 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2149 {
2150 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2151 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2152 struct ucc_fast_private *uccf;
2153 struct ucc_geth_info *ug_info;
2154 struct ucc_fast_info *uf_info;
2155 struct ucc_fast __iomem *uf_regs;
2156 struct ucc_geth __iomem *ug_regs;
2157 int ret_val = -EINVAL;
2158 u32 remoder = UCC_GETH_REMODER_INIT;
2159 u32 init_enet_pram_offset, cecr_subblock, command;
2160 u32 ifstat, i, j, size, l2qt, l3qt, length;
2161 u16 temoder = UCC_GETH_TEMODER_INIT;
2162 u16 test;
2163 u8 function_code = 0;
2164 u8 __iomem *bd;
2165 u8 __iomem *endOfRing;
2166 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2167
2168 ugeth_vdbg("%s: IN", __func__);
2169 uccf = ugeth->uccf;
2170 ug_info = ugeth->ug_info;
2171 uf_info = &ug_info->uf_info;
2172 uf_regs = uccf->uf_regs;
2173 ug_regs = ugeth->ug_regs;
2174
2175 switch (ug_info->numThreadsRx) {
2176 case UCC_GETH_NUM_OF_THREADS_1:
2177 numThreadsRxNumerical = 1;
2178 break;
2179 case UCC_GETH_NUM_OF_THREADS_2:
2180 numThreadsRxNumerical = 2;
2181 break;
2182 case UCC_GETH_NUM_OF_THREADS_4:
2183 numThreadsRxNumerical = 4;
2184 break;
2185 case UCC_GETH_NUM_OF_THREADS_6:
2186 numThreadsRxNumerical = 6;
2187 break;
2188 case UCC_GETH_NUM_OF_THREADS_8:
2189 numThreadsRxNumerical = 8;
2190 break;
2191 default:
2192 if (netif_msg_ifup(ugeth))
2193 ugeth_err("%s: Bad number of Rx threads value.",
2194 __func__);
2195 return -EINVAL;
2196 break;
2197 }
2198
2199 switch (ug_info->numThreadsTx) {
2200 case UCC_GETH_NUM_OF_THREADS_1:
2201 numThreadsTxNumerical = 1;
2202 break;
2203 case UCC_GETH_NUM_OF_THREADS_2:
2204 numThreadsTxNumerical = 2;
2205 break;
2206 case UCC_GETH_NUM_OF_THREADS_4:
2207 numThreadsTxNumerical = 4;
2208 break;
2209 case UCC_GETH_NUM_OF_THREADS_6:
2210 numThreadsTxNumerical = 6;
2211 break;
2212 case UCC_GETH_NUM_OF_THREADS_8:
2213 numThreadsTxNumerical = 8;
2214 break;
2215 default:
2216 if (netif_msg_ifup(ugeth))
2217 ugeth_err("%s: Bad number of Tx threads value.",
2218 __func__);
2219 return -EINVAL;
2220 break;
2221 }
2222
2223 /* Calculate rx_extended_features */
2224 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2225 ug_info->ipAddressAlignment ||
2226 (ug_info->numStationAddresses !=
2227 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2228
2229 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2230 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2231 || (ug_info->vlanOperationNonTagged !=
2232 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2233
2234 init_default_reg_vals(&uf_regs->upsmr,
2235 &ug_regs->maccfg1, &ug_regs->maccfg2);
2236
2237 /* Set UPSMR */
2238 /* For more details see the hardware spec. */
2239 init_rx_parameters(ug_info->bro,
2240 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2241
2242 /* We're going to ignore other registers for now, */
2243 /* except as needed to get up and running */
2244
2245 /* Set MACCFG1 */
2246 /* For more details see the hardware spec. */
2247 init_flow_control_params(ug_info->aufc,
2248 ug_info->receiveFlowControl,
2249 ug_info->transmitFlowControl,
2250 ug_info->pausePeriod,
2251 ug_info->extensionField,
2252 &uf_regs->upsmr,
2253 &ug_regs->uempr, &ug_regs->maccfg1);
2254
2255 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2256
2257 /* Set IPGIFG */
2258 /* For more details see the hardware spec. */
2259 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2260 ug_info->nonBackToBackIfgPart2,
2261 ug_info->
2262 miminumInterFrameGapEnforcement,
2263 ug_info->backToBackInterFrameGap,
2264 &ug_regs->ipgifg);
2265 if (ret_val != 0) {
2266 if (netif_msg_ifup(ugeth))
2267 ugeth_err("%s: IPGIFG initialization parameter too large.",
2268 __func__);
2269 return ret_val;
2270 }
2271
2272 /* Set HAFDUP */
2273 /* For more details see the hardware spec. */
2274 ret_val = init_half_duplex_params(ug_info->altBeb,
2275 ug_info->backPressureNoBackoff,
2276 ug_info->noBackoff,
2277 ug_info->excessDefer,
2278 ug_info->altBebTruncation,
2279 ug_info->maxRetransmission,
2280 ug_info->collisionWindow,
2281 &ug_regs->hafdup);
2282 if (ret_val != 0) {
2283 if (netif_msg_ifup(ugeth))
2284 ugeth_err("%s: Half Duplex initialization parameter too large.",
2285 __func__);
2286 return ret_val;
2287 }
2288
2289 /* Set IFSTAT */
2290 /* For more details see the hardware spec. */
2291 /* Read only - resets upon read */
2292 ifstat = in_be32(&ug_regs->ifstat);
2293
2294 /* Clear UEMPR */
2295 /* For more details see the hardware spec. */
2296 out_be32(&ug_regs->uempr, 0);
2297
2298 /* Set UESCR */
2299 /* For more details see the hardware spec. */
2300 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2301 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2302 0, &uf_regs->upsmr, &ug_regs->uescr);
2303
2304 /* Allocate Tx bds */
2305 for (j = 0; j < ug_info->numQueuesTx; j++) {
2306 /* Allocate in multiple of
2307 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2308 according to spec */
2309 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2310 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2311 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2312 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2313 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2314 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2315 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2316 u32 align = 4;
2317 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2318 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2319 ugeth->tx_bd_ring_offset[j] =
2320 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2321
2322 if (ugeth->tx_bd_ring_offset[j] != 0)
2323 ugeth->p_tx_bd_ring[j] =
2324 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2325 align) & ~(align - 1));
2326 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2327 ugeth->tx_bd_ring_offset[j] =
2328 qe_muram_alloc(length,
2329 UCC_GETH_TX_BD_RING_ALIGNMENT);
2330 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2331 ugeth->p_tx_bd_ring[j] =
2332 (u8 __iomem *) qe_muram_addr(ugeth->
2333 tx_bd_ring_offset[j]);
2334 }
2335 if (!ugeth->p_tx_bd_ring[j]) {
2336 if (netif_msg_ifup(ugeth))
2337 ugeth_err
2338 ("%s: Can not allocate memory for Tx bd rings.",
2339 __func__);
2340 return -ENOMEM;
2341 }
2342 /* Zero unused end of bd ring, according to spec */
2343 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2344 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2345 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2346 }
2347
2348 /* Allocate Rx bds */
2349 for (j = 0; j < ug_info->numQueuesRx; j++) {
2350 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2351 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2352 u32 align = 4;
2353 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2354 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2355 ugeth->rx_bd_ring_offset[j] =
2356 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2357 if (ugeth->rx_bd_ring_offset[j] != 0)
2358 ugeth->p_rx_bd_ring[j] =
2359 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2360 align) & ~(align - 1));
2361 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2362 ugeth->rx_bd_ring_offset[j] =
2363 qe_muram_alloc(length,
2364 UCC_GETH_RX_BD_RING_ALIGNMENT);
2365 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2366 ugeth->p_rx_bd_ring[j] =
2367 (u8 __iomem *) qe_muram_addr(ugeth->
2368 rx_bd_ring_offset[j]);
2369 }
2370 if (!ugeth->p_rx_bd_ring[j]) {
2371 if (netif_msg_ifup(ugeth))
2372 ugeth_err
2373 ("%s: Can not allocate memory for Rx bd rings.",
2374 __func__);
2375 return -ENOMEM;
2376 }
2377 }
2378
2379 /* Init Tx bds */
2380 for (j = 0; j < ug_info->numQueuesTx; j++) {
2381 /* Setup the skbuff rings */
2382 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2383 ugeth->ug_info->bdRingLenTx[j],
2384 GFP_KERNEL);
2385
2386 if (ugeth->tx_skbuff[j] == NULL) {
2387 if (netif_msg_ifup(ugeth))
2388 ugeth_err("%s: Could not allocate tx_skbuff",
2389 __func__);
2390 return -ENOMEM;
2391 }
2392
2393 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2394 ugeth->tx_skbuff[j][i] = NULL;
2395
2396 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2397 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2398 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2399 /* clear bd buffer */
2400 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2401 /* set bd status and length */
2402 out_be32((u32 __iomem *)bd, 0);
2403 bd += sizeof(struct qe_bd);
2404 }
2405 bd -= sizeof(struct qe_bd);
2406 /* set bd status and length */
2407 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2408 }
2409
2410 /* Init Rx bds */
2411 for (j = 0; j < ug_info->numQueuesRx; j++) {
2412 /* Setup the skbuff rings */
2413 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2414 ugeth->ug_info->bdRingLenRx[j],
2415 GFP_KERNEL);
2416
2417 if (ugeth->rx_skbuff[j] == NULL) {
2418 if (netif_msg_ifup(ugeth))
2419 ugeth_err("%s: Could not allocate rx_skbuff",
2420 __func__);
2421 return -ENOMEM;
2422 }
2423
2424 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2425 ugeth->rx_skbuff[j][i] = NULL;
2426
2427 ugeth->skb_currx[j] = 0;
2428 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2429 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2430 /* set bd status and length */
2431 out_be32((u32 __iomem *)bd, R_I);
2432 /* clear bd buffer */
2433 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2434 bd += sizeof(struct qe_bd);
2435 }
2436 bd -= sizeof(struct qe_bd);
2437 /* set bd status and length */
2438 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2439 }
2440
2441 /*
2442 * Global PRAM
2443 */
2444 /* Tx global PRAM */
2445 /* Allocate global tx parameter RAM page */
2446 ugeth->tx_glbl_pram_offset =
2447 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2448 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2449 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2450 if (netif_msg_ifup(ugeth))
2451 ugeth_err
2452 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2453 __func__);
2454 return -ENOMEM;
2455 }
2456 ugeth->p_tx_glbl_pram =
2457 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2458 tx_glbl_pram_offset);
2459 /* Zero out p_tx_glbl_pram */
2460 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2461
2462 /* Fill global PRAM */
2463
2464 /* TQPTR */
2465 /* Size varies with number of Tx threads */
2466 ugeth->thread_dat_tx_offset =
2467 qe_muram_alloc(numThreadsTxNumerical *
2468 sizeof(struct ucc_geth_thread_data_tx) +
2469 32 * (numThreadsTxNumerical == 1),
2470 UCC_GETH_THREAD_DATA_ALIGNMENT);
2471 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2472 if (netif_msg_ifup(ugeth))
2473 ugeth_err
2474 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2475 __func__);
2476 return -ENOMEM;
2477 }
2478
2479 ugeth->p_thread_data_tx =
2480 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2481 thread_dat_tx_offset);
2482 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2483
2484 /* vtagtable */
2485 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2486 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2487 ug_info->vtagtable[i]);
2488
2489 /* iphoffset */
2490 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2491 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2492 ug_info->iphoffset[i]);
2493
2494 /* SQPTR */
2495 /* Size varies with number of Tx queues */
2496 ugeth->send_q_mem_reg_offset =
2497 qe_muram_alloc(ug_info->numQueuesTx *
2498 sizeof(struct ucc_geth_send_queue_qd),
2499 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2500 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2501 if (netif_msg_ifup(ugeth))
2502 ugeth_err
2503 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2504 __func__);
2505 return -ENOMEM;
2506 }
2507
2508 ugeth->p_send_q_mem_reg =
2509 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2510 send_q_mem_reg_offset);
2511 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2512
2513 /* Setup the table */
2514 /* Assume BD rings are already established */
2515 for (i = 0; i < ug_info->numQueuesTx; i++) {
2516 endOfRing =
2517 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2518 1) * sizeof(struct qe_bd);
2519 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2520 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2521 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2522 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2523 last_bd_completed_address,
2524 (u32) virt_to_phys(endOfRing));
2525 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2526 MEM_PART_MURAM) {
2527 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2528 (u32) immrbar_virt_to_phys(ugeth->
2529 p_tx_bd_ring[i]));
2530 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2531 last_bd_completed_address,
2532 (u32) immrbar_virt_to_phys(endOfRing));
2533 }
2534 }
2535
2536 /* schedulerbasepointer */
2537
2538 if (ug_info->numQueuesTx > 1) {
2539 /* scheduler exists only if more than 1 tx queue */
2540 ugeth->scheduler_offset =
2541 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2542 UCC_GETH_SCHEDULER_ALIGNMENT);
2543 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2544 if (netif_msg_ifup(ugeth))
2545 ugeth_err
2546 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2547 __func__);
2548 return -ENOMEM;
2549 }
2550
2551 ugeth->p_scheduler =
2552 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2553 scheduler_offset);
2554 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2555 ugeth->scheduler_offset);
2556 /* Zero out p_scheduler */
2557 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2558
2559 /* Set values in scheduler */
2560 out_be32(&ugeth->p_scheduler->mblinterval,
2561 ug_info->mblinterval);
2562 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2563 ug_info->nortsrbytetime);
2564 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2565 out_8(&ugeth->p_scheduler->strictpriorityq,
2566 ug_info->strictpriorityq);
2567 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2568 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2569 for (i = 0; i < NUM_TX_QUEUES; i++)
2570 out_8(&ugeth->p_scheduler->weightfactor[i],
2571 ug_info->weightfactor[i]);
2572
2573 /* Set pointers to cpucount registers in scheduler */
2574 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2575 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2576 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2577 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2578 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2579 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2580 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2581 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2582 }
2583
2584 /* schedulerbasepointer */
2585 /* TxRMON_PTR (statistics) */
2586 if (ug_info->
2587 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2588 ugeth->tx_fw_statistics_pram_offset =
2589 qe_muram_alloc(sizeof
2590 (struct ucc_geth_tx_firmware_statistics_pram),
2591 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2592 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2593 if (netif_msg_ifup(ugeth))
2594 ugeth_err
2595 ("%s: Can not allocate DPRAM memory for"
2596 " p_tx_fw_statistics_pram.",
2597 __func__);
2598 return -ENOMEM;
2599 }
2600 ugeth->p_tx_fw_statistics_pram =
2601 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2602 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2603 /* Zero out p_tx_fw_statistics_pram */
2604 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2605 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2606 }
2607
2608 /* temoder */
2609 /* Already has speed set */
2610
2611 if (ug_info->numQueuesTx > 1)
2612 temoder |= TEMODER_SCHEDULER_ENABLE;
2613 if (ug_info->ipCheckSumGenerate)
2614 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2615 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2616 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2617
2618 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2619
2620 /* Function code register value to be used later */
2621 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2622 /* Required for QE */
2623
2624 /* function code register */
2625 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2626
2627 /* Rx global PRAM */
2628 /* Allocate global rx parameter RAM page */
2629 ugeth->rx_glbl_pram_offset =
2630 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2631 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2632 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2633 if (netif_msg_ifup(ugeth))
2634 ugeth_err
2635 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2636 __func__);
2637 return -ENOMEM;
2638 }
2639 ugeth->p_rx_glbl_pram =
2640 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2641 rx_glbl_pram_offset);
2642 /* Zero out p_rx_glbl_pram */
2643 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2644
2645 /* Fill global PRAM */
2646
2647 /* RQPTR */
2648 /* Size varies with number of Rx threads */
2649 ugeth->thread_dat_rx_offset =
2650 qe_muram_alloc(numThreadsRxNumerical *
2651 sizeof(struct ucc_geth_thread_data_rx),
2652 UCC_GETH_THREAD_DATA_ALIGNMENT);
2653 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2654 if (netif_msg_ifup(ugeth))
2655 ugeth_err
2656 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2657 __func__);
2658 return -ENOMEM;
2659 }
2660
2661 ugeth->p_thread_data_rx =
2662 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2663 thread_dat_rx_offset);
2664 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2665
2666 /* typeorlen */
2667 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2668
2669 /* rxrmonbaseptr (statistics) */
2670 if (ug_info->
2671 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2672 ugeth->rx_fw_statistics_pram_offset =
2673 qe_muram_alloc(sizeof
2674 (struct ucc_geth_rx_firmware_statistics_pram),
2675 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2676 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2677 if (netif_msg_ifup(ugeth))
2678 ugeth_err
2679 ("%s: Can not allocate DPRAM memory for"
2680 " p_rx_fw_statistics_pram.", __func__);
2681 return -ENOMEM;
2682 }
2683 ugeth->p_rx_fw_statistics_pram =
2684 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2685 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2686 /* Zero out p_rx_fw_statistics_pram */
2687 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2688 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2689 }
2690
2691 /* intCoalescingPtr */
2692
2693 /* Size varies with number of Rx queues */
2694 ugeth->rx_irq_coalescing_tbl_offset =
2695 qe_muram_alloc(ug_info->numQueuesRx *
2696 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2697 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2698 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2699 if (netif_msg_ifup(ugeth))
2700 ugeth_err
2701 ("%s: Can not allocate DPRAM memory for"
2702 " p_rx_irq_coalescing_tbl.", __func__);
2703 return -ENOMEM;
2704 }
2705
2706 ugeth->p_rx_irq_coalescing_tbl =
2707 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2708 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2709 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2710 ugeth->rx_irq_coalescing_tbl_offset);
2711
2712 /* Fill interrupt coalescing table */
2713 for (i = 0; i < ug_info->numQueuesRx; i++) {
2714 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2715 interruptcoalescingmaxvalue,
2716 ug_info->interruptcoalescingmaxvalue[i]);
2717 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2718 interruptcoalescingcounter,
2719 ug_info->interruptcoalescingmaxvalue[i]);
2720 }
2721
2722 /* MRBLR */
2723 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2724 &ugeth->p_rx_glbl_pram->mrblr);
2725 /* MFLR */
2726 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2727 /* MINFLR */
2728 init_min_frame_len(ug_info->minFrameLength,
2729 &ugeth->p_rx_glbl_pram->minflr,
2730 &ugeth->p_rx_glbl_pram->mrblr);
2731 /* MAXD1 */
2732 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2733 /* MAXD2 */
2734 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2735
2736 /* l2qt */
2737 l2qt = 0;
2738 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2739 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2740 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2741
2742 /* l3qt */
2743 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2744 l3qt = 0;
2745 for (i = 0; i < 8; i++)
2746 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2747 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2748 }
2749
2750 /* vlantype */
2751 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2752
2753 /* vlantci */
2754 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2755
2756 /* ecamptr */
2757 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2758
2759 /* RBDQPTR */
2760 /* Size varies with number of Rx queues */
2761 ugeth->rx_bd_qs_tbl_offset =
2762 qe_muram_alloc(ug_info->numQueuesRx *
2763 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2764 sizeof(struct ucc_geth_rx_prefetched_bds)),
2765 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2766 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2767 if (netif_msg_ifup(ugeth))
2768 ugeth_err
2769 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2770 __func__);
2771 return -ENOMEM;
2772 }
2773
2774 ugeth->p_rx_bd_qs_tbl =
2775 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2776 rx_bd_qs_tbl_offset);
2777 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2778 /* Zero out p_rx_bd_qs_tbl */
2779 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2780 0,
2781 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2782 sizeof(struct ucc_geth_rx_prefetched_bds)));
2783
2784 /* Setup the table */
2785 /* Assume BD rings are already established */
2786 for (i = 0; i < ug_info->numQueuesRx; i++) {
2787 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2788 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2789 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2790 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2791 MEM_PART_MURAM) {
2792 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2793 (u32) immrbar_virt_to_phys(ugeth->
2794 p_rx_bd_ring[i]));
2795 }
2796 /* rest of fields handled by QE */
2797 }
2798
2799 /* remoder */
2800 /* Already has speed set */
2801
2802 if (ugeth->rx_extended_features)
2803 remoder |= REMODER_RX_EXTENDED_FEATURES;
2804 if (ug_info->rxExtendedFiltering)
2805 remoder |= REMODER_RX_EXTENDED_FILTERING;
2806 if (ug_info->dynamicMaxFrameLength)
2807 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2808 if (ug_info->dynamicMinFrameLength)
2809 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2810 remoder |=
2811 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2812 remoder |=
2813 ug_info->
2814 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2815 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2816 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2817 if (ug_info->ipCheckSumCheck)
2818 remoder |= REMODER_IP_CHECKSUM_CHECK;
2819 if (ug_info->ipAddressAlignment)
2820 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2821 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2822
2823 /* Note that this function must be called */
2824 /* ONLY AFTER p_tx_fw_statistics_pram */
2825 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2826 init_firmware_statistics_gathering_mode((ug_info->
2827 statisticsMode &
2828 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2829 (ug_info->statisticsMode &
2830 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2831 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2832 ugeth->tx_fw_statistics_pram_offset,
2833 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2834 ugeth->rx_fw_statistics_pram_offset,
2835 &ugeth->p_tx_glbl_pram->temoder,
2836 &ugeth->p_rx_glbl_pram->remoder);
2837
2838 /* function code register */
2839 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2840
2841 /* initialize extended filtering */
2842 if (ug_info->rxExtendedFiltering) {
2843 if (!ug_info->extendedFilteringChainPointer) {
2844 if (netif_msg_ifup(ugeth))
2845 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2846 __func__);
2847 return -EINVAL;
2848 }
2849
2850 /* Allocate memory for extended filtering Mode Global
2851 Parameters */
2852 ugeth->exf_glbl_param_offset =
2853 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2854 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2855 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2856 if (netif_msg_ifup(ugeth))
2857 ugeth_err
2858 ("%s: Can not allocate DPRAM memory for"
2859 " p_exf_glbl_param.", __func__);
2860 return -ENOMEM;
2861 }
2862
2863 ugeth->p_exf_glbl_param =
2864 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2865 exf_glbl_param_offset);
2866 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2867 ugeth->exf_glbl_param_offset);
2868 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2869 (u32) ug_info->extendedFilteringChainPointer);
2870
2871 } else { /* initialize 82xx style address filtering */
2872
2873 /* Init individual address recognition registers to disabled */
2874
2875 for (j = 0; j < NUM_OF_PADDRS; j++)
2876 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2877
2878 p_82xx_addr_filt =
2879 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2880 p_rx_glbl_pram->addressfiltering;
2881
2882 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2883 ENET_ADDR_TYPE_GROUP);
2884 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2885 ENET_ADDR_TYPE_INDIVIDUAL);
2886 }
2887
2888 /*
2889 * Initialize UCC at QE level
2890 */
2891
2892 command = QE_INIT_TX_RX;
2893
2894 /* Allocate shadow InitEnet command parameter structure.
2895 * This is needed because after the InitEnet command is executed,
2896 * the structure in DPRAM is released, because DPRAM is a premium
2897 * resource.
2898 * This shadow structure keeps a copy of what was done so that the
2899 * allocated resources can be released when the channel is freed.
2900 */
2901 if (!(ugeth->p_init_enet_param_shadow =
2902 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2903 if (netif_msg_ifup(ugeth))
2904 ugeth_err
2905 ("%s: Can not allocate memory for"
2906 " p_UccInitEnetParamShadows.", __func__);
2907 return -ENOMEM;
2908 }
2909 /* Zero out *p_init_enet_param_shadow */
2910 memset((char *)ugeth->p_init_enet_param_shadow,
2911 0, sizeof(struct ucc_geth_init_pram));
2912
2913 /* Fill shadow InitEnet command parameter structure */
2914
2915 ugeth->p_init_enet_param_shadow->resinit1 =
2916 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2917 ugeth->p_init_enet_param_shadow->resinit2 =
2918 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2919 ugeth->p_init_enet_param_shadow->resinit3 =
2920 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2921 ugeth->p_init_enet_param_shadow->resinit4 =
2922 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2923 ugeth->p_init_enet_param_shadow->resinit5 =
2924 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2925 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2926 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2927 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2928 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2929
2930 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2931 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2932 if ((ug_info->largestexternallookupkeysize !=
2933 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2934 && (ug_info->largestexternallookupkeysize !=
2935 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2936 && (ug_info->largestexternallookupkeysize !=
2937 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2938 if (netif_msg_ifup(ugeth))
2939 ugeth_err("%s: Invalid largest External Lookup Key Size.",
2940 __func__);
2941 return -EINVAL;
2942 }
2943 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2944 ug_info->largestexternallookupkeysize;
2945 size = sizeof(struct ucc_geth_thread_rx_pram);
2946 if (ug_info->rxExtendedFiltering) {
2947 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2948 if (ug_info->largestexternallookupkeysize ==
2949 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2950 size +=
2951 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2952 if (ug_info->largestexternallookupkeysize ==
2953 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2954 size +=
2955 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2956 }
2957
2958 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2959 p_init_enet_param_shadow->rxthread[0]),
2960 (u8) (numThreadsRxNumerical + 1)
2961 /* Rx needs one extra for terminator */
2962 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2963 ug_info->riscRx, 1)) != 0) {
2964 if (netif_msg_ifup(ugeth))
2965 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2966 __func__);
2967 return ret_val;
2968 }
2969
2970 ugeth->p_init_enet_param_shadow->txglobal =
2971 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
2972 if ((ret_val =
2973 fill_init_enet_entries(ugeth,
2974 &(ugeth->p_init_enet_param_shadow->
2975 txthread[0]), numThreadsTxNumerical,
2976 sizeof(struct ucc_geth_thread_tx_pram),
2977 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
2978 ug_info->riscTx, 0)) != 0) {
2979 if (netif_msg_ifup(ugeth))
2980 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2981 __func__);
2982 return ret_val;
2983 }
2984
2985 /* Load Rx bds with buffers */
2986 for (i = 0; i < ug_info->numQueuesRx; i++) {
2987 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
2988 if (netif_msg_ifup(ugeth))
2989 ugeth_err("%s: Can not fill Rx bds with buffers.",
2990 __func__);
2991 return ret_val;
2992 }
2993 }
2994
2995 /* Allocate InitEnet command parameter structure */
2996 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
2997 if (IS_ERR_VALUE(init_enet_pram_offset)) {
2998 if (netif_msg_ifup(ugeth))
2999 ugeth_err
3000 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3001 __func__);
3002 return -ENOMEM;
3003 }
3004 p_init_enet_pram =
3005 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3006
3007 /* Copy shadow InitEnet command parameter structure into PRAM */
3008 out_8(&p_init_enet_pram->resinit1,
3009 ugeth->p_init_enet_param_shadow->resinit1);
3010 out_8(&p_init_enet_pram->resinit2,
3011 ugeth->p_init_enet_param_shadow->resinit2);
3012 out_8(&p_init_enet_pram->resinit3,
3013 ugeth->p_init_enet_param_shadow->resinit3);
3014 out_8(&p_init_enet_pram->resinit4,
3015 ugeth->p_init_enet_param_shadow->resinit4);
3016 out_be16(&p_init_enet_pram->resinit5,
3017 ugeth->p_init_enet_param_shadow->resinit5);
3018 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3019 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3020 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3021 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3022 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3023 out_be32(&p_init_enet_pram->rxthread[i],
3024 ugeth->p_init_enet_param_shadow->rxthread[i]);
3025 out_be32(&p_init_enet_pram->txglobal,
3026 ugeth->p_init_enet_param_shadow->txglobal);
3027 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3028 out_be32(&p_init_enet_pram->txthread[i],
3029 ugeth->p_init_enet_param_shadow->txthread[i]);
3030
3031 /* Issue QE command */
3032 cecr_subblock =
3033 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3034 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3035 init_enet_pram_offset);
3036
3037 /* Free InitEnet command parameter */
3038 qe_muram_free(init_enet_pram_offset);
3039
3040 return 0;
3041 }
3042
3043 /* This is called by the kernel when a frame is ready for transmission. */
3044 /* It is pointed to by the dev->hard_start_xmit function pointer */
3045 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3046 {
3047 struct ucc_geth_private *ugeth = netdev_priv(dev);
3048 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3049 struct ucc_fast_private *uccf;
3050 #endif
3051 u8 __iomem *bd; /* BD pointer */
3052 u32 bd_status;
3053 u8 txQ = 0;
3054
3055 ugeth_vdbg("%s: IN", __func__);
3056
3057 spin_lock_irq(&ugeth->lock);
3058
3059 dev->stats.tx_bytes += skb->len;
3060
3061 /* Start from the next BD that should be filled */
3062 bd = ugeth->txBd[txQ];
3063 bd_status = in_be32((u32 __iomem *)bd);
3064 /* Save the skb pointer so we can free it later */
3065 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3066
3067 /* Update the current skb pointer (wrapping if this was the last) */
3068 ugeth->skb_curtx[txQ] =
3069 (ugeth->skb_curtx[txQ] +
3070 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3071
3072 /* set up the buffer descriptor */
3073 out_be32(&((struct qe_bd __iomem *)bd)->buf,
3074 dma_map_single(ugeth->dev, skb->data,
3075 skb->len, DMA_TO_DEVICE));
3076
3077 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3078
3079 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3080
3081 /* set bd status and length */
3082 out_be32((u32 __iomem *)bd, bd_status);
3083
3084 dev->trans_start = jiffies;
3085
3086 /* Move to next BD in the ring */
3087 if (!(bd_status & T_W))
3088 bd += sizeof(struct qe_bd);
3089 else
3090 bd = ugeth->p_tx_bd_ring[txQ];
3091
3092 /* If the next BD still needs to be cleaned up, then the bds
3093 are full. We need to tell the kernel to stop sending us stuff. */
3094 if (bd == ugeth->confBd[txQ]) {
3095 if (!netif_queue_stopped(dev))
3096 netif_stop_queue(dev);
3097 }
3098
3099 ugeth->txBd[txQ] = bd;
3100
3101 if (ugeth->p_scheduler) {
3102 ugeth->cpucount[txQ]++;
3103 /* Indicate to QE that there are more Tx bds ready for
3104 transmission */
3105 /* This is done by writing a running counter of the bd
3106 count to the scheduler PRAM. */
3107 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3108 }
3109
3110 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3111 uccf = ugeth->uccf;
3112 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3113 #endif
3114 spin_unlock_irq(&ugeth->lock);
3115
3116 return 0;
3117 }
3118
3119 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3120 {
3121 struct sk_buff *skb;
3122 u8 __iomem *bd;
3123 u16 length, howmany = 0;
3124 u32 bd_status;
3125 u8 *bdBuffer;
3126 struct net_device *dev;
3127
3128 ugeth_vdbg("%s: IN", __func__);
3129
3130 dev = ugeth->ndev;
3131
3132 /* collect received buffers */
3133 bd = ugeth->rxBd[rxQ];
3134
3135 bd_status = in_be32((u32 __iomem *)bd);
3136
3137 /* while there are received buffers and BD is full (~R_E) */
3138 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3139 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3140 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3141 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3142
3143 /* determine whether buffer is first, last, first and last
3144 (single buffer frame) or middle (not first and not last) */
3145 if (!skb ||
3146 (!(bd_status & (R_F | R_L))) ||
3147 (bd_status & R_ERRORS_FATAL)) {
3148 if (netif_msg_rx_err(ugeth))
3149 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3150 __func__, __LINE__, (u32) skb);
3151 if (skb)
3152 dev_kfree_skb_any(skb);
3153
3154 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3155 dev->stats.rx_dropped++;
3156 } else {
3157 dev->stats.rx_packets++;
3158 howmany++;
3159
3160 /* Prep the skb for the packet */
3161 skb_put(skb, length);
3162
3163 /* Tell the skb what kind of packet this is */
3164 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3165
3166 dev->stats.rx_bytes += length;
3167 /* Send the packet up the stack */
3168 netif_receive_skb(skb);
3169 }
3170
3171 skb = get_new_skb(ugeth, bd);
3172 if (!skb) {
3173 if (netif_msg_rx_err(ugeth))
3174 ugeth_warn("%s: No Rx Data Buffer", __func__);
3175 dev->stats.rx_dropped++;
3176 break;
3177 }
3178
3179 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3180
3181 /* update to point at the next skb */
3182 ugeth->skb_currx[rxQ] =
3183 (ugeth->skb_currx[rxQ] +
3184 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3185
3186 if (bd_status & R_W)
3187 bd = ugeth->p_rx_bd_ring[rxQ];
3188 else
3189 bd += sizeof(struct qe_bd);
3190
3191 bd_status = in_be32((u32 __iomem *)bd);
3192 }
3193
3194 ugeth->rxBd[rxQ] = bd;
3195 return howmany;
3196 }
3197
3198 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3199 {
3200 /* Start from the next BD that should be filled */
3201 struct ucc_geth_private *ugeth = netdev_priv(dev);
3202 u8 __iomem *bd; /* BD pointer */
3203 u32 bd_status;
3204
3205 bd = ugeth->confBd[txQ];
3206 bd_status = in_be32((u32 __iomem *)bd);
3207
3208 /* Normal processing. */
3209 while ((bd_status & T_R) == 0) {
3210 /* BD contains already transmitted buffer. */
3211 /* Handle the transmitted buffer and release */
3212 /* the BD to be used with the current frame */
3213
3214 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3215 break;
3216
3217 dev->stats.tx_packets++;
3218
3219 /* Free the sk buffer associated with this TxBD */
3220 dev_kfree_skb_irq(ugeth->
3221 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3222 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3223 ugeth->skb_dirtytx[txQ] =
3224 (ugeth->skb_dirtytx[txQ] +
3225 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3226
3227 /* We freed a buffer, so now we can restart transmission */
3228 if (netif_queue_stopped(dev))
3229 netif_wake_queue(dev);
3230
3231 /* Advance the confirmation BD pointer */
3232 if (!(bd_status & T_W))
3233 bd += sizeof(struct qe_bd);
3234 else
3235 bd = ugeth->p_tx_bd_ring[txQ];
3236 bd_status = in_be32((u32 __iomem *)bd);
3237 }
3238 ugeth->confBd[txQ] = bd;
3239 return 0;
3240 }
3241
3242 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3243 {
3244 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3245 struct ucc_geth_info *ug_info;
3246 int howmany, i;
3247
3248 ug_info = ugeth->ug_info;
3249
3250 howmany = 0;
3251 for (i = 0; i < ug_info->numQueuesRx; i++)
3252 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3253
3254 if (howmany < budget) {
3255 napi_complete(napi);
3256 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS);
3257 }
3258
3259 return howmany;
3260 }
3261
3262 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3263 {
3264 struct net_device *dev = info;
3265 struct ucc_geth_private *ugeth = netdev_priv(dev);
3266 struct ucc_fast_private *uccf;
3267 struct ucc_geth_info *ug_info;
3268 register u32 ucce;
3269 register u32 uccm;
3270 register u32 tx_mask;
3271 u8 i;
3272
3273 ugeth_vdbg("%s: IN", __func__);
3274
3275 uccf = ugeth->uccf;
3276 ug_info = ugeth->ug_info;
3277
3278 /* read and clear events */
3279 ucce = (u32) in_be32(uccf->p_ucce);
3280 uccm = (u32) in_be32(uccf->p_uccm);
3281 ucce &= uccm;
3282 out_be32(uccf->p_ucce, ucce);
3283
3284 /* check for receive events that require processing */
3285 if (ucce & UCCE_RX_EVENTS) {
3286 if (napi_schedule_prep(&ugeth->napi)) {
3287 uccm &= ~UCCE_RX_EVENTS;
3288 out_be32(uccf->p_uccm, uccm);
3289 __napi_schedule(&ugeth->napi);
3290 }
3291 }
3292
3293 /* Tx event processing */
3294 if (ucce & UCCE_TX_EVENTS) {
3295 spin_lock(&ugeth->lock);
3296 tx_mask = UCC_GETH_UCCE_TXB0;
3297 for (i = 0; i < ug_info->numQueuesTx; i++) {
3298 if (ucce & tx_mask)
3299 ucc_geth_tx(dev, i);
3300 ucce &= ~tx_mask;
3301 tx_mask <<= 1;
3302 }
3303 spin_unlock(&ugeth->lock);
3304 }
3305
3306 /* Errors and other events */
3307 if (ucce & UCCE_OTHER) {
3308 if (ucce & UCC_GETH_UCCE_BSY)
3309 dev->stats.rx_errors++;
3310 if (ucce & UCC_GETH_UCCE_TXE)
3311 dev->stats.tx_errors++;
3312 }
3313
3314 return IRQ_HANDLED;
3315 }
3316
3317 #ifdef CONFIG_NET_POLL_CONTROLLER
3318 /*
3319 * Polling 'interrupt' - used by things like netconsole to send skbs
3320 * without having to re-enable interrupts. It's not called while
3321 * the interrupt routine is executing.
3322 */
3323 static void ucc_netpoll(struct net_device *dev)
3324 {
3325 struct ucc_geth_private *ugeth = netdev_priv(dev);
3326 int irq = ugeth->ug_info->uf_info.irq;
3327
3328 disable_irq(irq);
3329 ucc_geth_irq_handler(irq, dev);
3330 enable_irq(irq);
3331 }
3332 #endif /* CONFIG_NET_POLL_CONTROLLER */
3333
3334 /* Called when something needs to use the ethernet device */
3335 /* Returns 0 for success. */
3336 static int ucc_geth_open(struct net_device *dev)
3337 {
3338 struct ucc_geth_private *ugeth = netdev_priv(dev);
3339 int err;
3340
3341 ugeth_vdbg("%s: IN", __func__);
3342
3343 /* Test station address */
3344 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3345 if (netif_msg_ifup(ugeth))
3346 ugeth_err("%s: Multicast address used for station address"
3347 " - is this what you wanted?", __func__);
3348 return -EINVAL;
3349 }
3350
3351 err = init_phy(dev);
3352 if (err) {
3353 if (netif_msg_ifup(ugeth))
3354 ugeth_err("%s: Cannot initialize PHY, aborting.",
3355 dev->name);
3356 return err;
3357 }
3358
3359 err = ucc_struct_init(ugeth);
3360 if (err) {
3361 if (netif_msg_ifup(ugeth))
3362 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3363 goto out_err_stop;
3364 }
3365
3366 napi_enable(&ugeth->napi);
3367
3368 err = ucc_geth_startup(ugeth);
3369 if (err) {
3370 if (netif_msg_ifup(ugeth))
3371 ugeth_err("%s: Cannot configure net device, aborting.",
3372 dev->name);
3373 goto out_err;
3374 }
3375
3376 err = adjust_enet_interface(ugeth);
3377 if (err) {
3378 if (netif_msg_ifup(ugeth))
3379 ugeth_err("%s: Cannot configure net device, aborting.",
3380 dev->name);
3381 goto out_err;
3382 }
3383
3384 /* Set MACSTNADDR1, MACSTNADDR2 */
3385 /* For more details see the hardware spec. */
3386 init_mac_station_addr_regs(dev->dev_addr[0],
3387 dev->dev_addr[1],
3388 dev->dev_addr[2],
3389 dev->dev_addr[3],
3390 dev->dev_addr[4],
3391 dev->dev_addr[5],
3392 &ugeth->ug_regs->macstnaddr1,
3393 &ugeth->ug_regs->macstnaddr2);
3394
3395 phy_start(ugeth->phydev);
3396
3397 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3398 if (err) {
3399 if (netif_msg_ifup(ugeth))
3400 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3401 goto out_err;
3402 }
3403
3404 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3405 0, "UCC Geth", dev);
3406 if (err) {
3407 if (netif_msg_ifup(ugeth))
3408 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3409 dev->name);
3410 goto out_err;
3411 }
3412
3413 netif_start_queue(dev);
3414
3415 return err;
3416
3417 out_err:
3418 napi_disable(&ugeth->napi);
3419 out_err_stop:
3420 ucc_geth_stop(ugeth);
3421 return err;
3422 }
3423
3424 /* Stops the kernel queue, and halts the controller */
3425 static int ucc_geth_close(struct net_device *dev)
3426 {
3427 struct ucc_geth_private *ugeth = netdev_priv(dev);
3428
3429 ugeth_vdbg("%s: IN", __func__);
3430
3431 napi_disable(&ugeth->napi);
3432
3433 ucc_geth_stop(ugeth);
3434
3435 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3436
3437 netif_stop_queue(dev);
3438
3439 return 0;
3440 }
3441
3442 /* Reopen device. This will reset the MAC and PHY. */
3443 static void ucc_geth_timeout_work(struct work_struct *work)
3444 {
3445 struct ucc_geth_private *ugeth;
3446 struct net_device *dev;
3447
3448 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3449 dev = ugeth->ndev;
3450
3451 ugeth_vdbg("%s: IN", __func__);
3452
3453 dev->stats.tx_errors++;
3454
3455 ugeth_dump_regs(ugeth);
3456
3457 if (dev->flags & IFF_UP) {
3458 /*
3459 * Must reset MAC *and* PHY. This is done by reopening
3460 * the device.
3461 */
3462 ucc_geth_close(dev);
3463 ucc_geth_open(dev);
3464 }
3465
3466 netif_tx_schedule_all(dev);
3467 }
3468
3469 /*
3470 * ucc_geth_timeout gets called when a packet has not been
3471 * transmitted after a set amount of time.
3472 */
3473 static void ucc_geth_timeout(struct net_device *dev)
3474 {
3475 struct ucc_geth_private *ugeth = netdev_priv(dev);
3476
3477 netif_carrier_off(dev);
3478 schedule_work(&ugeth->timeout_work);
3479 }
3480
3481 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3482 {
3483 if (strcasecmp(phy_connection_type, "mii") == 0)
3484 return PHY_INTERFACE_MODE_MII;
3485 if (strcasecmp(phy_connection_type, "gmii") == 0)
3486 return PHY_INTERFACE_MODE_GMII;
3487 if (strcasecmp(phy_connection_type, "tbi") == 0)
3488 return PHY_INTERFACE_MODE_TBI;
3489 if (strcasecmp(phy_connection_type, "rmii") == 0)
3490 return PHY_INTERFACE_MODE_RMII;
3491 if (strcasecmp(phy_connection_type, "rgmii") == 0)
3492 return PHY_INTERFACE_MODE_RGMII;
3493 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3494 return PHY_INTERFACE_MODE_RGMII_ID;
3495 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3496 return PHY_INTERFACE_MODE_RGMII_TXID;
3497 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3498 return PHY_INTERFACE_MODE_RGMII_RXID;
3499 if (strcasecmp(phy_connection_type, "rtbi") == 0)
3500 return PHY_INTERFACE_MODE_RTBI;
3501
3502 return PHY_INTERFACE_MODE_MII;
3503 }
3504
3505 static const struct net_device_ops ucc_geth_netdev_ops = {
3506 .ndo_open = ucc_geth_open,
3507 .ndo_stop = ucc_geth_close,
3508 .ndo_start_xmit = ucc_geth_start_xmit,
3509 .ndo_validate_addr = eth_validate_addr,
3510 .ndo_set_mac_address = eth_mac_addr,
3511 .ndo_change_mtu = eth_change_mtu,
3512 .ndo_set_multicast_list = ucc_geth_set_multi,
3513 .ndo_tx_timeout = ucc_geth_timeout,
3514 #ifdef CONFIG_NET_POLL_CONTROLLER
3515 .ndo_poll_controller = ucc_netpoll,
3516 #endif
3517 };
3518
3519 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3520 {
3521 struct device *device = &ofdev->dev;
3522 struct device_node *np = ofdev->node;
3523 struct device_node *mdio;
3524 struct net_device *dev = NULL;
3525 struct ucc_geth_private *ugeth = NULL;
3526 struct ucc_geth_info *ug_info;
3527 struct resource res;
3528 struct device_node *phy;
3529 int err, ucc_num, max_speed = 0;
3530 const phandle *ph;
3531 const u32 *fixed_link;
3532 const unsigned int *prop;
3533 const char *sprop;
3534 const void *mac_addr;
3535 phy_interface_t phy_interface;
3536 static const int enet_to_speed[] = {
3537 SPEED_10, SPEED_10, SPEED_10,
3538 SPEED_100, SPEED_100, SPEED_100,
3539 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3540 };
3541 static const phy_interface_t enet_to_phy_interface[] = {
3542 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3543 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3544 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3545 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3546 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3547 };
3548
3549 ugeth_vdbg("%s: IN", __func__);
3550
3551 prop = of_get_property(np, "cell-index", NULL);
3552 if (!prop) {
3553 prop = of_get_property(np, "device-id", NULL);
3554 if (!prop)
3555 return -ENODEV;
3556 }
3557
3558 ucc_num = *prop - 1;
3559 if ((ucc_num < 0) || (ucc_num > 7))
3560 return -ENODEV;
3561
3562 ug_info = &ugeth_info[ucc_num];
3563 if (ug_info == NULL) {
3564 if (netif_msg_probe(&debug))
3565 ugeth_err("%s: [%d] Missing additional data!",
3566 __func__, ucc_num);
3567 return -ENODEV;
3568 }
3569
3570 ug_info->uf_info.ucc_num = ucc_num;
3571
3572 sprop = of_get_property(np, "rx-clock-name", NULL);
3573 if (sprop) {
3574 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3575 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3576 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3577 printk(KERN_ERR
3578 "ucc_geth: invalid rx-clock-name property\n");
3579 return -EINVAL;
3580 }
3581 } else {
3582 prop = of_get_property(np, "rx-clock", NULL);
3583 if (!prop) {
3584 /* If both rx-clock-name and rx-clock are missing,
3585 we want to tell people to use rx-clock-name. */
3586 printk(KERN_ERR
3587 "ucc_geth: missing rx-clock-name property\n");
3588 return -EINVAL;
3589 }
3590 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3591 printk(KERN_ERR
3592 "ucc_geth: invalid rx-clock propperty\n");
3593 return -EINVAL;
3594 }
3595 ug_info->uf_info.rx_clock = *prop;
3596 }
3597
3598 sprop = of_get_property(np, "tx-clock-name", NULL);
3599 if (sprop) {
3600 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3601 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3602 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3603 printk(KERN_ERR
3604 "ucc_geth: invalid tx-clock-name property\n");
3605 return -EINVAL;
3606 }
3607 } else {
3608 prop = of_get_property(np, "tx-clock", NULL);
3609 if (!prop) {
3610 printk(KERN_ERR
3611 "ucc_geth: mising tx-clock-name property\n");
3612 return -EINVAL;
3613 }
3614 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3615 printk(KERN_ERR
3616 "ucc_geth: invalid tx-clock property\n");
3617 return -EINVAL;
3618 }
3619 ug_info->uf_info.tx_clock = *prop;
3620 }
3621
3622 err = of_address_to_resource(np, 0, &res);
3623 if (err)
3624 return -EINVAL;
3625
3626 ug_info->uf_info.regs = res.start;
3627 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3628 fixed_link = of_get_property(np, "fixed-link", NULL);
3629 if (fixed_link) {
3630 snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id),
3631 PHY_ID_FMT, "0", fixed_link[0]);
3632 phy = NULL;
3633 } else {
3634 char bus_name[MII_BUS_ID_SIZE];
3635
3636 ph = of_get_property(np, "phy-handle", NULL);
3637 phy = of_find_node_by_phandle(*ph);
3638
3639 if (phy == NULL)
3640 return -ENODEV;
3641
3642 /* set the PHY address */
3643 prop = of_get_property(phy, "reg", NULL);
3644 if (prop == NULL)
3645 return -1;
3646
3647 /* Set the bus id */
3648 mdio = of_get_parent(phy);
3649
3650 if (mdio == NULL)
3651 return -ENODEV;
3652
3653 err = of_address_to_resource(mdio, 0, &res);
3654
3655 if (err) {
3656 of_node_put(mdio);
3657 return err;
3658 }
3659 fsl_pq_mdio_bus_name(bus_name, mdio);
3660 of_node_put(mdio);
3661 snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id),
3662 "%s:%02x", bus_name, *prop);
3663 }
3664
3665 /* get the phy interface type, or default to MII */
3666 prop = of_get_property(np, "phy-connection-type", NULL);
3667 if (!prop) {
3668 /* handle interface property present in old trees */
3669 prop = of_get_property(phy, "interface", NULL);
3670 if (prop != NULL) {
3671 phy_interface = enet_to_phy_interface[*prop];
3672 max_speed = enet_to_speed[*prop];
3673 } else
3674 phy_interface = PHY_INTERFACE_MODE_MII;
3675 } else {
3676 phy_interface = to_phy_interface((const char *)prop);
3677 }
3678
3679 /* get speed, or derive from PHY interface */
3680 if (max_speed == 0)
3681 switch (phy_interface) {
3682 case PHY_INTERFACE_MODE_GMII:
3683 case PHY_INTERFACE_MODE_RGMII:
3684 case PHY_INTERFACE_MODE_RGMII_ID:
3685 case PHY_INTERFACE_MODE_RGMII_RXID:
3686 case PHY_INTERFACE_MODE_RGMII_TXID:
3687 case PHY_INTERFACE_MODE_TBI:
3688 case PHY_INTERFACE_MODE_RTBI:
3689 max_speed = SPEED_1000;
3690 break;
3691 default:
3692 max_speed = SPEED_100;
3693 break;
3694 }
3695
3696 if (max_speed == SPEED_1000) {
3697 /* configure muram FIFOs for gigabit operation */
3698 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3699 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3700 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3701 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3702 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3703 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3704 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3705 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3706 }
3707
3708 if (netif_msg_probe(&debug))
3709 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3710 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3711 ug_info->uf_info.irq);
3712
3713 /* Create an ethernet device instance */
3714 dev = alloc_etherdev(sizeof(*ugeth));
3715
3716 if (dev == NULL)
3717 return -ENOMEM;
3718
3719 ugeth = netdev_priv(dev);
3720 spin_lock_init(&ugeth->lock);
3721
3722 /* Create CQs for hash tables */
3723 INIT_LIST_HEAD(&ugeth->group_hash_q);
3724 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3725
3726 dev_set_drvdata(device, dev);
3727
3728 /* Set the dev->base_addr to the gfar reg region */
3729 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3730
3731 SET_NETDEV_DEV(dev, device);
3732
3733 /* Fill in the dev structure */
3734 uec_set_ethtool_ops(dev);
3735 dev->netdev_ops = &ucc_geth_netdev_ops;
3736 dev->watchdog_timeo = TX_TIMEOUT;
3737 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3738 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
3739 dev->mtu = 1500;
3740
3741 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3742 ugeth->phy_interface = phy_interface;
3743 ugeth->max_speed = max_speed;
3744
3745 err = register_netdev(dev);
3746 if (err) {
3747 if (netif_msg_probe(ugeth))
3748 ugeth_err("%s: Cannot register net device, aborting.",
3749 dev->name);
3750 free_netdev(dev);
3751 return err;
3752 }
3753
3754 mac_addr = of_get_mac_address(np);
3755 if (mac_addr)
3756 memcpy(dev->dev_addr, mac_addr, 6);
3757
3758 ugeth->ug_info = ug_info;
3759 ugeth->dev = device;
3760 ugeth->ndev = dev;
3761 ugeth->node = np;
3762
3763 return 0;
3764 }
3765
3766 static int ucc_geth_remove(struct of_device* ofdev)
3767 {
3768 struct device *device = &ofdev->dev;
3769 struct net_device *dev = dev_get_drvdata(device);
3770 struct ucc_geth_private *ugeth = netdev_priv(dev);
3771
3772 unregister_netdev(dev);
3773 free_netdev(dev);
3774 ucc_geth_memclean(ugeth);
3775 dev_set_drvdata(device, NULL);
3776
3777 return 0;
3778 }
3779
3780 static struct of_device_id ucc_geth_match[] = {
3781 {
3782 .type = "network",
3783 .compatible = "ucc_geth",
3784 },
3785 {},
3786 };
3787
3788 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3789
3790 static struct of_platform_driver ucc_geth_driver = {
3791 .name = DRV_NAME,
3792 .match_table = ucc_geth_match,
3793 .probe = ucc_geth_probe,
3794 .remove = ucc_geth_remove,
3795 };
3796
3797 static int __init ucc_geth_init(void)
3798 {
3799 int i, ret;
3800
3801 if (netif_msg_drv(&debug))
3802 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3803 for (i = 0; i < 8; i++)
3804 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3805 sizeof(ugeth_primary_info));
3806
3807 ret = of_register_platform_driver(&ucc_geth_driver);
3808
3809 return ret;
3810 }
3811
3812 static void __exit ucc_geth_exit(void)
3813 {
3814 of_unregister_platform_driver(&ucc_geth_driver);
3815 }
3816
3817 module_init(ucc_geth_init);
3818 module_exit(ucc_geth_exit);
3819
3820 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3821 MODULE_DESCRIPTION(DRV_DESC);
3822 MODULE_VERSION(DRV_VERSION);
3823 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards