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Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable
[linux-2.6/mini2440.git] / drivers / net / forcedeth.c
blob9f6a68fb7b4573cb5ca5a91e9fb0bd2206927007
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42 #define FORCEDETH_VERSION "0.64"
43 #define DRV_NAME "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
61
62 #include <asm/irq.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
66
67 #if 0
68 #define dprintk printk
69 #else
70 #define dprintk(x...) do { } while (0)
71 #endif
72
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
75
76 /*
77 * Hardware access:
78 */
79
80 #define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x000040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x000600 /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3 0x000e00 /* device supports hw statistics version 3 */
92 #define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */
100 #define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */
101
102 enum {
103 NvRegIrqStatus = 0x000,
104 #define NVREG_IRQSTAT_MIIEVENT 0x040
105 #define NVREG_IRQSTAT_MASK 0x83ff
106 NvRegIrqMask = 0x004,
107 #define NVREG_IRQ_RX_ERROR 0x0001
108 #define NVREG_IRQ_RX 0x0002
109 #define NVREG_IRQ_RX_NOBUF 0x0004
110 #define NVREG_IRQ_TX_ERR 0x0008
111 #define NVREG_IRQ_TX_OK 0x0010
112 #define NVREG_IRQ_TIMER 0x0020
113 #define NVREG_IRQ_LINK 0x0040
114 #define NVREG_IRQ_RX_FORCED 0x0080
115 #define NVREG_IRQ_TX_FORCED 0x0100
116 #define NVREG_IRQ_RECOVER_ERROR 0x8200
117 #define NVREG_IRQMASK_THROUGHPUT 0x00df
118 #define NVREG_IRQMASK_CPU 0x0060
119 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
121 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122
123 NvRegUnknownSetupReg6 = 0x008,
124 #define NVREG_UNKSETUP6_VAL 3
125
126 /*
127 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
128 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
129 */
130 NvRegPollingInterval = 0x00c,
131 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
132 #define NVREG_POLL_DEFAULT_CPU 13
133 NvRegMSIMap0 = 0x020,
134 NvRegMSIMap1 = 0x024,
135 NvRegMSIIrqMask = 0x030,
136 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
137 NvRegMisc1 = 0x080,
138 #define NVREG_MISC1_PAUSE_TX 0x01
139 #define NVREG_MISC1_HD 0x02
140 #define NVREG_MISC1_FORCE 0x3b0f3c
141
142 NvRegMacReset = 0x34,
143 #define NVREG_MAC_RESET_ASSERT 0x0F3
144 NvRegTransmitterControl = 0x084,
145 #define NVREG_XMITCTL_START 0x01
146 #define NVREG_XMITCTL_MGMT_ST 0x40000000
147 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
148 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
149 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
150 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
151 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
152 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
153 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
154 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
155 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
156 #define NVREG_XMITCTL_DATA_START 0x00100000
157 #define NVREG_XMITCTL_DATA_READY 0x00010000
158 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
159 NvRegTransmitterStatus = 0x088,
160 #define NVREG_XMITSTAT_BUSY 0x01
161
162 NvRegPacketFilterFlags = 0x8c,
163 #define NVREG_PFF_PAUSE_RX 0x08
164 #define NVREG_PFF_ALWAYS 0x7F0000
165 #define NVREG_PFF_PROMISC 0x80
166 #define NVREG_PFF_MYADDR 0x20
167 #define NVREG_PFF_LOOPBACK 0x10
168
169 NvRegOffloadConfig = 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY 0x601
171 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
172 NvRegReceiverControl = 0x094,
173 #define NVREG_RCVCTL_START 0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175 NvRegReceiverStatus = 0x98,
176 #define NVREG_RCVSTAT_BUSY 0x01
177
178 NvRegSlotTime = 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
182 #define NVREG_SLOTTIME_HALF 0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
184 #define NVREG_SLOTTIME_MASK 0x000000ff
185
186 NvRegTxDeferral = 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
193 NvRegRxDeferral = 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
195 NvRegMacAddrA = 0xA8,
196 NvRegMacAddrB = 0xAC,
197 NvRegMulticastAddrA = 0xB0,
198 #define NVREG_MCASTADDRA_FORCE 0x01
199 NvRegMulticastAddrB = 0xB4,
200 NvRegMulticastMaskA = 0xB8,
201 #define NVREG_MCASTMASKA_NONE 0xffffffff
202 NvRegMulticastMaskB = 0xBC,
203 #define NVREG_MCASTMASKB_NONE 0xffff
204
205 NvRegPhyInterface = 0xC0,
206 #define PHY_RGMII 0x10000000
207 NvRegBackOffControl = 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT 24
211 #define NVREG_BKOFFCTRL_GEAR 12
212
213 NvRegTxRingPhysAddr = 0x100,
214 NvRegRxRingPhysAddr = 0x104,
215 NvRegRingSizes = 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218 NvRegTransmitPoll = 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220 NvRegLinkSpeed = 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10 1000
223 #define NVREG_LINKSPEED_100 100
224 #define NVREG_LINKSPEED_1000 50
225 #define NVREG_LINKSPEED_MASK (0xFFF)
226 NvRegUnknownSetupReg5 = 0x130,
227 #define NVREG_UNKSETUP5_BIT31 (1<<31)
228 NvRegTxWatermark = 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
232 NvRegTxRxControl = 0x144,
233 #define NVREG_TXRXCTL_KICK 0x0001
234 #define NVREG_TXRXCTL_BIT1 0x0002
235 #define NVREG_TXRXCTL_BIT2 0x0004
236 #define NVREG_TXRXCTL_IDLE 0x0008
237 #define NVREG_TXRXCTL_RESET 0x0010
238 #define NVREG_TXRXCTL_RXCHECK 0x0400
239 #define NVREG_TXRXCTL_DESC_1 0
240 #define NVREG_TXRXCTL_DESC_2 0x002100
241 #define NVREG_TXRXCTL_DESC_3 0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS 0x00080
244 NvRegTxRingPhysAddrHigh = 0x148,
245 NvRegRxRingPhysAddrHigh = 0x14C,
246 NvRegTxPauseFrame = 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
251 NvRegTxPauseFrameLimit = 0x174,
252 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
253 NvRegMIIStatus = 0x180,
254 #define NVREG_MIISTAT_ERROR 0x0001
255 #define NVREG_MIISTAT_LINKCHANGE 0x0008
256 #define NVREG_MIISTAT_MASK_RW 0x0007
257 #define NVREG_MIISTAT_MASK_ALL 0x000f
258 NvRegMIIMask = 0x184,
259 #define NVREG_MII_LINKCHANGE 0x0008
260
261 NvRegAdapterControl = 0x188,
262 #define NVREG_ADAPTCTL_START 0x02
263 #define NVREG_ADAPTCTL_LINKUP 0x04
264 #define NVREG_ADAPTCTL_PHYVALID 0x40000
265 #define NVREG_ADAPTCTL_RUNNING 0x100000
266 #define NVREG_ADAPTCTL_PHYSHIFT 24
267 NvRegMIISpeed = 0x18c,
268 #define NVREG_MIISPEED_BIT8 (1<<8)
269 #define NVREG_MIIDELAY 5
270 NvRegMIIControl = 0x190,
271 #define NVREG_MIICTL_INUSE 0x08000
272 #define NVREG_MIICTL_WRITE 0x00400
273 #define NVREG_MIICTL_ADDRSHIFT 5
274 NvRegMIIData = 0x194,
275 NvRegTxUnicast = 0x1a0,
276 NvRegTxMulticast = 0x1a4,
277 NvRegTxBroadcast = 0x1a8,
278 NvRegWakeUpFlags = 0x200,
279 #define NVREG_WAKEUPFLAGS_VAL 0x7770
280 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
281 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
282 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
283 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
284 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
285 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
286 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
287 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
288 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
289 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
290
291 NvRegMgmtUnitGetVersion = 0x204,
292 #define NVREG_MGMTUNITGETVERSION 0x01
293 NvRegMgmtUnitVersion = 0x208,
294 #define NVREG_MGMTUNITVERSION 0x08
295 NvRegPowerCap = 0x268,
296 #define NVREG_POWERCAP_D3SUPP (1<<30)
297 #define NVREG_POWERCAP_D2SUPP (1<<26)
298 #define NVREG_POWERCAP_D1SUPP (1<<25)
299 NvRegPowerState = 0x26c,
300 #define NVREG_POWERSTATE_POWEREDUP 0x8000
301 #define NVREG_POWERSTATE_VALID 0x0100
302 #define NVREG_POWERSTATE_MASK 0x0003
303 #define NVREG_POWERSTATE_D0 0x0000
304 #define NVREG_POWERSTATE_D1 0x0001
305 #define NVREG_POWERSTATE_D2 0x0002
306 #define NVREG_POWERSTATE_D3 0x0003
307 NvRegMgmtUnitControl = 0x278,
308 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
309 NvRegTxCnt = 0x280,
310 NvRegTxZeroReXmt = 0x284,
311 NvRegTxOneReXmt = 0x288,
312 NvRegTxManyReXmt = 0x28c,
313 NvRegTxLateCol = 0x290,
314 NvRegTxUnderflow = 0x294,
315 NvRegTxLossCarrier = 0x298,
316 NvRegTxExcessDef = 0x29c,
317 NvRegTxRetryErr = 0x2a0,
318 NvRegRxFrameErr = 0x2a4,
319 NvRegRxExtraByte = 0x2a8,
320 NvRegRxLateCol = 0x2ac,
321 NvRegRxRunt = 0x2b0,
322 NvRegRxFrameTooLong = 0x2b4,
323 NvRegRxOverflow = 0x2b8,
324 NvRegRxFCSErr = 0x2bc,
325 NvRegRxFrameAlignErr = 0x2c0,
326 NvRegRxLenErr = 0x2c4,
327 NvRegRxUnicast = 0x2c8,
328 NvRegRxMulticast = 0x2cc,
329 NvRegRxBroadcast = 0x2d0,
330 NvRegTxDef = 0x2d4,
331 NvRegTxFrame = 0x2d8,
332 NvRegRxCnt = 0x2dc,
333 NvRegTxPause = 0x2e0,
334 NvRegRxPause = 0x2e4,
335 NvRegRxDropFrame = 0x2e8,
336 NvRegVlanControl = 0x300,
337 #define NVREG_VLANCONTROL_ENABLE 0x2000
338 NvRegMSIXMap0 = 0x3e0,
339 NvRegMSIXMap1 = 0x3e4,
340 NvRegMSIXIrqStatus = 0x3f0,
341
342 NvRegPowerState2 = 0x600,
343 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
344 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
345 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
346 };
347
348 /* Big endian: should work, but is untested */
349 struct ring_desc {
350 __le32 buf;
351 __le32 flaglen;
352 };
353
354 struct ring_desc_ex {
355 __le32 bufhigh;
356 __le32 buflow;
357 __le32 txvlan;
358 __le32 flaglen;
359 };
360
361 union ring_type {
362 struct ring_desc* orig;
363 struct ring_desc_ex* ex;
364 };
365
366 #define FLAG_MASK_V1 0xffff0000
367 #define FLAG_MASK_V2 0xffffc000
368 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
369 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
370
371 #define NV_TX_LASTPACKET (1<<16)
372 #define NV_TX_RETRYERROR (1<<19)
373 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
374 #define NV_TX_FORCED_INTERRUPT (1<<24)
375 #define NV_TX_DEFERRED (1<<26)
376 #define NV_TX_CARRIERLOST (1<<27)
377 #define NV_TX_LATECOLLISION (1<<28)
378 #define NV_TX_UNDERFLOW (1<<29)
379 #define NV_TX_ERROR (1<<30)
380 #define NV_TX_VALID (1<<31)
381
382 #define NV_TX2_LASTPACKET (1<<29)
383 #define NV_TX2_RETRYERROR (1<<18)
384 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
385 #define NV_TX2_FORCED_INTERRUPT (1<<30)
386 #define NV_TX2_DEFERRED (1<<25)
387 #define NV_TX2_CARRIERLOST (1<<26)
388 #define NV_TX2_LATECOLLISION (1<<27)
389 #define NV_TX2_UNDERFLOW (1<<28)
390 /* error and valid are the same for both */
391 #define NV_TX2_ERROR (1<<30)
392 #define NV_TX2_VALID (1<<31)
393 #define NV_TX2_TSO (1<<28)
394 #define NV_TX2_TSO_SHIFT 14
395 #define NV_TX2_TSO_MAX_SHIFT 14
396 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
397 #define NV_TX2_CHECKSUM_L3 (1<<27)
398 #define NV_TX2_CHECKSUM_L4 (1<<26)
399
400 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
401
402 #define NV_RX_DESCRIPTORVALID (1<<16)
403 #define NV_RX_MISSEDFRAME (1<<17)
404 #define NV_RX_SUBSTRACT1 (1<<18)
405 #define NV_RX_ERROR1 (1<<23)
406 #define NV_RX_ERROR2 (1<<24)
407 #define NV_RX_ERROR3 (1<<25)
408 #define NV_RX_ERROR4 (1<<26)
409 #define NV_RX_CRCERR (1<<27)
410 #define NV_RX_OVERFLOW (1<<28)
411 #define NV_RX_FRAMINGERR (1<<29)
412 #define NV_RX_ERROR (1<<30)
413 #define NV_RX_AVAIL (1<<31)
414 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
415
416 #define NV_RX2_CHECKSUMMASK (0x1C000000)
417 #define NV_RX2_CHECKSUM_IP (0x10000000)
418 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
419 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
420 #define NV_RX2_DESCRIPTORVALID (1<<29)
421 #define NV_RX2_SUBSTRACT1 (1<<25)
422 #define NV_RX2_ERROR1 (1<<18)
423 #define NV_RX2_ERROR2 (1<<19)
424 #define NV_RX2_ERROR3 (1<<20)
425 #define NV_RX2_ERROR4 (1<<21)
426 #define NV_RX2_CRCERR (1<<22)
427 #define NV_RX2_OVERFLOW (1<<23)
428 #define NV_RX2_FRAMINGERR (1<<24)
429 /* error and avail are the same for both */
430 #define NV_RX2_ERROR (1<<30)
431 #define NV_RX2_AVAIL (1<<31)
432 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
433
434 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
435 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
436
437 /* Miscelaneous hardware related defines: */
438 #define NV_PCI_REGSZ_VER1 0x270
439 #define NV_PCI_REGSZ_VER2 0x2d4
440 #define NV_PCI_REGSZ_VER3 0x604
441 #define NV_PCI_REGSZ_MAX 0x604
442
443 /* various timeout delays: all in usec */
444 #define NV_TXRX_RESET_DELAY 4
445 #define NV_TXSTOP_DELAY1 10
446 #define NV_TXSTOP_DELAY1MAX 500000
447 #define NV_TXSTOP_DELAY2 100
448 #define NV_RXSTOP_DELAY1 10
449 #define NV_RXSTOP_DELAY1MAX 500000
450 #define NV_RXSTOP_DELAY2 100
451 #define NV_SETUP5_DELAY 5
452 #define NV_SETUP5_DELAYMAX 50000
453 #define NV_POWERUP_DELAY 5
454 #define NV_POWERUP_DELAYMAX 5000
455 #define NV_MIIBUSY_DELAY 50
456 #define NV_MIIPHY_DELAY 10
457 #define NV_MIIPHY_DELAYMAX 10000
458 #define NV_MAC_RESET_DELAY 64
459
460 #define NV_WAKEUPPATTERNS 5
461 #define NV_WAKEUPMASKENTRIES 4
462
463 /* General driver defaults */
464 #define NV_WATCHDOG_TIMEO (5*HZ)
465
466 #define RX_RING_DEFAULT 512
467 #define TX_RING_DEFAULT 256
468 #define RX_RING_MIN 128
469 #define TX_RING_MIN 64
470 #define RING_MAX_DESC_VER_1 1024
471 #define RING_MAX_DESC_VER_2_3 16384
472
473 /* rx/tx mac addr + type + vlan + align + slack*/
474 #define NV_RX_HEADERS (64)
475 /* even more slack. */
476 #define NV_RX_ALLOC_PAD (64)
477
478 /* maximum mtu size */
479 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
480 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
481
482 #define OOM_REFILL (1+HZ/20)
483 #define POLL_WAIT (1+HZ/100)
484 #define LINK_TIMEOUT (3*HZ)
485 #define STATS_INTERVAL (10*HZ)
486
487 /*
488 * desc_ver values:
489 * The nic supports three different descriptor types:
490 * - DESC_VER_1: Original
491 * - DESC_VER_2: support for jumbo frames.
492 * - DESC_VER_3: 64-bit format.
493 */
494 #define DESC_VER_1 1
495 #define DESC_VER_2 2
496 #define DESC_VER_3 3
497
498 /* PHY defines */
499 #define PHY_OUI_MARVELL 0x5043
500 #define PHY_OUI_CICADA 0x03f1
501 #define PHY_OUI_VITESSE 0x01c1
502 #define PHY_OUI_REALTEK 0x0732
503 #define PHY_OUI_REALTEK2 0x0020
504 #define PHYID1_OUI_MASK 0x03ff
505 #define PHYID1_OUI_SHFT 6
506 #define PHYID2_OUI_MASK 0xfc00
507 #define PHYID2_OUI_SHFT 10
508 #define PHYID2_MODEL_MASK 0x03f0
509 #define PHY_MODEL_REALTEK_8211 0x0110
510 #define PHY_REV_MASK 0x0001
511 #define PHY_REV_REALTEK_8211B 0x0000
512 #define PHY_REV_REALTEK_8211C 0x0001
513 #define PHY_MODEL_REALTEK_8201 0x0200
514 #define PHY_MODEL_MARVELL_E3016 0x0220
515 #define PHY_MARVELL_E3016_INITMASK 0x0300
516 #define PHY_CICADA_INIT1 0x0f000
517 #define PHY_CICADA_INIT2 0x0e00
518 #define PHY_CICADA_INIT3 0x01000
519 #define PHY_CICADA_INIT4 0x0200
520 #define PHY_CICADA_INIT5 0x0004
521 #define PHY_CICADA_INIT6 0x02000
522 #define PHY_VITESSE_INIT_REG1 0x1f
523 #define PHY_VITESSE_INIT_REG2 0x10
524 #define PHY_VITESSE_INIT_REG3 0x11
525 #define PHY_VITESSE_INIT_REG4 0x12
526 #define PHY_VITESSE_INIT_MSK1 0xc
527 #define PHY_VITESSE_INIT_MSK2 0x0180
528 #define PHY_VITESSE_INIT1 0x52b5
529 #define PHY_VITESSE_INIT2 0xaf8a
530 #define PHY_VITESSE_INIT3 0x8
531 #define PHY_VITESSE_INIT4 0x8f8a
532 #define PHY_VITESSE_INIT5 0xaf86
533 #define PHY_VITESSE_INIT6 0x8f86
534 #define PHY_VITESSE_INIT7 0xaf82
535 #define PHY_VITESSE_INIT8 0x0100
536 #define PHY_VITESSE_INIT9 0x8f82
537 #define PHY_VITESSE_INIT10 0x0
538 #define PHY_REALTEK_INIT_REG1 0x1f
539 #define PHY_REALTEK_INIT_REG2 0x19
540 #define PHY_REALTEK_INIT_REG3 0x13
541 #define PHY_REALTEK_INIT_REG4 0x14
542 #define PHY_REALTEK_INIT_REG5 0x18
543 #define PHY_REALTEK_INIT_REG6 0x11
544 #define PHY_REALTEK_INIT_REG7 0x01
545 #define PHY_REALTEK_INIT1 0x0000
546 #define PHY_REALTEK_INIT2 0x8e00
547 #define PHY_REALTEK_INIT3 0x0001
548 #define PHY_REALTEK_INIT4 0xad17
549 #define PHY_REALTEK_INIT5 0xfb54
550 #define PHY_REALTEK_INIT6 0xf5c7
551 #define PHY_REALTEK_INIT7 0x1000
552 #define PHY_REALTEK_INIT8 0x0003
553 #define PHY_REALTEK_INIT9 0x0008
554 #define PHY_REALTEK_INIT10 0x0005
555 #define PHY_REALTEK_INIT11 0x0200
556 #define PHY_REALTEK_INIT_MSK1 0x0003
557
558 #define PHY_GIGABIT 0x0100
559
560 #define PHY_TIMEOUT 0x1
561 #define PHY_ERROR 0x2
562
563 #define PHY_100 0x1
564 #define PHY_1000 0x2
565 #define PHY_HALF 0x100
566
567 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
568 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
569 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
570 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
571 #define NV_PAUSEFRAME_RX_REQ 0x0010
572 #define NV_PAUSEFRAME_TX_REQ 0x0020
573 #define NV_PAUSEFRAME_AUTONEG 0x0040
574
575 /* MSI/MSI-X defines */
576 #define NV_MSI_X_MAX_VECTORS 8
577 #define NV_MSI_X_VECTORS_MASK 0x000f
578 #define NV_MSI_CAPABLE 0x0010
579 #define NV_MSI_X_CAPABLE 0x0020
580 #define NV_MSI_ENABLED 0x0040
581 #define NV_MSI_X_ENABLED 0x0080
582
583 #define NV_MSI_X_VECTOR_ALL 0x0
584 #define NV_MSI_X_VECTOR_RX 0x0
585 #define NV_MSI_X_VECTOR_TX 0x1
586 #define NV_MSI_X_VECTOR_OTHER 0x2
587
588 #define NV_MSI_PRIV_OFFSET 0x68
589 #define NV_MSI_PRIV_VALUE 0xffffffff
590
591 #define NV_RESTART_TX 0x1
592 #define NV_RESTART_RX 0x2
593
594 #define NV_TX_LIMIT_COUNT 16
595
596 #define NV_DYNAMIC_THRESHOLD 4
597 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
598
599 /* statistics */
600 struct nv_ethtool_str {
601 char name[ETH_GSTRING_LEN];
602 };
603
604 static const struct nv_ethtool_str nv_estats_str[] = {
605 { "tx_bytes" },
606 { "tx_zero_rexmt" },
607 { "tx_one_rexmt" },
608 { "tx_many_rexmt" },
609 { "tx_late_collision" },
610 { "tx_fifo_errors" },
611 { "tx_carrier_errors" },
612 { "tx_excess_deferral" },
613 { "tx_retry_error" },
614 { "rx_frame_error" },
615 { "rx_extra_byte" },
616 { "rx_late_collision" },
617 { "rx_runt" },
618 { "rx_frame_too_long" },
619 { "rx_over_errors" },
620 { "rx_crc_errors" },
621 { "rx_frame_align_error" },
622 { "rx_length_error" },
623 { "rx_unicast" },
624 { "rx_multicast" },
625 { "rx_broadcast" },
626 { "rx_packets" },
627 { "rx_errors_total" },
628 { "tx_errors_total" },
629
630 /* version 2 stats */
631 { "tx_deferral" },
632 { "tx_packets" },
633 { "rx_bytes" },
634 { "tx_pause" },
635 { "rx_pause" },
636 { "rx_drop_frame" },
637
638 /* version 3 stats */
639 { "tx_unicast" },
640 { "tx_multicast" },
641 { "tx_broadcast" }
642 };
643
644 struct nv_ethtool_stats {
645 u64 tx_bytes;
646 u64 tx_zero_rexmt;
647 u64 tx_one_rexmt;
648 u64 tx_many_rexmt;
649 u64 tx_late_collision;
650 u64 tx_fifo_errors;
651 u64 tx_carrier_errors;
652 u64 tx_excess_deferral;
653 u64 tx_retry_error;
654 u64 rx_frame_error;
655 u64 rx_extra_byte;
656 u64 rx_late_collision;
657 u64 rx_runt;
658 u64 rx_frame_too_long;
659 u64 rx_over_errors;
660 u64 rx_crc_errors;
661 u64 rx_frame_align_error;
662 u64 rx_length_error;
663 u64 rx_unicast;
664 u64 rx_multicast;
665 u64 rx_broadcast;
666 u64 rx_packets;
667 u64 rx_errors_total;
668 u64 tx_errors_total;
669
670 /* version 2 stats */
671 u64 tx_deferral;
672 u64 tx_packets;
673 u64 rx_bytes;
674 u64 tx_pause;
675 u64 rx_pause;
676 u64 rx_drop_frame;
677
678 /* version 3 stats */
679 u64 tx_unicast;
680 u64 tx_multicast;
681 u64 tx_broadcast;
682 };
683
684 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
685 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
686 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
687
688 /* diagnostics */
689 #define NV_TEST_COUNT_BASE 3
690 #define NV_TEST_COUNT_EXTENDED 4
691
692 static const struct nv_ethtool_str nv_etests_str[] = {
693 { "link (online/offline)" },
694 { "register (offline) " },
695 { "interrupt (offline) " },
696 { "loopback (offline) " }
697 };
698
699 struct register_test {
700 __u32 reg;
701 __u32 mask;
702 };
703
704 static const struct register_test nv_registers_test[] = {
705 { NvRegUnknownSetupReg6, 0x01 },
706 { NvRegMisc1, 0x03c },
707 { NvRegOffloadConfig, 0x03ff },
708 { NvRegMulticastAddrA, 0xffffffff },
709 { NvRegTxWatermark, 0x0ff },
710 { NvRegWakeUpFlags, 0x07777 },
711 { 0,0 }
712 };
713
714 struct nv_skb_map {
715 struct sk_buff *skb;
716 dma_addr_t dma;
717 unsigned int dma_len;
718 struct ring_desc_ex *first_tx_desc;
719 struct nv_skb_map *next_tx_ctx;
720 };
721
722 /*
723 * SMP locking:
724 * All hardware access under netdev_priv(dev)->lock, except the performance
725 * critical parts:
726 * - rx is (pseudo-) lockless: it relies on the single-threading provided
727 * by the arch code for interrupts.
728 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
729 * needs netdev_priv(dev)->lock :-(
730 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
731 */
732
733 /* in dev: base, irq */
734 struct fe_priv {
735 spinlock_t lock;
736
737 struct net_device *dev;
738 struct napi_struct napi;
739
740 /* General data:
741 * Locking: spin_lock(&np->lock); */
742 struct nv_ethtool_stats estats;
743 int in_shutdown;
744 u32 linkspeed;
745 int duplex;
746 int autoneg;
747 int fixed_mode;
748 int phyaddr;
749 int wolenabled;
750 unsigned int phy_oui;
751 unsigned int phy_model;
752 unsigned int phy_rev;
753 u16 gigabit;
754 int intr_test;
755 int recover_error;
756 int quiet_count;
757
758 /* General data: RO fields */
759 dma_addr_t ring_addr;
760 struct pci_dev *pci_dev;
761 u32 orig_mac[2];
762 u32 events;
763 u32 irqmask;
764 u32 desc_ver;
765 u32 txrxctl_bits;
766 u32 vlanctl_bits;
767 u32 driver_data;
768 u32 device_id;
769 u32 register_size;
770 int rx_csum;
771 u32 mac_in_use;
772 int mgmt_version;
773 int mgmt_sema;
774
775 void __iomem *base;
776
777 /* rx specific fields.
778 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
779 */
780 union ring_type get_rx, put_rx, first_rx, last_rx;
781 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
782 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
783 struct nv_skb_map *rx_skb;
784
785 union ring_type rx_ring;
786 unsigned int rx_buf_sz;
787 unsigned int pkt_limit;
788 struct timer_list oom_kick;
789 struct timer_list nic_poll;
790 struct timer_list stats_poll;
791 u32 nic_poll_irq;
792 int rx_ring_size;
793
794 /* media detection workaround.
795 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
796 */
797 int need_linktimer;
798 unsigned long link_timeout;
799 /*
800 * tx specific fields.
801 */
802 union ring_type get_tx, put_tx, first_tx, last_tx;
803 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
804 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
805 struct nv_skb_map *tx_skb;
806
807 union ring_type tx_ring;
808 u32 tx_flags;
809 int tx_ring_size;
810 int tx_limit;
811 u32 tx_pkts_in_progress;
812 struct nv_skb_map *tx_change_owner;
813 struct nv_skb_map *tx_end_flip;
814 int tx_stop;
815
816 /* vlan fields */
817 struct vlan_group *vlangrp;
818
819 /* msi/msi-x fields */
820 u32 msi_flags;
821 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
822
823 /* flow control */
824 u32 pause_flags;
825
826 /* power saved state */
827 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
828
829 /* for different msi-x irq type */
830 char name_rx[IFNAMSIZ + 3]; /* -rx */
831 char name_tx[IFNAMSIZ + 3]; /* -tx */
832 char name_other[IFNAMSIZ + 6]; /* -other */
833 };
834
835 /*
836 * Maximum number of loops until we assume that a bit in the irq mask
837 * is stuck. Overridable with module param.
838 */
839 static int max_interrupt_work = 4;
840
841 /*
842 * Optimization can be either throuput mode or cpu mode
843 *
844 * Throughput Mode: Every tx and rx packet will generate an interrupt.
845 * CPU Mode: Interrupts are controlled by a timer.
846 */
847 enum {
848 NV_OPTIMIZATION_MODE_THROUGHPUT,
849 NV_OPTIMIZATION_MODE_CPU,
850 NV_OPTIMIZATION_MODE_DYNAMIC
851 };
852 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
853
854 /*
855 * Poll interval for timer irq
856 *
857 * This interval determines how frequent an interrupt is generated.
858 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
859 * Min = 0, and Max = 65535
860 */
861 static int poll_interval = -1;
862
863 /*
864 * MSI interrupts
865 */
866 enum {
867 NV_MSI_INT_DISABLED,
868 NV_MSI_INT_ENABLED
869 };
870 static int msi = NV_MSI_INT_ENABLED;
871
872 /*
873 * MSIX interrupts
874 */
875 enum {
876 NV_MSIX_INT_DISABLED,
877 NV_MSIX_INT_ENABLED
878 };
879 static int msix = NV_MSIX_INT_ENABLED;
880
881 /*
882 * DMA 64bit
883 */
884 enum {
885 NV_DMA_64BIT_DISABLED,
886 NV_DMA_64BIT_ENABLED
887 };
888 static int dma_64bit = NV_DMA_64BIT_ENABLED;
889
890 /*
891 * Crossover Detection
892 * Realtek 8201 phy + some OEM boards do not work properly.
893 */
894 enum {
895 NV_CROSSOVER_DETECTION_DISABLED,
896 NV_CROSSOVER_DETECTION_ENABLED
897 };
898 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
899
900 /*
901 * Power down phy when interface is down (persists through reboot;
902 * older Linux and other OSes may not power it up again)
903 */
904 static int phy_power_down = 0;
905
906 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
907 {
908 return netdev_priv(dev);
909 }
910
911 static inline u8 __iomem *get_hwbase(struct net_device *dev)
912 {
913 return ((struct fe_priv *)netdev_priv(dev))->base;
914 }
915
916 static inline void pci_push(u8 __iomem *base)
917 {
918 /* force out pending posted writes */
919 readl(base);
920 }
921
922 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
923 {
924 return le32_to_cpu(prd->flaglen)
925 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
926 }
927
928 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
929 {
930 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
931 }
932
933 static bool nv_optimized(struct fe_priv *np)
934 {
935 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
936 return false;
937 return true;
938 }
939
940 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
941 int delay, int delaymax, const char *msg)
942 {
943 u8 __iomem *base = get_hwbase(dev);
944
945 pci_push(base);
946 do {
947 udelay(delay);
948 delaymax -= delay;
949 if (delaymax < 0) {
950 if (msg)
951 printk("%s", msg);
952 return 1;
953 }
954 } while ((readl(base + offset) & mask) != target);
955 return 0;
956 }
957
958 #define NV_SETUP_RX_RING 0x01
959 #define NV_SETUP_TX_RING 0x02
960
961 static inline u32 dma_low(dma_addr_t addr)
962 {
963 return addr;
964 }
965
966 static inline u32 dma_high(dma_addr_t addr)
967 {
968 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
969 }
970
971 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
972 {
973 struct fe_priv *np = get_nvpriv(dev);
974 u8 __iomem *base = get_hwbase(dev);
975
976 if (!nv_optimized(np)) {
977 if (rxtx_flags & NV_SETUP_RX_RING) {
978 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
979 }
980 if (rxtx_flags & NV_SETUP_TX_RING) {
981 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
982 }
983 } else {
984 if (rxtx_flags & NV_SETUP_RX_RING) {
985 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
986 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
987 }
988 if (rxtx_flags & NV_SETUP_TX_RING) {
989 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
990 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
991 }
992 }
993 }
994
995 static void free_rings(struct net_device *dev)
996 {
997 struct fe_priv *np = get_nvpriv(dev);
998
999 if (!nv_optimized(np)) {
1000 if (np->rx_ring.orig)
1001 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1002 np->rx_ring.orig, np->ring_addr);
1003 } else {
1004 if (np->rx_ring.ex)
1005 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1006 np->rx_ring.ex, np->ring_addr);
1007 }
1008 if (np->rx_skb)
1009 kfree(np->rx_skb);
1010 if (np->tx_skb)
1011 kfree(np->tx_skb);
1012 }
1013
1014 static int using_multi_irqs(struct net_device *dev)
1015 {
1016 struct fe_priv *np = get_nvpriv(dev);
1017
1018 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1019 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1020 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1021 return 0;
1022 else
1023 return 1;
1024 }
1025
1026 static void nv_enable_irq(struct net_device *dev)
1027 {
1028 struct fe_priv *np = get_nvpriv(dev);
1029
1030 if (!using_multi_irqs(dev)) {
1031 if (np->msi_flags & NV_MSI_X_ENABLED)
1032 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1033 else
1034 enable_irq(np->pci_dev->irq);
1035 } else {
1036 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1037 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1038 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1039 }
1040 }
1041
1042 static void nv_disable_irq(struct net_device *dev)
1043 {
1044 struct fe_priv *np = get_nvpriv(dev);
1045
1046 if (!using_multi_irqs(dev)) {
1047 if (np->msi_flags & NV_MSI_X_ENABLED)
1048 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1049 else
1050 disable_irq(np->pci_dev->irq);
1051 } else {
1052 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1053 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1054 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1055 }
1056 }
1057
1058 /* In MSIX mode, a write to irqmask behaves as XOR */
1059 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1060 {
1061 u8 __iomem *base = get_hwbase(dev);
1062
1063 writel(mask, base + NvRegIrqMask);
1064 }
1065
1066 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1067 {
1068 struct fe_priv *np = get_nvpriv(dev);
1069 u8 __iomem *base = get_hwbase(dev);
1070
1071 if (np->msi_flags & NV_MSI_X_ENABLED) {
1072 writel(mask, base + NvRegIrqMask);
1073 } else {
1074 if (np->msi_flags & NV_MSI_ENABLED)
1075 writel(0, base + NvRegMSIIrqMask);
1076 writel(0, base + NvRegIrqMask);
1077 }
1078 }
1079
1080 static void nv_napi_enable(struct net_device *dev)
1081 {
1082 #ifdef CONFIG_FORCEDETH_NAPI
1083 struct fe_priv *np = get_nvpriv(dev);
1084
1085 napi_enable(&np->napi);
1086 #endif
1087 }
1088
1089 static void nv_napi_disable(struct net_device *dev)
1090 {
1091 #ifdef CONFIG_FORCEDETH_NAPI
1092 struct fe_priv *np = get_nvpriv(dev);
1093
1094 napi_disable(&np->napi);
1095 #endif
1096 }
1097
1098 #define MII_READ (-1)
1099 /* mii_rw: read/write a register on the PHY.
1100 *
1101 * Caller must guarantee serialization
1102 */
1103 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1104 {
1105 u8 __iomem *base = get_hwbase(dev);
1106 u32 reg;
1107 int retval;
1108
1109 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1110
1111 reg = readl(base + NvRegMIIControl);
1112 if (reg & NVREG_MIICTL_INUSE) {
1113 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1114 udelay(NV_MIIBUSY_DELAY);
1115 }
1116
1117 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1118 if (value != MII_READ) {
1119 writel(value, base + NvRegMIIData);
1120 reg |= NVREG_MIICTL_WRITE;
1121 }
1122 writel(reg, base + NvRegMIIControl);
1123
1124 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1125 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1126 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1127 dev->name, miireg, addr);
1128 retval = -1;
1129 } else if (value != MII_READ) {
1130 /* it was a write operation - fewer failures are detectable */
1131 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1132 dev->name, value, miireg, addr);
1133 retval = 0;
1134 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1135 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1136 dev->name, miireg, addr);
1137 retval = -1;
1138 } else {
1139 retval = readl(base + NvRegMIIData);
1140 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1141 dev->name, miireg, addr, retval);
1142 }
1143
1144 return retval;
1145 }
1146
1147 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1148 {
1149 struct fe_priv *np = netdev_priv(dev);
1150 u32 miicontrol;
1151 unsigned int tries = 0;
1152
1153 miicontrol = BMCR_RESET | bmcr_setup;
1154 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1155 return -1;
1156 }
1157
1158 /* wait for 500ms */
1159 msleep(500);
1160
1161 /* must wait till reset is deasserted */
1162 while (miicontrol & BMCR_RESET) {
1163 msleep(10);
1164 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1165 /* FIXME: 100 tries seem excessive */
1166 if (tries++ > 100)
1167 return -1;
1168 }
1169 return 0;
1170 }
1171
1172 static int phy_init(struct net_device *dev)
1173 {
1174 struct fe_priv *np = get_nvpriv(dev);
1175 u8 __iomem *base = get_hwbase(dev);
1176 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1177
1178 /* phy errata for E3016 phy */
1179 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1180 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1181 reg &= ~PHY_MARVELL_E3016_INITMASK;
1182 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1183 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1184 return PHY_ERROR;
1185 }
1186 }
1187 if (np->phy_oui == PHY_OUI_REALTEK) {
1188 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1189 np->phy_rev == PHY_REV_REALTEK_8211B) {
1190 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1191 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1192 return PHY_ERROR;
1193 }
1194 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1195 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1196 return PHY_ERROR;
1197 }
1198 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1199 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1200 return PHY_ERROR;
1201 }
1202 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1203 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1204 return PHY_ERROR;
1205 }
1206 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1207 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1208 return PHY_ERROR;
1209 }
1210 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1211 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1212 return PHY_ERROR;
1213 }
1214 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1215 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1216 return PHY_ERROR;
1217 }
1218 }
1219 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1220 np->phy_rev == PHY_REV_REALTEK_8211C) {
1221 u32 powerstate = readl(base + NvRegPowerState2);
1222
1223 /* need to perform hw phy reset */
1224 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1225 writel(powerstate, base + NvRegPowerState2);
1226 msleep(25);
1227
1228 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1229 writel(powerstate, base + NvRegPowerState2);
1230 msleep(25);
1231
1232 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1233 reg |= PHY_REALTEK_INIT9;
1234 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1235 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1236 return PHY_ERROR;
1237 }
1238 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1239 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1240 return PHY_ERROR;
1241 }
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1243 if (!(reg & PHY_REALTEK_INIT11)) {
1244 reg |= PHY_REALTEK_INIT11;
1245 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1246 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1247 return PHY_ERROR;
1248 }
1249 }
1250 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1251 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1252 return PHY_ERROR;
1253 }
1254 }
1255 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1256 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1257 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1258 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1259 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1260 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1261 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1262 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1263 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1264 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1265 phy_reserved |= PHY_REALTEK_INIT7;
1266 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1267 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1268 return PHY_ERROR;
1269 }
1270 }
1271 }
1272 }
1273
1274 /* set advertise register */
1275 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1276 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1277 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1278 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1279 return PHY_ERROR;
1280 }
1281
1282 /* get phy interface type */
1283 phyinterface = readl(base + NvRegPhyInterface);
1284
1285 /* see if gigabit phy */
1286 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1287 if (mii_status & PHY_GIGABIT) {
1288 np->gigabit = PHY_GIGABIT;
1289 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1290 mii_control_1000 &= ~ADVERTISE_1000HALF;
1291 if (phyinterface & PHY_RGMII)
1292 mii_control_1000 |= ADVERTISE_1000FULL;
1293 else
1294 mii_control_1000 &= ~ADVERTISE_1000FULL;
1295
1296 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1297 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1298 return PHY_ERROR;
1299 }
1300 }
1301 else
1302 np->gigabit = 0;
1303
1304 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1305 mii_control |= BMCR_ANENABLE;
1306
1307 if (np->phy_oui == PHY_OUI_REALTEK &&
1308 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1309 np->phy_rev == PHY_REV_REALTEK_8211C) {
1310 /* start autoneg since we already performed hw reset above */
1311 mii_control |= BMCR_ANRESTART;
1312 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1313 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1314 return PHY_ERROR;
1315 }
1316 } else {
1317 /* reset the phy
1318 * (certain phys need bmcr to be setup with reset)
1319 */
1320 if (phy_reset(dev, mii_control)) {
1321 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1322 return PHY_ERROR;
1323 }
1324 }
1325
1326 /* phy vendor specific configuration */
1327 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1328 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1329 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1330 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1331 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1332 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1333 return PHY_ERROR;
1334 }
1335 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1336 phy_reserved |= PHY_CICADA_INIT5;
1337 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1338 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1339 return PHY_ERROR;
1340 }
1341 }
1342 if (np->phy_oui == PHY_OUI_CICADA) {
1343 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1344 phy_reserved |= PHY_CICADA_INIT6;
1345 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1346 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1347 return PHY_ERROR;
1348 }
1349 }
1350 if (np->phy_oui == PHY_OUI_VITESSE) {
1351 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1352 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1353 return PHY_ERROR;
1354 }
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1356 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1357 return PHY_ERROR;
1358 }
1359 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1360 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1361 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1362 return PHY_ERROR;
1363 }
1364 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1365 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1366 phy_reserved |= PHY_VITESSE_INIT3;
1367 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1368 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369 return PHY_ERROR;
1370 }
1371 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1372 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1373 return PHY_ERROR;
1374 }
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1376 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1377 return PHY_ERROR;
1378 }
1379 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1380 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1381 phy_reserved |= PHY_VITESSE_INIT3;
1382 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1383 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1384 return PHY_ERROR;
1385 }
1386 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1387 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1388 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1389 return PHY_ERROR;
1390 }
1391 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1392 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1393 return PHY_ERROR;
1394 }
1395 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1396 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1397 return PHY_ERROR;
1398 }
1399 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1400 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1401 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1402 return PHY_ERROR;
1403 }
1404 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1405 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1406 phy_reserved |= PHY_VITESSE_INIT8;
1407 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1408 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1409 return PHY_ERROR;
1410 }
1411 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1412 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1413 return PHY_ERROR;
1414 }
1415 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1416 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1417 return PHY_ERROR;
1418 }
1419 }
1420 if (np->phy_oui == PHY_OUI_REALTEK) {
1421 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1422 np->phy_rev == PHY_REV_REALTEK_8211B) {
1423 /* reset could have cleared these out, set them back */
1424 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1425 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1426 return PHY_ERROR;
1427 }
1428 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1429 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1430 return PHY_ERROR;
1431 }
1432 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1433 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1434 return PHY_ERROR;
1435 }
1436 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1437 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1438 return PHY_ERROR;
1439 }
1440 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1441 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1442 return PHY_ERROR;
1443 }
1444 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1445 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1446 return PHY_ERROR;
1447 }
1448 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1449 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1450 return PHY_ERROR;
1451 }
1452 }
1453 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1454 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1455 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1456 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1457 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1458 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1459 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1460 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1461 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1462 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1463 phy_reserved |= PHY_REALTEK_INIT7;
1464 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1465 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1466 return PHY_ERROR;
1467 }
1468 }
1469 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1470 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1471 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1472 return PHY_ERROR;
1473 }
1474 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1475 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1476 phy_reserved |= PHY_REALTEK_INIT3;
1477 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1478 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1479 return PHY_ERROR;
1480 }
1481 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1482 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1483 return PHY_ERROR;
1484 }
1485 }
1486 }
1487 }
1488
1489 /* some phys clear out pause advertisment on reset, set it back */
1490 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1491
1492 /* restart auto negotiation, power down phy */
1493 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1494 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1495 if (phy_power_down) {
1496 mii_control |= BMCR_PDOWN;
1497 }
1498 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1499 return PHY_ERROR;
1500 }
1501
1502 return 0;
1503 }
1504
1505 static void nv_start_rx(struct net_device *dev)
1506 {
1507 struct fe_priv *np = netdev_priv(dev);
1508 u8 __iomem *base = get_hwbase(dev);
1509 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1510
1511 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1512 /* Already running? Stop it. */
1513 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1514 rx_ctrl &= ~NVREG_RCVCTL_START;
1515 writel(rx_ctrl, base + NvRegReceiverControl);
1516 pci_push(base);
1517 }
1518 writel(np->linkspeed, base + NvRegLinkSpeed);
1519 pci_push(base);
1520 rx_ctrl |= NVREG_RCVCTL_START;
1521 if (np->mac_in_use)
1522 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1523 writel(rx_ctrl, base + NvRegReceiverControl);
1524 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1525 dev->name, np->duplex, np->linkspeed);
1526 pci_push(base);
1527 }
1528
1529 static void nv_stop_rx(struct net_device *dev)
1530 {
1531 struct fe_priv *np = netdev_priv(dev);
1532 u8 __iomem *base = get_hwbase(dev);
1533 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1534
1535 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1536 if (!np->mac_in_use)
1537 rx_ctrl &= ~NVREG_RCVCTL_START;
1538 else
1539 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1540 writel(rx_ctrl, base + NvRegReceiverControl);
1541 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1542 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1543 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1544
1545 udelay(NV_RXSTOP_DELAY2);
1546 if (!np->mac_in_use)
1547 writel(0, base + NvRegLinkSpeed);
1548 }
1549
1550 static void nv_start_tx(struct net_device *dev)
1551 {
1552 struct fe_priv *np = netdev_priv(dev);
1553 u8 __iomem *base = get_hwbase(dev);
1554 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1555
1556 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1557 tx_ctrl |= NVREG_XMITCTL_START;
1558 if (np->mac_in_use)
1559 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1560 writel(tx_ctrl, base + NvRegTransmitterControl);
1561 pci_push(base);
1562 }
1563
1564 static void nv_stop_tx(struct net_device *dev)
1565 {
1566 struct fe_priv *np = netdev_priv(dev);
1567 u8 __iomem *base = get_hwbase(dev);
1568 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1569
1570 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1571 if (!np->mac_in_use)
1572 tx_ctrl &= ~NVREG_XMITCTL_START;
1573 else
1574 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1575 writel(tx_ctrl, base + NvRegTransmitterControl);
1576 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1577 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1578 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1579
1580 udelay(NV_TXSTOP_DELAY2);
1581 if (!np->mac_in_use)
1582 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1583 base + NvRegTransmitPoll);
1584 }
1585
1586 static void nv_start_rxtx(struct net_device *dev)
1587 {
1588 nv_start_rx(dev);
1589 nv_start_tx(dev);
1590 }
1591
1592 static void nv_stop_rxtx(struct net_device *dev)
1593 {
1594 nv_stop_rx(dev);
1595 nv_stop_tx(dev);
1596 }
1597
1598 static void nv_txrx_reset(struct net_device *dev)
1599 {
1600 struct fe_priv *np = netdev_priv(dev);
1601 u8 __iomem *base = get_hwbase(dev);
1602
1603 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1604 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1605 pci_push(base);
1606 udelay(NV_TXRX_RESET_DELAY);
1607 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1608 pci_push(base);
1609 }
1610
1611 static void nv_mac_reset(struct net_device *dev)
1612 {
1613 struct fe_priv *np = netdev_priv(dev);
1614 u8 __iomem *base = get_hwbase(dev);
1615 u32 temp1, temp2, temp3;
1616
1617 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1618
1619 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1620 pci_push(base);
1621
1622 /* save registers since they will be cleared on reset */
1623 temp1 = readl(base + NvRegMacAddrA);
1624 temp2 = readl(base + NvRegMacAddrB);
1625 temp3 = readl(base + NvRegTransmitPoll);
1626
1627 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1628 pci_push(base);
1629 udelay(NV_MAC_RESET_DELAY);
1630 writel(0, base + NvRegMacReset);
1631 pci_push(base);
1632 udelay(NV_MAC_RESET_DELAY);
1633
1634 /* restore saved registers */
1635 writel(temp1, base + NvRegMacAddrA);
1636 writel(temp2, base + NvRegMacAddrB);
1637 writel(temp3, base + NvRegTransmitPoll);
1638
1639 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1640 pci_push(base);
1641 }
1642
1643 static void nv_get_hw_stats(struct net_device *dev)
1644 {
1645 struct fe_priv *np = netdev_priv(dev);
1646 u8 __iomem *base = get_hwbase(dev);
1647
1648 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1649 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1650 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1651 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1652 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1653 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1654 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1655 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1656 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1657 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1658 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1659 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1660 np->estats.rx_runt += readl(base + NvRegRxRunt);
1661 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1662 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1663 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1664 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1665 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1666 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1667 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1668 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1669 np->estats.rx_packets =
1670 np->estats.rx_unicast +
1671 np->estats.rx_multicast +
1672 np->estats.rx_broadcast;
1673 np->estats.rx_errors_total =
1674 np->estats.rx_crc_errors +
1675 np->estats.rx_over_errors +
1676 np->estats.rx_frame_error +
1677 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1678 np->estats.rx_late_collision +
1679 np->estats.rx_runt +
1680 np->estats.rx_frame_too_long;
1681 np->estats.tx_errors_total =
1682 np->estats.tx_late_collision +
1683 np->estats.tx_fifo_errors +
1684 np->estats.tx_carrier_errors +
1685 np->estats.tx_excess_deferral +
1686 np->estats.tx_retry_error;
1687
1688 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1689 np->estats.tx_deferral += readl(base + NvRegTxDef);
1690 np->estats.tx_packets += readl(base + NvRegTxFrame);
1691 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1692 np->estats.tx_pause += readl(base + NvRegTxPause);
1693 np->estats.rx_pause += readl(base + NvRegRxPause);
1694 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1695 }
1696
1697 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1698 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1699 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1700 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1701 }
1702 }
1703
1704 /*
1705 * nv_get_stats: dev->get_stats function
1706 * Get latest stats value from the nic.
1707 * Called with read_lock(&dev_base_lock) held for read -
1708 * only synchronized against unregister_netdevice.
1709 */
1710 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1711 {
1712 struct fe_priv *np = netdev_priv(dev);
1713
1714 /* If the nic supports hw counters then retrieve latest values */
1715 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1716 nv_get_hw_stats(dev);
1717
1718 /* copy to net_device stats */
1719 dev->stats.tx_bytes = np->estats.tx_bytes;
1720 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1721 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1722 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1723 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1724 dev->stats.rx_errors = np->estats.rx_errors_total;
1725 dev->stats.tx_errors = np->estats.tx_errors_total;
1726 }
1727
1728 return &dev->stats;
1729 }
1730
1731 /*
1732 * nv_alloc_rx: fill rx ring entries.
1733 * Return 1 if the allocations for the skbs failed and the
1734 * rx engine is without Available descriptors
1735 */
1736 static int nv_alloc_rx(struct net_device *dev)
1737 {
1738 struct fe_priv *np = netdev_priv(dev);
1739 struct ring_desc* less_rx;
1740
1741 less_rx = np->get_rx.orig;
1742 if (less_rx-- == np->first_rx.orig)
1743 less_rx = np->last_rx.orig;
1744
1745 while (np->put_rx.orig != less_rx) {
1746 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1747 if (skb) {
1748 np->put_rx_ctx->skb = skb;
1749 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1750 skb->data,
1751 skb_tailroom(skb),
1752 PCI_DMA_FROMDEVICE);
1753 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1754 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1755 wmb();
1756 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1757 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1758 np->put_rx.orig = np->first_rx.orig;
1759 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1760 np->put_rx_ctx = np->first_rx_ctx;
1761 } else {
1762 return 1;
1763 }
1764 }
1765 return 0;
1766 }
1767
1768 static int nv_alloc_rx_optimized(struct net_device *dev)
1769 {
1770 struct fe_priv *np = netdev_priv(dev);
1771 struct ring_desc_ex* less_rx;
1772
1773 less_rx = np->get_rx.ex;
1774 if (less_rx-- == np->first_rx.ex)
1775 less_rx = np->last_rx.ex;
1776
1777 while (np->put_rx.ex != less_rx) {
1778 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1779 if (skb) {
1780 np->put_rx_ctx->skb = skb;
1781 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1782 skb->data,
1783 skb_tailroom(skb),
1784 PCI_DMA_FROMDEVICE);
1785 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1786 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1787 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1788 wmb();
1789 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1790 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1791 np->put_rx.ex = np->first_rx.ex;
1792 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1793 np->put_rx_ctx = np->first_rx_ctx;
1794 } else {
1795 return 1;
1796 }
1797 }
1798 return 0;
1799 }
1800
1801 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1802 #ifdef CONFIG_FORCEDETH_NAPI
1803 static void nv_do_rx_refill(unsigned long data)
1804 {
1805 struct net_device *dev = (struct net_device *) data;
1806 struct fe_priv *np = netdev_priv(dev);
1807
1808 /* Just reschedule NAPI rx processing */
1809 napi_schedule(&np->napi);
1810 }
1811 #else
1812 static void nv_do_rx_refill(unsigned long data)
1813 {
1814 struct net_device *dev = (struct net_device *) data;
1815 struct fe_priv *np = netdev_priv(dev);
1816 int retcode;
1817
1818 if (!using_multi_irqs(dev)) {
1819 if (np->msi_flags & NV_MSI_X_ENABLED)
1820 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1821 else
1822 disable_irq(np->pci_dev->irq);
1823 } else {
1824 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1825 }
1826 if (!nv_optimized(np))
1827 retcode = nv_alloc_rx(dev);
1828 else
1829 retcode = nv_alloc_rx_optimized(dev);
1830 if (retcode) {
1831 spin_lock_irq(&np->lock);
1832 if (!np->in_shutdown)
1833 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1834 spin_unlock_irq(&np->lock);
1835 }
1836 if (!using_multi_irqs(dev)) {
1837 if (np->msi_flags & NV_MSI_X_ENABLED)
1838 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1839 else
1840 enable_irq(np->pci_dev->irq);
1841 } else {
1842 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1843 }
1844 }
1845 #endif
1846
1847 static void nv_init_rx(struct net_device *dev)
1848 {
1849 struct fe_priv *np = netdev_priv(dev);
1850 int i;
1851
1852 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1853
1854 if (!nv_optimized(np))
1855 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1856 else
1857 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1858 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1859 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1860
1861 for (i = 0; i < np->rx_ring_size; i++) {
1862 if (!nv_optimized(np)) {
1863 np->rx_ring.orig[i].flaglen = 0;
1864 np->rx_ring.orig[i].buf = 0;
1865 } else {
1866 np->rx_ring.ex[i].flaglen = 0;
1867 np->rx_ring.ex[i].txvlan = 0;
1868 np->rx_ring.ex[i].bufhigh = 0;
1869 np->rx_ring.ex[i].buflow = 0;
1870 }
1871 np->rx_skb[i].skb = NULL;
1872 np->rx_skb[i].dma = 0;
1873 }
1874 }
1875
1876 static void nv_init_tx(struct net_device *dev)
1877 {
1878 struct fe_priv *np = netdev_priv(dev);
1879 int i;
1880
1881 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1882
1883 if (!nv_optimized(np))
1884 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1885 else
1886 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1887 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1888 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1889 np->tx_pkts_in_progress = 0;
1890 np->tx_change_owner = NULL;
1891 np->tx_end_flip = NULL;
1892 np->tx_stop = 0;
1893
1894 for (i = 0; i < np->tx_ring_size; i++) {
1895 if (!nv_optimized(np)) {
1896 np->tx_ring.orig[i].flaglen = 0;
1897 np->tx_ring.orig[i].buf = 0;
1898 } else {
1899 np->tx_ring.ex[i].flaglen = 0;
1900 np->tx_ring.ex[i].txvlan = 0;
1901 np->tx_ring.ex[i].bufhigh = 0;
1902 np->tx_ring.ex[i].buflow = 0;
1903 }
1904 np->tx_skb[i].skb = NULL;
1905 np->tx_skb[i].dma = 0;
1906 np->tx_skb[i].dma_len = 0;
1907 np->tx_skb[i].first_tx_desc = NULL;
1908 np->tx_skb[i].next_tx_ctx = NULL;
1909 }
1910 }
1911
1912 static int nv_init_ring(struct net_device *dev)
1913 {
1914 struct fe_priv *np = netdev_priv(dev);
1915
1916 nv_init_tx(dev);
1917 nv_init_rx(dev);
1918
1919 if (!nv_optimized(np))
1920 return nv_alloc_rx(dev);
1921 else
1922 return nv_alloc_rx_optimized(dev);
1923 }
1924
1925 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1926 {
1927 struct fe_priv *np = netdev_priv(dev);
1928
1929 if (tx_skb->dma) {
1930 pci_unmap_page(np->pci_dev, tx_skb->dma,
1931 tx_skb->dma_len,
1932 PCI_DMA_TODEVICE);
1933 tx_skb->dma = 0;
1934 }
1935 if (tx_skb->skb) {
1936 dev_kfree_skb_any(tx_skb->skb);
1937 tx_skb->skb = NULL;
1938 return 1;
1939 } else {
1940 return 0;
1941 }
1942 }
1943
1944 static void nv_drain_tx(struct net_device *dev)
1945 {
1946 struct fe_priv *np = netdev_priv(dev);
1947 unsigned int i;
1948
1949 for (i = 0; i < np->tx_ring_size; i++) {
1950 if (!nv_optimized(np)) {
1951 np->tx_ring.orig[i].flaglen = 0;
1952 np->tx_ring.orig[i].buf = 0;
1953 } else {
1954 np->tx_ring.ex[i].flaglen = 0;
1955 np->tx_ring.ex[i].txvlan = 0;
1956 np->tx_ring.ex[i].bufhigh = 0;
1957 np->tx_ring.ex[i].buflow = 0;
1958 }
1959 if (nv_release_txskb(dev, &np->tx_skb[i]))
1960 dev->stats.tx_dropped++;
1961 np->tx_skb[i].dma = 0;
1962 np->tx_skb[i].dma_len = 0;
1963 np->tx_skb[i].first_tx_desc = NULL;
1964 np->tx_skb[i].next_tx_ctx = NULL;
1965 }
1966 np->tx_pkts_in_progress = 0;
1967 np->tx_change_owner = NULL;
1968 np->tx_end_flip = NULL;
1969 }
1970
1971 static void nv_drain_rx(struct net_device *dev)
1972 {
1973 struct fe_priv *np = netdev_priv(dev);
1974 int i;
1975
1976 for (i = 0; i < np->rx_ring_size; i++) {
1977 if (!nv_optimized(np)) {
1978 np->rx_ring.orig[i].flaglen = 0;
1979 np->rx_ring.orig[i].buf = 0;
1980 } else {
1981 np->rx_ring.ex[i].flaglen = 0;
1982 np->rx_ring.ex[i].txvlan = 0;
1983 np->rx_ring.ex[i].bufhigh = 0;
1984 np->rx_ring.ex[i].buflow = 0;
1985 }
1986 wmb();
1987 if (np->rx_skb[i].skb) {
1988 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1989 (skb_end_pointer(np->rx_skb[i].skb) -
1990 np->rx_skb[i].skb->data),
1991 PCI_DMA_FROMDEVICE);
1992 dev_kfree_skb(np->rx_skb[i].skb);
1993 np->rx_skb[i].skb = NULL;
1994 }
1995 }
1996 }
1997
1998 static void nv_drain_rxtx(struct net_device *dev)
1999 {
2000 nv_drain_tx(dev);
2001 nv_drain_rx(dev);
2002 }
2003
2004 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2005 {
2006 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2007 }
2008
2009 static void nv_legacybackoff_reseed(struct net_device *dev)
2010 {
2011 u8 __iomem *base = get_hwbase(dev);
2012 u32 reg;
2013 u32 low;
2014 int tx_status = 0;
2015
2016 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2017 get_random_bytes(&low, sizeof(low));
2018 reg |= low & NVREG_SLOTTIME_MASK;
2019
2020 /* Need to stop tx before change takes effect.
2021 * Caller has already gained np->lock.
2022 */
2023 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2024 if (tx_status)
2025 nv_stop_tx(dev);
2026 nv_stop_rx(dev);
2027 writel(reg, base + NvRegSlotTime);
2028 if (tx_status)
2029 nv_start_tx(dev);
2030 nv_start_rx(dev);
2031 }
2032
2033 /* Gear Backoff Seeds */
2034 #define BACKOFF_SEEDSET_ROWS 8
2035 #define BACKOFF_SEEDSET_LFSRS 15
2036
2037 /* Known Good seed sets */
2038 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2039 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2040 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2041 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2042 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2043 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2044 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2045 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2046 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2047
2048 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2049 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2050 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2051 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2052 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2053 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2054 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2055 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2056 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2057
2058 static void nv_gear_backoff_reseed(struct net_device *dev)
2059 {
2060 u8 __iomem *base = get_hwbase(dev);
2061 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2062 u32 temp, seedset, combinedSeed;
2063 int i;
2064
2065 /* Setup seed for free running LFSR */
2066 /* We are going to read the time stamp counter 3 times
2067 and swizzle bits around to increase randomness */
2068 get_random_bytes(&miniseed1, sizeof(miniseed1));
2069 miniseed1 &= 0x0fff;
2070 if (miniseed1 == 0)
2071 miniseed1 = 0xabc;
2072
2073 get_random_bytes(&miniseed2, sizeof(miniseed2));
2074 miniseed2 &= 0x0fff;
2075 if (miniseed2 == 0)
2076 miniseed2 = 0xabc;
2077 miniseed2_reversed =
2078 ((miniseed2 & 0xF00) >> 8) |
2079 (miniseed2 & 0x0F0) |
2080 ((miniseed2 & 0x00F) << 8);
2081
2082 get_random_bytes(&miniseed3, sizeof(miniseed3));
2083 miniseed3 &= 0x0fff;
2084 if (miniseed3 == 0)
2085 miniseed3 = 0xabc;
2086 miniseed3_reversed =
2087 ((miniseed3 & 0xF00) >> 8) |
2088 (miniseed3 & 0x0F0) |
2089 ((miniseed3 & 0x00F) << 8);
2090
2091 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2092 (miniseed2 ^ miniseed3_reversed);
2093
2094 /* Seeds can not be zero */
2095 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2096 combinedSeed |= 0x08;
2097 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2098 combinedSeed |= 0x8000;
2099
2100 /* No need to disable tx here */
2101 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2102 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2103 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2104 writel(temp,base + NvRegBackOffControl);
2105
2106 /* Setup seeds for all gear LFSRs. */
2107 get_random_bytes(&seedset, sizeof(seedset));
2108 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2109 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2110 {
2111 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2112 temp |= main_seedset[seedset][i-1] & 0x3ff;
2113 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2114 writel(temp, base + NvRegBackOffControl);
2115 }
2116 }
2117
2118 /*
2119 * nv_start_xmit: dev->hard_start_xmit function
2120 * Called with netif_tx_lock held.
2121 */
2122 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2123 {
2124 struct fe_priv *np = netdev_priv(dev);
2125 u32 tx_flags = 0;
2126 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2127 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2128 unsigned int i;
2129 u32 offset = 0;
2130 u32 bcnt;
2131 u32 size = skb->len-skb->data_len;
2132 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2133 u32 empty_slots;
2134 struct ring_desc* put_tx;
2135 struct ring_desc* start_tx;
2136 struct ring_desc* prev_tx;
2137 struct nv_skb_map* prev_tx_ctx;
2138 unsigned long flags;
2139
2140 /* add fragments to entries count */
2141 for (i = 0; i < fragments; i++) {
2142 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2143 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2144 }
2145
2146 spin_lock_irqsave(&np->lock, flags);
2147 empty_slots = nv_get_empty_tx_slots(np);
2148 if (unlikely(empty_slots <= entries)) {
2149 netif_stop_queue(dev);
2150 np->tx_stop = 1;
2151 spin_unlock_irqrestore(&np->lock, flags);
2152 return NETDEV_TX_BUSY;
2153 }
2154 spin_unlock_irqrestore(&np->lock, flags);
2155
2156 start_tx = put_tx = np->put_tx.orig;
2157
2158 /* setup the header buffer */
2159 do {
2160 prev_tx = put_tx;
2161 prev_tx_ctx = np->put_tx_ctx;
2162 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2163 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2164 PCI_DMA_TODEVICE);
2165 np->put_tx_ctx->dma_len = bcnt;
2166 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2167 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2168
2169 tx_flags = np->tx_flags;
2170 offset += bcnt;
2171 size -= bcnt;
2172 if (unlikely(put_tx++ == np->last_tx.orig))
2173 put_tx = np->first_tx.orig;
2174 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2175 np->put_tx_ctx = np->first_tx_ctx;
2176 } while (size);
2177
2178 /* setup the fragments */
2179 for (i = 0; i < fragments; i++) {
2180 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2181 u32 size = frag->size;
2182 offset = 0;
2183
2184 do {
2185 prev_tx = put_tx;
2186 prev_tx_ctx = np->put_tx_ctx;
2187 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2188 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2189 PCI_DMA_TODEVICE);
2190 np->put_tx_ctx->dma_len = bcnt;
2191 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2192 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2193
2194 offset += bcnt;
2195 size -= bcnt;
2196 if (unlikely(put_tx++ == np->last_tx.orig))
2197 put_tx = np->first_tx.orig;
2198 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2199 np->put_tx_ctx = np->first_tx_ctx;
2200 } while (size);
2201 }
2202
2203 /* set last fragment flag */
2204 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2205
2206 /* save skb in this slot's context area */
2207 prev_tx_ctx->skb = skb;
2208
2209 if (skb_is_gso(skb))
2210 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2211 else
2212 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2213 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2214
2215 spin_lock_irqsave(&np->lock, flags);
2216
2217 /* set tx flags */
2218 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2219 np->put_tx.orig = put_tx;
2220
2221 spin_unlock_irqrestore(&np->lock, flags);
2222
2223 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2224 dev->name, entries, tx_flags_extra);
2225 {
2226 int j;
2227 for (j=0; j<64; j++) {
2228 if ((j%16) == 0)
2229 dprintk("\n%03x:", j);
2230 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2231 }
2232 dprintk("\n");
2233 }
2234
2235 dev->trans_start = jiffies;
2236 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2237 return NETDEV_TX_OK;
2238 }
2239
2240 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2241 {
2242 struct fe_priv *np = netdev_priv(dev);
2243 u32 tx_flags = 0;
2244 u32 tx_flags_extra;
2245 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2246 unsigned int i;
2247 u32 offset = 0;
2248 u32 bcnt;
2249 u32 size = skb->len-skb->data_len;
2250 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2251 u32 empty_slots;
2252 struct ring_desc_ex* put_tx;
2253 struct ring_desc_ex* start_tx;
2254 struct ring_desc_ex* prev_tx;
2255 struct nv_skb_map* prev_tx_ctx;
2256 struct nv_skb_map* start_tx_ctx;
2257 unsigned long flags;
2258
2259 /* add fragments to entries count */
2260 for (i = 0; i < fragments; i++) {
2261 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2262 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2263 }
2264
2265 spin_lock_irqsave(&np->lock, flags);
2266 empty_slots = nv_get_empty_tx_slots(np);
2267 if (unlikely(empty_slots <= entries)) {
2268 netif_stop_queue(dev);
2269 np->tx_stop = 1;
2270 spin_unlock_irqrestore(&np->lock, flags);
2271 return NETDEV_TX_BUSY;
2272 }
2273 spin_unlock_irqrestore(&np->lock, flags);
2274
2275 start_tx = put_tx = np->put_tx.ex;
2276 start_tx_ctx = np->put_tx_ctx;
2277
2278 /* setup the header buffer */
2279 do {
2280 prev_tx = put_tx;
2281 prev_tx_ctx = np->put_tx_ctx;
2282 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2283 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2284 PCI_DMA_TODEVICE);
2285 np->put_tx_ctx->dma_len = bcnt;
2286 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2287 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2288 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2289
2290 tx_flags = NV_TX2_VALID;
2291 offset += bcnt;
2292 size -= bcnt;
2293 if (unlikely(put_tx++ == np->last_tx.ex))
2294 put_tx = np->first_tx.ex;
2295 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2296 np->put_tx_ctx = np->first_tx_ctx;
2297 } while (size);
2298
2299 /* setup the fragments */
2300 for (i = 0; i < fragments; i++) {
2301 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2302 u32 size = frag->size;
2303 offset = 0;
2304
2305 do {
2306 prev_tx = put_tx;
2307 prev_tx_ctx = np->put_tx_ctx;
2308 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2309 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2310 PCI_DMA_TODEVICE);
2311 np->put_tx_ctx->dma_len = bcnt;
2312 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2313 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2314 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2315
2316 offset += bcnt;
2317 size -= bcnt;
2318 if (unlikely(put_tx++ == np->last_tx.ex))
2319 put_tx = np->first_tx.ex;
2320 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2321 np->put_tx_ctx = np->first_tx_ctx;
2322 } while (size);
2323 }
2324
2325 /* set last fragment flag */
2326 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2327
2328 /* save skb in this slot's context area */
2329 prev_tx_ctx->skb = skb;
2330
2331 if (skb_is_gso(skb))
2332 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2333 else
2334 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2335 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2336
2337 /* vlan tag */
2338 if (likely(!np->vlangrp)) {
2339 start_tx->txvlan = 0;
2340 } else {
2341 if (vlan_tx_tag_present(skb))
2342 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2343 else
2344 start_tx->txvlan = 0;
2345 }
2346
2347 spin_lock_irqsave(&np->lock, flags);
2348
2349 if (np->tx_limit) {
2350 /* Limit the number of outstanding tx. Setup all fragments, but
2351 * do not set the VALID bit on the first descriptor. Save a pointer
2352 * to that descriptor and also for next skb_map element.
2353 */
2354
2355 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2356 if (!np->tx_change_owner)
2357 np->tx_change_owner = start_tx_ctx;
2358
2359 /* remove VALID bit */
2360 tx_flags &= ~NV_TX2_VALID;
2361 start_tx_ctx->first_tx_desc = start_tx;
2362 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2363 np->tx_end_flip = np->put_tx_ctx;
2364 } else {
2365 np->tx_pkts_in_progress++;
2366 }
2367 }
2368
2369 /* set tx flags */
2370 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2371 np->put_tx.ex = put_tx;
2372
2373 spin_unlock_irqrestore(&np->lock, flags);
2374
2375 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2376 dev->name, entries, tx_flags_extra);
2377 {
2378 int j;
2379 for (j=0; j<64; j++) {
2380 if ((j%16) == 0)
2381 dprintk("\n%03x:", j);
2382 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2383 }
2384 dprintk("\n");
2385 }
2386
2387 dev->trans_start = jiffies;
2388 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2389 return NETDEV_TX_OK;
2390 }
2391
2392 static inline void nv_tx_flip_ownership(struct net_device *dev)
2393 {
2394 struct fe_priv *np = netdev_priv(dev);
2395
2396 np->tx_pkts_in_progress--;
2397 if (np->tx_change_owner) {
2398 np->tx_change_owner->first_tx_desc->flaglen |=
2399 cpu_to_le32(NV_TX2_VALID);
2400 np->tx_pkts_in_progress++;
2401
2402 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2403 if (np->tx_change_owner == np->tx_end_flip)
2404 np->tx_change_owner = NULL;
2405
2406 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2407 }
2408 }
2409
2410 /*
2411 * nv_tx_done: check for completed packets, release the skbs.
2412 *
2413 * Caller must own np->lock.
2414 */
2415 static int nv_tx_done(struct net_device *dev, int limit)
2416 {
2417 struct fe_priv *np = netdev_priv(dev);
2418 u32 flags;
2419 int tx_work = 0;
2420 struct ring_desc* orig_get_tx = np->get_tx.orig;
2421
2422 while ((np->get_tx.orig != np->put_tx.orig) &&
2423 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2424 (tx_work < limit)) {
2425
2426 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2427 dev->name, flags);
2428
2429 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2430 np->get_tx_ctx->dma_len,
2431 PCI_DMA_TODEVICE);
2432 np->get_tx_ctx->dma = 0;
2433
2434 if (np->desc_ver == DESC_VER_1) {
2435 if (flags & NV_TX_LASTPACKET) {
2436 if (flags & NV_TX_ERROR) {
2437 if (flags & NV_TX_UNDERFLOW)
2438 dev->stats.tx_fifo_errors++;
2439 if (flags & NV_TX_CARRIERLOST)
2440 dev->stats.tx_carrier_errors++;
2441 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2442 nv_legacybackoff_reseed(dev);
2443 dev->stats.tx_errors++;
2444 } else {
2445 dev->stats.tx_packets++;
2446 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2447 }
2448 dev_kfree_skb_any(np->get_tx_ctx->skb);
2449 np->get_tx_ctx->skb = NULL;
2450 tx_work++;
2451 }
2452 } else {
2453 if (flags & NV_TX2_LASTPACKET) {
2454 if (flags & NV_TX2_ERROR) {
2455 if (flags & NV_TX2_UNDERFLOW)
2456 dev->stats.tx_fifo_errors++;
2457 if (flags & NV_TX2_CARRIERLOST)
2458 dev->stats.tx_carrier_errors++;
2459 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2460 nv_legacybackoff_reseed(dev);
2461 dev->stats.tx_errors++;
2462 } else {
2463 dev->stats.tx_packets++;
2464 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2465 }
2466 dev_kfree_skb_any(np->get_tx_ctx->skb);
2467 np->get_tx_ctx->skb = NULL;
2468 tx_work++;
2469 }
2470 }
2471 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2472 np->get_tx.orig = np->first_tx.orig;
2473 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2474 np->get_tx_ctx = np->first_tx_ctx;
2475 }
2476 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2477 np->tx_stop = 0;
2478 netif_wake_queue(dev);
2479 }
2480 return tx_work;
2481 }
2482
2483 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2484 {
2485 struct fe_priv *np = netdev_priv(dev);
2486 u32 flags;
2487 int tx_work = 0;
2488 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2489
2490 while ((np->get_tx.ex != np->put_tx.ex) &&
2491 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2492 (tx_work < limit)) {
2493
2494 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2495 dev->name, flags);
2496
2497 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2498 np->get_tx_ctx->dma_len,
2499 PCI_DMA_TODEVICE);
2500 np->get_tx_ctx->dma = 0;
2501
2502 if (flags & NV_TX2_LASTPACKET) {
2503 if (!(flags & NV_TX2_ERROR))
2504 dev->stats.tx_packets++;
2505 else {
2506 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2507 if (np->driver_data & DEV_HAS_GEAR_MODE)
2508 nv_gear_backoff_reseed(dev);
2509 else
2510 nv_legacybackoff_reseed(dev);
2511 }
2512 }
2513
2514 dev_kfree_skb_any(np->get_tx_ctx->skb);
2515 np->get_tx_ctx->skb = NULL;
2516 tx_work++;
2517
2518 if (np->tx_limit) {
2519 nv_tx_flip_ownership(dev);
2520 }
2521 }
2522 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2523 np->get_tx.ex = np->first_tx.ex;
2524 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2525 np->get_tx_ctx = np->first_tx_ctx;
2526 }
2527 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2528 np->tx_stop = 0;
2529 netif_wake_queue(dev);
2530 }
2531 return tx_work;
2532 }
2533
2534 /*
2535 * nv_tx_timeout: dev->tx_timeout function
2536 * Called with netif_tx_lock held.
2537 */
2538 static void nv_tx_timeout(struct net_device *dev)
2539 {
2540 struct fe_priv *np = netdev_priv(dev);
2541 u8 __iomem *base = get_hwbase(dev);
2542 u32 status;
2543 union ring_type put_tx;
2544 int saved_tx_limit;
2545
2546 if (np->msi_flags & NV_MSI_X_ENABLED)
2547 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2548 else
2549 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2550
2551 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2552
2553 {
2554 int i;
2555
2556 printk(KERN_INFO "%s: Ring at %lx\n",
2557 dev->name, (unsigned long)np->ring_addr);
2558 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2559 for (i=0;i<=np->register_size;i+= 32) {
2560 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2561 i,
2562 readl(base + i + 0), readl(base + i + 4),
2563 readl(base + i + 8), readl(base + i + 12),
2564 readl(base + i + 16), readl(base + i + 20),
2565 readl(base + i + 24), readl(base + i + 28));
2566 }
2567 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2568 for (i=0;i<np->tx_ring_size;i+= 4) {
2569 if (!nv_optimized(np)) {
2570 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2571 i,
2572 le32_to_cpu(np->tx_ring.orig[i].buf),
2573 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2574 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2575 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2576 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2577 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2578 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2579 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2580 } else {
2581 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2582 i,
2583 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2584 le32_to_cpu(np->tx_ring.ex[i].buflow),
2585 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2586 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2587 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2588 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2589 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2590 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2591 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2592 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2593 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2594 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2595 }
2596 }
2597 }
2598
2599 spin_lock_irq(&np->lock);
2600
2601 /* 1) stop tx engine */
2602 nv_stop_tx(dev);
2603
2604 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2605 saved_tx_limit = np->tx_limit;
2606 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2607 np->tx_stop = 0; /* prevent waking tx queue */
2608 if (!nv_optimized(np))
2609 nv_tx_done(dev, np->tx_ring_size);
2610 else
2611 nv_tx_done_optimized(dev, np->tx_ring_size);
2612
2613 /* save current HW postion */
2614 if (np->tx_change_owner)
2615 put_tx.ex = np->tx_change_owner->first_tx_desc;
2616 else
2617 put_tx = np->put_tx;
2618
2619 /* 3) clear all tx state */
2620 nv_drain_tx(dev);
2621 nv_init_tx(dev);
2622
2623 /* 4) restore state to current HW position */
2624 np->get_tx = np->put_tx = put_tx;
2625 np->tx_limit = saved_tx_limit;
2626
2627 /* 5) restart tx engine */
2628 nv_start_tx(dev);
2629 netif_wake_queue(dev);
2630 spin_unlock_irq(&np->lock);
2631 }
2632
2633 /*
2634 * Called when the nic notices a mismatch between the actual data len on the
2635 * wire and the len indicated in the 802 header
2636 */
2637 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2638 {
2639 int hdrlen; /* length of the 802 header */
2640 int protolen; /* length as stored in the proto field */
2641
2642 /* 1) calculate len according to header */
2643 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2644 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2645 hdrlen = VLAN_HLEN;
2646 } else {
2647 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2648 hdrlen = ETH_HLEN;
2649 }
2650 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2651 dev->name, datalen, protolen, hdrlen);
2652 if (protolen > ETH_DATA_LEN)
2653 return datalen; /* Value in proto field not a len, no checks possible */
2654
2655 protolen += hdrlen;
2656 /* consistency checks: */
2657 if (datalen > ETH_ZLEN) {
2658 if (datalen >= protolen) {
2659 /* more data on wire than in 802 header, trim of
2660 * additional data.
2661 */
2662 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2663 dev->name, protolen);
2664 return protolen;
2665 } else {
2666 /* less data on wire than mentioned in header.
2667 * Discard the packet.
2668 */
2669 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2670 dev->name);
2671 return -1;
2672 }
2673 } else {
2674 /* short packet. Accept only if 802 values are also short */
2675 if (protolen > ETH_ZLEN) {
2676 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2677 dev->name);
2678 return -1;
2679 }
2680 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2681 dev->name, datalen);
2682 return datalen;
2683 }
2684 }
2685
2686 static int nv_rx_process(struct net_device *dev, int limit)
2687 {
2688 struct fe_priv *np = netdev_priv(dev);
2689 u32 flags;
2690 int rx_work = 0;
2691 struct sk_buff *skb;
2692 int len;
2693
2694 while((np->get_rx.orig != np->put_rx.orig) &&
2695 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2696 (rx_work < limit)) {
2697
2698 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2699 dev->name, flags);
2700
2701 /*
2702 * the packet is for us - immediately tear down the pci mapping.
2703 * TODO: check if a prefetch of the first cacheline improves
2704 * the performance.
2705 */
2706 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2707 np->get_rx_ctx->dma_len,
2708 PCI_DMA_FROMDEVICE);
2709 skb = np->get_rx_ctx->skb;
2710 np->get_rx_ctx->skb = NULL;
2711
2712 {
2713 int j;
2714 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2715 for (j=0; j<64; j++) {
2716 if ((j%16) == 0)
2717 dprintk("\n%03x:", j);
2718 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2719 }
2720 dprintk("\n");
2721 }
2722 /* look at what we actually got: */
2723 if (np->desc_ver == DESC_VER_1) {
2724 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2725 len = flags & LEN_MASK_V1;
2726 if (unlikely(flags & NV_RX_ERROR)) {
2727 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2728 len = nv_getlen(dev, skb->data, len);
2729 if (len < 0) {
2730 dev->stats.rx_errors++;
2731 dev_kfree_skb(skb);
2732 goto next_pkt;
2733 }
2734 }
2735 /* framing errors are soft errors */
2736 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2737 if (flags & NV_RX_SUBSTRACT1) {
2738 len--;
2739 }
2740 }
2741 /* the rest are hard errors */
2742 else {
2743 if (flags & NV_RX_MISSEDFRAME)
2744 dev->stats.rx_missed_errors++;
2745 if (flags & NV_RX_CRCERR)
2746 dev->stats.rx_crc_errors++;
2747 if (flags & NV_RX_OVERFLOW)
2748 dev->stats.rx_over_errors++;
2749 dev->stats.rx_errors++;
2750 dev_kfree_skb(skb);
2751 goto next_pkt;
2752 }
2753 }
2754 } else {
2755 dev_kfree_skb(skb);
2756 goto next_pkt;
2757 }
2758 } else {
2759 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2760 len = flags & LEN_MASK_V2;
2761 if (unlikely(flags & NV_RX2_ERROR)) {
2762 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2763 len = nv_getlen(dev, skb->data, len);
2764 if (len < 0) {
2765 dev->stats.rx_errors++;
2766 dev_kfree_skb(skb);
2767 goto next_pkt;
2768 }
2769 }
2770 /* framing errors are soft errors */
2771 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2772 if (flags & NV_RX2_SUBSTRACT1) {
2773 len--;
2774 }
2775 }
2776 /* the rest are hard errors */
2777 else {
2778 if (flags & NV_RX2_CRCERR)
2779 dev->stats.rx_crc_errors++;
2780 if (flags & NV_RX2_OVERFLOW)
2781 dev->stats.rx_over_errors++;
2782 dev->stats.rx_errors++;
2783 dev_kfree_skb(skb);
2784 goto next_pkt;
2785 }
2786 }
2787 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2788 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2789 skb->ip_summed = CHECKSUM_UNNECESSARY;
2790 } else {
2791 dev_kfree_skb(skb);
2792 goto next_pkt;
2793 }
2794 }
2795 /* got a valid packet - forward it to the network core */
2796 skb_put(skb, len);
2797 skb->protocol = eth_type_trans(skb, dev);
2798 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2799 dev->name, len, skb->protocol);
2800 #ifdef CONFIG_FORCEDETH_NAPI
2801 netif_receive_skb(skb);
2802 #else
2803 netif_rx(skb);
2804 #endif
2805 dev->stats.rx_packets++;
2806 dev->stats.rx_bytes += len;
2807 next_pkt:
2808 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2809 np->get_rx.orig = np->first_rx.orig;
2810 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2811 np->get_rx_ctx = np->first_rx_ctx;
2812
2813 rx_work++;
2814 }
2815
2816 return rx_work;
2817 }
2818
2819 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2820 {
2821 struct fe_priv *np = netdev_priv(dev);
2822 u32 flags;
2823 u32 vlanflags = 0;
2824 int rx_work = 0;
2825 struct sk_buff *skb;
2826 int len;
2827
2828 while((np->get_rx.ex != np->put_rx.ex) &&
2829 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2830 (rx_work < limit)) {
2831
2832 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2833 dev->name, flags);
2834
2835 /*
2836 * the packet is for us - immediately tear down the pci mapping.
2837 * TODO: check if a prefetch of the first cacheline improves
2838 * the performance.
2839 */
2840 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2841 np->get_rx_ctx->dma_len,
2842 PCI_DMA_FROMDEVICE);
2843 skb = np->get_rx_ctx->skb;
2844 np->get_rx_ctx->skb = NULL;
2845
2846 {
2847 int j;
2848 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2849 for (j=0; j<64; j++) {
2850 if ((j%16) == 0)
2851 dprintk("\n%03x:", j);
2852 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2853 }
2854 dprintk("\n");
2855 }
2856 /* look at what we actually got: */
2857 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2858 len = flags & LEN_MASK_V2;
2859 if (unlikely(flags & NV_RX2_ERROR)) {
2860 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2861 len = nv_getlen(dev, skb->data, len);
2862 if (len < 0) {
2863 dev_kfree_skb(skb);
2864 goto next_pkt;
2865 }
2866 }
2867 /* framing errors are soft errors */
2868 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2869 if (flags & NV_RX2_SUBSTRACT1) {
2870 len--;
2871 }
2872 }
2873 /* the rest are hard errors */
2874 else {
2875 dev_kfree_skb(skb);
2876 goto next_pkt;
2877 }
2878 }
2879
2880 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2881 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2882 skb->ip_summed = CHECKSUM_UNNECESSARY;
2883
2884 /* got a valid packet - forward it to the network core */
2885 skb_put(skb, len);
2886 skb->protocol = eth_type_trans(skb, dev);
2887 prefetch(skb->data);
2888
2889 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2890 dev->name, len, skb->protocol);
2891
2892 if (likely(!np->vlangrp)) {
2893 #ifdef CONFIG_FORCEDETH_NAPI
2894 netif_receive_skb(skb);
2895 #else
2896 netif_rx(skb);
2897 #endif
2898 } else {
2899 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2900 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2901 #ifdef CONFIG_FORCEDETH_NAPI
2902 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2903 vlanflags & NV_RX3_VLAN_TAG_MASK);
2904 #else
2905 vlan_hwaccel_rx(skb, np->vlangrp,
2906 vlanflags & NV_RX3_VLAN_TAG_MASK);
2907 #endif
2908 } else {
2909 #ifdef CONFIG_FORCEDETH_NAPI
2910 netif_receive_skb(skb);
2911 #else
2912 netif_rx(skb);
2913 #endif
2914 }
2915 }
2916
2917 dev->stats.rx_packets++;
2918 dev->stats.rx_bytes += len;
2919 } else {
2920 dev_kfree_skb(skb);
2921 }
2922 next_pkt:
2923 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2924 np->get_rx.ex = np->first_rx.ex;
2925 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2926 np->get_rx_ctx = np->first_rx_ctx;
2927
2928 rx_work++;
2929 }
2930
2931 return rx_work;
2932 }
2933
2934 static void set_bufsize(struct net_device *dev)
2935 {
2936 struct fe_priv *np = netdev_priv(dev);
2937
2938 if (dev->mtu <= ETH_DATA_LEN)
2939 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2940 else
2941 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2942 }
2943
2944 /*
2945 * nv_change_mtu: dev->change_mtu function
2946 * Called with dev_base_lock held for read.
2947 */
2948 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2949 {
2950 struct fe_priv *np = netdev_priv(dev);
2951 int old_mtu;
2952
2953 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2954 return -EINVAL;
2955
2956 old_mtu = dev->mtu;
2957 dev->mtu = new_mtu;
2958
2959 /* return early if the buffer sizes will not change */
2960 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2961 return 0;
2962 if (old_mtu == new_mtu)
2963 return 0;
2964
2965 /* synchronized against open : rtnl_lock() held by caller */
2966 if (netif_running(dev)) {
2967 u8 __iomem *base = get_hwbase(dev);
2968 /*
2969 * It seems that the nic preloads valid ring entries into an
2970 * internal buffer. The procedure for flushing everything is
2971 * guessed, there is probably a simpler approach.
2972 * Changing the MTU is a rare event, it shouldn't matter.
2973 */
2974 nv_disable_irq(dev);
2975 nv_napi_disable(dev);
2976 netif_tx_lock_bh(dev);
2977 netif_addr_lock(dev);
2978 spin_lock(&np->lock);
2979 /* stop engines */
2980 nv_stop_rxtx(dev);
2981 nv_txrx_reset(dev);
2982 /* drain rx queue */
2983 nv_drain_rxtx(dev);
2984 /* reinit driver view of the rx queue */
2985 set_bufsize(dev);
2986 if (nv_init_ring(dev)) {
2987 if (!np->in_shutdown)
2988 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2989 }
2990 /* reinit nic view of the rx queue */
2991 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2992 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2993 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2994 base + NvRegRingSizes);
2995 pci_push(base);
2996 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2997 pci_push(base);
2998
2999 /* restart rx engine */
3000 nv_start_rxtx(dev);
3001 spin_unlock(&np->lock);
3002 netif_addr_unlock(dev);
3003 netif_tx_unlock_bh(dev);
3004 nv_napi_enable(dev);
3005 nv_enable_irq(dev);
3006 }
3007 return 0;
3008 }
3009
3010 static void nv_copy_mac_to_hw(struct net_device *dev)
3011 {
3012 u8 __iomem *base = get_hwbase(dev);
3013 u32 mac[2];
3014
3015 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3016 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3017 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3018
3019 writel(mac[0], base + NvRegMacAddrA);
3020 writel(mac[1], base + NvRegMacAddrB);
3021 }
3022
3023 /*
3024 * nv_set_mac_address: dev->set_mac_address function
3025 * Called with rtnl_lock() held.
3026 */
3027 static int nv_set_mac_address(struct net_device *dev, void *addr)
3028 {
3029 struct fe_priv *np = netdev_priv(dev);
3030 struct sockaddr *macaddr = (struct sockaddr*)addr;
3031
3032 if (!is_valid_ether_addr(macaddr->sa_data))
3033 return -EADDRNOTAVAIL;
3034
3035 /* synchronized against open : rtnl_lock() held by caller */
3036 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3037
3038 if (netif_running(dev)) {
3039 netif_tx_lock_bh(dev);
3040 netif_addr_lock(dev);
3041 spin_lock_irq(&np->lock);
3042
3043 /* stop rx engine */
3044 nv_stop_rx(dev);
3045
3046 /* set mac address */
3047 nv_copy_mac_to_hw(dev);
3048
3049 /* restart rx engine */
3050 nv_start_rx(dev);
3051 spin_unlock_irq(&np->lock);
3052 netif_addr_unlock(dev);
3053 netif_tx_unlock_bh(dev);
3054 } else {
3055 nv_copy_mac_to_hw(dev);
3056 }
3057 return 0;
3058 }
3059
3060 /*
3061 * nv_set_multicast: dev->set_multicast function
3062 * Called with netif_tx_lock held.
3063 */
3064 static void nv_set_multicast(struct net_device *dev)
3065 {
3066 struct fe_priv *np = netdev_priv(dev);
3067 u8 __iomem *base = get_hwbase(dev);
3068 u32 addr[2];
3069 u32 mask[2];
3070 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3071
3072 memset(addr, 0, sizeof(addr));
3073 memset(mask, 0, sizeof(mask));
3074
3075 if (dev->flags & IFF_PROMISC) {
3076 pff |= NVREG_PFF_PROMISC;
3077 } else {
3078 pff |= NVREG_PFF_MYADDR;
3079
3080 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3081 u32 alwaysOff[2];
3082 u32 alwaysOn[2];
3083
3084 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3085 if (dev->flags & IFF_ALLMULTI) {
3086 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3087 } else {
3088 struct dev_mc_list *walk;
3089
3090 walk = dev->mc_list;
3091 while (walk != NULL) {
3092 u32 a, b;
3093 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3094 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3095 alwaysOn[0] &= a;
3096 alwaysOff[0] &= ~a;
3097 alwaysOn[1] &= b;
3098 alwaysOff[1] &= ~b;
3099 walk = walk->next;
3100 }
3101 }
3102 addr[0] = alwaysOn[0];
3103 addr[1] = alwaysOn[1];
3104 mask[0] = alwaysOn[0] | alwaysOff[0];
3105 mask[1] = alwaysOn[1] | alwaysOff[1];
3106 } else {
3107 mask[0] = NVREG_MCASTMASKA_NONE;
3108 mask[1] = NVREG_MCASTMASKB_NONE;
3109 }
3110 }
3111 addr[0] |= NVREG_MCASTADDRA_FORCE;
3112 pff |= NVREG_PFF_ALWAYS;
3113 spin_lock_irq(&np->lock);
3114 nv_stop_rx(dev);
3115 writel(addr[0], base + NvRegMulticastAddrA);
3116 writel(addr[1], base + NvRegMulticastAddrB);
3117 writel(mask[0], base + NvRegMulticastMaskA);
3118 writel(mask[1], base + NvRegMulticastMaskB);
3119 writel(pff, base + NvRegPacketFilterFlags);
3120 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3121 dev->name);
3122 nv_start_rx(dev);
3123 spin_unlock_irq(&np->lock);
3124 }
3125
3126 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3127 {
3128 struct fe_priv *np = netdev_priv(dev);
3129 u8 __iomem *base = get_hwbase(dev);
3130
3131 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3132
3133 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3134 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3135 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3136 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3137 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3138 } else {
3139 writel(pff, base + NvRegPacketFilterFlags);
3140 }
3141 }
3142 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3143 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3144 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3145 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3146 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3147 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3148 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3149 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3150 /* limit the number of tx pause frames to a default of 8 */
3151 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3152 }
3153 writel(pause_enable, base + NvRegTxPauseFrame);
3154 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3155 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3156 } else {
3157 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3158 writel(regmisc, base + NvRegMisc1);
3159 }
3160 }
3161 }
3162
3163 /**
3164 * nv_update_linkspeed: Setup the MAC according to the link partner
3165 * @dev: Network device to be configured
3166 *
3167 * The function queries the PHY and checks if there is a link partner.
3168 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3169 * set to 10 MBit HD.
3170 *
3171 * The function returns 0 if there is no link partner and 1 if there is
3172 * a good link partner.
3173 */
3174 static int nv_update_linkspeed(struct net_device *dev)
3175 {
3176 struct fe_priv *np = netdev_priv(dev);
3177 u8 __iomem *base = get_hwbase(dev);
3178 int adv = 0;
3179 int lpa = 0;
3180 int adv_lpa, adv_pause, lpa_pause;
3181 int newls = np->linkspeed;
3182 int newdup = np->duplex;
3183 int mii_status;
3184 int retval = 0;
3185 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3186 u32 txrxFlags = 0;
3187 u32 phy_exp;
3188
3189 /* BMSR_LSTATUS is latched, read it twice:
3190 * we want the current value.
3191 */
3192 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3193 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3194
3195 if (!(mii_status & BMSR_LSTATUS)) {
3196 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3197 dev->name);
3198 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3199 newdup = 0;
3200 retval = 0;
3201 goto set_speed;
3202 }
3203
3204 if (np->autoneg == 0) {
3205 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3206 dev->name, np->fixed_mode);
3207 if (np->fixed_mode & LPA_100FULL) {
3208 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3209 newdup = 1;
3210 } else if (np->fixed_mode & LPA_100HALF) {
3211 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3212 newdup = 0;
3213 } else if (np->fixed_mode & LPA_10FULL) {
3214 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3215 newdup = 1;
3216 } else {
3217 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3218 newdup = 0;
3219 }
3220 retval = 1;
3221 goto set_speed;
3222 }
3223 /* check auto negotiation is complete */
3224 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3225 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3226 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3227 newdup = 0;
3228 retval = 0;
3229 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3230 goto set_speed;
3231 }
3232
3233 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3234 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3235 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3236 dev->name, adv, lpa);
3237
3238 retval = 1;
3239 if (np->gigabit == PHY_GIGABIT) {
3240 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3241 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3242
3243 if ((control_1000 & ADVERTISE_1000FULL) &&
3244 (status_1000 & LPA_1000FULL)) {
3245 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3246 dev->name);
3247 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3248 newdup = 1;
3249 goto set_speed;
3250 }
3251 }
3252
3253 /* FIXME: handle parallel detection properly */
3254 adv_lpa = lpa & adv;
3255 if (adv_lpa & LPA_100FULL) {
3256 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3257 newdup = 1;
3258 } else if (adv_lpa & LPA_100HALF) {
3259 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3260 newdup = 0;
3261 } else if (adv_lpa & LPA_10FULL) {
3262 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3263 newdup = 1;
3264 } else if (adv_lpa & LPA_10HALF) {
3265 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3266 newdup = 0;
3267 } else {
3268 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3269 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3270 newdup = 0;
3271 }
3272
3273 set_speed:
3274 if (np->duplex == newdup && np->linkspeed == newls)
3275 return retval;
3276
3277 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3278 dev->name, np->linkspeed, np->duplex, newls, newdup);
3279
3280 np->duplex = newdup;
3281 np->linkspeed = newls;
3282
3283 /* The transmitter and receiver must be restarted for safe update */
3284 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3285 txrxFlags |= NV_RESTART_TX;
3286 nv_stop_tx(dev);
3287 }
3288 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3289 txrxFlags |= NV_RESTART_RX;
3290 nv_stop_rx(dev);
3291 }
3292
3293 if (np->gigabit == PHY_GIGABIT) {
3294 phyreg = readl(base + NvRegSlotTime);
3295 phyreg &= ~(0x3FF00);
3296 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3297 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3298 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3299 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3300 phyreg |= NVREG_SLOTTIME_1000_FULL;
3301 writel(phyreg, base + NvRegSlotTime);
3302 }
3303
3304 phyreg = readl(base + NvRegPhyInterface);
3305 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3306 if (np->duplex == 0)
3307 phyreg |= PHY_HALF;
3308 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3309 phyreg |= PHY_100;
3310 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3311 phyreg |= PHY_1000;
3312 writel(phyreg, base + NvRegPhyInterface);
3313
3314 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3315 if (phyreg & PHY_RGMII) {
3316 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3317 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3318 } else {
3319 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3320 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3321 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3322 else
3323 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3324 } else {
3325 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3326 }
3327 }
3328 } else {
3329 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3330 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3331 else
3332 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3333 }
3334 writel(txreg, base + NvRegTxDeferral);
3335
3336 if (np->desc_ver == DESC_VER_1) {
3337 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3338 } else {
3339 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3340 txreg = NVREG_TX_WM_DESC2_3_1000;
3341 else
3342 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3343 }
3344 writel(txreg, base + NvRegTxWatermark);
3345
3346 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3347 base + NvRegMisc1);
3348 pci_push(base);
3349 writel(np->linkspeed, base + NvRegLinkSpeed);
3350 pci_push(base);
3351
3352 pause_flags = 0;
3353 /* setup pause frame */
3354 if (np->duplex != 0) {
3355 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3356 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3357 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3358
3359 switch (adv_pause) {
3360 case ADVERTISE_PAUSE_CAP:
3361 if (lpa_pause & LPA_PAUSE_CAP) {
3362 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3363 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3364 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3365 }
3366 break;
3367 case ADVERTISE_PAUSE_ASYM:
3368 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3369 {
3370 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3371 }
3372 break;
3373 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3374 if (lpa_pause & LPA_PAUSE_CAP)
3375 {
3376 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3377 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3378 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3379 }
3380 if (lpa_pause == LPA_PAUSE_ASYM)
3381 {
3382 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3383 }
3384 break;
3385 }
3386 } else {
3387 pause_flags = np->pause_flags;
3388 }
3389 }
3390 nv_update_pause(dev, pause_flags);
3391
3392 if (txrxFlags & NV_RESTART_TX)
3393 nv_start_tx(dev);
3394 if (txrxFlags & NV_RESTART_RX)
3395 nv_start_rx(dev);
3396
3397 return retval;
3398 }
3399
3400 static void nv_linkchange(struct net_device *dev)
3401 {
3402 if (nv_update_linkspeed(dev)) {
3403 if (!netif_carrier_ok(dev)) {
3404 netif_carrier_on(dev);
3405 printk(KERN_INFO "%s: link up.\n", dev->name);
3406 nv_start_rx(dev);
3407 }
3408 } else {
3409 if (netif_carrier_ok(dev)) {
3410 netif_carrier_off(dev);
3411 printk(KERN_INFO "%s: link down.\n", dev->name);
3412 nv_stop_rx(dev);
3413 }
3414 }
3415 }
3416
3417 static void nv_link_irq(struct net_device *dev)
3418 {
3419 u8 __iomem *base = get_hwbase(dev);
3420 u32 miistat;
3421
3422 miistat = readl(base + NvRegMIIStatus);
3423 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3424 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3425
3426 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3427 nv_linkchange(dev);
3428 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3429 }
3430
3431 static void nv_msi_workaround(struct fe_priv *np)
3432 {
3433
3434 /* Need to toggle the msi irq mask within the ethernet device,
3435 * otherwise, future interrupts will not be detected.
3436 */
3437 if (np->msi_flags & NV_MSI_ENABLED) {
3438 u8 __iomem *base = np->base;
3439
3440 writel(0, base + NvRegMSIIrqMask);
3441 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3442 }
3443 }
3444
3445 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3446 {
3447 struct fe_priv *np = netdev_priv(dev);
3448
3449 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3450 if (total_work > NV_DYNAMIC_THRESHOLD) {
3451 /* transition to poll based interrupts */
3452 np->quiet_count = 0;
3453 if (np->irqmask != NVREG_IRQMASK_CPU) {
3454 np->irqmask = NVREG_IRQMASK_CPU;
3455 return 1;
3456 }
3457 } else {
3458 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3459 np->quiet_count++;
3460 } else {
3461 /* reached a period of low activity, switch
3462 to per tx/rx packet interrupts */
3463 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3464 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3465 return 1;
3466 }
3467 }
3468 }
3469 }
3470 return 0;
3471 }
3472
3473 static irqreturn_t nv_nic_irq(int foo, void *data)
3474 {
3475 struct net_device *dev = (struct net_device *) data;
3476 struct fe_priv *np = netdev_priv(dev);
3477 u8 __iomem *base = get_hwbase(dev);
3478 #ifndef CONFIG_FORCEDETH_NAPI
3479 int total_work = 0;
3480 int loop_count = 0;
3481 #endif
3482
3483 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3484
3485 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3486 np->events = readl(base + NvRegIrqStatus);
3487 writel(np->events, base + NvRegIrqStatus);
3488 } else {
3489 np->events = readl(base + NvRegMSIXIrqStatus);
3490 writel(np->events, base + NvRegMSIXIrqStatus);
3491 }
3492 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3493 if (!(np->events & np->irqmask))
3494 return IRQ_NONE;
3495
3496 nv_msi_workaround(np);
3497
3498 #ifdef CONFIG_FORCEDETH_NAPI
3499 napi_schedule(&np->napi);
3500
3501 /* Disable furthur irq's
3502 (msix not enabled with napi) */
3503 writel(0, base + NvRegIrqMask);
3504
3505 #else
3506 do
3507 {
3508 int work = 0;
3509 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3510 if (unlikely(nv_alloc_rx(dev))) {
3511 spin_lock(&np->lock);
3512 if (!np->in_shutdown)
3513 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3514 spin_unlock(&np->lock);
3515 }
3516 }
3517
3518 spin_lock(&np->lock);
3519 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3520 spin_unlock(&np->lock);
3521
3522 if (!work)
3523 break;
3524
3525 total_work += work;
3526
3527 loop_count++;
3528 }
3529 while (loop_count < max_interrupt_work);
3530
3531 if (nv_change_interrupt_mode(dev, total_work)) {
3532 /* setup new irq mask */
3533 writel(np->irqmask, base + NvRegIrqMask);
3534 }
3535
3536 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3537 spin_lock(&np->lock);
3538 nv_link_irq(dev);
3539 spin_unlock(&np->lock);
3540 }
3541 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3542 spin_lock(&np->lock);
3543 nv_linkchange(dev);
3544 spin_unlock(&np->lock);
3545 np->link_timeout = jiffies + LINK_TIMEOUT;
3546 }
3547 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3548 spin_lock(&np->lock);
3549 /* disable interrupts on the nic */
3550 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3551 writel(0, base + NvRegIrqMask);
3552 else
3553 writel(np->irqmask, base + NvRegIrqMask);
3554 pci_push(base);
3555
3556 if (!np->in_shutdown) {
3557 np->nic_poll_irq = np->irqmask;
3558 np->recover_error = 1;
3559 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3560 }
3561 spin_unlock(&np->lock);
3562 }
3563 #endif
3564 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3565
3566 return IRQ_HANDLED;
3567 }
3568
3569 /**
3570 * All _optimized functions are used to help increase performance
3571 * (reduce CPU and increase throughput). They use descripter version 3,
3572 * compiler directives, and reduce memory accesses.
3573 */
3574 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3575 {
3576 struct net_device *dev = (struct net_device *) data;
3577 struct fe_priv *np = netdev_priv(dev);
3578 u8 __iomem *base = get_hwbase(dev);
3579 #ifndef CONFIG_FORCEDETH_NAPI
3580 int total_work = 0;
3581 int loop_count = 0;
3582 #endif
3583
3584 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3585
3586 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3587 np->events = readl(base + NvRegIrqStatus);
3588 writel(np->events, base + NvRegIrqStatus);
3589 } else {
3590 np->events = readl(base + NvRegMSIXIrqStatus);
3591 writel(np->events, base + NvRegMSIXIrqStatus);
3592 }
3593 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3594 if (!(np->events & np->irqmask))
3595 return IRQ_NONE;
3596
3597 nv_msi_workaround(np);
3598
3599 #ifdef CONFIG_FORCEDETH_NAPI
3600 napi_schedule(&np->napi);
3601
3602 /* Disable furthur irq's
3603 (msix not enabled with napi) */
3604 writel(0, base + NvRegIrqMask);
3605
3606 #else
3607 do
3608 {
3609 int work = 0;
3610 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3611 if (unlikely(nv_alloc_rx_optimized(dev))) {
3612 spin_lock(&np->lock);
3613 if (!np->in_shutdown)
3614 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3615 spin_unlock(&np->lock);
3616 }
3617 }
3618
3619 spin_lock(&np->lock);
3620 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3621 spin_unlock(&np->lock);
3622
3623 if (!work)
3624 break;
3625
3626 total_work += work;
3627
3628 loop_count++;
3629 }
3630 while (loop_count < max_interrupt_work);
3631
3632 if (nv_change_interrupt_mode(dev, total_work)) {
3633 /* setup new irq mask */
3634 writel(np->irqmask, base + NvRegIrqMask);
3635 }
3636
3637 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3638 spin_lock(&np->lock);
3639 nv_link_irq(dev);
3640 spin_unlock(&np->lock);
3641 }
3642 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3643 spin_lock(&np->lock);
3644 nv_linkchange(dev);
3645 spin_unlock(&np->lock);
3646 np->link_timeout = jiffies + LINK_TIMEOUT;
3647 }
3648 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3649 spin_lock(&np->lock);
3650 /* disable interrupts on the nic */
3651 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3652 writel(0, base + NvRegIrqMask);
3653 else
3654 writel(np->irqmask, base + NvRegIrqMask);
3655 pci_push(base);
3656
3657 if (!np->in_shutdown) {
3658 np->nic_poll_irq = np->irqmask;
3659 np->recover_error = 1;
3660 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3661 }
3662 spin_unlock(&np->lock);
3663 }
3664
3665 #endif
3666 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3667
3668 return IRQ_HANDLED;
3669 }
3670
3671 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3672 {
3673 struct net_device *dev = (struct net_device *) data;
3674 struct fe_priv *np = netdev_priv(dev);
3675 u8 __iomem *base = get_hwbase(dev);
3676 u32 events;
3677 int i;
3678 unsigned long flags;
3679
3680 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3681
3682 for (i=0; ; i++) {
3683 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3684 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3685 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3686 if (!(events & np->irqmask))
3687 break;
3688
3689 spin_lock_irqsave(&np->lock, flags);
3690 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3691 spin_unlock_irqrestore(&np->lock, flags);
3692
3693 if (unlikely(i > max_interrupt_work)) {
3694 spin_lock_irqsave(&np->lock, flags);
3695 /* disable interrupts on the nic */
3696 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3697 pci_push(base);
3698
3699 if (!np->in_shutdown) {
3700 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3701 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3702 }
3703 spin_unlock_irqrestore(&np->lock, flags);
3704 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3705 break;
3706 }
3707
3708 }
3709 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3710
3711 return IRQ_RETVAL(i);
3712 }
3713
3714 #ifdef CONFIG_FORCEDETH_NAPI
3715 static int nv_napi_poll(struct napi_struct *napi, int budget)
3716 {
3717 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3718 struct net_device *dev = np->dev;
3719 u8 __iomem *base = get_hwbase(dev);
3720 unsigned long flags;
3721 int retcode;
3722 int tx_work, rx_work;
3723
3724 if (!nv_optimized(np)) {
3725 spin_lock_irqsave(&np->lock, flags);
3726 tx_work = nv_tx_done(dev, np->tx_ring_size);
3727 spin_unlock_irqrestore(&np->lock, flags);
3728
3729 rx_work = nv_rx_process(dev, budget);
3730 retcode = nv_alloc_rx(dev);
3731 } else {
3732 spin_lock_irqsave(&np->lock, flags);
3733 tx_work = nv_tx_done_optimized(dev, np->tx_ring_size);
3734 spin_unlock_irqrestore(&np->lock, flags);
3735
3736 rx_work = nv_rx_process_optimized(dev, budget);
3737 retcode = nv_alloc_rx_optimized(dev);
3738 }
3739
3740 if (retcode) {
3741 spin_lock_irqsave(&np->lock, flags);
3742 if (!np->in_shutdown)
3743 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3744 spin_unlock_irqrestore(&np->lock, flags);
3745 }
3746
3747 nv_change_interrupt_mode(dev, tx_work + rx_work);
3748
3749 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3750 spin_lock_irqsave(&np->lock, flags);
3751 nv_link_irq(dev);
3752 spin_unlock_irqrestore(&np->lock, flags);
3753 }
3754 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3755 spin_lock_irqsave(&np->lock, flags);
3756 nv_linkchange(dev);
3757 spin_unlock_irqrestore(&np->lock, flags);
3758 np->link_timeout = jiffies + LINK_TIMEOUT;
3759 }
3760 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3761 spin_lock_irqsave(&np->lock, flags);
3762 if (!np->in_shutdown) {
3763 np->nic_poll_irq = np->irqmask;
3764 np->recover_error = 1;
3765 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3766 }
3767 spin_unlock_irqrestore(&np->lock, flags);
3768 napi_complete(napi);
3769 return rx_work;
3770 }
3771
3772 if (rx_work < budget) {
3773 /* re-enable interrupts
3774 (msix not enabled in napi) */
3775 napi_complete(napi);
3776
3777 writel(np->irqmask, base + NvRegIrqMask);
3778 }
3779 return rx_work;
3780 }
3781 #endif
3782
3783 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3784 {
3785 struct net_device *dev = (struct net_device *) data;
3786 struct fe_priv *np = netdev_priv(dev);
3787 u8 __iomem *base = get_hwbase(dev);
3788 u32 events;
3789 int i;
3790 unsigned long flags;
3791
3792 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3793
3794 for (i=0; ; i++) {
3795 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3796 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3797 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3798 if (!(events & np->irqmask))
3799 break;
3800
3801 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3802 if (unlikely(nv_alloc_rx_optimized(dev))) {
3803 spin_lock_irqsave(&np->lock, flags);
3804 if (!np->in_shutdown)
3805 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3806 spin_unlock_irqrestore(&np->lock, flags);
3807 }
3808 }
3809
3810 if (unlikely(i > max_interrupt_work)) {
3811 spin_lock_irqsave(&np->lock, flags);
3812 /* disable interrupts on the nic */
3813 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3814 pci_push(base);
3815
3816 if (!np->in_shutdown) {
3817 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3818 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3819 }
3820 spin_unlock_irqrestore(&np->lock, flags);
3821 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3822 break;
3823 }
3824 }
3825 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3826
3827 return IRQ_RETVAL(i);
3828 }
3829
3830 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3831 {
3832 struct net_device *dev = (struct net_device *) data;
3833 struct fe_priv *np = netdev_priv(dev);
3834 u8 __iomem *base = get_hwbase(dev);
3835 u32 events;
3836 int i;
3837 unsigned long flags;
3838
3839 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3840
3841 for (i=0; ; i++) {
3842 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3843 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3844 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3845 if (!(events & np->irqmask))
3846 break;
3847
3848 /* check tx in case we reached max loop limit in tx isr */
3849 spin_lock_irqsave(&np->lock, flags);
3850 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3851 spin_unlock_irqrestore(&np->lock, flags);
3852
3853 if (events & NVREG_IRQ_LINK) {
3854 spin_lock_irqsave(&np->lock, flags);
3855 nv_link_irq(dev);
3856 spin_unlock_irqrestore(&np->lock, flags);
3857 }
3858 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3859 spin_lock_irqsave(&np->lock, flags);
3860 nv_linkchange(dev);
3861 spin_unlock_irqrestore(&np->lock, flags);
3862 np->link_timeout = jiffies + LINK_TIMEOUT;
3863 }
3864 if (events & NVREG_IRQ_RECOVER_ERROR) {
3865 spin_lock_irq(&np->lock);
3866 /* disable interrupts on the nic */
3867 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3868 pci_push(base);
3869
3870 if (!np->in_shutdown) {
3871 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3872 np->recover_error = 1;
3873 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3874 }
3875 spin_unlock_irq(&np->lock);
3876 break;
3877 }
3878 if (unlikely(i > max_interrupt_work)) {
3879 spin_lock_irqsave(&np->lock, flags);
3880 /* disable interrupts on the nic */
3881 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3882 pci_push(base);
3883
3884 if (!np->in_shutdown) {
3885 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3886 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3887 }
3888 spin_unlock_irqrestore(&np->lock, flags);
3889 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3890 break;
3891 }
3892
3893 }
3894 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3895
3896 return IRQ_RETVAL(i);
3897 }
3898
3899 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3900 {
3901 struct net_device *dev = (struct net_device *) data;
3902 struct fe_priv *np = netdev_priv(dev);
3903 u8 __iomem *base = get_hwbase(dev);
3904 u32 events;
3905
3906 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3907
3908 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3909 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3910 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3911 } else {
3912 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3913 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3914 }
3915 pci_push(base);
3916 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3917 if (!(events & NVREG_IRQ_TIMER))
3918 return IRQ_RETVAL(0);
3919
3920 nv_msi_workaround(np);
3921
3922 spin_lock(&np->lock);
3923 np->intr_test = 1;
3924 spin_unlock(&np->lock);
3925
3926 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3927
3928 return IRQ_RETVAL(1);
3929 }
3930
3931 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3932 {
3933 u8 __iomem *base = get_hwbase(dev);
3934 int i;
3935 u32 msixmap = 0;
3936
3937 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3938 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3939 * the remaining 8 interrupts.
3940 */
3941 for (i = 0; i < 8; i++) {
3942 if ((irqmask >> i) & 0x1) {
3943 msixmap |= vector << (i << 2);
3944 }
3945 }
3946 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3947
3948 msixmap = 0;
3949 for (i = 0; i < 8; i++) {
3950 if ((irqmask >> (i + 8)) & 0x1) {
3951 msixmap |= vector << (i << 2);
3952 }
3953 }
3954 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3955 }
3956
3957 static int nv_request_irq(struct net_device *dev, int intr_test)
3958 {
3959 struct fe_priv *np = get_nvpriv(dev);
3960 u8 __iomem *base = get_hwbase(dev);
3961 int ret = 1;
3962 int i;
3963 irqreturn_t (*handler)(int foo, void *data);
3964
3965 if (intr_test) {
3966 handler = nv_nic_irq_test;
3967 } else {
3968 if (nv_optimized(np))
3969 handler = nv_nic_irq_optimized;
3970 else
3971 handler = nv_nic_irq;
3972 }
3973
3974 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3975 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3976 np->msi_x_entry[i].entry = i;
3977 }
3978 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3979 np->msi_flags |= NV_MSI_X_ENABLED;
3980 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3981 /* Request irq for rx handling */
3982 sprintf(np->name_rx, "%s-rx", dev->name);
3983 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3984 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3985 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3986 pci_disable_msix(np->pci_dev);
3987 np->msi_flags &= ~NV_MSI_X_ENABLED;
3988 goto out_err;
3989 }
3990 /* Request irq for tx handling */
3991 sprintf(np->name_tx, "%s-tx", dev->name);
3992 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3993 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3994 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3995 pci_disable_msix(np->pci_dev);
3996 np->msi_flags &= ~NV_MSI_X_ENABLED;
3997 goto out_free_rx;
3998 }
3999 /* Request irq for link and timer handling */
4000 sprintf(np->name_other, "%s-other", dev->name);
4001 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4002 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
4003 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4004 pci_disable_msix(np->pci_dev);
4005 np->msi_flags &= ~NV_MSI_X_ENABLED;
4006 goto out_free_tx;
4007 }
4008 /* map interrupts to their respective vector */
4009 writel(0, base + NvRegMSIXMap0);
4010 writel(0, base + NvRegMSIXMap1);
4011 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4012 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4013 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4014 } else {
4015 /* Request irq for all interrupts */
4016 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
4017 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4018 pci_disable_msix(np->pci_dev);
4019 np->msi_flags &= ~NV_MSI_X_ENABLED;
4020 goto out_err;
4021 }
4022
4023 /* map interrupts to vector 0 */
4024 writel(0, base + NvRegMSIXMap0);
4025 writel(0, base + NvRegMSIXMap1);
4026 }
4027 }
4028 }
4029 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4030 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4031 np->msi_flags |= NV_MSI_ENABLED;
4032 dev->irq = np->pci_dev->irq;
4033 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4034 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4035 pci_disable_msi(np->pci_dev);
4036 np->msi_flags &= ~NV_MSI_ENABLED;
4037 dev->irq = np->pci_dev->irq;
4038 goto out_err;
4039 }
4040
4041 /* map interrupts to vector 0 */
4042 writel(0, base + NvRegMSIMap0);
4043 writel(0, base + NvRegMSIMap1);
4044 /* enable msi vector 0 */
4045 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4046 }
4047 }
4048 if (ret != 0) {
4049 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4050 goto out_err;
4051
4052 }
4053
4054 return 0;
4055 out_free_tx:
4056 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4057 out_free_rx:
4058 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4059 out_err:
4060 return 1;
4061 }
4062
4063 static void nv_free_irq(struct net_device *dev)
4064 {
4065 struct fe_priv *np = get_nvpriv(dev);
4066 int i;
4067
4068 if (np->msi_flags & NV_MSI_X_ENABLED) {
4069 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4070 free_irq(np->msi_x_entry[i].vector, dev);
4071 }
4072 pci_disable_msix(np->pci_dev);
4073 np->msi_flags &= ~NV_MSI_X_ENABLED;
4074 } else {
4075 free_irq(np->pci_dev->irq, dev);
4076 if (np->msi_flags & NV_MSI_ENABLED) {
4077 pci_disable_msi(np->pci_dev);
4078 np->msi_flags &= ~NV_MSI_ENABLED;
4079 }
4080 }
4081 }
4082
4083 static void nv_do_nic_poll(unsigned long data)
4084 {
4085 struct net_device *dev = (struct net_device *) data;
4086 struct fe_priv *np = netdev_priv(dev);
4087 u8 __iomem *base = get_hwbase(dev);
4088 u32 mask = 0;
4089
4090 /*
4091 * First disable irq(s) and then
4092 * reenable interrupts on the nic, we have to do this before calling
4093 * nv_nic_irq because that may decide to do otherwise
4094 */
4095
4096 if (!using_multi_irqs(dev)) {
4097 if (np->msi_flags & NV_MSI_X_ENABLED)
4098 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4099 else
4100 disable_irq_lockdep(np->pci_dev->irq);
4101 mask = np->irqmask;
4102 } else {
4103 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4104 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4105 mask |= NVREG_IRQ_RX_ALL;
4106 }
4107 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4108 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4109 mask |= NVREG_IRQ_TX_ALL;
4110 }
4111 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4112 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4113 mask |= NVREG_IRQ_OTHER;
4114 }
4115 }
4116 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4117
4118 if (np->recover_error) {
4119 np->recover_error = 0;
4120 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4121 if (netif_running(dev)) {
4122 netif_tx_lock_bh(dev);
4123 netif_addr_lock(dev);
4124 spin_lock(&np->lock);
4125 /* stop engines */
4126 nv_stop_rxtx(dev);
4127 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4128 nv_mac_reset(dev);
4129 nv_txrx_reset(dev);
4130 /* drain rx queue */
4131 nv_drain_rxtx(dev);
4132 /* reinit driver view of the rx queue */
4133 set_bufsize(dev);
4134 if (nv_init_ring(dev)) {
4135 if (!np->in_shutdown)
4136 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4137 }
4138 /* reinit nic view of the rx queue */
4139 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4140 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4141 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4142 base + NvRegRingSizes);
4143 pci_push(base);
4144 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4145 pci_push(base);
4146 /* clear interrupts */
4147 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4148 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4149 else
4150 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4151
4152 /* restart rx engine */
4153 nv_start_rxtx(dev);
4154 spin_unlock(&np->lock);
4155 netif_addr_unlock(dev);
4156 netif_tx_unlock_bh(dev);
4157 }
4158 }
4159
4160 writel(mask, base + NvRegIrqMask);
4161 pci_push(base);
4162
4163 if (!using_multi_irqs(dev)) {
4164 np->nic_poll_irq = 0;
4165 if (nv_optimized(np))
4166 nv_nic_irq_optimized(0, dev);
4167 else
4168 nv_nic_irq(0, dev);
4169 if (np->msi_flags & NV_MSI_X_ENABLED)
4170 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4171 else
4172 enable_irq_lockdep(np->pci_dev->irq);
4173 } else {
4174 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4175 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4176 nv_nic_irq_rx(0, dev);
4177 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4178 }
4179 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4180 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4181 nv_nic_irq_tx(0, dev);
4182 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4183 }
4184 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4185 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4186 nv_nic_irq_other(0, dev);
4187 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4188 }
4189 }
4190
4191 }
4192
4193 #ifdef CONFIG_NET_POLL_CONTROLLER
4194 static void nv_poll_controller(struct net_device *dev)
4195 {
4196 nv_do_nic_poll((unsigned long) dev);
4197 }
4198 #endif
4199
4200 static void nv_do_stats_poll(unsigned long data)
4201 {
4202 struct net_device *dev = (struct net_device *) data;
4203 struct fe_priv *np = netdev_priv(dev);
4204
4205 nv_get_hw_stats(dev);
4206
4207 if (!np->in_shutdown)
4208 mod_timer(&np->stats_poll,
4209 round_jiffies(jiffies + STATS_INTERVAL));
4210 }
4211
4212 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4213 {
4214 struct fe_priv *np = netdev_priv(dev);
4215 strcpy(info->driver, DRV_NAME);
4216 strcpy(info->version, FORCEDETH_VERSION);
4217 strcpy(info->bus_info, pci_name(np->pci_dev));
4218 }
4219
4220 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4221 {
4222 struct fe_priv *np = netdev_priv(dev);
4223 wolinfo->supported = WAKE_MAGIC;
4224
4225 spin_lock_irq(&np->lock);
4226 if (np->wolenabled)
4227 wolinfo->wolopts = WAKE_MAGIC;
4228 spin_unlock_irq(&np->lock);
4229 }
4230
4231 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4232 {
4233 struct fe_priv *np = netdev_priv(dev);
4234 u8 __iomem *base = get_hwbase(dev);
4235 u32 flags = 0;
4236
4237 if (wolinfo->wolopts == 0) {
4238 np->wolenabled = 0;
4239 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4240 np->wolenabled = 1;
4241 flags = NVREG_WAKEUPFLAGS_ENABLE;
4242 }
4243 if (netif_running(dev)) {
4244 spin_lock_irq(&np->lock);
4245 writel(flags, base + NvRegWakeUpFlags);
4246 spin_unlock_irq(&np->lock);
4247 }
4248 return 0;
4249 }
4250
4251 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4252 {
4253 struct fe_priv *np = netdev_priv(dev);
4254 int adv;
4255
4256 spin_lock_irq(&np->lock);
4257 ecmd->port = PORT_MII;
4258 if (!netif_running(dev)) {
4259 /* We do not track link speed / duplex setting if the
4260 * interface is disabled. Force a link check */
4261 if (nv_update_linkspeed(dev)) {
4262 if (!netif_carrier_ok(dev))
4263 netif_carrier_on(dev);
4264 } else {
4265 if (netif_carrier_ok(dev))
4266 netif_carrier_off(dev);
4267 }
4268 }
4269
4270 if (netif_carrier_ok(dev)) {
4271 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4272 case NVREG_LINKSPEED_10:
4273 ecmd->speed = SPEED_10;
4274 break;
4275 case NVREG_LINKSPEED_100:
4276 ecmd->speed = SPEED_100;
4277 break;
4278 case NVREG_LINKSPEED_1000:
4279 ecmd->speed = SPEED_1000;
4280 break;
4281 }
4282 ecmd->duplex = DUPLEX_HALF;
4283 if (np->duplex)
4284 ecmd->duplex = DUPLEX_FULL;
4285 } else {
4286 ecmd->speed = -1;
4287 ecmd->duplex = -1;
4288 }
4289
4290 ecmd->autoneg = np->autoneg;
4291
4292 ecmd->advertising = ADVERTISED_MII;
4293 if (np->autoneg) {
4294 ecmd->advertising |= ADVERTISED_Autoneg;
4295 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4296 if (adv & ADVERTISE_10HALF)
4297 ecmd->advertising |= ADVERTISED_10baseT_Half;
4298 if (adv & ADVERTISE_10FULL)
4299 ecmd->advertising |= ADVERTISED_10baseT_Full;
4300 if (adv & ADVERTISE_100HALF)
4301 ecmd->advertising |= ADVERTISED_100baseT_Half;
4302 if (adv & ADVERTISE_100FULL)
4303 ecmd->advertising |= ADVERTISED_100baseT_Full;
4304 if (np->gigabit == PHY_GIGABIT) {
4305 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4306 if (adv & ADVERTISE_1000FULL)
4307 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4308 }
4309 }
4310 ecmd->supported = (SUPPORTED_Autoneg |
4311 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4312 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4313 SUPPORTED_MII);
4314 if (np->gigabit == PHY_GIGABIT)
4315 ecmd->supported |= SUPPORTED_1000baseT_Full;
4316
4317 ecmd->phy_address = np->phyaddr;
4318 ecmd->transceiver = XCVR_EXTERNAL;
4319
4320 /* ignore maxtxpkt, maxrxpkt for now */
4321 spin_unlock_irq(&np->lock);
4322 return 0;
4323 }
4324
4325 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4326 {
4327 struct fe_priv *np = netdev_priv(dev);
4328
4329 if (ecmd->port != PORT_MII)
4330 return -EINVAL;
4331 if (ecmd->transceiver != XCVR_EXTERNAL)
4332 return -EINVAL;
4333 if (ecmd->phy_address != np->phyaddr) {
4334 /* TODO: support switching between multiple phys. Should be
4335 * trivial, but not enabled due to lack of test hardware. */
4336 return -EINVAL;
4337 }
4338 if (ecmd->autoneg == AUTONEG_ENABLE) {
4339 u32 mask;
4340
4341 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4342 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4343 if (np->gigabit == PHY_GIGABIT)
4344 mask |= ADVERTISED_1000baseT_Full;
4345
4346 if ((ecmd->advertising & mask) == 0)
4347 return -EINVAL;
4348
4349 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4350 /* Note: autonegotiation disable, speed 1000 intentionally
4351 * forbidden - noone should need that. */
4352
4353 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4354 return -EINVAL;
4355 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4356 return -EINVAL;
4357 } else {
4358 return -EINVAL;
4359 }
4360
4361 netif_carrier_off(dev);
4362 if (netif_running(dev)) {
4363 unsigned long flags;
4364
4365 nv_disable_irq(dev);
4366 netif_tx_lock_bh(dev);
4367 netif_addr_lock(dev);
4368 /* with plain spinlock lockdep complains */
4369 spin_lock_irqsave(&np->lock, flags);
4370 /* stop engines */
4371 /* FIXME:
4372 * this can take some time, and interrupts are disabled
4373 * due to spin_lock_irqsave, but let's hope no daemon
4374 * is going to change the settings very often...
4375 * Worst case:
4376 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4377 * + some minor delays, which is up to a second approximately
4378 */
4379 nv_stop_rxtx(dev);
4380 spin_unlock_irqrestore(&np->lock, flags);
4381 netif_addr_unlock(dev);
4382 netif_tx_unlock_bh(dev);
4383 }
4384
4385 if (ecmd->autoneg == AUTONEG_ENABLE) {
4386 int adv, bmcr;
4387
4388 np->autoneg = 1;
4389
4390 /* advertise only what has been requested */
4391 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4392 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4393 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4394 adv |= ADVERTISE_10HALF;
4395 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4396 adv |= ADVERTISE_10FULL;
4397 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4398 adv |= ADVERTISE_100HALF;
4399 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4400 adv |= ADVERTISE_100FULL;
4401 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4402 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4403 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4404 adv |= ADVERTISE_PAUSE_ASYM;
4405 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4406
4407 if (np->gigabit == PHY_GIGABIT) {
4408 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4409 adv &= ~ADVERTISE_1000FULL;
4410 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4411 adv |= ADVERTISE_1000FULL;
4412 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4413 }
4414
4415 if (netif_running(dev))
4416 printk(KERN_INFO "%s: link down.\n", dev->name);
4417 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4418 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4419 bmcr |= BMCR_ANENABLE;
4420 /* reset the phy in order for settings to stick,
4421 * and cause autoneg to start */
4422 if (phy_reset(dev, bmcr)) {
4423 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4424 return -EINVAL;
4425 }
4426 } else {
4427 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4428 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4429 }
4430 } else {
4431 int adv, bmcr;
4432
4433 np->autoneg = 0;
4434
4435 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4436 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4437 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4438 adv |= ADVERTISE_10HALF;
4439 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4440 adv |= ADVERTISE_10FULL;
4441 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4442 adv |= ADVERTISE_100HALF;
4443 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4444 adv |= ADVERTISE_100FULL;
4445 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4446 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4447 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4448 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4449 }
4450 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4451 adv |= ADVERTISE_PAUSE_ASYM;
4452 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4453 }
4454 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4455 np->fixed_mode = adv;
4456
4457 if (np->gigabit == PHY_GIGABIT) {
4458 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4459 adv &= ~ADVERTISE_1000FULL;
4460 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4461 }
4462
4463 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4464 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4465 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4466 bmcr |= BMCR_FULLDPLX;
4467 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4468 bmcr |= BMCR_SPEED100;
4469 if (np->phy_oui == PHY_OUI_MARVELL) {
4470 /* reset the phy in order for forced mode settings to stick */
4471 if (phy_reset(dev, bmcr)) {
4472 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4473 return -EINVAL;
4474 }
4475 } else {
4476 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4477 if (netif_running(dev)) {
4478 /* Wait a bit and then reconfigure the nic. */
4479 udelay(10);
4480 nv_linkchange(dev);
4481 }
4482 }
4483 }
4484
4485 if (netif_running(dev)) {
4486 nv_start_rxtx(dev);
4487 nv_enable_irq(dev);
4488 }
4489
4490 return 0;
4491 }
4492
4493 #define FORCEDETH_REGS_VER 1
4494
4495 static int nv_get_regs_len(struct net_device *dev)
4496 {
4497 struct fe_priv *np = netdev_priv(dev);
4498 return np->register_size;
4499 }
4500
4501 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4502 {
4503 struct fe_priv *np = netdev_priv(dev);
4504 u8 __iomem *base = get_hwbase(dev);
4505 u32 *rbuf = buf;
4506 int i;
4507
4508 regs->version = FORCEDETH_REGS_VER;
4509 spin_lock_irq(&np->lock);
4510 for (i = 0;i <= np->register_size/sizeof(u32); i++)
4511 rbuf[i] = readl(base + i*sizeof(u32));
4512 spin_unlock_irq(&np->lock);
4513 }
4514
4515 static int nv_nway_reset(struct net_device *dev)
4516 {
4517 struct fe_priv *np = netdev_priv(dev);
4518 int ret;
4519
4520 if (np->autoneg) {
4521 int bmcr;
4522
4523 netif_carrier_off(dev);
4524 if (netif_running(dev)) {
4525 nv_disable_irq(dev);
4526 netif_tx_lock_bh(dev);
4527 netif_addr_lock(dev);
4528 spin_lock(&np->lock);
4529 /* stop engines */
4530 nv_stop_rxtx(dev);
4531 spin_unlock(&np->lock);
4532 netif_addr_unlock(dev);
4533 netif_tx_unlock_bh(dev);
4534 printk(KERN_INFO "%s: link down.\n", dev->name);
4535 }
4536
4537 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4538 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4539 bmcr |= BMCR_ANENABLE;
4540 /* reset the phy in order for settings to stick*/
4541 if (phy_reset(dev, bmcr)) {
4542 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4543 return -EINVAL;
4544 }
4545 } else {
4546 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4547 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4548 }
4549
4550 if (netif_running(dev)) {
4551 nv_start_rxtx(dev);
4552 nv_enable_irq(dev);
4553 }
4554 ret = 0;
4555 } else {
4556 ret = -EINVAL;
4557 }
4558
4559 return ret;
4560 }
4561
4562 static int nv_set_tso(struct net_device *dev, u32 value)
4563 {
4564 struct fe_priv *np = netdev_priv(dev);
4565
4566 if ((np->driver_data & DEV_HAS_CHECKSUM))
4567 return ethtool_op_set_tso(dev, value);
4568 else
4569 return -EOPNOTSUPP;
4570 }
4571
4572 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4573 {
4574 struct fe_priv *np = netdev_priv(dev);
4575
4576 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4577 ring->rx_mini_max_pending = 0;
4578 ring->rx_jumbo_max_pending = 0;
4579 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4580
4581 ring->rx_pending = np->rx_ring_size;
4582 ring->rx_mini_pending = 0;
4583 ring->rx_jumbo_pending = 0;
4584 ring->tx_pending = np->tx_ring_size;
4585 }
4586
4587 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4588 {
4589 struct fe_priv *np = netdev_priv(dev);
4590 u8 __iomem *base = get_hwbase(dev);
4591 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4592 dma_addr_t ring_addr;
4593
4594 if (ring->rx_pending < RX_RING_MIN ||
4595 ring->tx_pending < TX_RING_MIN ||
4596 ring->rx_mini_pending != 0 ||
4597 ring->rx_jumbo_pending != 0 ||
4598 (np->desc_ver == DESC_VER_1 &&
4599 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4600 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4601 (np->desc_ver != DESC_VER_1 &&
4602 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4603 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4604 return -EINVAL;
4605 }
4606
4607 /* allocate new rings */
4608 if (!nv_optimized(np)) {
4609 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4610 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4611 &ring_addr);
4612 } else {
4613 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4614 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4615 &ring_addr);
4616 }
4617 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4618 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4619 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4620 /* fall back to old rings */
4621 if (!nv_optimized(np)) {
4622 if (rxtx_ring)
4623 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4624 rxtx_ring, ring_addr);
4625 } else {
4626 if (rxtx_ring)
4627 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4628 rxtx_ring, ring_addr);
4629 }
4630 if (rx_skbuff)
4631 kfree(rx_skbuff);
4632 if (tx_skbuff)
4633 kfree(tx_skbuff);
4634 goto exit;
4635 }
4636
4637 if (netif_running(dev)) {
4638 nv_disable_irq(dev);
4639 nv_napi_disable(dev);
4640 netif_tx_lock_bh(dev);
4641 netif_addr_lock(dev);
4642 spin_lock(&np->lock);
4643 /* stop engines */
4644 nv_stop_rxtx(dev);
4645 nv_txrx_reset(dev);
4646 /* drain queues */
4647 nv_drain_rxtx(dev);
4648 /* delete queues */
4649 free_rings(dev);
4650 }
4651
4652 /* set new values */
4653 np->rx_ring_size = ring->rx_pending;
4654 np->tx_ring_size = ring->tx_pending;
4655
4656 if (!nv_optimized(np)) {
4657 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4658 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4659 } else {
4660 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4661 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4662 }
4663 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4664 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4665 np->ring_addr = ring_addr;
4666
4667 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4668 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4669
4670 if (netif_running(dev)) {
4671 /* reinit driver view of the queues */
4672 set_bufsize(dev);
4673 if (nv_init_ring(dev)) {
4674 if (!np->in_shutdown)
4675 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4676 }
4677
4678 /* reinit nic view of the queues */
4679 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4680 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4681 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4682 base + NvRegRingSizes);
4683 pci_push(base);
4684 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4685 pci_push(base);
4686
4687 /* restart engines */
4688 nv_start_rxtx(dev);
4689 spin_unlock(&np->lock);
4690 netif_addr_unlock(dev);
4691 netif_tx_unlock_bh(dev);
4692 nv_napi_enable(dev);
4693 nv_enable_irq(dev);
4694 }
4695 return 0;
4696 exit:
4697 return -ENOMEM;
4698 }
4699
4700 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4701 {
4702 struct fe_priv *np = netdev_priv(dev);
4703
4704 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4705 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4706 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4707 }
4708
4709 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4710 {
4711 struct fe_priv *np = netdev_priv(dev);
4712 int adv, bmcr;
4713
4714 if ((!np->autoneg && np->duplex == 0) ||
4715 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4716 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4717 dev->name);
4718 return -EINVAL;
4719 }
4720 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4721 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4722 return -EINVAL;
4723 }
4724
4725 netif_carrier_off(dev);
4726 if (netif_running(dev)) {
4727 nv_disable_irq(dev);
4728 netif_tx_lock_bh(dev);
4729 netif_addr_lock(dev);
4730 spin_lock(&np->lock);
4731 /* stop engines */
4732 nv_stop_rxtx(dev);
4733 spin_unlock(&np->lock);
4734 netif_addr_unlock(dev);
4735 netif_tx_unlock_bh(dev);
4736 }
4737
4738 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4739 if (pause->rx_pause)
4740 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4741 if (pause->tx_pause)
4742 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4743
4744 if (np->autoneg && pause->autoneg) {
4745 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4746
4747 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4748 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4749 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4750 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4751 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4752 adv |= ADVERTISE_PAUSE_ASYM;
4753 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4754
4755 if (netif_running(dev))
4756 printk(KERN_INFO "%s: link down.\n", dev->name);
4757 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4758 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4759 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4760 } else {
4761 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4762 if (pause->rx_pause)
4763 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4764 if (pause->tx_pause)
4765 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4766
4767 if (!netif_running(dev))
4768 nv_update_linkspeed(dev);
4769 else
4770 nv_update_pause(dev, np->pause_flags);
4771 }
4772
4773 if (netif_running(dev)) {
4774 nv_start_rxtx(dev);
4775 nv_enable_irq(dev);
4776 }
4777 return 0;
4778 }
4779
4780 static u32 nv_get_rx_csum(struct net_device *dev)
4781 {
4782 struct fe_priv *np = netdev_priv(dev);
4783 return (np->rx_csum) != 0;
4784 }
4785
4786 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4787 {
4788 struct fe_priv *np = netdev_priv(dev);
4789 u8 __iomem *base = get_hwbase(dev);
4790 int retcode = 0;
4791
4792 if (np->driver_data & DEV_HAS_CHECKSUM) {
4793 if (data) {
4794 np->rx_csum = 1;
4795 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4796 } else {
4797 np->rx_csum = 0;
4798 /* vlan is dependent on rx checksum offload */
4799 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4800 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4801 }
4802 if (netif_running(dev)) {
4803 spin_lock_irq(&np->lock);
4804 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4805 spin_unlock_irq(&np->lock);
4806 }
4807 } else {
4808 return -EINVAL;
4809 }
4810
4811 return retcode;
4812 }
4813
4814 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4815 {
4816 struct fe_priv *np = netdev_priv(dev);
4817
4818 if (np->driver_data & DEV_HAS_CHECKSUM)
4819 return ethtool_op_set_tx_csum(dev, data);
4820 else
4821 return -EOPNOTSUPP;
4822 }
4823
4824 static int nv_set_sg(struct net_device *dev, u32 data)
4825 {
4826 struct fe_priv *np = netdev_priv(dev);
4827
4828 if (np->driver_data & DEV_HAS_CHECKSUM)
4829 return ethtool_op_set_sg(dev, data);
4830 else
4831 return -EOPNOTSUPP;
4832 }
4833
4834 static int nv_get_sset_count(struct net_device *dev, int sset)
4835 {
4836 struct fe_priv *np = netdev_priv(dev);
4837
4838 switch (sset) {
4839 case ETH_SS_TEST:
4840 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4841 return NV_TEST_COUNT_EXTENDED;
4842 else
4843 return NV_TEST_COUNT_BASE;
4844 case ETH_SS_STATS:
4845 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4846 return NV_DEV_STATISTICS_V3_COUNT;
4847 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4848 return NV_DEV_STATISTICS_V2_COUNT;
4849 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4850 return NV_DEV_STATISTICS_V1_COUNT;
4851 else
4852 return 0;
4853 default:
4854 return -EOPNOTSUPP;
4855 }
4856 }
4857
4858 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4859 {
4860 struct fe_priv *np = netdev_priv(dev);
4861
4862 /* update stats */
4863 nv_do_stats_poll((unsigned long)dev);
4864
4865 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4866 }
4867
4868 static int nv_link_test(struct net_device *dev)
4869 {
4870 struct fe_priv *np = netdev_priv(dev);
4871 int mii_status;
4872
4873 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4874 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4875
4876 /* check phy link status */
4877 if (!(mii_status & BMSR_LSTATUS))
4878 return 0;
4879 else
4880 return 1;
4881 }
4882
4883 static int nv_register_test(struct net_device *dev)
4884 {
4885 u8 __iomem *base = get_hwbase(dev);
4886 int i = 0;
4887 u32 orig_read, new_read;
4888
4889 do {
4890 orig_read = readl(base + nv_registers_test[i].reg);
4891
4892 /* xor with mask to toggle bits */
4893 orig_read ^= nv_registers_test[i].mask;
4894
4895 writel(orig_read, base + nv_registers_test[i].reg);
4896
4897 new_read = readl(base + nv_registers_test[i].reg);
4898
4899 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4900 return 0;
4901
4902 /* restore original value */
4903 orig_read ^= nv_registers_test[i].mask;
4904 writel(orig_read, base + nv_registers_test[i].reg);
4905
4906 } while (nv_registers_test[++i].reg != 0);
4907
4908 return 1;
4909 }
4910
4911 static int nv_interrupt_test(struct net_device *dev)
4912 {
4913 struct fe_priv *np = netdev_priv(dev);
4914 u8 __iomem *base = get_hwbase(dev);
4915 int ret = 1;
4916 int testcnt;
4917 u32 save_msi_flags, save_poll_interval = 0;
4918
4919 if (netif_running(dev)) {
4920 /* free current irq */
4921 nv_free_irq(dev);
4922 save_poll_interval = readl(base+NvRegPollingInterval);
4923 }
4924
4925 /* flag to test interrupt handler */
4926 np->intr_test = 0;
4927
4928 /* setup test irq */
4929 save_msi_flags = np->msi_flags;
4930 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4931 np->msi_flags |= 0x001; /* setup 1 vector */
4932 if (nv_request_irq(dev, 1))
4933 return 0;
4934
4935 /* setup timer interrupt */
4936 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4937 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4938
4939 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4940
4941 /* wait for at least one interrupt */
4942 msleep(100);
4943
4944 spin_lock_irq(&np->lock);
4945
4946 /* flag should be set within ISR */
4947 testcnt = np->intr_test;
4948 if (!testcnt)
4949 ret = 2;
4950
4951 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4952 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4953 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4954 else
4955 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4956
4957 spin_unlock_irq(&np->lock);
4958
4959 nv_free_irq(dev);
4960
4961 np->msi_flags = save_msi_flags;
4962
4963 if (netif_running(dev)) {
4964 writel(save_poll_interval, base + NvRegPollingInterval);
4965 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4966 /* restore original irq */
4967 if (nv_request_irq(dev, 0))
4968 return 0;
4969 }
4970
4971 return ret;
4972 }
4973
4974 static int nv_loopback_test(struct net_device *dev)
4975 {
4976 struct fe_priv *np = netdev_priv(dev);
4977 u8 __iomem *base = get_hwbase(dev);
4978 struct sk_buff *tx_skb, *rx_skb;
4979 dma_addr_t test_dma_addr;
4980 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4981 u32 flags;
4982 int len, i, pkt_len;
4983 u8 *pkt_data;
4984 u32 filter_flags = 0;
4985 u32 misc1_flags = 0;
4986 int ret = 1;
4987
4988 if (netif_running(dev)) {
4989 nv_disable_irq(dev);
4990 filter_flags = readl(base + NvRegPacketFilterFlags);
4991 misc1_flags = readl(base + NvRegMisc1);
4992 } else {
4993 nv_txrx_reset(dev);
4994 }
4995
4996 /* reinit driver view of the rx queue */
4997 set_bufsize(dev);
4998 nv_init_ring(dev);
4999
5000 /* setup hardware for loopback */
5001 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5002 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5003
5004 /* reinit nic view of the rx queue */
5005 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5006 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5007 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5008 base + NvRegRingSizes);
5009 pci_push(base);
5010
5011 /* restart rx engine */
5012 nv_start_rxtx(dev);
5013
5014 /* setup packet for tx */
5015 pkt_len = ETH_DATA_LEN;
5016 tx_skb = dev_alloc_skb(pkt_len);
5017 if (!tx_skb) {
5018 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5019 " of %s\n", dev->name);
5020 ret = 0;
5021 goto out;
5022 }
5023 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5024 skb_tailroom(tx_skb),
5025 PCI_DMA_FROMDEVICE);
5026 pkt_data = skb_put(tx_skb, pkt_len);
5027 for (i = 0; i < pkt_len; i++)
5028 pkt_data[i] = (u8)(i & 0xff);
5029
5030 if (!nv_optimized(np)) {
5031 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5032 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5033 } else {
5034 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5035 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5036 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5037 }
5038 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5039 pci_push(get_hwbase(dev));
5040
5041 msleep(500);
5042
5043 /* check for rx of the packet */
5044 if (!nv_optimized(np)) {
5045 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5046 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5047
5048 } else {
5049 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5050 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5051 }
5052
5053 if (flags & NV_RX_AVAIL) {
5054 ret = 0;
5055 } else if (np->desc_ver == DESC_VER_1) {
5056 if (flags & NV_RX_ERROR)
5057 ret = 0;
5058 } else {
5059 if (flags & NV_RX2_ERROR) {
5060 ret = 0;
5061 }
5062 }
5063
5064 if (ret) {
5065 if (len != pkt_len) {
5066 ret = 0;
5067 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5068 dev->name, len, pkt_len);
5069 } else {
5070 rx_skb = np->rx_skb[0].skb;
5071 for (i = 0; i < pkt_len; i++) {
5072 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5073 ret = 0;
5074 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5075 dev->name, i);
5076 break;
5077 }
5078 }
5079 }
5080 } else {
5081 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5082 }
5083
5084 pci_unmap_page(np->pci_dev, test_dma_addr,
5085 (skb_end_pointer(tx_skb) - tx_skb->data),
5086 PCI_DMA_TODEVICE);
5087 dev_kfree_skb_any(tx_skb);
5088 out:
5089 /* stop engines */
5090 nv_stop_rxtx(dev);
5091 nv_txrx_reset(dev);
5092 /* drain rx queue */
5093 nv_drain_rxtx(dev);
5094
5095 if (netif_running(dev)) {
5096 writel(misc1_flags, base + NvRegMisc1);
5097 writel(filter_flags, base + NvRegPacketFilterFlags);
5098 nv_enable_irq(dev);
5099 }
5100
5101 return ret;
5102 }
5103
5104 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5105 {
5106 struct fe_priv *np = netdev_priv(dev);
5107 u8 __iomem *base = get_hwbase(dev);
5108 int result;
5109 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5110
5111 if (!nv_link_test(dev)) {
5112 test->flags |= ETH_TEST_FL_FAILED;
5113 buffer[0] = 1;
5114 }
5115
5116 if (test->flags & ETH_TEST_FL_OFFLINE) {
5117 if (netif_running(dev)) {
5118 netif_stop_queue(dev);
5119 nv_napi_disable(dev);
5120 netif_tx_lock_bh(dev);
5121 netif_addr_lock(dev);
5122 spin_lock_irq(&np->lock);
5123 nv_disable_hw_interrupts(dev, np->irqmask);
5124 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5125 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5126 } else {
5127 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5128 }
5129 /* stop engines */
5130 nv_stop_rxtx(dev);
5131 nv_txrx_reset(dev);
5132 /* drain rx queue */
5133 nv_drain_rxtx(dev);
5134 spin_unlock_irq(&np->lock);
5135 netif_addr_unlock(dev);
5136 netif_tx_unlock_bh(dev);
5137 }
5138
5139 if (!nv_register_test(dev)) {
5140 test->flags |= ETH_TEST_FL_FAILED;
5141 buffer[1] = 1;
5142 }
5143
5144 result = nv_interrupt_test(dev);
5145 if (result != 1) {
5146 test->flags |= ETH_TEST_FL_FAILED;
5147 buffer[2] = 1;
5148 }
5149 if (result == 0) {
5150 /* bail out */
5151 return;
5152 }
5153
5154 if (!nv_loopback_test(dev)) {
5155 test->flags |= ETH_TEST_FL_FAILED;
5156 buffer[3] = 1;
5157 }
5158
5159 if (netif_running(dev)) {
5160 /* reinit driver view of the rx queue */
5161 set_bufsize(dev);
5162 if (nv_init_ring(dev)) {
5163 if (!np->in_shutdown)
5164 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5165 }
5166 /* reinit nic view of the rx queue */
5167 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5168 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5169 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5170 base + NvRegRingSizes);
5171 pci_push(base);
5172 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5173 pci_push(base);
5174 /* restart rx engine */
5175 nv_start_rxtx(dev);
5176 netif_start_queue(dev);
5177 nv_napi_enable(dev);
5178 nv_enable_hw_interrupts(dev, np->irqmask);
5179 }
5180 }
5181 }
5182
5183 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5184 {
5185 switch (stringset) {
5186 case ETH_SS_STATS:
5187 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5188 break;
5189 case ETH_SS_TEST:
5190 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5191 break;
5192 }
5193 }
5194
5195 static const struct ethtool_ops ops = {
5196 .get_drvinfo = nv_get_drvinfo,
5197 .get_link = ethtool_op_get_link,
5198 .get_wol = nv_get_wol,
5199 .set_wol = nv_set_wol,
5200 .get_settings = nv_get_settings,
5201 .set_settings = nv_set_settings,
5202 .get_regs_len = nv_get_regs_len,
5203 .get_regs = nv_get_regs,
5204 .nway_reset = nv_nway_reset,
5205 .set_tso = nv_set_tso,
5206 .get_ringparam = nv_get_ringparam,
5207 .set_ringparam = nv_set_ringparam,
5208 .get_pauseparam = nv_get_pauseparam,
5209 .set_pauseparam = nv_set_pauseparam,
5210 .get_rx_csum = nv_get_rx_csum,
5211 .set_rx_csum = nv_set_rx_csum,
5212 .set_tx_csum = nv_set_tx_csum,
5213 .set_sg = nv_set_sg,
5214 .get_strings = nv_get_strings,
5215 .get_ethtool_stats = nv_get_ethtool_stats,
5216 .get_sset_count = nv_get_sset_count,
5217 .self_test = nv_self_test,
5218 };
5219
5220 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5221 {
5222 struct fe_priv *np = get_nvpriv(dev);
5223
5224 spin_lock_irq(&np->lock);
5225
5226 /* save vlan group */
5227 np->vlangrp = grp;
5228
5229 if (grp) {
5230 /* enable vlan on MAC */
5231 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5232 } else {
5233 /* disable vlan on MAC */
5234 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5235 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5236 }
5237
5238 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5239
5240 spin_unlock_irq(&np->lock);
5241 }
5242
5243 /* The mgmt unit and driver use a semaphore to access the phy during init */
5244 static int nv_mgmt_acquire_sema(struct net_device *dev)
5245 {
5246 struct fe_priv *np = netdev_priv(dev);
5247 u8 __iomem *base = get_hwbase(dev);
5248 int i;
5249 u32 tx_ctrl, mgmt_sema;
5250
5251 for (i = 0; i < 10; i++) {
5252 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5253 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5254 break;
5255 msleep(500);
5256 }
5257
5258 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5259 return 0;
5260
5261 for (i = 0; i < 2; i++) {
5262 tx_ctrl = readl(base + NvRegTransmitterControl);
5263 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5264 writel(tx_ctrl, base + NvRegTransmitterControl);
5265
5266 /* verify that semaphore was acquired */
5267 tx_ctrl = readl(base + NvRegTransmitterControl);
5268 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5269 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5270 np->mgmt_sema = 1;
5271 return 1;
5272 }
5273 else
5274 udelay(50);
5275 }
5276
5277 return 0;
5278 }
5279
5280 static void nv_mgmt_release_sema(struct net_device *dev)
5281 {
5282 struct fe_priv *np = netdev_priv(dev);
5283 u8 __iomem *base = get_hwbase(dev);
5284 u32 tx_ctrl;
5285
5286 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5287 if (np->mgmt_sema) {
5288 tx_ctrl = readl(base + NvRegTransmitterControl);
5289 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5290 writel(tx_ctrl, base + NvRegTransmitterControl);
5291 }
5292 }
5293 }
5294
5295
5296 static int nv_mgmt_get_version(struct net_device *dev)
5297 {
5298 struct fe_priv *np = netdev_priv(dev);
5299 u8 __iomem *base = get_hwbase(dev);
5300 u32 data_ready = readl(base + NvRegTransmitterControl);
5301 u32 data_ready2 = 0;
5302 unsigned long start;
5303 int ready = 0;
5304
5305 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5306 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5307 start = jiffies;
5308 while (time_before(jiffies, start + 5*HZ)) {
5309 data_ready2 = readl(base + NvRegTransmitterControl);
5310 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5311 ready = 1;
5312 break;
5313 }
5314 schedule_timeout_uninterruptible(1);
5315 }
5316
5317 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5318 return 0;
5319
5320 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5321
5322 return 1;
5323 }
5324
5325 static int nv_open(struct net_device *dev)
5326 {
5327 struct fe_priv *np = netdev_priv(dev);
5328 u8 __iomem *base = get_hwbase(dev);
5329 int ret = 1;
5330 int oom, i;
5331 u32 low;
5332
5333 dprintk(KERN_DEBUG "nv_open: begin\n");
5334
5335 /* power up phy */
5336 mii_rw(dev, np->phyaddr, MII_BMCR,
5337 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5338
5339 /* erase previous misconfiguration */
5340 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5341 nv_mac_reset(dev);
5342 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5343 writel(0, base + NvRegMulticastAddrB);
5344 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5345 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5346 writel(0, base + NvRegPacketFilterFlags);
5347
5348 writel(0, base + NvRegTransmitterControl);
5349 writel(0, base + NvRegReceiverControl);
5350
5351 writel(0, base + NvRegAdapterControl);
5352
5353 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5354 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5355
5356 /* initialize descriptor rings */
5357 set_bufsize(dev);
5358 oom = nv_init_ring(dev);
5359
5360 writel(0, base + NvRegLinkSpeed);
5361 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5362 nv_txrx_reset(dev);
5363 writel(0, base + NvRegUnknownSetupReg6);
5364
5365 np->in_shutdown = 0;
5366
5367 /* give hw rings */
5368 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5369 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5370 base + NvRegRingSizes);
5371
5372 writel(np->linkspeed, base + NvRegLinkSpeed);
5373 if (np->desc_ver == DESC_VER_1)
5374 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5375 else
5376 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5377 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5378 writel(np->vlanctl_bits, base + NvRegVlanControl);
5379 pci_push(base);
5380 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5381 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5382 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5383 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5384
5385 writel(0, base + NvRegMIIMask);
5386 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5387 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5388
5389 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5390 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5391 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5392 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5393
5394 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5395
5396 get_random_bytes(&low, sizeof(low));
5397 low &= NVREG_SLOTTIME_MASK;
5398 if (np->desc_ver == DESC_VER_1) {
5399 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5400 } else {
5401 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5402 /* setup legacy backoff */
5403 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5404 } else {
5405 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5406 nv_gear_backoff_reseed(dev);
5407 }
5408 }
5409 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5410 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5411 if (poll_interval == -1) {
5412 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5413 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5414 else
5415 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5416 }
5417 else
5418 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5419 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5420 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5421 base + NvRegAdapterControl);
5422 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5423 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5424 if (np->wolenabled)
5425 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5426
5427 i = readl(base + NvRegPowerState);
5428 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5429 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5430
5431 pci_push(base);
5432 udelay(10);
5433 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5434
5435 nv_disable_hw_interrupts(dev, np->irqmask);
5436 pci_push(base);
5437 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5438 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5439 pci_push(base);
5440
5441 if (nv_request_irq(dev, 0)) {
5442 goto out_drain;
5443 }
5444
5445 /* ask for interrupts */
5446 nv_enable_hw_interrupts(dev, np->irqmask);
5447
5448 spin_lock_irq(&np->lock);
5449 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5450 writel(0, base + NvRegMulticastAddrB);
5451 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5452 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5453 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5454 /* One manual link speed update: Interrupts are enabled, future link
5455 * speed changes cause interrupts and are handled by nv_link_irq().
5456 */
5457 {
5458 u32 miistat;
5459 miistat = readl(base + NvRegMIIStatus);
5460 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5461 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5462 }
5463 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5464 * to init hw */
5465 np->linkspeed = 0;
5466 ret = nv_update_linkspeed(dev);
5467 nv_start_rxtx(dev);
5468 netif_start_queue(dev);
5469 nv_napi_enable(dev);
5470
5471 if (ret) {
5472 netif_carrier_on(dev);
5473 } else {
5474 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5475 netif_carrier_off(dev);
5476 }
5477 if (oom)
5478 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5479
5480 /* start statistics timer */
5481 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5482 mod_timer(&np->stats_poll,
5483 round_jiffies(jiffies + STATS_INTERVAL));
5484
5485 spin_unlock_irq(&np->lock);
5486
5487 return 0;
5488 out_drain:
5489 nv_drain_rxtx(dev);
5490 return ret;
5491 }
5492
5493 static int nv_close(struct net_device *dev)
5494 {
5495 struct fe_priv *np = netdev_priv(dev);
5496 u8 __iomem *base;
5497
5498 spin_lock_irq(&np->lock);
5499 np->in_shutdown = 1;
5500 spin_unlock_irq(&np->lock);
5501 nv_napi_disable(dev);
5502 synchronize_irq(np->pci_dev->irq);
5503
5504 del_timer_sync(&np->oom_kick);
5505 del_timer_sync(&np->nic_poll);
5506 del_timer_sync(&np->stats_poll);
5507
5508 netif_stop_queue(dev);
5509 spin_lock_irq(&np->lock);
5510 nv_stop_rxtx(dev);
5511 nv_txrx_reset(dev);
5512
5513 /* disable interrupts on the nic or we will lock up */
5514 base = get_hwbase(dev);
5515 nv_disable_hw_interrupts(dev, np->irqmask);
5516 pci_push(base);
5517 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5518
5519 spin_unlock_irq(&np->lock);
5520
5521 nv_free_irq(dev);
5522
5523 nv_drain_rxtx(dev);
5524
5525 if (np->wolenabled || !phy_power_down) {
5526 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5527 nv_start_rx(dev);
5528 } else {
5529 /* power down phy */
5530 mii_rw(dev, np->phyaddr, MII_BMCR,
5531 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5532 }
5533
5534 /* FIXME: power down nic */
5535
5536 return 0;
5537 }
5538
5539 static const struct net_device_ops nv_netdev_ops = {
5540 .ndo_open = nv_open,
5541 .ndo_stop = nv_close,
5542 .ndo_get_stats = nv_get_stats,
5543 .ndo_start_xmit = nv_start_xmit,
5544 .ndo_tx_timeout = nv_tx_timeout,
5545 .ndo_change_mtu = nv_change_mtu,
5546 .ndo_validate_addr = eth_validate_addr,
5547 .ndo_set_mac_address = nv_set_mac_address,
5548 .ndo_set_multicast_list = nv_set_multicast,
5549 .ndo_vlan_rx_register = nv_vlan_rx_register,
5550 #ifdef CONFIG_NET_POLL_CONTROLLER
5551 .ndo_poll_controller = nv_poll_controller,
5552 #endif
5553 };
5554
5555 static const struct net_device_ops nv_netdev_ops_optimized = {
5556 .ndo_open = nv_open,
5557 .ndo_stop = nv_close,
5558 .ndo_get_stats = nv_get_stats,
5559 .ndo_start_xmit = nv_start_xmit_optimized,
5560 .ndo_tx_timeout = nv_tx_timeout,
5561 .ndo_change_mtu = nv_change_mtu,
5562 .ndo_validate_addr = eth_validate_addr,
5563 .ndo_set_mac_address = nv_set_mac_address,
5564 .ndo_set_multicast_list = nv_set_multicast,
5565 .ndo_vlan_rx_register = nv_vlan_rx_register,
5566 #ifdef CONFIG_NET_POLL_CONTROLLER
5567 .ndo_poll_controller = nv_poll_controller,
5568 #endif
5569 };
5570
5571 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5572 {
5573 struct net_device *dev;
5574 struct fe_priv *np;
5575 unsigned long addr;
5576 u8 __iomem *base;
5577 int err, i;
5578 u32 powerstate, txreg;
5579 u32 phystate_orig = 0, phystate;
5580 int phyinitialized = 0;
5581 static int printed_version;
5582
5583 if (!printed_version++)
5584 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5585 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5586
5587 dev = alloc_etherdev(sizeof(struct fe_priv));
5588 err = -ENOMEM;
5589 if (!dev)
5590 goto out;
5591
5592 np = netdev_priv(dev);
5593 np->dev = dev;
5594 np->pci_dev = pci_dev;
5595 spin_lock_init(&np->lock);
5596 SET_NETDEV_DEV(dev, &pci_dev->dev);
5597
5598 init_timer(&np->oom_kick);
5599 np->oom_kick.data = (unsigned long) dev;
5600 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5601 init_timer(&np->nic_poll);
5602 np->nic_poll.data = (unsigned long) dev;
5603 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
5604 init_timer(&np->stats_poll);
5605 np->stats_poll.data = (unsigned long) dev;
5606 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
5607
5608 err = pci_enable_device(pci_dev);
5609 if (err)
5610 goto out_free;
5611
5612 pci_set_master(pci_dev);
5613
5614 err = pci_request_regions(pci_dev, DRV_NAME);
5615 if (err < 0)
5616 goto out_disable;
5617
5618 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5619 np->register_size = NV_PCI_REGSZ_VER3;
5620 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5621 np->register_size = NV_PCI_REGSZ_VER2;
5622 else
5623 np->register_size = NV_PCI_REGSZ_VER1;
5624
5625 err = -EINVAL;
5626 addr = 0;
5627 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5628 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5629 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5630 pci_resource_len(pci_dev, i),
5631 pci_resource_flags(pci_dev, i));
5632 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5633 pci_resource_len(pci_dev, i) >= np->register_size) {
5634 addr = pci_resource_start(pci_dev, i);
5635 break;
5636 }
5637 }
5638 if (i == DEVICE_COUNT_RESOURCE) {
5639 dev_printk(KERN_INFO, &pci_dev->dev,
5640 "Couldn't find register window\n");
5641 goto out_relreg;
5642 }
5643
5644 /* copy of driver data */
5645 np->driver_data = id->driver_data;
5646 /* copy of device id */
5647 np->device_id = id->device;
5648
5649 /* handle different descriptor versions */
5650 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5651 /* packet format 3: supports 40-bit addressing */
5652 np->desc_ver = DESC_VER_3;
5653 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5654 if (dma_64bit) {
5655 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5656 dev_printk(KERN_INFO, &pci_dev->dev,
5657 "64-bit DMA failed, using 32-bit addressing\n");
5658 else
5659 dev->features |= NETIF_F_HIGHDMA;
5660 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5661 dev_printk(KERN_INFO, &pci_dev->dev,
5662 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5663 }
5664 }
5665 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5666 /* packet format 2: supports jumbo frames */
5667 np->desc_ver = DESC_VER_2;
5668 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5669 } else {
5670 /* original packet format */
5671 np->desc_ver = DESC_VER_1;
5672 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5673 }
5674
5675 np->pkt_limit = NV_PKTLIMIT_1;
5676 if (id->driver_data & DEV_HAS_LARGEDESC)
5677 np->pkt_limit = NV_PKTLIMIT_2;
5678
5679 if (id->driver_data & DEV_HAS_CHECKSUM) {
5680 np->rx_csum = 1;
5681 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5682 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5683 dev->features |= NETIF_F_TSO;
5684 }
5685
5686 np->vlanctl_bits = 0;
5687 if (id->driver_data & DEV_HAS_VLAN) {
5688 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5689 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5690 }
5691
5692 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5693 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5694 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5695 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5696 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5697 }
5698
5699
5700 err = -ENOMEM;
5701 np->base = ioremap(addr, np->register_size);
5702 if (!np->base)
5703 goto out_relreg;
5704 dev->base_addr = (unsigned long)np->base;
5705
5706 dev->irq = pci_dev->irq;
5707
5708 np->rx_ring_size = RX_RING_DEFAULT;
5709 np->tx_ring_size = TX_RING_DEFAULT;
5710
5711 if (!nv_optimized(np)) {
5712 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5713 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5714 &np->ring_addr);
5715 if (!np->rx_ring.orig)
5716 goto out_unmap;
5717 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5718 } else {
5719 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5720 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5721 &np->ring_addr);
5722 if (!np->rx_ring.ex)
5723 goto out_unmap;
5724 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5725 }
5726 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5727 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5728 if (!np->rx_skb || !np->tx_skb)
5729 goto out_freering;
5730
5731 if (!nv_optimized(np))
5732 dev->netdev_ops = &nv_netdev_ops;
5733 else
5734 dev->netdev_ops = &nv_netdev_ops_optimized;
5735
5736 #ifdef CONFIG_FORCEDETH_NAPI
5737 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5738 #endif
5739 SET_ETHTOOL_OPS(dev, &ops);
5740 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5741
5742 pci_set_drvdata(pci_dev, dev);
5743
5744 /* read the mac address */
5745 base = get_hwbase(dev);
5746 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5747 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5748
5749 /* check the workaround bit for correct mac address order */
5750 txreg = readl(base + NvRegTransmitPoll);
5751 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5752 /* mac address is already in correct order */
5753 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5754 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5755 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5756 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5757 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5758 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5759 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5760 /* mac address is already in correct order */
5761 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5762 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5763 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5764 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5765 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5766 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5767 /*
5768 * Set orig mac address back to the reversed version.
5769 * This flag will be cleared during low power transition.
5770 * Therefore, we should always put back the reversed address.
5771 */
5772 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5773 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5774 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5775 } else {
5776 /* need to reverse mac address to correct order */
5777 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5778 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5779 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5780 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5781 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5782 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5783 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5784 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5785 }
5786 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5787
5788 if (!is_valid_ether_addr(dev->perm_addr)) {
5789 /*
5790 * Bad mac address. At least one bios sets the mac address
5791 * to 01:23:45:67:89:ab
5792 */
5793 dev_printk(KERN_ERR, &pci_dev->dev,
5794 "Invalid Mac address detected: %pM\n",
5795 dev->dev_addr);
5796 dev_printk(KERN_ERR, &pci_dev->dev,
5797 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5798 dev->dev_addr[0] = 0x00;
5799 dev->dev_addr[1] = 0x00;
5800 dev->dev_addr[2] = 0x6c;
5801 get_random_bytes(&dev->dev_addr[3], 3);
5802 }
5803
5804 dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5805 pci_name(pci_dev), dev->dev_addr);
5806
5807 /* set mac address */
5808 nv_copy_mac_to_hw(dev);
5809
5810 /* Workaround current PCI init glitch: wakeup bits aren't
5811 * being set from PCI PM capability.
5812 */
5813 device_init_wakeup(&pci_dev->dev, 1);
5814
5815 /* disable WOL */
5816 writel(0, base + NvRegWakeUpFlags);
5817 np->wolenabled = 0;
5818
5819 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5820
5821 /* take phy and nic out of low power mode */
5822 powerstate = readl(base + NvRegPowerState2);
5823 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5824 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5825 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5826 pci_dev->revision >= 0xA3)
5827 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5828 writel(powerstate, base + NvRegPowerState2);
5829 }
5830
5831 if (np->desc_ver == DESC_VER_1) {
5832 np->tx_flags = NV_TX_VALID;
5833 } else {
5834 np->tx_flags = NV_TX2_VALID;
5835 }
5836
5837 np->msi_flags = 0;
5838 if ((id->driver_data & DEV_HAS_MSI) && msi) {
5839 np->msi_flags |= NV_MSI_CAPABLE;
5840 }
5841 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5842 /* msix has had reported issues when modifying irqmask
5843 as in the case of napi, therefore, disable for now
5844 */
5845 #ifndef CONFIG_FORCEDETH_NAPI
5846 np->msi_flags |= NV_MSI_X_CAPABLE;
5847 #endif
5848 }
5849
5850 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5851 np->irqmask = NVREG_IRQMASK_CPU;
5852 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5853 np->msi_flags |= 0x0001;
5854 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5855 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5856 /* start off in throughput mode */
5857 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5858 /* remove support for msix mode */
5859 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5860 } else {
5861 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5862 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5863 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5864 np->msi_flags |= 0x0003;
5865 }
5866
5867 if (id->driver_data & DEV_NEED_TIMERIRQ)
5868 np->irqmask |= NVREG_IRQ_TIMER;
5869 if (id->driver_data & DEV_NEED_LINKTIMER) {
5870 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5871 np->need_linktimer = 1;
5872 np->link_timeout = jiffies + LINK_TIMEOUT;
5873 } else {
5874 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5875 np->need_linktimer = 0;
5876 }
5877
5878 /* Limit the number of tx's outstanding for hw bug */
5879 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5880 np->tx_limit = 1;
5881 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5882 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5883 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5884 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5885 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5886 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5887 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5888 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5889 pci_dev->revision >= 0xA2)
5890 np->tx_limit = 0;
5891 }
5892
5893 /* clear phy state and temporarily halt phy interrupts */
5894 writel(0, base + NvRegMIIMask);
5895 phystate = readl(base + NvRegAdapterControl);
5896 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5897 phystate_orig = 1;
5898 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5899 writel(phystate, base + NvRegAdapterControl);
5900 }
5901 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5902
5903 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5904 /* management unit running on the mac? */
5905 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5906 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5907 nv_mgmt_acquire_sema(dev) &&
5908 nv_mgmt_get_version(dev)) {
5909 np->mac_in_use = 1;
5910 if (np->mgmt_version > 0) {
5911 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5912 }
5913 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5914 pci_name(pci_dev), np->mac_in_use);
5915 /* management unit setup the phy already? */
5916 if (np->mac_in_use &&
5917 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5918 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5919 /* phy is inited by mgmt unit */
5920 phyinitialized = 1;
5921 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5922 pci_name(pci_dev));
5923 } else {
5924 /* we need to init the phy */
5925 }
5926 }
5927 }
5928
5929 /* find a suitable phy */
5930 for (i = 1; i <= 32; i++) {
5931 int id1, id2;
5932 int phyaddr = i & 0x1F;
5933
5934 spin_lock_irq(&np->lock);
5935 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5936 spin_unlock_irq(&np->lock);
5937 if (id1 < 0 || id1 == 0xffff)
5938 continue;
5939 spin_lock_irq(&np->lock);
5940 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5941 spin_unlock_irq(&np->lock);
5942 if (id2 < 0 || id2 == 0xffff)
5943 continue;
5944
5945 np->phy_model = id2 & PHYID2_MODEL_MASK;
5946 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5947 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5948 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5949 pci_name(pci_dev), id1, id2, phyaddr);
5950 np->phyaddr = phyaddr;
5951 np->phy_oui = id1 | id2;
5952
5953 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5954 if (np->phy_oui == PHY_OUI_REALTEK2)
5955 np->phy_oui = PHY_OUI_REALTEK;
5956 /* Setup phy revision for Realtek */
5957 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5958 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5959
5960 break;
5961 }
5962 if (i == 33) {
5963 dev_printk(KERN_INFO, &pci_dev->dev,
5964 "open: Could not find a valid PHY.\n");
5965 goto out_error;
5966 }
5967
5968 if (!phyinitialized) {
5969 /* reset it */
5970 phy_init(dev);
5971 } else {
5972 /* see if it is a gigabit phy */
5973 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5974 if (mii_status & PHY_GIGABIT) {
5975 np->gigabit = PHY_GIGABIT;
5976 }
5977 }
5978
5979 /* set default link speed settings */
5980 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5981 np->duplex = 0;
5982 np->autoneg = 1;
5983
5984 err = register_netdev(dev);
5985 if (err) {
5986 dev_printk(KERN_INFO, &pci_dev->dev,
5987 "unable to register netdev: %d\n", err);
5988 goto out_error;
5989 }
5990
5991 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5992 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5993 dev->name,
5994 np->phy_oui,
5995 np->phyaddr,
5996 dev->dev_addr[0],
5997 dev->dev_addr[1],
5998 dev->dev_addr[2],
5999 dev->dev_addr[3],
6000 dev->dev_addr[4],
6001 dev->dev_addr[5]);
6002
6003 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6004 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6005 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6006 "csum " : "",
6007 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
6008 "vlan " : "",
6009 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6010 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6011 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6012 np->gigabit == PHY_GIGABIT ? "gbit " : "",
6013 np->need_linktimer ? "lnktim " : "",
6014 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6015 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6016 np->desc_ver);
6017
6018 return 0;
6019
6020 out_error:
6021 if (phystate_orig)
6022 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6023 pci_set_drvdata(pci_dev, NULL);
6024 out_freering:
6025 free_rings(dev);
6026 out_unmap:
6027 iounmap(get_hwbase(dev));
6028 out_relreg:
6029 pci_release_regions(pci_dev);
6030 out_disable:
6031 pci_disable_device(pci_dev);
6032 out_free:
6033 free_netdev(dev);
6034 out:
6035 return err;
6036 }
6037
6038 static void nv_restore_phy(struct net_device *dev)
6039 {
6040 struct fe_priv *np = netdev_priv(dev);
6041 u16 phy_reserved, mii_control;
6042
6043 if (np->phy_oui == PHY_OUI_REALTEK &&
6044 np->phy_model == PHY_MODEL_REALTEK_8201 &&
6045 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6046 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6047 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6048 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6049 phy_reserved |= PHY_REALTEK_INIT8;
6050 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6051 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6052
6053 /* restart auto negotiation */
6054 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6055 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6056 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6057 }
6058 }
6059
6060 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6061 {
6062 struct net_device *dev = pci_get_drvdata(pci_dev);
6063 struct fe_priv *np = netdev_priv(dev);
6064 u8 __iomem *base = get_hwbase(dev);
6065
6066 /* special op: write back the misordered MAC address - otherwise
6067 * the next nv_probe would see a wrong address.
6068 */
6069 writel(np->orig_mac[0], base + NvRegMacAddrA);
6070 writel(np->orig_mac[1], base + NvRegMacAddrB);
6071 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6072 base + NvRegTransmitPoll);
6073 }
6074
6075 static void __devexit nv_remove(struct pci_dev *pci_dev)
6076 {
6077 struct net_device *dev = pci_get_drvdata(pci_dev);
6078
6079 unregister_netdev(dev);
6080
6081 nv_restore_mac_addr(pci_dev);
6082
6083 /* restore any phy related changes */
6084 nv_restore_phy(dev);
6085
6086 nv_mgmt_release_sema(dev);
6087
6088 /* free all structures */
6089 free_rings(dev);
6090 iounmap(get_hwbase(dev));
6091 pci_release_regions(pci_dev);
6092 pci_disable_device(pci_dev);
6093 free_netdev(dev);
6094 pci_set_drvdata(pci_dev, NULL);
6095 }
6096
6097 #ifdef CONFIG_PM
6098 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6099 {
6100 struct net_device *dev = pci_get_drvdata(pdev);
6101 struct fe_priv *np = netdev_priv(dev);
6102 u8 __iomem *base = get_hwbase(dev);
6103 int i;
6104
6105 if (netif_running(dev)) {
6106 // Gross.
6107 nv_close(dev);
6108 }
6109 netif_device_detach(dev);
6110
6111 /* save non-pci configuration space */
6112 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6113 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6114
6115 pci_save_state(pdev);
6116 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6117 pci_disable_device(pdev);
6118 pci_set_power_state(pdev, pci_choose_state(pdev, state));
6119 return 0;
6120 }
6121
6122 static int nv_resume(struct pci_dev *pdev)
6123 {
6124 struct net_device *dev = pci_get_drvdata(pdev);
6125 struct fe_priv *np = netdev_priv(dev);
6126 u8 __iomem *base = get_hwbase(dev);
6127 int i, rc = 0;
6128
6129 pci_set_power_state(pdev, PCI_D0);
6130 pci_restore_state(pdev);
6131 /* ack any pending wake events, disable PME */
6132 pci_enable_wake(pdev, PCI_D0, 0);
6133
6134 /* restore non-pci configuration space */
6135 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6136 writel(np->saved_config_space[i], base+i*sizeof(u32));
6137
6138 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6139
6140 /* restore phy state, including autoneg */
6141 phy_init(dev);
6142
6143 netif_device_attach(dev);
6144 if (netif_running(dev)) {
6145 rc = nv_open(dev);
6146 nv_set_multicast(dev);
6147 }
6148 return rc;
6149 }
6150
6151 static void nv_shutdown(struct pci_dev *pdev)
6152 {
6153 struct net_device *dev = pci_get_drvdata(pdev);
6154 struct fe_priv *np = netdev_priv(dev);
6155
6156 if (netif_running(dev))
6157 nv_close(dev);
6158
6159 /*
6160 * Restore the MAC so a kernel started by kexec won't get confused.
6161 * If we really go for poweroff, we must not restore the MAC,
6162 * otherwise the MAC for WOL will be reversed at least on some boards.
6163 */
6164 if (system_state != SYSTEM_POWER_OFF) {
6165 nv_restore_mac_addr(pdev);
6166 }
6167
6168 pci_disable_device(pdev);
6169 /*
6170 * Apparently it is not possible to reinitialise from D3 hot,
6171 * only put the device into D3 if we really go for poweroff.
6172 */
6173 if (system_state == SYSTEM_POWER_OFF) {
6174 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6175 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6176 pci_set_power_state(pdev, PCI_D3hot);
6177 }
6178 }
6179 #else
6180 #define nv_suspend NULL
6181 #define nv_shutdown NULL
6182 #define nv_resume NULL
6183 #endif /* CONFIG_PM */
6184
6185 static struct pci_device_id pci_tbl[] = {
6186 { /* nForce Ethernet Controller */
6187 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
6188 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6189 },
6190 { /* nForce2 Ethernet Controller */
6191 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
6192 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6193 },
6194 { /* nForce3 Ethernet Controller */
6195 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
6196 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6197 },
6198 { /* nForce3 Ethernet Controller */
6199 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
6200 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6201 },
6202 { /* nForce3 Ethernet Controller */
6203 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
6204 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6205 },
6206 { /* nForce3 Ethernet Controller */
6207 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
6208 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6209 },
6210 { /* nForce3 Ethernet Controller */
6211 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
6212 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6213 },
6214 { /* CK804 Ethernet Controller */
6215 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
6216 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6217 },
6218 { /* CK804 Ethernet Controller */
6219 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
6220 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6221 },
6222 { /* MCP04 Ethernet Controller */
6223 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
6224 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6225 },
6226 { /* MCP04 Ethernet Controller */
6227 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
6228 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6229 },
6230 { /* MCP51 Ethernet Controller */
6231 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
6232 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6233 },
6234 { /* MCP51 Ethernet Controller */
6235 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
6236 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6237 },
6238 { /* MCP55 Ethernet Controller */
6239 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
6240 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6241 },
6242 { /* MCP55 Ethernet Controller */
6243 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
6244 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6245 },
6246 { /* MCP61 Ethernet Controller */
6247 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
6248 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6249 },
6250 { /* MCP61 Ethernet Controller */
6251 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
6252 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6253 },
6254 { /* MCP61 Ethernet Controller */
6255 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
6256 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6257 },
6258 { /* MCP61 Ethernet Controller */
6259 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
6260 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6261 },
6262 { /* MCP65 Ethernet Controller */
6263 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
6264 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6265 },
6266 { /* MCP65 Ethernet Controller */
6267 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
6268 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6269 },
6270 { /* MCP65 Ethernet Controller */
6271 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
6272 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6273 },
6274 { /* MCP65 Ethernet Controller */
6275 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
6276 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6277 },
6278 { /* MCP67 Ethernet Controller */
6279 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
6280 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6281 },
6282 { /* MCP67 Ethernet Controller */
6283 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
6284 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6285 },
6286 { /* MCP67 Ethernet Controller */
6287 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
6288 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6289 },
6290 { /* MCP67 Ethernet Controller */
6291 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
6292 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6293 },
6294 { /* MCP73 Ethernet Controller */
6295 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
6296 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6297 },
6298 { /* MCP73 Ethernet Controller */
6299 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
6300 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6301 },
6302 { /* MCP73 Ethernet Controller */
6303 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
6304 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6305 },
6306 { /* MCP73 Ethernet Controller */
6307 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
6308 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6309 },
6310 { /* MCP77 Ethernet Controller */
6311 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6312 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6313 },
6314 { /* MCP77 Ethernet Controller */
6315 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6316 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6317 },
6318 { /* MCP77 Ethernet Controller */
6319 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6320 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6321 },
6322 { /* MCP77 Ethernet Controller */
6323 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6324 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6325 },
6326 { /* MCP79 Ethernet Controller */
6327 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6328 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6329 },
6330 { /* MCP79 Ethernet Controller */
6331 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6332 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6333 },
6334 { /* MCP79 Ethernet Controller */
6335 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6336 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6337 },
6338 { /* MCP79 Ethernet Controller */
6339 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6340 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6341 },
6342 {0,},
6343 };
6344
6345 static struct pci_driver driver = {
6346 .name = DRV_NAME,
6347 .id_table = pci_tbl,
6348 .probe = nv_probe,
6349 .remove = __devexit_p(nv_remove),
6350 .suspend = nv_suspend,
6351 .resume = nv_resume,
6352 .shutdown = nv_shutdown,
6353 };
6354
6355 static int __init init_nic(void)
6356 {
6357 return pci_register_driver(&driver);
6358 }
6359
6360 static void __exit exit_nic(void)
6361 {
6362 pci_unregister_driver(&driver);
6363 }
6364
6365 module_param(max_interrupt_work, int, 0);
6366 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6367 module_param(optimization_mode, int, 0);
6368 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6369 module_param(poll_interval, int, 0);
6370 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6371 module_param(msi, int, 0);
6372 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6373 module_param(msix, int, 0);
6374 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6375 module_param(dma_64bit, int, 0);
6376 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6377 module_param(phy_cross, int, 0);
6378 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6379 module_param(phy_power_down, int, 0);
6380 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6381
6382 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6383 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6384 MODULE_LICENSE("GPL");
6385
6386 MODULE_DEVICE_TABLE(pci, pci_tbl);
6387
6388 module_init(init_nic);
6389 module_exit(exit_nic);
Support for the Chinese Samsung S3C2440 based development boards