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Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable
[linux-2.6/mini2440.git] / drivers / net / 8139too.c
blob1fc45431a6209c6ace608cff2ed87174fea4bd55
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #if RTL8139_DEBUG
130 /* note: prints function name for you */
131 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
132 #else
133 # define DPRINTK(fmt, args...)
134 #endif
135
136 #ifdef RTL8139_NDEBUG
137 # define assert(expr) do {} while (0)
138 #else
139 # define assert(expr) \
140 if(unlikely(!(expr))) { \
141 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
142 #expr, __FILE__, __func__, __LINE__); \
143 }
144 #endif
145
146
147 /* A few user-configurable values. */
148 /* media options */
149 #define MAX_UNITS 8
150 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
151 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
152
153 /* Whether to use MMIO or PIO. Default to MMIO. */
154 #ifdef CONFIG_8139TOO_PIO
155 static int use_io = 1;
156 #else
157 static int use_io = 0;
158 #endif
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 0 /* 8K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static const struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 TimerInt = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 static const struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasHltClk /* XXX undocumented? */
556 | HasLWake,
557 },
558
559 { "RTL-8101",
560 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 HasLWake,
562 },
563 };
564
565 struct rtl_extra_stats {
566 unsigned long early_rx;
567 unsigned long tx_buf_mapped;
568 unsigned long tx_timeouts;
569 unsigned long rx_lost_in_ring;
570 };
571
572 struct rtl8139_private {
573 void __iomem *mmio_addr;
574 int drv_flags;
575 struct pci_dev *pci_dev;
576 u32 msg_enable;
577 struct napi_struct napi;
578 struct net_device *dev;
579
580 unsigned char *rx_ring;
581 unsigned int cur_rx; /* RX buf index of next pkt */
582 dma_addr_t rx_ring_dma;
583
584 unsigned int tx_flag;
585 unsigned long cur_tx;
586 unsigned long dirty_tx;
587 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
588 unsigned char *tx_bufs; /* Tx bounce buffer region. */
589 dma_addr_t tx_bufs_dma;
590
591 signed char phys[4]; /* MII device addresses. */
592
593 /* Twister tune state. */
594 char twistie, twist_row, twist_col;
595
596 unsigned int watchdog_fired : 1;
597 unsigned int default_port : 4; /* Last dev->if_port value. */
598 unsigned int have_thread : 1;
599
600 spinlock_t lock;
601 spinlock_t rx_lock;
602
603 chip_t chipset;
604 u32 rx_config;
605 struct rtl_extra_stats xstats;
606
607 struct delayed_work thread;
608
609 struct mii_if_info mii;
610 unsigned int regs_len;
611 unsigned long fifo_copy_timeout;
612 };
613
614 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
615 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
616 MODULE_LICENSE("GPL");
617 MODULE_VERSION(DRV_VERSION);
618
619 module_param(use_io, int, 0);
620 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
621 module_param(multicast_filter_limit, int, 0);
622 module_param_array(media, int, NULL, 0);
623 module_param_array(full_duplex, int, NULL, 0);
624 module_param(debug, int, 0);
625 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
626 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
627 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
628 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
629
630 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
631 static int rtl8139_open (struct net_device *dev);
632 static int mdio_read (struct net_device *dev, int phy_id, int location);
633 static void mdio_write (struct net_device *dev, int phy_id, int location,
634 int val);
635 static void rtl8139_start_thread(struct rtl8139_private *tp);
636 static void rtl8139_tx_timeout (struct net_device *dev);
637 static void rtl8139_init_ring (struct net_device *dev);
638 static int rtl8139_start_xmit (struct sk_buff *skb,
639 struct net_device *dev);
640 #ifdef CONFIG_NET_POLL_CONTROLLER
641 static void rtl8139_poll_controller(struct net_device *dev);
642 #endif
643 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
644 static int rtl8139_poll(struct napi_struct *napi, int budget);
645 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
646 static int rtl8139_close (struct net_device *dev);
647 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
648 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
649 static void rtl8139_set_rx_mode (struct net_device *dev);
650 static void __set_rx_mode (struct net_device *dev);
651 static void rtl8139_hw_start (struct net_device *dev);
652 static void rtl8139_thread (struct work_struct *work);
653 static void rtl8139_tx_timeout_task(struct work_struct *work);
654 static const struct ethtool_ops rtl8139_ethtool_ops;
655
656 /* write MMIO register, with flush */
657 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
658 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
659 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
660 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
661
662 /* write MMIO register */
663 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
664 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
665 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
666
667 /* read MMIO register */
668 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
669 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
670 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
671
672
673 static const u16 rtl8139_intr_mask =
674 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
675 TxErr | TxOK | RxErr | RxOK;
676
677 static const u16 rtl8139_norx_intr_mask =
678 PCIErr | PCSTimeout | RxUnderrun |
679 TxErr | TxOK | RxErr ;
680
681 #if RX_BUF_IDX == 0
682 static const unsigned int rtl8139_rx_config =
683 RxCfgRcv8K | RxNoWrap |
684 (RX_FIFO_THRESH << RxCfgFIFOShift) |
685 (RX_DMA_BURST << RxCfgDMAShift);
686 #elif RX_BUF_IDX == 1
687 static const unsigned int rtl8139_rx_config =
688 RxCfgRcv16K | RxNoWrap |
689 (RX_FIFO_THRESH << RxCfgFIFOShift) |
690 (RX_DMA_BURST << RxCfgDMAShift);
691 #elif RX_BUF_IDX == 2
692 static const unsigned int rtl8139_rx_config =
693 RxCfgRcv32K | RxNoWrap |
694 (RX_FIFO_THRESH << RxCfgFIFOShift) |
695 (RX_DMA_BURST << RxCfgDMAShift);
696 #elif RX_BUF_IDX == 3
697 static const unsigned int rtl8139_rx_config =
698 RxCfgRcv64K |
699 (RX_FIFO_THRESH << RxCfgFIFOShift) |
700 (RX_DMA_BURST << RxCfgDMAShift);
701 #else
702 #error "Invalid configuration for 8139_RXBUF_IDX"
703 #endif
704
705 static const unsigned int rtl8139_tx_config =
706 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
707
708 static void __rtl8139_cleanup_dev (struct net_device *dev)
709 {
710 struct rtl8139_private *tp = netdev_priv(dev);
711 struct pci_dev *pdev;
712
713 assert (dev != NULL);
714 assert (tp->pci_dev != NULL);
715 pdev = tp->pci_dev;
716
717 if (tp->mmio_addr)
718 pci_iounmap (pdev, tp->mmio_addr);
719
720 /* it's ok to call this even if we have no regions to free */
721 pci_release_regions (pdev);
722
723 free_netdev(dev);
724 pci_set_drvdata (pdev, NULL);
725 }
726
727
728 static void rtl8139_chip_reset (void __iomem *ioaddr)
729 {
730 int i;
731
732 /* Soft reset the chip. */
733 RTL_W8 (ChipCmd, CmdReset);
734
735 /* Check that the chip has finished the reset. */
736 for (i = 1000; i > 0; i--) {
737 barrier();
738 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
739 break;
740 udelay (10);
741 }
742 }
743
744
745 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
746 {
747 void __iomem *ioaddr;
748 struct net_device *dev;
749 struct rtl8139_private *tp;
750 u8 tmp8;
751 int rc, disable_dev_on_err = 0;
752 unsigned int i;
753 unsigned long pio_start, pio_end, pio_flags, pio_len;
754 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
755 u32 version;
756
757 assert (pdev != NULL);
758
759 /* dev and priv zeroed in alloc_etherdev */
760 dev = alloc_etherdev (sizeof (*tp));
761 if (dev == NULL) {
762 dev_err(&pdev->dev, "Unable to alloc new net device\n");
763 return ERR_PTR(-ENOMEM);
764 }
765 SET_NETDEV_DEV(dev, &pdev->dev);
766
767 tp = netdev_priv(dev);
768 tp->pci_dev = pdev;
769
770 /* enable device (incl. PCI PM wakeup and hotplug setup) */
771 rc = pci_enable_device (pdev);
772 if (rc)
773 goto err_out;
774
775 pio_start = pci_resource_start (pdev, 0);
776 pio_end = pci_resource_end (pdev, 0);
777 pio_flags = pci_resource_flags (pdev, 0);
778 pio_len = pci_resource_len (pdev, 0);
779
780 mmio_start = pci_resource_start (pdev, 1);
781 mmio_end = pci_resource_end (pdev, 1);
782 mmio_flags = pci_resource_flags (pdev, 1);
783 mmio_len = pci_resource_len (pdev, 1);
784
785 /* set this immediately, we need to know before
786 * we talk to the chip directly */
787 DPRINTK("PIO region size == 0x%02X\n", pio_len);
788 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
789
790 retry:
791 if (use_io) {
792 /* make sure PCI base addr 0 is PIO */
793 if (!(pio_flags & IORESOURCE_IO)) {
794 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
795 rc = -ENODEV;
796 goto err_out;
797 }
798 /* check for weird/broken PCI region reporting */
799 if (pio_len < RTL_MIN_IO_SIZE) {
800 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
801 rc = -ENODEV;
802 goto err_out;
803 }
804 } else {
805 /* make sure PCI base addr 1 is MMIO */
806 if (!(mmio_flags & IORESOURCE_MEM)) {
807 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
808 rc = -ENODEV;
809 goto err_out;
810 }
811 if (mmio_len < RTL_MIN_IO_SIZE) {
812 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
813 rc = -ENODEV;
814 goto err_out;
815 }
816 }
817
818 rc = pci_request_regions (pdev, DRV_NAME);
819 if (rc)
820 goto err_out;
821 disable_dev_on_err = 1;
822
823 /* enable PCI bus-mastering */
824 pci_set_master (pdev);
825
826 if (use_io) {
827 ioaddr = pci_iomap(pdev, 0, 0);
828 if (!ioaddr) {
829 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
830 rc = -EIO;
831 goto err_out;
832 }
833 dev->base_addr = pio_start;
834 tp->regs_len = pio_len;
835 } else {
836 /* ioremap MMIO region */
837 ioaddr = pci_iomap(pdev, 1, 0);
838 if (ioaddr == NULL) {
839 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
840 pci_release_regions(pdev);
841 use_io = 1;
842 goto retry;
843 }
844 dev->base_addr = (long) ioaddr;
845 tp->regs_len = mmio_len;
846 }
847 tp->mmio_addr = ioaddr;
848
849 /* Bring old chips out of low-power mode. */
850 RTL_W8 (HltClk, 'R');
851
852 /* check for missing/broken hardware */
853 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
854 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
855 rc = -EIO;
856 goto err_out;
857 }
858
859 /* identify chip attached to board */
860 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
861 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
862 if (version == rtl_chip_info[i].version) {
863 tp->chipset = i;
864 goto match;
865 }
866
867 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
868 dev_printk (KERN_DEBUG, &pdev->dev,
869 "unknown chip version, assuming RTL-8139\n");
870 dev_printk (KERN_DEBUG, &pdev->dev,
871 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
872 tp->chipset = 0;
873
874 match:
875 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
876 version, i, rtl_chip_info[i].name);
877
878 if (tp->chipset >= CH_8139B) {
879 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
880 DPRINTK("PCI PM wakeup\n");
881 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
882 (tmp8 & LWAKE))
883 new_tmp8 &= ~LWAKE;
884 new_tmp8 |= Cfg1_PM_Enable;
885 if (new_tmp8 != tmp8) {
886 RTL_W8 (Cfg9346, Cfg9346_Unlock);
887 RTL_W8 (Config1, tmp8);
888 RTL_W8 (Cfg9346, Cfg9346_Lock);
889 }
890 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
891 tmp8 = RTL_R8 (Config4);
892 if (tmp8 & LWPTN) {
893 RTL_W8 (Cfg9346, Cfg9346_Unlock);
894 RTL_W8 (Config4, tmp8 & ~LWPTN);
895 RTL_W8 (Cfg9346, Cfg9346_Lock);
896 }
897 }
898 } else {
899 DPRINTK("Old chip wakeup\n");
900 tmp8 = RTL_R8 (Config1);
901 tmp8 &= ~(SLEEP | PWRDN);
902 RTL_W8 (Config1, tmp8);
903 }
904
905 rtl8139_chip_reset (ioaddr);
906
907 return dev;
908
909 err_out:
910 __rtl8139_cleanup_dev (dev);
911 if (disable_dev_on_err)
912 pci_disable_device (pdev);
913 return ERR_PTR(rc);
914 }
915
916 static const struct net_device_ops rtl8139_netdev_ops = {
917 .ndo_open = rtl8139_open,
918 .ndo_stop = rtl8139_close,
919 .ndo_get_stats = rtl8139_get_stats,
920 .ndo_validate_addr = eth_validate_addr,
921 .ndo_set_mac_address = rtl8139_set_mac_address,
922 .ndo_start_xmit = rtl8139_start_xmit,
923 .ndo_set_multicast_list = rtl8139_set_rx_mode,
924 .ndo_do_ioctl = netdev_ioctl,
925 .ndo_tx_timeout = rtl8139_tx_timeout,
926 #ifdef CONFIG_NET_POLL_CONTROLLER
927 .ndo_poll_controller = rtl8139_poll_controller,
928 #endif
929 };
930
931 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
932 const struct pci_device_id *ent)
933 {
934 struct net_device *dev = NULL;
935 struct rtl8139_private *tp;
936 int i, addr_len, option;
937 void __iomem *ioaddr;
938 static int board_idx = -1;
939
940 assert (pdev != NULL);
941 assert (ent != NULL);
942
943 board_idx++;
944
945 /* when we're built into the kernel, the driver version message
946 * is only printed if at least one 8139 board has been found
947 */
948 #ifndef MODULE
949 {
950 static int printed_version;
951 if (!printed_version++)
952 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
953 }
954 #endif
955
956 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
957 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
958 dev_info(&pdev->dev,
959 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
960 pdev->vendor, pdev->device, pdev->revision);
961 return -ENODEV;
962 }
963
964 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
965 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
966 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
967 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
968 printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");
969 use_io = 1;
970 }
971
972 dev = rtl8139_init_board (pdev);
973 if (IS_ERR(dev))
974 return PTR_ERR(dev);
975
976 assert (dev != NULL);
977 tp = netdev_priv(dev);
978 tp->dev = dev;
979
980 ioaddr = tp->mmio_addr;
981 assert (ioaddr != NULL);
982
983 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
984 for (i = 0; i < 3; i++)
985 ((__le16 *) (dev->dev_addr))[i] =
986 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
987 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
988
989 /* The Rtl8139-specific entries in the device structure. */
990 dev->netdev_ops = &rtl8139_netdev_ops;
991 dev->ethtool_ops = &rtl8139_ethtool_ops;
992 dev->watchdog_timeo = TX_TIMEOUT;
993 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
994
995 /* note: the hardware is not capable of sg/csum/highdma, however
996 * through the use of skb_copy_and_csum_dev we enable these
997 * features
998 */
999 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1000
1001 dev->irq = pdev->irq;
1002
1003 /* tp zeroed and aligned in alloc_etherdev */
1004 tp = netdev_priv(dev);
1005
1006 /* note: tp->chipset set in rtl8139_init_board */
1007 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1008 tp->mmio_addr = ioaddr;
1009 tp->msg_enable =
1010 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1011 spin_lock_init (&tp->lock);
1012 spin_lock_init (&tp->rx_lock);
1013 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1014 tp->mii.dev = dev;
1015 tp->mii.mdio_read = mdio_read;
1016 tp->mii.mdio_write = mdio_write;
1017 tp->mii.phy_id_mask = 0x3f;
1018 tp->mii.reg_num_mask = 0x1f;
1019
1020 /* dev is fully set up and ready to use now */
1021 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1022 i = register_netdev (dev);
1023 if (i) goto err_out;
1024
1025 pci_set_drvdata (pdev, dev);
1026
1027 printk (KERN_INFO "%s: %s at 0x%lx, "
1028 "%pM, IRQ %d\n",
1029 dev->name,
1030 board_info[ent->driver_data].name,
1031 dev->base_addr,
1032 dev->dev_addr,
1033 dev->irq);
1034
1035 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1036 dev->name, rtl_chip_info[tp->chipset].name);
1037
1038 /* Find the connected MII xcvrs.
1039 Doing this in open() would allow detecting external xcvrs later, but
1040 takes too much time. */
1041 #ifdef CONFIG_8139TOO_8129
1042 if (tp->drv_flags & HAS_MII_XCVR) {
1043 int phy, phy_idx = 0;
1044 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1045 int mii_status = mdio_read(dev, phy, 1);
1046 if (mii_status != 0xffff && mii_status != 0x0000) {
1047 u16 advertising = mdio_read(dev, phy, 4);
1048 tp->phys[phy_idx++] = phy;
1049 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1050 "advertising %4.4x.\n",
1051 dev->name, phy, mii_status, advertising);
1052 }
1053 }
1054 if (phy_idx == 0) {
1055 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1056 "transceiver.\n",
1057 dev->name);
1058 tp->phys[0] = 32;
1059 }
1060 } else
1061 #endif
1062 tp->phys[0] = 32;
1063 tp->mii.phy_id = tp->phys[0];
1064
1065 /* The lower four bits are the media type. */
1066 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1067 if (option > 0) {
1068 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1069 tp->default_port = option & 0xFF;
1070 if (tp->default_port)
1071 tp->mii.force_media = 1;
1072 }
1073 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1074 tp->mii.full_duplex = full_duplex[board_idx];
1075 if (tp->mii.full_duplex) {
1076 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1077 /* Changing the MII-advertised media because might prevent
1078 re-connection. */
1079 tp->mii.force_media = 1;
1080 }
1081 if (tp->default_port) {
1082 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1083 (option & 0x20 ? 100 : 10),
1084 (option & 0x10 ? "full" : "half"));
1085 mdio_write(dev, tp->phys[0], 0,
1086 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1087 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1088 }
1089
1090 /* Put the chip into low-power mode. */
1091 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1092 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1093
1094 return 0;
1095
1096 err_out:
1097 __rtl8139_cleanup_dev (dev);
1098 pci_disable_device (pdev);
1099 return i;
1100 }
1101
1102
1103 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1104 {
1105 struct net_device *dev = pci_get_drvdata (pdev);
1106
1107 assert (dev != NULL);
1108
1109 flush_scheduled_work();
1110
1111 unregister_netdev (dev);
1112
1113 __rtl8139_cleanup_dev (dev);
1114 pci_disable_device (pdev);
1115 }
1116
1117
1118 /* Serial EEPROM section. */
1119
1120 /* EEPROM_Ctrl bits. */
1121 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1122 #define EE_CS 0x08 /* EEPROM chip select. */
1123 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1124 #define EE_WRITE_0 0x00
1125 #define EE_WRITE_1 0x02
1126 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1127 #define EE_ENB (0x80 | EE_CS)
1128
1129 /* Delay between EEPROM clock transitions.
1130 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1131 */
1132
1133 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1134
1135 /* The EEPROM commands include the alway-set leading bit. */
1136 #define EE_WRITE_CMD (5)
1137 #define EE_READ_CMD (6)
1138 #define EE_ERASE_CMD (7)
1139
1140 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1141 {
1142 int i;
1143 unsigned retval = 0;
1144 int read_cmd = location | (EE_READ_CMD << addr_len);
1145
1146 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1147 RTL_W8 (Cfg9346, EE_ENB);
1148 eeprom_delay ();
1149
1150 /* Shift the read command bits out. */
1151 for (i = 4 + addr_len; i >= 0; i--) {
1152 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1153 RTL_W8 (Cfg9346, EE_ENB | dataval);
1154 eeprom_delay ();
1155 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1156 eeprom_delay ();
1157 }
1158 RTL_W8 (Cfg9346, EE_ENB);
1159 eeprom_delay ();
1160
1161 for (i = 16; i > 0; i--) {
1162 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1163 eeprom_delay ();
1164 retval =
1165 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1166 0);
1167 RTL_W8 (Cfg9346, EE_ENB);
1168 eeprom_delay ();
1169 }
1170
1171 /* Terminate the EEPROM access. */
1172 RTL_W8 (Cfg9346, ~EE_CS);
1173 eeprom_delay ();
1174
1175 return retval;
1176 }
1177
1178 /* MII serial management: mostly bogus for now. */
1179 /* Read and write the MII management registers using software-generated
1180 serial MDIO protocol.
1181 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1182 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1183 "overclocking" issues. */
1184 #define MDIO_DIR 0x80
1185 #define MDIO_DATA_OUT 0x04
1186 #define MDIO_DATA_IN 0x02
1187 #define MDIO_CLK 0x01
1188 #define MDIO_WRITE0 (MDIO_DIR)
1189 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1190
1191 #define mdio_delay() RTL_R8(Config4)
1192
1193
1194 static const char mii_2_8139_map[8] = {
1195 BasicModeCtrl,
1196 BasicModeStatus,
1197 0,
1198 0,
1199 NWayAdvert,
1200 NWayLPAR,
1201 NWayExpansion,
1202 0
1203 };
1204
1205
1206 #ifdef CONFIG_8139TOO_8129
1207 /* Syncronize the MII management interface by shifting 32 one bits out. */
1208 static void mdio_sync (void __iomem *ioaddr)
1209 {
1210 int i;
1211
1212 for (i = 32; i >= 0; i--) {
1213 RTL_W8 (Config4, MDIO_WRITE1);
1214 mdio_delay ();
1215 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1216 mdio_delay ();
1217 }
1218 }
1219 #endif
1220
1221 static int mdio_read (struct net_device *dev, int phy_id, int location)
1222 {
1223 struct rtl8139_private *tp = netdev_priv(dev);
1224 int retval = 0;
1225 #ifdef CONFIG_8139TOO_8129
1226 void __iomem *ioaddr = tp->mmio_addr;
1227 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1228 int i;
1229 #endif
1230
1231 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1232 void __iomem *ioaddr = tp->mmio_addr;
1233 return location < 8 && mii_2_8139_map[location] ?
1234 RTL_R16 (mii_2_8139_map[location]) : 0;
1235 }
1236
1237 #ifdef CONFIG_8139TOO_8129
1238 mdio_sync (ioaddr);
1239 /* Shift the read command bits out. */
1240 for (i = 15; i >= 0; i--) {
1241 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1242
1243 RTL_W8 (Config4, MDIO_DIR | dataval);
1244 mdio_delay ();
1245 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1246 mdio_delay ();
1247 }
1248
1249 /* Read the two transition, 16 data, and wire-idle bits. */
1250 for (i = 19; i > 0; i--) {
1251 RTL_W8 (Config4, 0);
1252 mdio_delay ();
1253 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1254 RTL_W8 (Config4, MDIO_CLK);
1255 mdio_delay ();
1256 }
1257 #endif
1258
1259 return (retval >> 1) & 0xffff;
1260 }
1261
1262
1263 static void mdio_write (struct net_device *dev, int phy_id, int location,
1264 int value)
1265 {
1266 struct rtl8139_private *tp = netdev_priv(dev);
1267 #ifdef CONFIG_8139TOO_8129
1268 void __iomem *ioaddr = tp->mmio_addr;
1269 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1270 int i;
1271 #endif
1272
1273 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1274 void __iomem *ioaddr = tp->mmio_addr;
1275 if (location == 0) {
1276 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1277 RTL_W16 (BasicModeCtrl, value);
1278 RTL_W8 (Cfg9346, Cfg9346_Lock);
1279 } else if (location < 8 && mii_2_8139_map[location])
1280 RTL_W16 (mii_2_8139_map[location], value);
1281 return;
1282 }
1283
1284 #ifdef CONFIG_8139TOO_8129
1285 mdio_sync (ioaddr);
1286
1287 /* Shift the command bits out. */
1288 for (i = 31; i >= 0; i--) {
1289 int dataval =
1290 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1291 RTL_W8 (Config4, dataval);
1292 mdio_delay ();
1293 RTL_W8 (Config4, dataval | MDIO_CLK);
1294 mdio_delay ();
1295 }
1296 /* Clear out extra bits. */
1297 for (i = 2; i > 0; i--) {
1298 RTL_W8 (Config4, 0);
1299 mdio_delay ();
1300 RTL_W8 (Config4, MDIO_CLK);
1301 mdio_delay ();
1302 }
1303 #endif
1304 }
1305
1306
1307 static int rtl8139_open (struct net_device *dev)
1308 {
1309 struct rtl8139_private *tp = netdev_priv(dev);
1310 int retval;
1311 void __iomem *ioaddr = tp->mmio_addr;
1312
1313 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1314 if (retval)
1315 return retval;
1316
1317 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1318 &tp->tx_bufs_dma, GFP_KERNEL);
1319 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1320 &tp->rx_ring_dma, GFP_KERNEL);
1321 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1322 free_irq(dev->irq, dev);
1323
1324 if (tp->tx_bufs)
1325 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1326 tp->tx_bufs, tp->tx_bufs_dma);
1327 if (tp->rx_ring)
1328 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1329 tp->rx_ring, tp->rx_ring_dma);
1330
1331 return -ENOMEM;
1332
1333 }
1334
1335 napi_enable(&tp->napi);
1336
1337 tp->mii.full_duplex = tp->mii.force_media;
1338 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1339
1340 rtl8139_init_ring (dev);
1341 rtl8139_hw_start (dev);
1342 netif_start_queue (dev);
1343
1344 if (netif_msg_ifup(tp))
1345 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1346 " GP Pins %2.2x %s-duplex.\n", dev->name,
1347 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1348 dev->irq, RTL_R8 (MediaStatus),
1349 tp->mii.full_duplex ? "full" : "half");
1350
1351 rtl8139_start_thread(tp);
1352
1353 return 0;
1354 }
1355
1356
1357 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1358 {
1359 struct rtl8139_private *tp = netdev_priv(dev);
1360
1361 if (tp->phys[0] >= 0) {
1362 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1363 }
1364 }
1365
1366 /* Start the hardware at open or resume. */
1367 static void rtl8139_hw_start (struct net_device *dev)
1368 {
1369 struct rtl8139_private *tp = netdev_priv(dev);
1370 void __iomem *ioaddr = tp->mmio_addr;
1371 u32 i;
1372 u8 tmp;
1373
1374 /* Bring old chips out of low-power mode. */
1375 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1376 RTL_W8 (HltClk, 'R');
1377
1378 rtl8139_chip_reset (ioaddr);
1379
1380 /* unlock Config[01234] and BMCR register writes */
1381 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1382 /* Restore our idea of the MAC address. */
1383 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1384 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1385
1386 tp->cur_rx = 0;
1387
1388 /* init Rx ring buffer DMA address */
1389 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1390
1391 /* Must enable Tx/Rx before setting transfer thresholds! */
1392 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1393
1394 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1395 RTL_W32 (RxConfig, tp->rx_config);
1396 RTL_W32 (TxConfig, rtl8139_tx_config);
1397
1398 rtl_check_media (dev, 1);
1399
1400 if (tp->chipset >= CH_8139B) {
1401 /* Disable magic packet scanning, which is enabled
1402 * when PM is enabled in Config1. It can be reenabled
1403 * via ETHTOOL_SWOL if desired. */
1404 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1405 }
1406
1407 DPRINTK("init buffer addresses\n");
1408
1409 /* Lock Config[01234] and BMCR register writes */
1410 RTL_W8 (Cfg9346, Cfg9346_Lock);
1411
1412 /* init Tx buffer DMA addresses */
1413 for (i = 0; i < NUM_TX_DESC; i++)
1414 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1415
1416 RTL_W32 (RxMissed, 0);
1417
1418 rtl8139_set_rx_mode (dev);
1419
1420 /* no early-rx interrupts */
1421 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1422
1423 /* make sure RxTx has started */
1424 tmp = RTL_R8 (ChipCmd);
1425 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1426 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1427
1428 /* Enable all known interrupts by setting the interrupt mask. */
1429 RTL_W16 (IntrMask, rtl8139_intr_mask);
1430 }
1431
1432
1433 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1434 static void rtl8139_init_ring (struct net_device *dev)
1435 {
1436 struct rtl8139_private *tp = netdev_priv(dev);
1437 int i;
1438
1439 tp->cur_rx = 0;
1440 tp->cur_tx = 0;
1441 tp->dirty_tx = 0;
1442
1443 for (i = 0; i < NUM_TX_DESC; i++)
1444 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1445 }
1446
1447
1448 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1449 static int next_tick = 3 * HZ;
1450
1451 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1452 static inline void rtl8139_tune_twister (struct net_device *dev,
1453 struct rtl8139_private *tp) {}
1454 #else
1455 enum TwisterParamVals {
1456 PARA78_default = 0x78fa8388,
1457 PARA7c_default = 0xcb38de43, /* param[0][3] */
1458 PARA7c_xxx = 0xcb38de43,
1459 };
1460
1461 static const unsigned long param[4][4] = {
1462 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1463 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1464 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1465 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1466 };
1467
1468 static void rtl8139_tune_twister (struct net_device *dev,
1469 struct rtl8139_private *tp)
1470 {
1471 int linkcase;
1472 void __iomem *ioaddr = tp->mmio_addr;
1473
1474 /* This is a complicated state machine to configure the "twister" for
1475 impedance/echos based on the cable length.
1476 All of this is magic and undocumented.
1477 */
1478 switch (tp->twistie) {
1479 case 1:
1480 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1481 /* We have link beat, let us tune the twister. */
1482 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1483 tp->twistie = 2; /* Change to state 2. */
1484 next_tick = HZ / 10;
1485 } else {
1486 /* Just put in some reasonable defaults for when beat returns. */
1487 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1488 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1489 RTL_W32 (PARA78, PARA78_default);
1490 RTL_W32 (PARA7c, PARA7c_default);
1491 tp->twistie = 0; /* Bail from future actions. */
1492 }
1493 break;
1494 case 2:
1495 /* Read how long it took to hear the echo. */
1496 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1497 if (linkcase == 0x7000)
1498 tp->twist_row = 3;
1499 else if (linkcase == 0x3000)
1500 tp->twist_row = 2;
1501 else if (linkcase == 0x1000)
1502 tp->twist_row = 1;
1503 else
1504 tp->twist_row = 0;
1505 tp->twist_col = 0;
1506 tp->twistie = 3; /* Change to state 2. */
1507 next_tick = HZ / 10;
1508 break;
1509 case 3:
1510 /* Put out four tuning parameters, one per 100msec. */
1511 if (tp->twist_col == 0)
1512 RTL_W16 (FIFOTMS, 0);
1513 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1514 [(int) tp->twist_col]);
1515 next_tick = HZ / 10;
1516 if (++tp->twist_col >= 4) {
1517 /* For short cables we are done.
1518 For long cables (row == 3) check for mistune. */
1519 tp->twistie =
1520 (tp->twist_row == 3) ? 4 : 0;
1521 }
1522 break;
1523 case 4:
1524 /* Special case for long cables: check for mistune. */
1525 if ((RTL_R16 (CSCR) &
1526 CSCR_LinkStatusBits) == 0x7000) {
1527 tp->twistie = 0;
1528 break;
1529 } else {
1530 RTL_W32 (PARA7c, 0xfb38de03);
1531 tp->twistie = 5;
1532 next_tick = HZ / 10;
1533 }
1534 break;
1535 case 5:
1536 /* Retune for shorter cable (column 2). */
1537 RTL_W32 (FIFOTMS, 0x20);
1538 RTL_W32 (PARA78, PARA78_default);
1539 RTL_W32 (PARA7c, PARA7c_default);
1540 RTL_W32 (FIFOTMS, 0x00);
1541 tp->twist_row = 2;
1542 tp->twist_col = 0;
1543 tp->twistie = 3;
1544 next_tick = HZ / 10;
1545 break;
1546
1547 default:
1548 /* do nothing */
1549 break;
1550 }
1551 }
1552 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1553
1554 static inline void rtl8139_thread_iter (struct net_device *dev,
1555 struct rtl8139_private *tp,
1556 void __iomem *ioaddr)
1557 {
1558 int mii_lpa;
1559
1560 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1561
1562 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1563 int duplex = (mii_lpa & LPA_100FULL)
1564 || (mii_lpa & 0x01C0) == 0x0040;
1565 if (tp->mii.full_duplex != duplex) {
1566 tp->mii.full_duplex = duplex;
1567
1568 if (mii_lpa) {
1569 printk (KERN_INFO
1570 "%s: Setting %s-duplex based on MII #%d link"
1571 " partner ability of %4.4x.\n",
1572 dev->name,
1573 tp->mii.full_duplex ? "full" : "half",
1574 tp->phys[0], mii_lpa);
1575 } else {
1576 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1577 dev->name);
1578 }
1579 #if 0
1580 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1581 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1582 RTL_W8 (Cfg9346, Cfg9346_Lock);
1583 #endif
1584 }
1585 }
1586
1587 next_tick = HZ * 60;
1588
1589 rtl8139_tune_twister (dev, tp);
1590
1591 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1592 dev->name, RTL_R16 (NWayLPAR));
1593 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1594 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1595 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1596 dev->name, RTL_R8 (Config0),
1597 RTL_R8 (Config1));
1598 }
1599
1600 static void rtl8139_thread (struct work_struct *work)
1601 {
1602 struct rtl8139_private *tp =
1603 container_of(work, struct rtl8139_private, thread.work);
1604 struct net_device *dev = tp->mii.dev;
1605 unsigned long thr_delay = next_tick;
1606
1607 rtnl_lock();
1608
1609 if (!netif_running(dev))
1610 goto out_unlock;
1611
1612 if (tp->watchdog_fired) {
1613 tp->watchdog_fired = 0;
1614 rtl8139_tx_timeout_task(work);
1615 } else
1616 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1617
1618 if (tp->have_thread)
1619 schedule_delayed_work(&tp->thread, thr_delay);
1620 out_unlock:
1621 rtnl_unlock ();
1622 }
1623
1624 static void rtl8139_start_thread(struct rtl8139_private *tp)
1625 {
1626 tp->twistie = 0;
1627 if (tp->chipset == CH_8139_K)
1628 tp->twistie = 1;
1629 else if (tp->drv_flags & HAS_LNK_CHNG)
1630 return;
1631
1632 tp->have_thread = 1;
1633 tp->watchdog_fired = 0;
1634
1635 schedule_delayed_work(&tp->thread, next_tick);
1636 }
1637
1638 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1639 {
1640 tp->cur_tx = 0;
1641 tp->dirty_tx = 0;
1642
1643 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1644 }
1645
1646 static void rtl8139_tx_timeout_task (struct work_struct *work)
1647 {
1648 struct rtl8139_private *tp =
1649 container_of(work, struct rtl8139_private, thread.work);
1650 struct net_device *dev = tp->mii.dev;
1651 void __iomem *ioaddr = tp->mmio_addr;
1652 int i;
1653 u8 tmp8;
1654
1655 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1656 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1657 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1658 /* Emit info to figure out what went wrong. */
1659 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1660 dev->name, tp->cur_tx, tp->dirty_tx);
1661 for (i = 0; i < NUM_TX_DESC; i++)
1662 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1663 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1664 i == tp->dirty_tx % NUM_TX_DESC ?
1665 " (queue head)" : "");
1666
1667 tp->xstats.tx_timeouts++;
1668
1669 /* disable Tx ASAP, if not already */
1670 tmp8 = RTL_R8 (ChipCmd);
1671 if (tmp8 & CmdTxEnb)
1672 RTL_W8 (ChipCmd, CmdRxEnb);
1673
1674 spin_lock_bh(&tp->rx_lock);
1675 /* Disable interrupts by clearing the interrupt mask. */
1676 RTL_W16 (IntrMask, 0x0000);
1677
1678 /* Stop a shared interrupt from scavenging while we are. */
1679 spin_lock_irq(&tp->lock);
1680 rtl8139_tx_clear (tp);
1681 spin_unlock_irq(&tp->lock);
1682
1683 /* ...and finally, reset everything */
1684 if (netif_running(dev)) {
1685 rtl8139_hw_start (dev);
1686 netif_wake_queue (dev);
1687 }
1688 spin_unlock_bh(&tp->rx_lock);
1689 }
1690
1691 static void rtl8139_tx_timeout (struct net_device *dev)
1692 {
1693 struct rtl8139_private *tp = netdev_priv(dev);
1694
1695 tp->watchdog_fired = 1;
1696 if (!tp->have_thread) {
1697 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1698 schedule_delayed_work(&tp->thread, next_tick);
1699 }
1700 }
1701
1702 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1703 {
1704 struct rtl8139_private *tp = netdev_priv(dev);
1705 void __iomem *ioaddr = tp->mmio_addr;
1706 unsigned int entry;
1707 unsigned int len = skb->len;
1708 unsigned long flags;
1709
1710 /* Calculate the next Tx descriptor entry. */
1711 entry = tp->cur_tx % NUM_TX_DESC;
1712
1713 /* Note: the chip doesn't have auto-pad! */
1714 if (likely(len < TX_BUF_SIZE)) {
1715 if (len < ETH_ZLEN)
1716 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1717 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1718 dev_kfree_skb(skb);
1719 } else {
1720 dev_kfree_skb(skb);
1721 dev->stats.tx_dropped++;
1722 return 0;
1723 }
1724
1725 spin_lock_irqsave(&tp->lock, flags);
1726 /*
1727 * Writing to TxStatus triggers a DMA transfer of the data
1728 * copied to tp->tx_buf[entry] above. Use a memory barrier
1729 * to make sure that the device sees the updated data.
1730 */
1731 wmb();
1732 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1733 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1734
1735 dev->trans_start = jiffies;
1736
1737 tp->cur_tx++;
1738
1739 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1740 netif_stop_queue (dev);
1741 spin_unlock_irqrestore(&tp->lock, flags);
1742
1743 if (netif_msg_tx_queued(tp))
1744 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1745 dev->name, len, entry);
1746
1747 return 0;
1748 }
1749
1750
1751 static void rtl8139_tx_interrupt (struct net_device *dev,
1752 struct rtl8139_private *tp,
1753 void __iomem *ioaddr)
1754 {
1755 unsigned long dirty_tx, tx_left;
1756
1757 assert (dev != NULL);
1758 assert (ioaddr != NULL);
1759
1760 dirty_tx = tp->dirty_tx;
1761 tx_left = tp->cur_tx - dirty_tx;
1762 while (tx_left > 0) {
1763 int entry = dirty_tx % NUM_TX_DESC;
1764 int txstatus;
1765
1766 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1767
1768 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1769 break; /* It still hasn't been Txed */
1770
1771 /* Note: TxCarrierLost is always asserted at 100mbps. */
1772 if (txstatus & (TxOutOfWindow | TxAborted)) {
1773 /* There was an major error, log it. */
1774 if (netif_msg_tx_err(tp))
1775 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1776 dev->name, txstatus);
1777 dev->stats.tx_errors++;
1778 if (txstatus & TxAborted) {
1779 dev->stats.tx_aborted_errors++;
1780 RTL_W32 (TxConfig, TxClearAbt);
1781 RTL_W16 (IntrStatus, TxErr);
1782 wmb();
1783 }
1784 if (txstatus & TxCarrierLost)
1785 dev->stats.tx_carrier_errors++;
1786 if (txstatus & TxOutOfWindow)
1787 dev->stats.tx_window_errors++;
1788 } else {
1789 if (txstatus & TxUnderrun) {
1790 /* Add 64 to the Tx FIFO threshold. */
1791 if (tp->tx_flag < 0x00300000)
1792 tp->tx_flag += 0x00020000;
1793 dev->stats.tx_fifo_errors++;
1794 }
1795 dev->stats.collisions += (txstatus >> 24) & 15;
1796 dev->stats.tx_bytes += txstatus & 0x7ff;
1797 dev->stats.tx_packets++;
1798 }
1799
1800 dirty_tx++;
1801 tx_left--;
1802 }
1803
1804 #ifndef RTL8139_NDEBUG
1805 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1806 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1807 dev->name, dirty_tx, tp->cur_tx);
1808 dirty_tx += NUM_TX_DESC;
1809 }
1810 #endif /* RTL8139_NDEBUG */
1811
1812 /* only wake the queue if we did work, and the queue is stopped */
1813 if (tp->dirty_tx != dirty_tx) {
1814 tp->dirty_tx = dirty_tx;
1815 mb();
1816 netif_wake_queue (dev);
1817 }
1818 }
1819
1820
1821 /* TODO: clean this up! Rx reset need not be this intensive */
1822 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1823 struct rtl8139_private *tp, void __iomem *ioaddr)
1824 {
1825 u8 tmp8;
1826 #ifdef CONFIG_8139_OLD_RX_RESET
1827 int tmp_work;
1828 #endif
1829
1830 if (netif_msg_rx_err (tp))
1831 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1832 dev->name, rx_status);
1833 dev->stats.rx_errors++;
1834 if (!(rx_status & RxStatusOK)) {
1835 if (rx_status & RxTooLong) {
1836 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1837 dev->name, rx_status);
1838 /* A.C.: The chip hangs here. */
1839 }
1840 if (rx_status & (RxBadSymbol | RxBadAlign))
1841 dev->stats.rx_frame_errors++;
1842 if (rx_status & (RxRunt | RxTooLong))
1843 dev->stats.rx_length_errors++;
1844 if (rx_status & RxCRCErr)
1845 dev->stats.rx_crc_errors++;
1846 } else {
1847 tp->xstats.rx_lost_in_ring++;
1848 }
1849
1850 #ifndef CONFIG_8139_OLD_RX_RESET
1851 tmp8 = RTL_R8 (ChipCmd);
1852 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1853 RTL_W8 (ChipCmd, tmp8);
1854 RTL_W32 (RxConfig, tp->rx_config);
1855 tp->cur_rx = 0;
1856 #else
1857 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1858
1859 /* disable receive */
1860 RTL_W8_F (ChipCmd, CmdTxEnb);
1861 tmp_work = 200;
1862 while (--tmp_work > 0) {
1863 udelay(1);
1864 tmp8 = RTL_R8 (ChipCmd);
1865 if (!(tmp8 & CmdRxEnb))
1866 break;
1867 }
1868 if (tmp_work <= 0)
1869 printk (KERN_WARNING PFX "rx stop wait too long\n");
1870 /* restart receive */
1871 tmp_work = 200;
1872 while (--tmp_work > 0) {
1873 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1874 udelay(1);
1875 tmp8 = RTL_R8 (ChipCmd);
1876 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1877 break;
1878 }
1879 if (tmp_work <= 0)
1880 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1881
1882 /* and reinitialize all rx related registers */
1883 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1884 /* Must enable Tx/Rx before setting transfer thresholds! */
1885 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1886
1887 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1888 RTL_W32 (RxConfig, tp->rx_config);
1889 tp->cur_rx = 0;
1890
1891 DPRINTK("init buffer addresses\n");
1892
1893 /* Lock Config[01234] and BMCR register writes */
1894 RTL_W8 (Cfg9346, Cfg9346_Lock);
1895
1896 /* init Rx ring buffer DMA address */
1897 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1898
1899 /* A.C.: Reset the multicast list. */
1900 __set_rx_mode (dev);
1901 #endif
1902 }
1903
1904 #if RX_BUF_IDX == 3
1905 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1906 u32 offset, unsigned int size)
1907 {
1908 u32 left = RX_BUF_LEN - offset;
1909
1910 if (size > left) {
1911 skb_copy_to_linear_data(skb, ring + offset, left);
1912 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1913 } else
1914 skb_copy_to_linear_data(skb, ring + offset, size);
1915 }
1916 #endif
1917
1918 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1919 {
1920 void __iomem *ioaddr = tp->mmio_addr;
1921 u16 status;
1922
1923 status = RTL_R16 (IntrStatus) & RxAckBits;
1924
1925 /* Clear out errors and receive interrupts */
1926 if (likely(status != 0)) {
1927 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1928 tp->dev->stats.rx_errors++;
1929 if (status & RxFIFOOver)
1930 tp->dev->stats.rx_fifo_errors++;
1931 }
1932 RTL_W16_F (IntrStatus, RxAckBits);
1933 }
1934 }
1935
1936 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1937 int budget)
1938 {
1939 void __iomem *ioaddr = tp->mmio_addr;
1940 int received = 0;
1941 unsigned char *rx_ring = tp->rx_ring;
1942 unsigned int cur_rx = tp->cur_rx;
1943 unsigned int rx_size = 0;
1944
1945 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1946 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1947 RTL_R16 (RxBufAddr),
1948 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1949
1950 while (netif_running(dev) && received < budget
1951 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1952 u32 ring_offset = cur_rx % RX_BUF_LEN;
1953 u32 rx_status;
1954 unsigned int pkt_size;
1955 struct sk_buff *skb;
1956
1957 rmb();
1958
1959 /* read size+status of next frame from DMA ring buffer */
1960 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1961 rx_size = rx_status >> 16;
1962 pkt_size = rx_size - 4;
1963
1964 if (netif_msg_rx_status(tp))
1965 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1966 " cur %4.4x.\n", dev->name, rx_status,
1967 rx_size, cur_rx);
1968 #if RTL8139_DEBUG > 2
1969 {
1970 int i;
1971 DPRINTK ("%s: Frame contents ", dev->name);
1972 for (i = 0; i < 70; i++)
1973 printk (" %2.2x",
1974 rx_ring[ring_offset + i]);
1975 printk (".\n");
1976 }
1977 #endif
1978
1979 /* Packet copy from FIFO still in progress.
1980 * Theoretically, this should never happen
1981 * since EarlyRx is disabled.
1982 */
1983 if (unlikely(rx_size == 0xfff0)) {
1984 if (!tp->fifo_copy_timeout)
1985 tp->fifo_copy_timeout = jiffies + 2;
1986 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1987 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1988 rx_size = 0;
1989 goto no_early_rx;
1990 }
1991 if (netif_msg_intr(tp)) {
1992 printk(KERN_DEBUG "%s: fifo copy in progress.",
1993 dev->name);
1994 }
1995 tp->xstats.early_rx++;
1996 break;
1997 }
1998
1999 no_early_rx:
2000 tp->fifo_copy_timeout = 0;
2001
2002 /* If Rx err or invalid rx_size/rx_status received
2003 * (which happens if we get lost in the ring),
2004 * Rx process gets reset, so we abort any further
2005 * Rx processing.
2006 */
2007 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2008 (rx_size < 8) ||
2009 (!(rx_status & RxStatusOK)))) {
2010 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2011 received = -1;
2012 goto out;
2013 }
2014
2015 /* Malloc up new buffer, compatible with net-2e. */
2016 /* Omit the four octet CRC from the length. */
2017
2018 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
2019 if (likely(skb)) {
2020 skb_reserve (skb, NET_IP_ALIGN); /* 16 byte align the IP fields. */
2021 #if RX_BUF_IDX == 3
2022 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2023 #else
2024 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2025 #endif
2026 skb_put (skb, pkt_size);
2027
2028 skb->protocol = eth_type_trans (skb, dev);
2029
2030 dev->stats.rx_bytes += pkt_size;
2031 dev->stats.rx_packets++;
2032
2033 netif_receive_skb (skb);
2034 } else {
2035 if (net_ratelimit())
2036 printk (KERN_WARNING
2037 "%s: Memory squeeze, dropping packet.\n",
2038 dev->name);
2039 dev->stats.rx_dropped++;
2040 }
2041 received++;
2042
2043 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2044 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2045
2046 rtl8139_isr_ack(tp);
2047 }
2048
2049 if (unlikely(!received || rx_size == 0xfff0))
2050 rtl8139_isr_ack(tp);
2051
2052 #if RTL8139_DEBUG > 1
2053 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2054 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2055 RTL_R16 (RxBufAddr),
2056 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2057 #endif
2058
2059 tp->cur_rx = cur_rx;
2060
2061 /*
2062 * The receive buffer should be mostly empty.
2063 * Tell NAPI to reenable the Rx irq.
2064 */
2065 if (tp->fifo_copy_timeout)
2066 received = budget;
2067
2068 out:
2069 return received;
2070 }
2071
2072
2073 static void rtl8139_weird_interrupt (struct net_device *dev,
2074 struct rtl8139_private *tp,
2075 void __iomem *ioaddr,
2076 int status, int link_changed)
2077 {
2078 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2079 dev->name, status);
2080
2081 assert (dev != NULL);
2082 assert (tp != NULL);
2083 assert (ioaddr != NULL);
2084
2085 /* Update the error count. */
2086 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2087 RTL_W32 (RxMissed, 0);
2088
2089 if ((status & RxUnderrun) && link_changed &&
2090 (tp->drv_flags & HAS_LNK_CHNG)) {
2091 rtl_check_media(dev, 0);
2092 status &= ~RxUnderrun;
2093 }
2094
2095 if (status & (RxUnderrun | RxErr))
2096 dev->stats.rx_errors++;
2097
2098 if (status & PCSTimeout)
2099 dev->stats.rx_length_errors++;
2100 if (status & RxUnderrun)
2101 dev->stats.rx_fifo_errors++;
2102 if (status & PCIErr) {
2103 u16 pci_cmd_status;
2104 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2105 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2106
2107 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2108 dev->name, pci_cmd_status);
2109 }
2110 }
2111
2112 static int rtl8139_poll(struct napi_struct *napi, int budget)
2113 {
2114 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2115 struct net_device *dev = tp->dev;
2116 void __iomem *ioaddr = tp->mmio_addr;
2117 int work_done;
2118
2119 spin_lock(&tp->rx_lock);
2120 work_done = 0;
2121 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2122 work_done += rtl8139_rx(dev, tp, budget);
2123
2124 if (work_done < budget) {
2125 unsigned long flags;
2126 /*
2127 * Order is important since data can get interrupted
2128 * again when we think we are done.
2129 */
2130 spin_lock_irqsave(&tp->lock, flags);
2131 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2132 __napi_complete(napi);
2133 spin_unlock_irqrestore(&tp->lock, flags);
2134 }
2135 spin_unlock(&tp->rx_lock);
2136
2137 return work_done;
2138 }
2139
2140 /* The interrupt handler does all of the Rx thread work and cleans up
2141 after the Tx thread. */
2142 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2143 {
2144 struct net_device *dev = (struct net_device *) dev_instance;
2145 struct rtl8139_private *tp = netdev_priv(dev);
2146 void __iomem *ioaddr = tp->mmio_addr;
2147 u16 status, ackstat;
2148 int link_changed = 0; /* avoid bogus "uninit" warning */
2149 int handled = 0;
2150
2151 spin_lock (&tp->lock);
2152 status = RTL_R16 (IntrStatus);
2153
2154 /* shared irq? */
2155 if (unlikely((status & rtl8139_intr_mask) == 0))
2156 goto out;
2157
2158 handled = 1;
2159
2160 /* h/w no longer present (hotplug?) or major error, bail */
2161 if (unlikely(status == 0xFFFF))
2162 goto out;
2163
2164 /* close possible race's with dev_close */
2165 if (unlikely(!netif_running(dev))) {
2166 RTL_W16 (IntrMask, 0);
2167 goto out;
2168 }
2169
2170 /* Acknowledge all of the current interrupt sources ASAP, but
2171 an first get an additional status bit from CSCR. */
2172 if (unlikely(status & RxUnderrun))
2173 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2174
2175 ackstat = status & ~(RxAckBits | TxErr);
2176 if (ackstat)
2177 RTL_W16 (IntrStatus, ackstat);
2178
2179 /* Receive packets are processed by poll routine.
2180 If not running start it now. */
2181 if (status & RxAckBits){
2182 if (napi_schedule_prep(&tp->napi)) {
2183 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2184 __napi_schedule(&tp->napi);
2185 }
2186 }
2187
2188 /* Check uncommon events with one test. */
2189 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2190 rtl8139_weird_interrupt (dev, tp, ioaddr,
2191 status, link_changed);
2192
2193 if (status & (TxOK | TxErr)) {
2194 rtl8139_tx_interrupt (dev, tp, ioaddr);
2195 if (status & TxErr)
2196 RTL_W16 (IntrStatus, TxErr);
2197 }
2198 out:
2199 spin_unlock (&tp->lock);
2200
2201 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2202 dev->name, RTL_R16 (IntrStatus));
2203 return IRQ_RETVAL(handled);
2204 }
2205
2206 #ifdef CONFIG_NET_POLL_CONTROLLER
2207 /*
2208 * Polling receive - used by netconsole and other diagnostic tools
2209 * to allow network i/o with interrupts disabled.
2210 */
2211 static void rtl8139_poll_controller(struct net_device *dev)
2212 {
2213 disable_irq(dev->irq);
2214 rtl8139_interrupt(dev->irq, dev);
2215 enable_irq(dev->irq);
2216 }
2217 #endif
2218
2219 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2220 {
2221 struct rtl8139_private *tp = netdev_priv(dev);
2222 void __iomem *ioaddr = tp->mmio_addr;
2223 struct sockaddr *addr = p;
2224
2225 if (!is_valid_ether_addr(addr->sa_data))
2226 return -EADDRNOTAVAIL;
2227
2228 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2229
2230 spin_lock_irq(&tp->lock);
2231
2232 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2233 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2234 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2235 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2236
2237 spin_unlock_irq(&tp->lock);
2238
2239 return 0;
2240 }
2241
2242 static int rtl8139_close (struct net_device *dev)
2243 {
2244 struct rtl8139_private *tp = netdev_priv(dev);
2245 void __iomem *ioaddr = tp->mmio_addr;
2246 unsigned long flags;
2247
2248 netif_stop_queue(dev);
2249 napi_disable(&tp->napi);
2250
2251 if (netif_msg_ifdown(tp))
2252 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2253 dev->name, RTL_R16 (IntrStatus));
2254
2255 spin_lock_irqsave (&tp->lock, flags);
2256
2257 /* Stop the chip's Tx and Rx DMA processes. */
2258 RTL_W8 (ChipCmd, 0);
2259
2260 /* Disable interrupts by clearing the interrupt mask. */
2261 RTL_W16 (IntrMask, 0);
2262
2263 /* Update the error counts. */
2264 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2265 RTL_W32 (RxMissed, 0);
2266
2267 spin_unlock_irqrestore (&tp->lock, flags);
2268
2269 free_irq (dev->irq, dev);
2270
2271 rtl8139_tx_clear (tp);
2272
2273 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2274 tp->rx_ring, tp->rx_ring_dma);
2275 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2276 tp->tx_bufs, tp->tx_bufs_dma);
2277 tp->rx_ring = NULL;
2278 tp->tx_bufs = NULL;
2279
2280 /* Green! Put the chip in low-power mode. */
2281 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2282
2283 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2284 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2285
2286 return 0;
2287 }
2288
2289
2290 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2291 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2292 other threads or interrupts aren't messing with the 8139. */
2293 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2294 {
2295 struct rtl8139_private *np = netdev_priv(dev);
2296 void __iomem *ioaddr = np->mmio_addr;
2297
2298 spin_lock_irq(&np->lock);
2299 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2300 u8 cfg3 = RTL_R8 (Config3);
2301 u8 cfg5 = RTL_R8 (Config5);
2302
2303 wol->supported = WAKE_PHY | WAKE_MAGIC
2304 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2305
2306 wol->wolopts = 0;
2307 if (cfg3 & Cfg3_LinkUp)
2308 wol->wolopts |= WAKE_PHY;
2309 if (cfg3 & Cfg3_Magic)
2310 wol->wolopts |= WAKE_MAGIC;
2311 /* (KON)FIXME: See how netdev_set_wol() handles the
2312 following constants. */
2313 if (cfg5 & Cfg5_UWF)
2314 wol->wolopts |= WAKE_UCAST;
2315 if (cfg5 & Cfg5_MWF)
2316 wol->wolopts |= WAKE_MCAST;
2317 if (cfg5 & Cfg5_BWF)
2318 wol->wolopts |= WAKE_BCAST;
2319 }
2320 spin_unlock_irq(&np->lock);
2321 }
2322
2323
2324 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2325 that wol points to kernel memory and other threads or interrupts
2326 aren't messing with the 8139. */
2327 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2328 {
2329 struct rtl8139_private *np = netdev_priv(dev);
2330 void __iomem *ioaddr = np->mmio_addr;
2331 u32 support;
2332 u8 cfg3, cfg5;
2333
2334 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2335 ? (WAKE_PHY | WAKE_MAGIC
2336 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2337 : 0);
2338 if (wol->wolopts & ~support)
2339 return -EINVAL;
2340
2341 spin_lock_irq(&np->lock);
2342 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2343 if (wol->wolopts & WAKE_PHY)
2344 cfg3 |= Cfg3_LinkUp;
2345 if (wol->wolopts & WAKE_MAGIC)
2346 cfg3 |= Cfg3_Magic;
2347 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2348 RTL_W8 (Config3, cfg3);
2349 RTL_W8 (Cfg9346, Cfg9346_Lock);
2350
2351 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2352 /* (KON)FIXME: These are untested. We may have to set the
2353 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2354 documentation. */
2355 if (wol->wolopts & WAKE_UCAST)
2356 cfg5 |= Cfg5_UWF;
2357 if (wol->wolopts & WAKE_MCAST)
2358 cfg5 |= Cfg5_MWF;
2359 if (wol->wolopts & WAKE_BCAST)
2360 cfg5 |= Cfg5_BWF;
2361 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2362 spin_unlock_irq(&np->lock);
2363
2364 return 0;
2365 }
2366
2367 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2368 {
2369 struct rtl8139_private *np = netdev_priv(dev);
2370 strcpy(info->driver, DRV_NAME);
2371 strcpy(info->version, DRV_VERSION);
2372 strcpy(info->bus_info, pci_name(np->pci_dev));
2373 info->regdump_len = np->regs_len;
2374 }
2375
2376 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2377 {
2378 struct rtl8139_private *np = netdev_priv(dev);
2379 spin_lock_irq(&np->lock);
2380 mii_ethtool_gset(&np->mii, cmd);
2381 spin_unlock_irq(&np->lock);
2382 return 0;
2383 }
2384
2385 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2386 {
2387 struct rtl8139_private *np = netdev_priv(dev);
2388 int rc;
2389 spin_lock_irq(&np->lock);
2390 rc = mii_ethtool_sset(&np->mii, cmd);
2391 spin_unlock_irq(&np->lock);
2392 return rc;
2393 }
2394
2395 static int rtl8139_nway_reset(struct net_device *dev)
2396 {
2397 struct rtl8139_private *np = netdev_priv(dev);
2398 return mii_nway_restart(&np->mii);
2399 }
2400
2401 static u32 rtl8139_get_link(struct net_device *dev)
2402 {
2403 struct rtl8139_private *np = netdev_priv(dev);
2404 return mii_link_ok(&np->mii);
2405 }
2406
2407 static u32 rtl8139_get_msglevel(struct net_device *dev)
2408 {
2409 struct rtl8139_private *np = netdev_priv(dev);
2410 return np->msg_enable;
2411 }
2412
2413 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2414 {
2415 struct rtl8139_private *np = netdev_priv(dev);
2416 np->msg_enable = datum;
2417 }
2418
2419 static int rtl8139_get_regs_len(struct net_device *dev)
2420 {
2421 struct rtl8139_private *np;
2422 /* TODO: we are too slack to do reg dumping for pio, for now */
2423 if (use_io)
2424 return 0;
2425 np = netdev_priv(dev);
2426 return np->regs_len;
2427 }
2428
2429 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2430 {
2431 struct rtl8139_private *np;
2432
2433 /* TODO: we are too slack to do reg dumping for pio, for now */
2434 if (use_io)
2435 return;
2436 np = netdev_priv(dev);
2437
2438 regs->version = RTL_REGS_VER;
2439
2440 spin_lock_irq(&np->lock);
2441 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2442 spin_unlock_irq(&np->lock);
2443 }
2444
2445 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2446 {
2447 switch (sset) {
2448 case ETH_SS_STATS:
2449 return RTL_NUM_STATS;
2450 default:
2451 return -EOPNOTSUPP;
2452 }
2453 }
2454
2455 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2456 {
2457 struct rtl8139_private *np = netdev_priv(dev);
2458
2459 data[0] = np->xstats.early_rx;
2460 data[1] = np->xstats.tx_buf_mapped;
2461 data[2] = np->xstats.tx_timeouts;
2462 data[3] = np->xstats.rx_lost_in_ring;
2463 }
2464
2465 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2466 {
2467 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2468 }
2469
2470 static const struct ethtool_ops rtl8139_ethtool_ops = {
2471 .get_drvinfo = rtl8139_get_drvinfo,
2472 .get_settings = rtl8139_get_settings,
2473 .set_settings = rtl8139_set_settings,
2474 .get_regs_len = rtl8139_get_regs_len,
2475 .get_regs = rtl8139_get_regs,
2476 .nway_reset = rtl8139_nway_reset,
2477 .get_link = rtl8139_get_link,
2478 .get_msglevel = rtl8139_get_msglevel,
2479 .set_msglevel = rtl8139_set_msglevel,
2480 .get_wol = rtl8139_get_wol,
2481 .set_wol = rtl8139_set_wol,
2482 .get_strings = rtl8139_get_strings,
2483 .get_sset_count = rtl8139_get_sset_count,
2484 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2485 };
2486
2487 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2488 {
2489 struct rtl8139_private *np = netdev_priv(dev);
2490 int rc;
2491
2492 if (!netif_running(dev))
2493 return -EINVAL;
2494
2495 spin_lock_irq(&np->lock);
2496 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2497 spin_unlock_irq(&np->lock);
2498
2499 return rc;
2500 }
2501
2502
2503 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2504 {
2505 struct rtl8139_private *tp = netdev_priv(dev);
2506 void __iomem *ioaddr = tp->mmio_addr;
2507 unsigned long flags;
2508
2509 if (netif_running(dev)) {
2510 spin_lock_irqsave (&tp->lock, flags);
2511 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2512 RTL_W32 (RxMissed, 0);
2513 spin_unlock_irqrestore (&tp->lock, flags);
2514 }
2515
2516 return &dev->stats;
2517 }
2518
2519 /* Set or clear the multicast filter for this adaptor.
2520 This routine is not state sensitive and need not be SMP locked. */
2521
2522 static void __set_rx_mode (struct net_device *dev)
2523 {
2524 struct rtl8139_private *tp = netdev_priv(dev);
2525 void __iomem *ioaddr = tp->mmio_addr;
2526 u32 mc_filter[2]; /* Multicast hash filter */
2527 int i, rx_mode;
2528 u32 tmp;
2529
2530 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2531 dev->name, dev->flags, RTL_R32 (RxConfig));
2532
2533 /* Note: do not reorder, GCC is clever about common statements. */
2534 if (dev->flags & IFF_PROMISC) {
2535 rx_mode =
2536 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2537 AcceptAllPhys;
2538 mc_filter[1] = mc_filter[0] = 0xffffffff;
2539 } else if ((dev->mc_count > multicast_filter_limit)
2540 || (dev->flags & IFF_ALLMULTI)) {
2541 /* Too many to filter perfectly -- accept all multicasts. */
2542 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2543 mc_filter[1] = mc_filter[0] = 0xffffffff;
2544 } else {
2545 struct dev_mc_list *mclist;
2546 rx_mode = AcceptBroadcast | AcceptMyPhys;
2547 mc_filter[1] = mc_filter[0] = 0;
2548 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2549 i++, mclist = mclist->next) {
2550 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2551
2552 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2553 rx_mode |= AcceptMulticast;
2554 }
2555 }
2556
2557 /* We can safely update without stopping the chip. */
2558 tmp = rtl8139_rx_config | rx_mode;
2559 if (tp->rx_config != tmp) {
2560 RTL_W32_F (RxConfig, tmp);
2561 tp->rx_config = tmp;
2562 }
2563 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2564 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2565 }
2566
2567 static void rtl8139_set_rx_mode (struct net_device *dev)
2568 {
2569 unsigned long flags;
2570 struct rtl8139_private *tp = netdev_priv(dev);
2571
2572 spin_lock_irqsave (&tp->lock, flags);
2573 __set_rx_mode(dev);
2574 spin_unlock_irqrestore (&tp->lock, flags);
2575 }
2576
2577 #ifdef CONFIG_PM
2578
2579 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2580 {
2581 struct net_device *dev = pci_get_drvdata (pdev);
2582 struct rtl8139_private *tp = netdev_priv(dev);
2583 void __iomem *ioaddr = tp->mmio_addr;
2584 unsigned long flags;
2585
2586 pci_save_state (pdev);
2587
2588 if (!netif_running (dev))
2589 return 0;
2590
2591 netif_device_detach (dev);
2592
2593 spin_lock_irqsave (&tp->lock, flags);
2594
2595 /* Disable interrupts, stop Tx and Rx. */
2596 RTL_W16 (IntrMask, 0);
2597 RTL_W8 (ChipCmd, 0);
2598
2599 /* Update the error counts. */
2600 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2601 RTL_W32 (RxMissed, 0);
2602
2603 spin_unlock_irqrestore (&tp->lock, flags);
2604
2605 pci_set_power_state (pdev, PCI_D3hot);
2606
2607 return 0;
2608 }
2609
2610
2611 static int rtl8139_resume (struct pci_dev *pdev)
2612 {
2613 struct net_device *dev = pci_get_drvdata (pdev);
2614
2615 pci_restore_state (pdev);
2616 if (!netif_running (dev))
2617 return 0;
2618 pci_set_power_state (pdev, PCI_D0);
2619 rtl8139_init_ring (dev);
2620 rtl8139_hw_start (dev);
2621 netif_device_attach (dev);
2622 return 0;
2623 }
2624
2625 #endif /* CONFIG_PM */
2626
2627
2628 static struct pci_driver rtl8139_pci_driver = {
2629 .name = DRV_NAME,
2630 .id_table = rtl8139_pci_tbl,
2631 .probe = rtl8139_init_one,
2632 .remove = __devexit_p(rtl8139_remove_one),
2633 #ifdef CONFIG_PM
2634 .suspend = rtl8139_suspend,
2635 .resume = rtl8139_resume,
2636 #endif /* CONFIG_PM */
2637 };
2638
2639
2640 static int __init rtl8139_init_module (void)
2641 {
2642 /* when we're a module, we always print a version message,
2643 * even if no 8139 board is found.
2644 */
2645 #ifdef MODULE
2646 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2647 #endif
2648
2649 return pci_register_driver(&rtl8139_pci_driver);
2650 }
2651
2652
2653 static void __exit rtl8139_cleanup_module (void)
2654 {
2655 pci_unregister_driver (&rtl8139_pci_driver);
2656 }
2657
2658
2659 module_init(rtl8139_init_module);
2660 module_exit(rtl8139_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards