drivers/hwmon/lis3lv02d.h

   1 /*
   2  *  lis3lv02d.h - ST LIS3LV02DL accelerometer driver
   3  *
   4  *  Copyright (C) 2007-2008 Yan Burman
   5  *  Copyright (C) 2008 Eric Piel
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23  * The actual chip is STMicroelectronics LIS3LV02DL or LIS3LV02DQ that seems to
  24  * be connected via SPI. There exists also several similar chips (such as LIS302DL or
  25  * LIS3L02DQ) and they have slightly different registers, but we can provide a
  26  * common interface for all of them.
  27  * They can also be connected via I²C.
  28  */
  29
  30 /* 2-byte registers */
  31 #define LIS_DOUBLE_ID   0x3A /* LIS3LV02D[LQ] */
  32 /* 1-byte registers */
  33 #define LIS_SINGLE_ID   0x3B /* LIS[32]02DL and others */
  34
  35 enum lis3lv02d_reg {
  36         WHO_AM_I        = 0x0F,
  37         OFFSET_X        = 0x16,
  38         OFFSET_Y        = 0x17,
  39         OFFSET_Z        = 0x18,
  40         GAIN_X          = 0x19,
  41         GAIN_Y          = 0x1A,
  42         GAIN_Z          = 0x1B,
  43         CTRL_REG1       = 0x20,
  44         CTRL_REG2       = 0x21,
  45         CTRL_REG3       = 0x22,
  46         HP_FILTER_RESET = 0x23,
  47         STATUS_REG      = 0x27,
  48         OUTX_L          = 0x28,
  49         OUTX_H          = 0x29,
  50         OUTX            = 0x29,
  51         OUTY_L          = 0x2A,
  52         OUTY_H          = 0x2B,
  53         OUTY            = 0x2B,
  54         OUTZ_L          = 0x2C,
  55         OUTZ_H          = 0x2D,
  56         OUTZ            = 0x2D,
  57         FF_WU_CFG       = 0x30,
  58         FF_WU_SRC       = 0x31,
  59         FF_WU_ACK       = 0x32,
  60         FF_WU_THS_L     = 0x34,
  61         FF_WU_THS_H     = 0x35,
  62         FF_WU_DURATION  = 0x36,
  63         DD_CFG          = 0x38,
  64         DD_SRC          = 0x39,
  65         DD_ACK          = 0x3A,
  66         DD_THSI_L       = 0x3C,
  67         DD_THSI_H       = 0x3D,
  68         DD_THSE_L       = 0x3E,
  69         DD_THSE_H       = 0x3F,
  70 };
  71
  72 enum lis3lv02d_ctrl1 {
  73         CTRL1_Xen       = 0x01,
  74         CTRL1_Yen       = 0x02,
  75         CTRL1_Zen       = 0x04,
  76         CTRL1_ST        = 0x08,
  77         CTRL1_DF0       = 0x10,
  78         CTRL1_DF1       = 0x20,
  79         CTRL1_PD0       = 0x40,
  80         CTRL1_PD1       = 0x80,
  81 };
  82 enum lis3lv02d_ctrl2 {
  83         CTRL2_DAS       = 0x01,
  84         CTRL2_SIM       = 0x02,
  85         CTRL2_DRDY      = 0x04,
  86         CTRL2_IEN       = 0x08,
  87         CTRL2_BOOT      = 0x10,
  88         CTRL2_BLE       = 0x20,
  89         CTRL2_BDU       = 0x40, /* Block Data Update */
  90         CTRL2_FS        = 0x80, /* Full Scale selection */
  91 };
  92
  93
  94 enum lis3lv02d_ctrl3 {
  95         CTRL3_CFS0      = 0x01,
  96         CTRL3_CFS1      = 0x02,
  97         CTRL3_FDS       = 0x10,
  98         CTRL3_HPFF      = 0x20,
  99         CTRL3_HPDD      = 0x40,
 100         CTRL3_ECK       = 0x80,
 101 };
 102
 103 enum lis3lv02d_status_reg {
 104         STATUS_XDA      = 0x01,
 105         STATUS_YDA      = 0x02,
 106         STATUS_ZDA      = 0x04,
 107         STATUS_XYZDA    = 0x08,
 108         STATUS_XOR      = 0x10,
 109         STATUS_YOR      = 0x20,
 110         STATUS_ZOR      = 0x40,
 111         STATUS_XYZOR    = 0x80,
 112 };
 113
 114 enum lis3lv02d_ff_wu_cfg {
 115         FF_WU_CFG_XLIE  = 0x01,
 116         FF_WU_CFG_XHIE  = 0x02,
 117         FF_WU_CFG_YLIE  = 0x04,
 118         FF_WU_CFG_YHIE  = 0x08,
 119         FF_WU_CFG_ZLIE  = 0x10,
 120         FF_WU_CFG_ZHIE  = 0x20,
 121         FF_WU_CFG_LIR   = 0x40,
 122         FF_WU_CFG_AOI   = 0x80,
 123 };
 124
 125 enum lis3lv02d_ff_wu_src {
 126         FF_WU_SRC_XL    = 0x01,
 127         FF_WU_SRC_XH    = 0x02,
 128         FF_WU_SRC_YL    = 0x04,
 129         FF_WU_SRC_YH    = 0x08,
 130         FF_WU_SRC_ZL    = 0x10,
 131         FF_WU_SRC_ZH    = 0x20,
 132         FF_WU_SRC_IA    = 0x40,
 133 };
 134
 135 enum lis3lv02d_dd_cfg {
 136         DD_CFG_XLIE     = 0x01,
 137         DD_CFG_XHIE     = 0x02,
 138         DD_CFG_YLIE     = 0x04,
 139         DD_CFG_YHIE     = 0x08,
 140         DD_CFG_ZLIE     = 0x10,
 141         DD_CFG_ZHIE     = 0x20,
 142         DD_CFG_LIR      = 0x40,
 143         DD_CFG_IEND     = 0x80,
 144 };
 145
 146 enum lis3lv02d_dd_src {
 147         DD_SRC_XL       = 0x01,
 148         DD_SRC_XH       = 0x02,
 149         DD_SRC_YL       = 0x04,
 150         DD_SRC_YH       = 0x08,
 151         DD_SRC_ZL       = 0x10,
 152         DD_SRC_ZH       = 0x20,
 153         DD_SRC_IA       = 0x40,
 154 };
 155
 156 struct axis_conversion {
 157         s8      x;
 158         s8      y;
 159         s8      z;
 160 };
 161
 162 struct lis3lv02d {
 163         void                    *bus_priv; /* used by the bus layer only */
 164         int (*init) (struct lis3lv02d *lis3);
 165         int (*write) (struct lis3lv02d *lis3, int reg, u8 val);
 166         int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret);
 167
 168         u8                      whoami;    /* 3Ah: 2-byte registries, 3Bh: 1-byte registries */
 169         s16 (*read_data) (struct lis3lv02d *lis3, int reg);
 170         int                     mdps_max_val;
 171
 172         struct input_dev        *idev;     /* input device */
 173         struct task_struct      *kthread;  /* kthread for input */
 174         struct mutex            lock;
 175         struct platform_device  *pdev;     /* platform device */
 176         atomic_t                count;     /* interrupt count after last read */
 177         int                     xcalib;    /* calibrated null value for x */
 178         int                     ycalib;    /* calibrated null value for y */
 179         int                     zcalib;    /* calibrated null value for z */
 180         unsigned char           is_on;     /* whether the device is on or off */
 181         unsigned char           usage;     /* usage counter */
 182         struct axis_conversion  ac;        /* hw -> logical axis */
 183
 184         u32                     irq;       /* IRQ number */
 185         struct fasync_struct    *async_queue; /* queue for the misc device */
 186         wait_queue_head_t       misc_wait; /* Wait queue for the misc device */
 187         unsigned long           misc_opened; /* bit0: whether the device is open */
 188 };
 189
 190 int lis3lv02d_init_device(struct lis3lv02d *lis3);
 191 int lis3lv02d_joystick_enable(void);
 192 void lis3lv02d_joystick_disable(void);
 193 void lis3lv02d_poweroff(struct lis3lv02d *lis3);
 194 void lis3lv02d_poweron(struct lis3lv02d *lis3);
 195 int lis3lv02d_remove_fs(void);
 196
 197 extern struct lis3lv02d lis3_dev;