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intel-gtt: i830: adjust ioremap of regs and gtt to i9xx
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / intel-gtt.c
blob7359fbe94428db0e2527c831777815d885af7641
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #endif
39
40 /* Max amount of stolen space, anything above will be returned to Linux */
41 int intel_max_stolen = 32 * 1024 * 1024;
42 EXPORT_SYMBOL(intel_max_stolen);
43
44 static const struct aper_size_info_fixed intel_i810_sizes[] =
45 {
46 {64, 16384, 4},
47 /* The 32M mode still requires a 64k gatt */
48 {32, 8192, 4}
49 };
50
51 #define AGP_DCACHE_MEMORY 1
52 #define AGP_PHYS_MEMORY 2
53 #define INTEL_AGP_CACHED_MEMORY 3
54
55 static struct gatt_mask intel_i810_masks[] =
56 {
57 {.mask = I810_PTE_VALID, .type = 0},
58 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
59 {.mask = I810_PTE_VALID, .type = 0},
60 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
61 .type = INTEL_AGP_CACHED_MEMORY}
62 };
63
64 #define INTEL_AGP_UNCACHED_MEMORY 0
65 #define INTEL_AGP_CACHED_MEMORY_LLC 1
66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
69
70 static struct gatt_mask intel_gen6_masks[] =
71 {
72 {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
73 .type = INTEL_AGP_UNCACHED_MEMORY },
74 {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
75 .type = INTEL_AGP_CACHED_MEMORY_LLC },
76 {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
77 .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
78 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
79 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
80 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
81 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
82 };
83
84 struct intel_gtt_driver {
85 unsigned int gen : 8;
86 unsigned int is_g33 : 1;
87 unsigned int is_pineview : 1;
88 unsigned int is_ironlake : 1;
89 };
90
91 static struct _intel_private {
92 struct intel_gtt base;
93 const struct intel_gtt_driver *driver;
94 struct pci_dev *pcidev; /* device one */
95 struct pci_dev *bridge_dev;
96 u8 __iomem *registers;
97 u32 __iomem *gtt; /* I915G */
98 int num_dcache_entries;
99 union {
100 void __iomem *i9xx_flush_page;
101 void *i8xx_flush_page;
102 };
103 struct page *i8xx_page;
104 struct resource ifp_resource;
105 int resource_valid;
106 } intel_private;
107
108 #define INTEL_GTT_GEN intel_private.driver->gen
109 #define IS_G33 intel_private.driver->is_g33
110 #define IS_PINEVIEW intel_private.driver->is_pineview
111 #define IS_IRONLAKE intel_private.driver->is_ironlake
112
113 #ifdef USE_PCI_DMA_API
114 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
115 {
116 *ret = pci_map_page(intel_private.pcidev, page, 0,
117 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
118 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
119 return -EINVAL;
120 return 0;
121 }
122
123 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
124 {
125 pci_unmap_page(intel_private.pcidev, dma,
126 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
127 }
128
129 static void intel_agp_free_sglist(struct agp_memory *mem)
130 {
131 struct sg_table st;
132
133 st.sgl = mem->sg_list;
134 st.orig_nents = st.nents = mem->page_count;
135
136 sg_free_table(&st);
137
138 mem->sg_list = NULL;
139 mem->num_sg = 0;
140 }
141
142 static int intel_agp_map_memory(struct agp_memory *mem)
143 {
144 struct sg_table st;
145 struct scatterlist *sg;
146 int i;
147
148 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
149
150 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
151 goto err;
152
153 mem->sg_list = sg = st.sgl;
154
155 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
156 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
157
158 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
159 mem->page_count, PCI_DMA_BIDIRECTIONAL);
160 if (unlikely(!mem->num_sg))
161 goto err;
162
163 return 0;
164
165 err:
166 sg_free_table(&st);
167 return -ENOMEM;
168 }
169
170 static void intel_agp_unmap_memory(struct agp_memory *mem)
171 {
172 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
173
174 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
175 mem->page_count, PCI_DMA_BIDIRECTIONAL);
176 intel_agp_free_sglist(mem);
177 }
178
179 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
180 off_t pg_start, int mask_type)
181 {
182 struct scatterlist *sg;
183 int i, j;
184
185 j = pg_start;
186
187 WARN_ON(!mem->num_sg);
188
189 if (mem->num_sg == mem->page_count) {
190 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
191 writel(agp_bridge->driver->mask_memory(agp_bridge,
192 sg_dma_address(sg), mask_type),
193 intel_private.gtt+j);
194 j++;
195 }
196 } else {
197 /* sg may merge pages, but we have to separate
198 * per-page addr for GTT */
199 unsigned int len, m;
200
201 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
202 len = sg_dma_len(sg) / PAGE_SIZE;
203 for (m = 0; m < len; m++) {
204 writel(agp_bridge->driver->mask_memory(agp_bridge,
205 sg_dma_address(sg) + m * PAGE_SIZE,
206 mask_type),
207 intel_private.gtt+j);
208 j++;
209 }
210 }
211 }
212 readl(intel_private.gtt+j-1);
213 }
214
215 #else
216
217 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
218 off_t pg_start, int mask_type)
219 {
220 int i, j;
221
222 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
223 writel(agp_bridge->driver->mask_memory(agp_bridge,
224 page_to_phys(mem->pages[i]), mask_type),
225 intel_private.gtt+j);
226 }
227
228 readl(intel_private.gtt+j-1);
229 }
230
231 #endif
232
233 static int intel_i810_fetch_size(void)
234 {
235 u32 smram_miscc;
236 struct aper_size_info_fixed *values;
237
238 pci_read_config_dword(intel_private.bridge_dev,
239 I810_SMRAM_MISCC, &smram_miscc);
240 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
241
242 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
243 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
244 return 0;
245 }
246 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
247 agp_bridge->current_size = (void *) (values + 1);
248 agp_bridge->aperture_size_idx = 1;
249 return values[1].size;
250 } else {
251 agp_bridge->current_size = (void *) (values);
252 agp_bridge->aperture_size_idx = 0;
253 return values[0].size;
254 }
255
256 return 0;
257 }
258
259 static int intel_i810_configure(void)
260 {
261 struct aper_size_info_fixed *current_size;
262 u32 temp;
263 int i;
264
265 current_size = A_SIZE_FIX(agp_bridge->current_size);
266
267 if (!intel_private.registers) {
268 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
269 temp &= 0xfff80000;
270
271 intel_private.registers = ioremap(temp, 128 * 4096);
272 if (!intel_private.registers) {
273 dev_err(&intel_private.pcidev->dev,
274 "can't remap memory\n");
275 return -ENOMEM;
276 }
277 }
278
279 if ((readl(intel_private.registers+I810_DRAM_CTL)
280 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
281 /* This will need to be dynamically assigned */
282 dev_info(&intel_private.pcidev->dev,
283 "detected 4MB dedicated video ram\n");
284 intel_private.num_dcache_entries = 1024;
285 }
286 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
287 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
288 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
289 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
290
291 if (agp_bridge->driver->needs_scratch_page) {
292 for (i = 0; i < current_size->num_entries; i++) {
293 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
294 }
295 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
296 }
297 global_cache_flush();
298 return 0;
299 }
300
301 static void intel_i810_cleanup(void)
302 {
303 writel(0, intel_private.registers+I810_PGETBL_CTL);
304 readl(intel_private.registers); /* PCI Posting. */
305 iounmap(intel_private.registers);
306 }
307
308 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
309 {
310 return;
311 }
312
313 /* Exists to support ARGB cursors */
314 static struct page *i8xx_alloc_pages(void)
315 {
316 struct page *page;
317
318 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
319 if (page == NULL)
320 return NULL;
321
322 if (set_pages_uc(page, 4) < 0) {
323 set_pages_wb(page, 4);
324 __free_pages(page, 2);
325 return NULL;
326 }
327 get_page(page);
328 atomic_inc(&agp_bridge->current_memory_agp);
329 return page;
330 }
331
332 static void i8xx_destroy_pages(struct page *page)
333 {
334 if (page == NULL)
335 return;
336
337 set_pages_wb(page, 4);
338 put_page(page);
339 __free_pages(page, 2);
340 atomic_dec(&agp_bridge->current_memory_agp);
341 }
342
343 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
344 int type)
345 {
346 if (type < AGP_USER_TYPES)
347 return type;
348 else if (type == AGP_USER_CACHED_MEMORY)
349 return INTEL_AGP_CACHED_MEMORY;
350 else
351 return 0;
352 }
353
354 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
355 int type)
356 {
357 unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
358 unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
359
360 if (type_mask == AGP_USER_UNCACHED_MEMORY)
361 return INTEL_AGP_UNCACHED_MEMORY;
362 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
363 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
364 INTEL_AGP_CACHED_MEMORY_LLC_MLC;
365 else /* set 'normal'/'cached' to LLC by default */
366 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
367 INTEL_AGP_CACHED_MEMORY_LLC;
368 }
369
370
371 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
372 int type)
373 {
374 int i, j, num_entries;
375 void *temp;
376 int ret = -EINVAL;
377 int mask_type;
378
379 if (mem->page_count == 0)
380 goto out;
381
382 temp = agp_bridge->current_size;
383 num_entries = A_SIZE_FIX(temp)->num_entries;
384
385 if ((pg_start + mem->page_count) > num_entries)
386 goto out_err;
387
388
389 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
390 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
391 ret = -EBUSY;
392 goto out_err;
393 }
394 }
395
396 if (type != mem->type)
397 goto out_err;
398
399 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
400
401 switch (mask_type) {
402 case AGP_DCACHE_MEMORY:
403 if (!mem->is_flushed)
404 global_cache_flush();
405 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
406 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
407 intel_private.registers+I810_PTE_BASE+(i*4));
408 }
409 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
410 break;
411 case AGP_PHYS_MEMORY:
412 case AGP_NORMAL_MEMORY:
413 if (!mem->is_flushed)
414 global_cache_flush();
415 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
416 writel(agp_bridge->driver->mask_memory(agp_bridge,
417 page_to_phys(mem->pages[i]), mask_type),
418 intel_private.registers+I810_PTE_BASE+(j*4));
419 }
420 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
421 break;
422 default:
423 goto out_err;
424 }
425
426 out:
427 ret = 0;
428 out_err:
429 mem->is_flushed = true;
430 return ret;
431 }
432
433 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
434 int type)
435 {
436 int i;
437
438 if (mem->page_count == 0)
439 return 0;
440
441 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
442 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
443 }
444 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
445
446 return 0;
447 }
448
449 /*
450 * The i810/i830 requires a physical address to program its mouse
451 * pointer into hardware.
452 * However the Xserver still writes to it through the agp aperture.
453 */
454 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
455 {
456 struct agp_memory *new;
457 struct page *page;
458
459 switch (pg_count) {
460 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
461 break;
462 case 4:
463 /* kludge to get 4 physical pages for ARGB cursor */
464 page = i8xx_alloc_pages();
465 break;
466 default:
467 return NULL;
468 }
469
470 if (page == NULL)
471 return NULL;
472
473 new = agp_create_memory(pg_count);
474 if (new == NULL)
475 return NULL;
476
477 new->pages[0] = page;
478 if (pg_count == 4) {
479 /* kludge to get 4 physical pages for ARGB cursor */
480 new->pages[1] = new->pages[0] + 1;
481 new->pages[2] = new->pages[1] + 1;
482 new->pages[3] = new->pages[2] + 1;
483 }
484 new->page_count = pg_count;
485 new->num_scratch_pages = pg_count;
486 new->type = AGP_PHYS_MEMORY;
487 new->physical = page_to_phys(new->pages[0]);
488 return new;
489 }
490
491 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
492 {
493 struct agp_memory *new;
494
495 if (type == AGP_DCACHE_MEMORY) {
496 if (pg_count != intel_private.num_dcache_entries)
497 return NULL;
498
499 new = agp_create_memory(1);
500 if (new == NULL)
501 return NULL;
502
503 new->type = AGP_DCACHE_MEMORY;
504 new->page_count = pg_count;
505 new->num_scratch_pages = 0;
506 agp_free_page_array(new);
507 return new;
508 }
509 if (type == AGP_PHYS_MEMORY)
510 return alloc_agpphysmem_i8xx(pg_count, type);
511 return NULL;
512 }
513
514 static void intel_i810_free_by_type(struct agp_memory *curr)
515 {
516 agp_free_key(curr->key);
517 if (curr->type == AGP_PHYS_MEMORY) {
518 if (curr->page_count == 4)
519 i8xx_destroy_pages(curr->pages[0]);
520 else {
521 agp_bridge->driver->agp_destroy_page(curr->pages[0],
522 AGP_PAGE_DESTROY_UNMAP);
523 agp_bridge->driver->agp_destroy_page(curr->pages[0],
524 AGP_PAGE_DESTROY_FREE);
525 }
526 agp_free_page_array(curr);
527 }
528 kfree(curr);
529 }
530
531 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
532 dma_addr_t addr, int type)
533 {
534 /* Type checking must be done elsewhere */
535 return addr | bridge->driver->masks[type].mask;
536 }
537
538 static struct aper_size_info_fixed intel_fake_agp_sizes[] =
539 {
540 {128, 32768, 5},
541 /* The 64M mode still requires a 128k gatt */
542 {64, 16384, 5},
543 {256, 65536, 6},
544 {512, 131072, 7},
545 };
546
547 static unsigned int intel_gtt_stolen_entries(void)
548 {
549 u16 gmch_ctrl;
550 u8 rdct;
551 int local = 0;
552 static const int ddt[4] = { 0, 16, 32, 64 };
553 unsigned int overhead_entries, stolen_entries;
554 unsigned int stolen_size = 0;
555
556 pci_read_config_word(intel_private.bridge_dev,
557 I830_GMCH_CTRL, &gmch_ctrl);
558
559 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
560 overhead_entries = 0;
561 else
562 overhead_entries = intel_private.base.gtt_mappable_entries
563 / 1024;
564
565 overhead_entries += 1; /* BIOS popup */
566
567 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
568 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
569 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
570 case I830_GMCH_GMS_STOLEN_512:
571 stolen_size = KB(512);
572 break;
573 case I830_GMCH_GMS_STOLEN_1024:
574 stolen_size = MB(1);
575 break;
576 case I830_GMCH_GMS_STOLEN_8192:
577 stolen_size = MB(8);
578 break;
579 case I830_GMCH_GMS_LOCAL:
580 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
581 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
582 MB(ddt[I830_RDRAM_DDT(rdct)]);
583 local = 1;
584 break;
585 default:
586 stolen_size = 0;
587 break;
588 }
589 } else if (INTEL_GTT_GEN == 6) {
590 /*
591 * SandyBridge has new memory control reg at 0x50.w
592 */
593 u16 snb_gmch_ctl;
594 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
595 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
596 case SNB_GMCH_GMS_STOLEN_32M:
597 stolen_size = MB(32);
598 break;
599 case SNB_GMCH_GMS_STOLEN_64M:
600 stolen_size = MB(64);
601 break;
602 case SNB_GMCH_GMS_STOLEN_96M:
603 stolen_size = MB(96);
604 break;
605 case SNB_GMCH_GMS_STOLEN_128M:
606 stolen_size = MB(128);
607 break;
608 case SNB_GMCH_GMS_STOLEN_160M:
609 stolen_size = MB(160);
610 break;
611 case SNB_GMCH_GMS_STOLEN_192M:
612 stolen_size = MB(192);
613 break;
614 case SNB_GMCH_GMS_STOLEN_224M:
615 stolen_size = MB(224);
616 break;
617 case SNB_GMCH_GMS_STOLEN_256M:
618 stolen_size = MB(256);
619 break;
620 case SNB_GMCH_GMS_STOLEN_288M:
621 stolen_size = MB(288);
622 break;
623 case SNB_GMCH_GMS_STOLEN_320M:
624 stolen_size = MB(320);
625 break;
626 case SNB_GMCH_GMS_STOLEN_352M:
627 stolen_size = MB(352);
628 break;
629 case SNB_GMCH_GMS_STOLEN_384M:
630 stolen_size = MB(384);
631 break;
632 case SNB_GMCH_GMS_STOLEN_416M:
633 stolen_size = MB(416);
634 break;
635 case SNB_GMCH_GMS_STOLEN_448M:
636 stolen_size = MB(448);
637 break;
638 case SNB_GMCH_GMS_STOLEN_480M:
639 stolen_size = MB(480);
640 break;
641 case SNB_GMCH_GMS_STOLEN_512M:
642 stolen_size = MB(512);
643 break;
644 }
645 } else {
646 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
647 case I855_GMCH_GMS_STOLEN_1M:
648 stolen_size = MB(1);
649 break;
650 case I855_GMCH_GMS_STOLEN_4M:
651 stolen_size = MB(4);
652 break;
653 case I855_GMCH_GMS_STOLEN_8M:
654 stolen_size = MB(8);
655 break;
656 case I855_GMCH_GMS_STOLEN_16M:
657 stolen_size = MB(16);
658 break;
659 case I855_GMCH_GMS_STOLEN_32M:
660 stolen_size = MB(32);
661 break;
662 case I915_GMCH_GMS_STOLEN_48M:
663 stolen_size = MB(48);
664 break;
665 case I915_GMCH_GMS_STOLEN_64M:
666 stolen_size = MB(64);
667 break;
668 case G33_GMCH_GMS_STOLEN_128M:
669 stolen_size = MB(128);
670 break;
671 case G33_GMCH_GMS_STOLEN_256M:
672 stolen_size = MB(256);
673 break;
674 case INTEL_GMCH_GMS_STOLEN_96M:
675 stolen_size = MB(96);
676 break;
677 case INTEL_GMCH_GMS_STOLEN_160M:
678 stolen_size = MB(160);
679 break;
680 case INTEL_GMCH_GMS_STOLEN_224M:
681 stolen_size = MB(224);
682 break;
683 case INTEL_GMCH_GMS_STOLEN_352M:
684 stolen_size = MB(352);
685 break;
686 default:
687 stolen_size = 0;
688 break;
689 }
690 }
691
692 if (!local && stolen_size > intel_max_stolen) {
693 dev_info(&intel_private.bridge_dev->dev,
694 "detected %dK stolen memory, trimming to %dK\n",
695 stolen_size / KB(1), intel_max_stolen / KB(1));
696 stolen_size = intel_max_stolen;
697 } else if (stolen_size > 0) {
698 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
699 stolen_size / KB(1), local ? "local" : "stolen");
700 } else {
701 dev_info(&intel_private.bridge_dev->dev,
702 "no pre-allocated video memory detected\n");
703 stolen_size = 0;
704 }
705
706 stolen_entries = stolen_size/KB(4) - overhead_entries;
707
708 return stolen_entries;
709 }
710
711 static unsigned int intel_gtt_total_entries(void)
712 {
713 int size;
714
715 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) {
716 u32 pgetbl_ctl;
717 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
718
719 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
720 case I965_PGETBL_SIZE_128KB:
721 size = KB(128);
722 break;
723 case I965_PGETBL_SIZE_256KB:
724 size = KB(256);
725 break;
726 case I965_PGETBL_SIZE_512KB:
727 size = KB(512);
728 break;
729 case I965_PGETBL_SIZE_1MB:
730 size = KB(1024);
731 break;
732 case I965_PGETBL_SIZE_2MB:
733 size = KB(2048);
734 break;
735 case I965_PGETBL_SIZE_1_5MB:
736 size = KB(1024 + 512);
737 break;
738 default:
739 dev_info(&intel_private.pcidev->dev,
740 "unknown page table size, assuming 512KB\n");
741 size = KB(512);
742 }
743
744 return size/4;
745 } else if (INTEL_GTT_GEN == 6) {
746 u16 snb_gmch_ctl;
747
748 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
749 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
750 default:
751 case SNB_GTT_SIZE_0M:
752 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
753 size = MB(0);
754 break;
755 case SNB_GTT_SIZE_1M:
756 size = MB(1);
757 break;
758 case SNB_GTT_SIZE_2M:
759 size = MB(2);
760 break;
761 }
762 return size/4;
763 } else {
764 /* On previous hardware, the GTT size was just what was
765 * required to map the aperture.
766 */
767 return intel_private.base.gtt_mappable_entries;
768 }
769 }
770
771 static unsigned int intel_gtt_mappable_entries(void)
772 {
773 unsigned int aperture_size;
774 u16 gmch_ctrl;
775
776 aperture_size = 1024 * 1024;
777
778 pci_read_config_word(intel_private.bridge_dev,
779 I830_GMCH_CTRL, &gmch_ctrl);
780
781 switch (intel_private.pcidev->device) {
782 case PCI_DEVICE_ID_INTEL_82830_CGC:
783 case PCI_DEVICE_ID_INTEL_82845G_IG:
784 case PCI_DEVICE_ID_INTEL_82855GM_IG:
785 case PCI_DEVICE_ID_INTEL_82865_IG:
786 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
787 aperture_size *= 64;
788 else
789 aperture_size *= 128;
790 break;
791 default:
792 /* 9xx supports large sizes, just look at the length */
793 aperture_size = pci_resource_len(intel_private.pcidev, 2);
794 break;
795 }
796
797 return aperture_size >> PAGE_SHIFT;
798 }
799
800 static int intel_gtt_init(void)
801 {
802 /* we have to call this as early as possible after the MMIO base address is known */
803 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
804 if (intel_private.base.gtt_stolen_entries == 0) {
805 iounmap(intel_private.registers);
806 return -ENOMEM;
807 }
808
809 return 0;
810 }
811
812 static int intel_fake_agp_fetch_size(void)
813 {
814 unsigned int aper_size;
815 int i;
816 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
817
818 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
819 / MB(1);
820
821 for (i = 0; i < num_sizes; i++) {
822 if (aper_size == intel_fake_agp_sizes[i].size) {
823 agp_bridge->current_size = intel_fake_agp_sizes + i;
824 return aper_size;
825 }
826 }
827
828 return 0;
829 }
830
831 static void intel_i830_fini_flush(void)
832 {
833 kunmap(intel_private.i8xx_page);
834 intel_private.i8xx_flush_page = NULL;
835 unmap_page_from_agp(intel_private.i8xx_page);
836
837 __free_page(intel_private.i8xx_page);
838 intel_private.i8xx_page = NULL;
839 }
840
841 static void intel_i830_setup_flush(void)
842 {
843 /* return if we've already set the flush mechanism up */
844 if (intel_private.i8xx_page)
845 return;
846
847 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
848 if (!intel_private.i8xx_page)
849 return;
850
851 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
852 if (!intel_private.i8xx_flush_page)
853 intel_i830_fini_flush();
854 }
855
856 /* The chipset_flush interface needs to get data that has already been
857 * flushed out of the CPU all the way out to main memory, because the GPU
858 * doesn't snoop those buffers.
859 *
860 * The 8xx series doesn't have the same lovely interface for flushing the
861 * chipset write buffers that the later chips do. According to the 865
862 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
863 * that buffer out, we just fill 1KB and clflush it out, on the assumption
864 * that it'll push whatever was in there out. It appears to work.
865 */
866 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
867 {
868 unsigned int *pg = intel_private.i8xx_flush_page;
869
870 memset(pg, 0, 1024);
871
872 if (cpu_has_clflush)
873 clflush_cache_range(pg, 1024);
874 else if (wbinvd_on_all_cpus() != 0)
875 printk(KERN_ERR "Timed out waiting for cache flush.\n");
876 }
877
878 /* The intel i830 automatically initializes the agp aperture during POST.
879 * Use the memory already set aside for in the GTT.
880 */
881 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
882 {
883 int page_order, ret;
884 struct aper_size_info_fixed *size;
885 int num_entries;
886 int gtt_map_size;
887 u32 temp;
888
889 size = agp_bridge->current_size;
890 page_order = size->page_order;
891 num_entries = size->num_entries;
892 agp_bridge->gatt_table_real = NULL;
893
894 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
895 temp &= 0xfff80000;
896
897 intel_private.registers = ioremap(temp, KB(64));
898 if (!intel_private.registers)
899 return -ENOMEM;
900
901 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
902 gtt_map_size = intel_private.base.gtt_total_entries * 4;
903
904 intel_private.gtt = ioremap(temp + I810_PTE_BASE, gtt_map_size);
905 if (!intel_private.gtt) {
906 iounmap(intel_private.registers);
907 return -ENOMEM;
908 }
909
910 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
911 global_cache_flush(); /* FIXME: ?? */
912
913 ret = intel_gtt_init();
914 if (ret != 0)
915 return ret;
916
917 agp_bridge->gatt_table = NULL;
918
919 agp_bridge->gatt_bus_addr = temp;
920
921 return 0;
922 }
923
924 /* Return the gatt table to a sane state. Use the top of stolen
925 * memory for the GTT.
926 */
927 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
928 {
929 return 0;
930 }
931
932 static int intel_i830_configure(void)
933 {
934 struct aper_size_info_fixed *current_size;
935 u32 temp;
936 u16 gmch_ctrl;
937 int i;
938
939 current_size = A_SIZE_FIX(agp_bridge->current_size);
940
941 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
942 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
943
944 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
945 gmch_ctrl |= I830_GMCH_ENABLED;
946 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
947
948 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
949 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
950
951 if (agp_bridge->driver->needs_scratch_page) {
952 for (i = intel_private.base.gtt_stolen_entries; i < current_size->num_entries; i++) {
953 writel(agp_bridge->scratch_page, intel_private.gtt+i);
954 }
955 readl(intel_private.gtt+i-1); /* PCI Posting. */
956 }
957
958 global_cache_flush();
959
960 intel_i830_setup_flush();
961 return 0;
962 }
963
964 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
965 int type)
966 {
967 int i, j, num_entries;
968 void *temp;
969 int ret = -EINVAL;
970 int mask_type;
971
972 if (mem->page_count == 0)
973 goto out;
974
975 temp = agp_bridge->current_size;
976 num_entries = A_SIZE_FIX(temp)->num_entries;
977
978 if (pg_start < intel_private.base.gtt_stolen_entries) {
979 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
980 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
981 pg_start, intel_private.base.gtt_stolen_entries);
982
983 dev_info(&intel_private.pcidev->dev,
984 "trying to insert into local/stolen memory\n");
985 goto out_err;
986 }
987
988 if ((pg_start + mem->page_count) > num_entries)
989 goto out_err;
990
991 /* The i830 can't check the GTT for entries since its read only,
992 * depend on the caller to make the correct offset decisions.
993 */
994
995 if (type != mem->type)
996 goto out_err;
997
998 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
999
1000 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1001 mask_type != INTEL_AGP_CACHED_MEMORY)
1002 goto out_err;
1003
1004 if (!mem->is_flushed)
1005 global_cache_flush();
1006
1007 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1008 writel(agp_bridge->driver->mask_memory(agp_bridge,
1009 page_to_phys(mem->pages[i]), mask_type),
1010 intel_private.gtt+j);
1011 }
1012 readl(intel_private.gtt+j-1);
1013
1014 out:
1015 ret = 0;
1016 out_err:
1017 mem->is_flushed = true;
1018 return ret;
1019 }
1020
1021 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1022 int type)
1023 {
1024 int i;
1025
1026 if (mem->page_count == 0)
1027 return 0;
1028
1029 if (pg_start < intel_private.base.gtt_stolen_entries) {
1030 dev_info(&intel_private.pcidev->dev,
1031 "trying to disable local/stolen memory\n");
1032 return -EINVAL;
1033 }
1034
1035 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1036 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1037 }
1038 readl(intel_private.gtt+i-1);
1039
1040 return 0;
1041 }
1042
1043 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1044 int type)
1045 {
1046 if (type == AGP_PHYS_MEMORY)
1047 return alloc_agpphysmem_i8xx(pg_count, type);
1048 /* always return NULL for other allocation types for now */
1049 return NULL;
1050 }
1051
1052 static int intel_alloc_chipset_flush_resource(void)
1053 {
1054 int ret;
1055 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1056 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1057 pcibios_align_resource, intel_private.bridge_dev);
1058
1059 return ret;
1060 }
1061
1062 static void intel_i915_setup_chipset_flush(void)
1063 {
1064 int ret;
1065 u32 temp;
1066
1067 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1068 if (!(temp & 0x1)) {
1069 intel_alloc_chipset_flush_resource();
1070 intel_private.resource_valid = 1;
1071 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1072 } else {
1073 temp &= ~1;
1074
1075 intel_private.resource_valid = 1;
1076 intel_private.ifp_resource.start = temp;
1077 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1078 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1079 /* some BIOSes reserve this area in a pnp some don't */
1080 if (ret)
1081 intel_private.resource_valid = 0;
1082 }
1083 }
1084
1085 static void intel_i965_g33_setup_chipset_flush(void)
1086 {
1087 u32 temp_hi, temp_lo;
1088 int ret;
1089
1090 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1091 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1092
1093 if (!(temp_lo & 0x1)) {
1094
1095 intel_alloc_chipset_flush_resource();
1096
1097 intel_private.resource_valid = 1;
1098 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1099 upper_32_bits(intel_private.ifp_resource.start));
1100 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1101 } else {
1102 u64 l64;
1103
1104 temp_lo &= ~0x1;
1105 l64 = ((u64)temp_hi << 32) | temp_lo;
1106
1107 intel_private.resource_valid = 1;
1108 intel_private.ifp_resource.start = l64;
1109 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1110 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1111 /* some BIOSes reserve this area in a pnp some don't */
1112 if (ret)
1113 intel_private.resource_valid = 0;
1114 }
1115 }
1116
1117 static void intel_i9xx_setup_flush(void)
1118 {
1119 /* return if already configured */
1120 if (intel_private.ifp_resource.start)
1121 return;
1122
1123 if (INTEL_GTT_GEN == 6)
1124 return;
1125
1126 /* setup a resource for this object */
1127 intel_private.ifp_resource.name = "Intel Flush Page";
1128 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1129
1130 /* Setup chipset flush for 915 */
1131 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1132 intel_i965_g33_setup_chipset_flush();
1133 } else {
1134 intel_i915_setup_chipset_flush();
1135 }
1136
1137 if (intel_private.ifp_resource.start)
1138 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1139 if (!intel_private.i9xx_flush_page)
1140 dev_err(&intel_private.pcidev->dev,
1141 "can't ioremap flush page - no chipset flushing\n");
1142 }
1143
1144 static int intel_i9xx_configure(void)
1145 {
1146 struct aper_size_info_fixed *current_size;
1147 u32 temp;
1148 u16 gmch_ctrl;
1149 int i;
1150
1151 current_size = A_SIZE_FIX(agp_bridge->current_size);
1152
1153 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1154
1155 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1156
1157 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
1158 gmch_ctrl |= I830_GMCH_ENABLED;
1159 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
1160
1161 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1162 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1163
1164 if (agp_bridge->driver->needs_scratch_page) {
1165 for (i = intel_private.base.gtt_stolen_entries; i <
1166 intel_private.base.gtt_total_entries; i++) {
1167 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1168 }
1169 readl(intel_private.gtt+i-1); /* PCI Posting. */
1170 }
1171
1172 global_cache_flush();
1173
1174 intel_i9xx_setup_flush();
1175
1176 return 0;
1177 }
1178
1179 static void intel_gtt_cleanup(void)
1180 {
1181 if (intel_private.i9xx_flush_page)
1182 iounmap(intel_private.i9xx_flush_page);
1183 if (intel_private.resource_valid)
1184 release_resource(&intel_private.ifp_resource);
1185 intel_private.ifp_resource.start = 0;
1186 intel_private.resource_valid = 0;
1187 iounmap(intel_private.gtt);
1188 iounmap(intel_private.registers);
1189 }
1190
1191 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1192 {
1193 if (intel_private.i9xx_flush_page)
1194 writel(1, intel_private.i9xx_flush_page);
1195 }
1196
1197 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1198 int type)
1199 {
1200 int num_entries;
1201 void *temp;
1202 int ret = -EINVAL;
1203 int mask_type;
1204
1205 if (mem->page_count == 0)
1206 goto out;
1207
1208 temp = agp_bridge->current_size;
1209 num_entries = A_SIZE_FIX(temp)->num_entries;
1210
1211 if (pg_start < intel_private.base.gtt_stolen_entries) {
1212 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1213 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1214 pg_start, intel_private.base.gtt_stolen_entries);
1215
1216 dev_info(&intel_private.pcidev->dev,
1217 "trying to insert into local/stolen memory\n");
1218 goto out_err;
1219 }
1220
1221 if ((pg_start + mem->page_count) > num_entries)
1222 goto out_err;
1223
1224 /* The i915 can't check the GTT for entries since it's read only;
1225 * depend on the caller to make the correct offset decisions.
1226 */
1227
1228 if (type != mem->type)
1229 goto out_err;
1230
1231 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1232
1233 if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1234 mask_type != AGP_PHYS_MEMORY &&
1235 mask_type != INTEL_AGP_CACHED_MEMORY)
1236 goto out_err;
1237
1238 if (!mem->is_flushed)
1239 global_cache_flush();
1240
1241 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1242
1243 out:
1244 ret = 0;
1245 out_err:
1246 mem->is_flushed = true;
1247 return ret;
1248 }
1249
1250 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1251 int type)
1252 {
1253 int i;
1254
1255 if (mem->page_count == 0)
1256 return 0;
1257
1258 if (pg_start < intel_private.base.gtt_stolen_entries) {
1259 dev_info(&intel_private.pcidev->dev,
1260 "trying to disable local/stolen memory\n");
1261 return -EINVAL;
1262 }
1263
1264 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1265 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1266
1267 readl(intel_private.gtt+i-1);
1268
1269 return 0;
1270 }
1271
1272 /* The intel i915 automatically initializes the agp aperture during POST.
1273 * Use the memory already set aside for in the GTT.
1274 */
1275 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1276 {
1277 int page_order, ret;
1278 struct aper_size_info_fixed *size;
1279 int num_entries;
1280 u32 temp, temp2;
1281 int gtt_map_size;
1282
1283 size = agp_bridge->current_size;
1284 page_order = size->page_order;
1285 num_entries = size->num_entries;
1286 agp_bridge->gatt_table_real = NULL;
1287
1288 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1289 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1290
1291 temp &= 0xfff80000;
1292
1293 intel_private.registers = ioremap(temp, 128 * 4096);
1294 if (!intel_private.registers)
1295 return -ENOMEM;
1296
1297 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
1298 gtt_map_size = intel_private.base.gtt_total_entries * 4;
1299
1300 intel_private.gtt = ioremap(temp2, gtt_map_size);
1301 if (!intel_private.gtt) {
1302 iounmap(intel_private.registers);
1303 return -ENOMEM;
1304 }
1305
1306 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1307 global_cache_flush(); /* FIXME: ? */
1308
1309 ret = intel_gtt_init();
1310 if (ret != 0) {
1311 iounmap(intel_private.gtt);
1312 return ret;
1313 }
1314
1315 agp_bridge->gatt_table = NULL;
1316
1317 agp_bridge->gatt_bus_addr = temp;
1318
1319 return 0;
1320 }
1321
1322 /*
1323 * The i965 supports 36-bit physical addresses, but to keep
1324 * the format of the GTT the same, the bits that don't fit
1325 * in a 32-bit word are shifted down to bits 4..7.
1326 *
1327 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1328 * is always zero on 32-bit architectures, so no need to make
1329 * this conditional.
1330 */
1331 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1332 dma_addr_t addr, int type)
1333 {
1334 /* Shift high bits down */
1335 addr |= (addr >> 28) & 0xf0;
1336
1337 /* Type checking must be done elsewhere */
1338 return addr | bridge->driver->masks[type].mask;
1339 }
1340
1341 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1342 dma_addr_t addr, int type)
1343 {
1344 /* gen6 has bit11-4 for physical addr bit39-32 */
1345 addr |= (addr >> 28) & 0xff0;
1346
1347 /* Type checking must be done elsewhere */
1348 return addr | bridge->driver->masks[type].mask;
1349 }
1350
1351 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1352 {
1353 switch (INTEL_GTT_GEN) {
1354 case 5:
1355 case 6:
1356 *gtt_offset = MB(2);
1357 break;
1358 case 4:
1359 default:
1360 *gtt_offset = KB(512);
1361 break;
1362 }
1363
1364 *gtt_size = intel_private.base.gtt_total_entries * 4;
1365 }
1366
1367 /* The intel i965 automatically initializes the agp aperture during POST.
1368 * Use the memory already set aside for in the GTT.
1369 */
1370 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1371 {
1372 int page_order, ret;
1373 struct aper_size_info_fixed *size;
1374 int num_entries;
1375 u32 temp;
1376 int gtt_offset, gtt_size;
1377
1378 size = agp_bridge->current_size;
1379 page_order = size->page_order;
1380 num_entries = size->num_entries;
1381 agp_bridge->gatt_table_real = NULL;
1382
1383 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1384
1385 temp &= 0xfff00000;
1386
1387 intel_private.registers = ioremap(temp, 128 * 4096);
1388 if (!intel_private.registers)
1389 return -ENOMEM;
1390
1391 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
1392
1393 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1394
1395 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1396
1397 if (!intel_private.gtt) {
1398 iounmap(intel_private.gtt);
1399 return -ENOMEM;
1400 }
1401
1402 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1403 global_cache_flush(); /* FIXME: ? */
1404
1405 ret = intel_gtt_init();
1406 if (ret != 0) {
1407 iounmap(intel_private.gtt);
1408 return ret;
1409 }
1410
1411 agp_bridge->gatt_table = NULL;
1412
1413 agp_bridge->gatt_bus_addr = temp;
1414
1415 return 0;
1416 }
1417
1418 static const struct agp_bridge_driver intel_810_driver = {
1419 .owner = THIS_MODULE,
1420 .aperture_sizes = intel_i810_sizes,
1421 .size_type = FIXED_APER_SIZE,
1422 .num_aperture_sizes = 2,
1423 .needs_scratch_page = true,
1424 .configure = intel_i810_configure,
1425 .fetch_size = intel_i810_fetch_size,
1426 .cleanup = intel_i810_cleanup,
1427 .mask_memory = intel_i810_mask_memory,
1428 .masks = intel_i810_masks,
1429 .agp_enable = intel_fake_agp_enable,
1430 .cache_flush = global_cache_flush,
1431 .create_gatt_table = agp_generic_create_gatt_table,
1432 .free_gatt_table = agp_generic_free_gatt_table,
1433 .insert_memory = intel_i810_insert_entries,
1434 .remove_memory = intel_i810_remove_entries,
1435 .alloc_by_type = intel_i810_alloc_by_type,
1436 .free_by_type = intel_i810_free_by_type,
1437 .agp_alloc_page = agp_generic_alloc_page,
1438 .agp_alloc_pages = agp_generic_alloc_pages,
1439 .agp_destroy_page = agp_generic_destroy_page,
1440 .agp_destroy_pages = agp_generic_destroy_pages,
1441 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1442 };
1443
1444 static const struct agp_bridge_driver intel_830_driver = {
1445 .owner = THIS_MODULE,
1446 .aperture_sizes = intel_fake_agp_sizes,
1447 .size_type = FIXED_APER_SIZE,
1448 .num_aperture_sizes = 4,
1449 .needs_scratch_page = true,
1450 .configure = intel_i830_configure,
1451 .fetch_size = intel_fake_agp_fetch_size,
1452 .cleanup = intel_gtt_cleanup,
1453 .mask_memory = intel_i810_mask_memory,
1454 .masks = intel_i810_masks,
1455 .agp_enable = intel_fake_agp_enable,
1456 .cache_flush = global_cache_flush,
1457 .create_gatt_table = intel_i830_create_gatt_table,
1458 .free_gatt_table = intel_fake_agp_free_gatt_table,
1459 .insert_memory = intel_i830_insert_entries,
1460 .remove_memory = intel_i830_remove_entries,
1461 .alloc_by_type = intel_fake_agp_alloc_by_type,
1462 .free_by_type = intel_i810_free_by_type,
1463 .agp_alloc_page = agp_generic_alloc_page,
1464 .agp_alloc_pages = agp_generic_alloc_pages,
1465 .agp_destroy_page = agp_generic_destroy_page,
1466 .agp_destroy_pages = agp_generic_destroy_pages,
1467 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1468 .chipset_flush = intel_i830_chipset_flush,
1469 };
1470
1471 static const struct agp_bridge_driver intel_915_driver = {
1472 .owner = THIS_MODULE,
1473 .aperture_sizes = intel_fake_agp_sizes,
1474 .size_type = FIXED_APER_SIZE,
1475 .num_aperture_sizes = 4,
1476 .needs_scratch_page = true,
1477 .configure = intel_i9xx_configure,
1478 .fetch_size = intel_fake_agp_fetch_size,
1479 .cleanup = intel_gtt_cleanup,
1480 .mask_memory = intel_i810_mask_memory,
1481 .masks = intel_i810_masks,
1482 .agp_enable = intel_fake_agp_enable,
1483 .cache_flush = global_cache_flush,
1484 .create_gatt_table = intel_i915_create_gatt_table,
1485 .free_gatt_table = intel_fake_agp_free_gatt_table,
1486 .insert_memory = intel_i915_insert_entries,
1487 .remove_memory = intel_i915_remove_entries,
1488 .alloc_by_type = intel_fake_agp_alloc_by_type,
1489 .free_by_type = intel_i810_free_by_type,
1490 .agp_alloc_page = agp_generic_alloc_page,
1491 .agp_alloc_pages = agp_generic_alloc_pages,
1492 .agp_destroy_page = agp_generic_destroy_page,
1493 .agp_destroy_pages = agp_generic_destroy_pages,
1494 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1495 .chipset_flush = intel_i915_chipset_flush,
1496 #ifdef USE_PCI_DMA_API
1497 .agp_map_page = intel_agp_map_page,
1498 .agp_unmap_page = intel_agp_unmap_page,
1499 .agp_map_memory = intel_agp_map_memory,
1500 .agp_unmap_memory = intel_agp_unmap_memory,
1501 #endif
1502 };
1503
1504 static const struct agp_bridge_driver intel_i965_driver = {
1505 .owner = THIS_MODULE,
1506 .aperture_sizes = intel_fake_agp_sizes,
1507 .size_type = FIXED_APER_SIZE,
1508 .num_aperture_sizes = 4,
1509 .needs_scratch_page = true,
1510 .configure = intel_i9xx_configure,
1511 .fetch_size = intel_fake_agp_fetch_size,
1512 .cleanup = intel_gtt_cleanup,
1513 .mask_memory = intel_i965_mask_memory,
1514 .masks = intel_i810_masks,
1515 .agp_enable = intel_fake_agp_enable,
1516 .cache_flush = global_cache_flush,
1517 .create_gatt_table = intel_i965_create_gatt_table,
1518 .free_gatt_table = intel_fake_agp_free_gatt_table,
1519 .insert_memory = intel_i915_insert_entries,
1520 .remove_memory = intel_i915_remove_entries,
1521 .alloc_by_type = intel_fake_agp_alloc_by_type,
1522 .free_by_type = intel_i810_free_by_type,
1523 .agp_alloc_page = agp_generic_alloc_page,
1524 .agp_alloc_pages = agp_generic_alloc_pages,
1525 .agp_destroy_page = agp_generic_destroy_page,
1526 .agp_destroy_pages = agp_generic_destroy_pages,
1527 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1528 .chipset_flush = intel_i915_chipset_flush,
1529 #ifdef USE_PCI_DMA_API
1530 .agp_map_page = intel_agp_map_page,
1531 .agp_unmap_page = intel_agp_unmap_page,
1532 .agp_map_memory = intel_agp_map_memory,
1533 .agp_unmap_memory = intel_agp_unmap_memory,
1534 #endif
1535 };
1536
1537 static const struct agp_bridge_driver intel_gen6_driver = {
1538 .owner = THIS_MODULE,
1539 .aperture_sizes = intel_fake_agp_sizes,
1540 .size_type = FIXED_APER_SIZE,
1541 .num_aperture_sizes = 4,
1542 .needs_scratch_page = true,
1543 .configure = intel_i9xx_configure,
1544 .fetch_size = intel_fake_agp_fetch_size,
1545 .cleanup = intel_gtt_cleanup,
1546 .mask_memory = intel_gen6_mask_memory,
1547 .masks = intel_gen6_masks,
1548 .agp_enable = intel_fake_agp_enable,
1549 .cache_flush = global_cache_flush,
1550 .create_gatt_table = intel_i965_create_gatt_table,
1551 .free_gatt_table = intel_fake_agp_free_gatt_table,
1552 .insert_memory = intel_i915_insert_entries,
1553 .remove_memory = intel_i915_remove_entries,
1554 .alloc_by_type = intel_fake_agp_alloc_by_type,
1555 .free_by_type = intel_i810_free_by_type,
1556 .agp_alloc_page = agp_generic_alloc_page,
1557 .agp_alloc_pages = agp_generic_alloc_pages,
1558 .agp_destroy_page = agp_generic_destroy_page,
1559 .agp_destroy_pages = agp_generic_destroy_pages,
1560 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
1561 .chipset_flush = intel_i915_chipset_flush,
1562 #ifdef USE_PCI_DMA_API
1563 .agp_map_page = intel_agp_map_page,
1564 .agp_unmap_page = intel_agp_unmap_page,
1565 .agp_map_memory = intel_agp_map_memory,
1566 .agp_unmap_memory = intel_agp_unmap_memory,
1567 #endif
1568 };
1569
1570 static const struct agp_bridge_driver intel_g33_driver = {
1571 .owner = THIS_MODULE,
1572 .aperture_sizes = intel_fake_agp_sizes,
1573 .size_type = FIXED_APER_SIZE,
1574 .num_aperture_sizes = 4,
1575 .needs_scratch_page = true,
1576 .configure = intel_i9xx_configure,
1577 .fetch_size = intel_fake_agp_fetch_size,
1578 .cleanup = intel_gtt_cleanup,
1579 .mask_memory = intel_i965_mask_memory,
1580 .masks = intel_i810_masks,
1581 .agp_enable = intel_fake_agp_enable,
1582 .cache_flush = global_cache_flush,
1583 .create_gatt_table = intel_i915_create_gatt_table,
1584 .free_gatt_table = intel_fake_agp_free_gatt_table,
1585 .insert_memory = intel_i915_insert_entries,
1586 .remove_memory = intel_i915_remove_entries,
1587 .alloc_by_type = intel_fake_agp_alloc_by_type,
1588 .free_by_type = intel_i810_free_by_type,
1589 .agp_alloc_page = agp_generic_alloc_page,
1590 .agp_alloc_pages = agp_generic_alloc_pages,
1591 .agp_destroy_page = agp_generic_destroy_page,
1592 .agp_destroy_pages = agp_generic_destroy_pages,
1593 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1594 .chipset_flush = intel_i915_chipset_flush,
1595 #ifdef USE_PCI_DMA_API
1596 .agp_map_page = intel_agp_map_page,
1597 .agp_unmap_page = intel_agp_unmap_page,
1598 .agp_map_memory = intel_agp_map_memory,
1599 .agp_unmap_memory = intel_agp_unmap_memory,
1600 #endif
1601 };
1602
1603 static const struct intel_gtt_driver i8xx_gtt_driver = {
1604 .gen = 2,
1605 };
1606 static const struct intel_gtt_driver i915_gtt_driver = {
1607 .gen = 3,
1608 };
1609 static const struct intel_gtt_driver g33_gtt_driver = {
1610 .gen = 3,
1611 .is_g33 = 1,
1612 };
1613 static const struct intel_gtt_driver pineview_gtt_driver = {
1614 .gen = 3,
1615 .is_pineview = 1, .is_g33 = 1,
1616 };
1617 static const struct intel_gtt_driver i965_gtt_driver = {
1618 .gen = 4,
1619 };
1620 static const struct intel_gtt_driver g4x_gtt_driver = {
1621 .gen = 5,
1622 };
1623 static const struct intel_gtt_driver ironlake_gtt_driver = {
1624 .gen = 5,
1625 .is_ironlake = 1,
1626 };
1627 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1628 .gen = 6,
1629 };
1630
1631 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1632 * driver and gmch_driver must be non-null, and find_gmch will determine
1633 * which one should be used if a gmch_chip_id is present.
1634 */
1635 static const struct intel_gtt_driver_description {
1636 unsigned int gmch_chip_id;
1637 char *name;
1638 const struct agp_bridge_driver *gmch_driver;
1639 const struct intel_gtt_driver *gtt_driver;
1640 } intel_gtt_chipsets[] = {
1641 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL},
1642 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL},
1643 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL},
1644 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL},
1645 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1646 &intel_830_driver , &i8xx_gtt_driver},
1647 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1648 &intel_830_driver , &i8xx_gtt_driver},
1649 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1650 &intel_830_driver , &i8xx_gtt_driver},
1651 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1652 &intel_830_driver , &i8xx_gtt_driver},
1653 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1654 &intel_830_driver , &i8xx_gtt_driver},
1655 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1656 &intel_915_driver , &i915_gtt_driver },
1657 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1658 &intel_915_driver , &i915_gtt_driver },
1659 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1660 &intel_915_driver , &i915_gtt_driver },
1661 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1662 &intel_915_driver , &i915_gtt_driver },
1663 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1664 &intel_915_driver , &i915_gtt_driver },
1665 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1666 &intel_915_driver , &i915_gtt_driver },
1667 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1668 &intel_i965_driver , &i965_gtt_driver },
1669 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1670 &intel_i965_driver , &i965_gtt_driver },
1671 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1672 &intel_i965_driver , &i965_gtt_driver },
1673 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1674 &intel_i965_driver , &i965_gtt_driver },
1675 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1676 &intel_i965_driver , &i965_gtt_driver },
1677 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1678 &intel_i965_driver , &i965_gtt_driver },
1679 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1680 &intel_g33_driver , &g33_gtt_driver },
1681 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1682 &intel_g33_driver , &g33_gtt_driver },
1683 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1684 &intel_g33_driver , &g33_gtt_driver },
1685 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1686 &intel_g33_driver , &pineview_gtt_driver },
1687 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1688 &intel_g33_driver , &pineview_gtt_driver },
1689 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1690 &intel_i965_driver , &g4x_gtt_driver },
1691 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1692 &intel_i965_driver , &g4x_gtt_driver },
1693 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1694 &intel_i965_driver , &g4x_gtt_driver },
1695 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1696 &intel_i965_driver , &g4x_gtt_driver },
1697 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1698 &intel_i965_driver , &g4x_gtt_driver },
1699 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1700 &intel_i965_driver , &g4x_gtt_driver },
1701 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1702 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1703 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1704 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1705 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1706 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1707 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1708 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1709 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1710 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1711 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1712 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1713 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1714 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1715 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1716 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1717 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1718 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1719 { 0, NULL, NULL }
1720 };
1721
1722 static int find_gmch(u16 device)
1723 {
1724 struct pci_dev *gmch_device;
1725
1726 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1727 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1728 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1729 device, gmch_device);
1730 }
1731
1732 if (!gmch_device)
1733 return 0;
1734
1735 intel_private.pcidev = gmch_device;
1736 return 1;
1737 }
1738
1739 int intel_gmch_probe(struct pci_dev *pdev,
1740 struct agp_bridge_data *bridge)
1741 {
1742 int i, mask;
1743 bridge->driver = NULL;
1744
1745 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1746 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1747 bridge->driver =
1748 intel_gtt_chipsets[i].gmch_driver;
1749 intel_private.driver =
1750 intel_gtt_chipsets[i].gtt_driver;
1751 break;
1752 }
1753 }
1754
1755 if (!bridge->driver)
1756 return 0;
1757
1758 bridge->dev_private_data = &intel_private;
1759 bridge->dev = pdev;
1760
1761 intel_private.bridge_dev = pci_dev_get(pdev);
1762
1763 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1764
1765 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1766 mask = 40;
1767 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1768 mask = 36;
1769 else
1770 mask = 32;
1771
1772 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1773 dev_err(&intel_private.pcidev->dev,
1774 "set gfx device dma mask %d-bit failed!\n", mask);
1775 else
1776 pci_set_consistent_dma_mask(intel_private.pcidev,
1777 DMA_BIT_MASK(mask));
1778
1779 if (bridge->driver == &intel_810_driver)
1780 return 1;
1781
1782 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
1783
1784 return 1;
1785 }
1786 EXPORT_SYMBOL(intel_gmch_probe);
1787
1788 void intel_gmch_remove(struct pci_dev *pdev)
1789 {
1790 if (intel_private.pcidev)
1791 pci_dev_put(intel_private.pcidev);
1792 if (intel_private.bridge_dev)
1793 pci_dev_put(intel_private.bridge_dev);
1794 }
1795 EXPORT_SYMBOL(intel_gmch_remove);
1796
1797 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1798 MODULE_LICENSE("GPL and additional rights");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree