arch/arm/mach-ux500/cpu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/io.h>
  10 #include <linux/clk.h>
  11
  12 #include <asm/cacheflush.h>
  13 #include <asm/hardware/cache-l2x0.h>
  14 #include <asm/hardware/gic.h>
  15 #include <asm/mach/map.h>
  16 #include <asm/localtimer.h>
  17
  18 #include <plat/mtu.h>
  19 #include <mach/hardware.h>
  20 #include <mach/setup.h>
  21 #include <mach/devices.h>
  22
  23 #include "clock.h"
  24
  25 static struct map_desc ux500_io_desc[] __initdata = {
  26         __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
  27         __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
  28
  29         __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
  30         __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
  31         __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
  32         __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K),
  33         __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K),
  34
  35         __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
  36         __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
  37         __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
  38         __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
  39         __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
  40
  41         __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
  42         __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
  43
  44         __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
  45 };
  46
  47 void __init ux500_map_io(void)
  48 {
  49         iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
  50 }
  51
  52 void __init ux500_init_irq(void)
  53 {
  54         gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
  55         gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
  56
  57         /*
  58          * Init clocks here so that they are available for system timer
  59          * initialization.
  60          */
  61         clk_init();
  62 }
  63
  64 #ifdef CONFIG_CACHE_L2X0
  65 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
  66 {
  67         /* wait for the operation to complete */
  68         while (readl_relaxed(reg) & mask)
  69                 ;
  70 }
  71
  72 static inline void ux500_cache_sync(void)
  73 {
  74         void __iomem *base = __io_address(UX500_L2CC_BASE);
  75         writel_relaxed(0, base + L2X0_CACHE_SYNC);
  76         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
  77 }
  78
  79 /*
  80  * The L2 cache cannot be turned off in the non-secure world.
  81  * Dummy until a secure service is in place.
  82  */
  83 static void ux500_l2x0_disable(void)
  84 {
  85 }
  86
  87 /*
  88  * This is only called when doing a kexec, just after turning off the L2
  89  * and L1 cache, and it is surrounded by a spinlock in the generic version.
  90  * However, we're not really turning off the L2 cache right now and the
  91  * PL310 does not support exclusive accesses (used to implement the spinlock).
  92  * So, the invalidation needs to be done without the spinlock.
  93  */
  94 static void ux500_l2x0_inv_all(void)
  95 {
  96         void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE);
  97         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
  98
  99         /* invalidate all ways */
 100         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
 101         ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
 102         ux500_cache_sync();
 103 }
 104
 105 static int ux500_l2x0_init(void)
 106 {
 107         void __iomem *l2x0_base;
 108
 109         l2x0_base = __io_address(UX500_L2CC_BASE);
 110
 111         /* 64KB way size, 8 way associativity, force WA */
 112         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 113
 114         /* Override invalidate function */
 115         outer_cache.disable = ux500_l2x0_disable;
 116         outer_cache.inv_all = ux500_l2x0_inv_all;
 117
 118         return 0;
 119 }
 120 early_initcall(ux500_l2x0_init);
 121 #endif
 122
 123 static void __init ux500_timer_init(void)
 124 {
 125 #ifdef CONFIG_LOCAL_TIMERS
 126         /* Setup the local timer base */
 127         twd_base = __io_address(UX500_TWD_BASE);
 128 #endif
 129         /* Setup the MTU base */
 130         if (cpu_is_u8500ed())
 131                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
 132         else
 133                 mtu_base = __io_address(UX500_MTU0_BASE);
 134
 135         nmdk_timer_init();
 136 }
 137
 138 struct sys_timer ux500_timer = {
 139         .init   = ux500_timer_init,
 140 };