drivers/staging/tidspbridge/core/_tiomap.h

   1 /*
   2  * _tiomap.h
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Definitions and types private to this Bridge driver.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #ifndef _TIOMAP_
  20 #define _TIOMAP_
  21
  22 #include <plat/powerdomain.h>
  23 #include <plat/clockdomain.h>
  24 #include <mach-omap2/prm-regbits-34xx.h>
  25 #include <mach-omap2/cm-regbits-34xx.h>
  26 #include <plat/iommu.h>
  27 #include <plat/iovmm.h>
  28 #include <dspbridge/devdefs.h>
  29 #include <dspbridge/dspioctl.h> /* for bridge_ioctl_extproc defn */
  30 #include <dspbridge/sync.h>
  31 #include <dspbridge/clk.h>
  32
  33 struct map_l4_peripheral {
  34         u32 phys_addr;
  35         u32 dsp_virt_addr;
  36 };
  37
  38 #define ARM_MAILBOX_START               0xfffcf000
  39 #define ARM_MAILBOX_LENGTH              0x800
  40
  41 /* New Registers in OMAP3.1 */
  42
  43 #define TESTBLOCK_ID_START              0xfffed400
  44 #define TESTBLOCK_ID_LENGTH             0xff
  45
  46 /* ID Returned by OMAP1510 */
  47 #define TBC_ID_VALUE                    0xB47002F
  48
  49 #define SPACE_LENGTH                    0x2000
  50 #define API_CLKM_DPLL_DMA               0xfffec000
  51 #define ARM_INTERRUPT_OFFSET            0xb00
  52
  53 #define BIOS24XX
  54
  55 #define L4_PERIPHERAL_NULL          0x0
  56 #define DSPVA_PERIPHERAL_NULL       0x0
  57
  58 #define MAX_LOCK_TLB_ENTRIES 15
  59
  60 #define L4_PERIPHERAL_PRM        0x48306000     /*PRM L4 Peripheral */
  61 #define DSPVA_PERIPHERAL_PRM     0x1181e000
  62 #define L4_PERIPHERAL_SCM        0x48002000     /*SCM L4 Peripheral */
  63 #define DSPVA_PERIPHERAL_SCM     0x1181f000
  64 #define L4_PERIPHERAL_MMU        0x5D000000     /*MMU L4 Peripheral */
  65 #define DSPVA_PERIPHERAL_MMU     0x11820000
  66 #define L4_PERIPHERAL_CM        0x48004000      /* Core L4, Clock Management */
  67 #define DSPVA_PERIPHERAL_CM     0x1181c000
  68 #define L4_PERIPHERAL_PER        0x48005000     /*  PER */
  69 #define DSPVA_PERIPHERAL_PER     0x1181d000
  70
  71 #define L4_PERIPHERAL_GPIO1       0x48310000
  72 #define DSPVA_PERIPHERAL_GPIO1    0x11809000
  73 #define L4_PERIPHERAL_GPIO2       0x49050000
  74 #define DSPVA_PERIPHERAL_GPIO2    0x1180a000
  75 #define L4_PERIPHERAL_GPIO3       0x49052000
  76 #define DSPVA_PERIPHERAL_GPIO3    0x1180b000
  77 #define L4_PERIPHERAL_GPIO4       0x49054000
  78 #define DSPVA_PERIPHERAL_GPIO4    0x1180c000
  79 #define L4_PERIPHERAL_GPIO5       0x49056000
  80 #define DSPVA_PERIPHERAL_GPIO5    0x1180d000
  81
  82 #define L4_PERIPHERAL_IVA2WDT      0x49030000
  83 #define DSPVA_PERIPHERAL_IVA2WDT   0x1180e000
  84
  85 #define L4_PERIPHERAL_DISPLAY     0x48050000
  86 #define DSPVA_PERIPHERAL_DISPLAY  0x1180f000
  87
  88 #define L4_PERIPHERAL_SSI         0x48058000
  89 #define DSPVA_PERIPHERAL_SSI      0x11804000
  90 #define L4_PERIPHERAL_GDD         0x48059000
  91 #define DSPVA_PERIPHERAL_GDD      0x11805000
  92 #define L4_PERIPHERAL_SS1         0x4805a000
  93 #define DSPVA_PERIPHERAL_SS1      0x11806000
  94 #define L4_PERIPHERAL_SS2         0x4805b000
  95 #define DSPVA_PERIPHERAL_SS2      0x11807000
  96
  97 #define L4_PERIPHERAL_CAMERA      0x480BC000
  98 #define DSPVA_PERIPHERAL_CAMERA   0x11819000
  99
 100 #define L4_PERIPHERAL_SDMA        0x48056000
 101 #define DSPVA_PERIPHERAL_SDMA     0x11810000    /* 0x1181d000 conflict w/ PER */
 102
 103 #define L4_PERIPHERAL_UART1             0x4806a000
 104 #define DSPVA_PERIPHERAL_UART1          0x11811000
 105 #define L4_PERIPHERAL_UART2             0x4806c000
 106 #define DSPVA_PERIPHERAL_UART2          0x11812000
 107 #define L4_PERIPHERAL_UART3             0x49020000
 108 #define DSPVA_PERIPHERAL_UART3    0x11813000
 109
 110 #define L4_PERIPHERAL_MCBSP1      0x48074000
 111 #define DSPVA_PERIPHERAL_MCBSP1   0x11814000
 112 #define L4_PERIPHERAL_MCBSP2      0x49022000
 113 #define DSPVA_PERIPHERAL_MCBSP2   0x11815000
 114 #define L4_PERIPHERAL_MCBSP3      0x49024000
 115 #define DSPVA_PERIPHERAL_MCBSP3   0x11816000
 116 #define L4_PERIPHERAL_MCBSP4      0x49026000
 117 #define DSPVA_PERIPHERAL_MCBSP4   0x11817000
 118 #define L4_PERIPHERAL_MCBSP5      0x48096000
 119 #define DSPVA_PERIPHERAL_MCBSP5   0x11818000
 120
 121 #define L4_PERIPHERAL_GPTIMER5    0x49038000
 122 #define DSPVA_PERIPHERAL_GPTIMER5 0x11800000
 123 #define L4_PERIPHERAL_GPTIMER6    0x4903a000
 124 #define DSPVA_PERIPHERAL_GPTIMER6 0x11801000
 125 #define L4_PERIPHERAL_GPTIMER7    0x4903c000
 126 #define DSPVA_PERIPHERAL_GPTIMER7 0x11802000
 127 #define L4_PERIPHERAL_GPTIMER8    0x4903e000
 128 #define DSPVA_PERIPHERAL_GPTIMER8 0x11803000
 129
 130 #define L4_PERIPHERAL_SPI1      0x48098000
 131 #define DSPVA_PERIPHERAL_SPI1   0x1181a000
 132 #define L4_PERIPHERAL_SPI2      0x4809a000
 133 #define DSPVA_PERIPHERAL_SPI2   0x1181b000
 134
 135 #define L4_PERIPHERAL_MBOX        0x48094000
 136 #define DSPVA_PERIPHERAL_MBOX     0x11808000
 137
 138 #define PM_GRPSEL_BASE                  0x48307000
 139 #define DSPVA_GRPSEL_BASE               0x11821000
 140
 141 #define L4_PERIPHERAL_SIDETONE_MCBSP2        0x49028000
 142 #define DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000
 143 #define L4_PERIPHERAL_SIDETONE_MCBSP3        0x4902a000
 144 #define DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000
 145
 146 /* define a static array with L4 mappings */
 147 static const struct map_l4_peripheral l4_peripheral_table[] = {
 148         {L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX},
 149         {L4_PERIPHERAL_SCM, DSPVA_PERIPHERAL_SCM},
 150         {L4_PERIPHERAL_MMU, DSPVA_PERIPHERAL_MMU},
 151         {L4_PERIPHERAL_GPTIMER5, DSPVA_PERIPHERAL_GPTIMER5},
 152         {L4_PERIPHERAL_GPTIMER6, DSPVA_PERIPHERAL_GPTIMER6},
 153         {L4_PERIPHERAL_GPTIMER7, DSPVA_PERIPHERAL_GPTIMER7},
 154         {L4_PERIPHERAL_GPTIMER8, DSPVA_PERIPHERAL_GPTIMER8},
 155         {L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1},
 156         {L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2},
 157         {L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3},
 158         {L4_PERIPHERAL_GPIO4, DSPVA_PERIPHERAL_GPIO4},
 159         {L4_PERIPHERAL_GPIO5, DSPVA_PERIPHERAL_GPIO5},
 160         {L4_PERIPHERAL_IVA2WDT, DSPVA_PERIPHERAL_IVA2WDT},
 161         {L4_PERIPHERAL_DISPLAY, DSPVA_PERIPHERAL_DISPLAY},
 162         {L4_PERIPHERAL_SSI, DSPVA_PERIPHERAL_SSI},
 163         {L4_PERIPHERAL_GDD, DSPVA_PERIPHERAL_GDD},
 164         {L4_PERIPHERAL_SS1, DSPVA_PERIPHERAL_SS1},
 165         {L4_PERIPHERAL_SS2, DSPVA_PERIPHERAL_SS2},
 166         {L4_PERIPHERAL_UART1, DSPVA_PERIPHERAL_UART1},
 167         {L4_PERIPHERAL_UART2, DSPVA_PERIPHERAL_UART2},
 168         {L4_PERIPHERAL_UART3, DSPVA_PERIPHERAL_UART3},
 169         {L4_PERIPHERAL_MCBSP1, DSPVA_PERIPHERAL_MCBSP1},
 170         {L4_PERIPHERAL_MCBSP2, DSPVA_PERIPHERAL_MCBSP2},
 171         {L4_PERIPHERAL_MCBSP3, DSPVA_PERIPHERAL_MCBSP3},
 172         {L4_PERIPHERAL_MCBSP4, DSPVA_PERIPHERAL_MCBSP4},
 173         {L4_PERIPHERAL_MCBSP5, DSPVA_PERIPHERAL_MCBSP5},
 174         {L4_PERIPHERAL_CAMERA, DSPVA_PERIPHERAL_CAMERA},
 175         {L4_PERIPHERAL_SPI1, DSPVA_PERIPHERAL_SPI1},
 176         {L4_PERIPHERAL_SPI2, DSPVA_PERIPHERAL_SPI2},
 177         {L4_PERIPHERAL_PRM, DSPVA_PERIPHERAL_PRM},
 178         {L4_PERIPHERAL_CM, DSPVA_PERIPHERAL_CM},
 179         {L4_PERIPHERAL_PER, DSPVA_PERIPHERAL_PER},
 180         {PM_GRPSEL_BASE, DSPVA_GRPSEL_BASE},
 181         {L4_PERIPHERAL_SIDETONE_MCBSP2, DSPVA_PERIPHERAL_SIDETONE_MCBSP2},
 182         {L4_PERIPHERAL_SIDETONE_MCBSP3, DSPVA_PERIPHERAL_SIDETONE_MCBSP3},
 183         {L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL}
 184 };
 185
 186 /*
 187  *   15         10                  0
 188  *   ---------------------------------
 189  *  |0|0|1|0|0|0|c|c|c|i|i|i|i|i|i|i|
 190  *  ---------------------------------
 191  *  |  (class)  | (module specific) |
 192  *
 193  *  where  c -> Externel Clock Command: Clk & Autoidle Disable/Enable
 194  *  i -> External Clock ID Timers 5,6,7,8, McBSP1,2 and WDT3
 195  */
 196
 197 /* MBX_PM_CLK_IDMASK: DSP External clock id mask. */
 198 #define MBX_PM_CLK_IDMASK   0x7F
 199
 200 /* MBX_PM_CLK_CMDSHIFT: DSP External clock command shift. */
 201 #define MBX_PM_CLK_CMDSHIFT 7
 202
 203 /* MBX_PM_CLK_CMDMASK: DSP External clock command mask. */
 204 #define MBX_PM_CLK_CMDMASK 7
 205
 206 /* MBX_PM_MAX_RESOURCES: CORE 1 Clock resources. */
 207 #define MBX_CORE1_RESOURCES 7
 208
 209 /* MBX_PM_MAX_RESOURCES: CORE 2 Clock Resources. */
 210 #define MBX_CORE2_RESOURCES 1
 211
 212 /* MBX_PM_MAX_RESOURCES: TOTAL Clock Reosurces. */
 213 #define MBX_PM_MAX_RESOURCES 11
 214
 215 /*  Power Management Commands */
 216 #define BPWR_DISABLE_CLOCK      0
 217 #define BPWR_ENABLE_CLOCK       1
 218
 219 /* OMAP242x specific resources */
 220 enum bpwr_ext_clock_id {
 221         BPWR_GP_TIMER5 = 0x10,
 222         BPWR_GP_TIMER6,
 223         BPWR_GP_TIMER7,
 224         BPWR_GP_TIMER8,
 225         BPWR_WD_TIMER3,
 226         BPWR_MCBSP1,
 227         BPWR_MCBSP2,
 228         BPWR_MCBSP3,
 229         BPWR_MCBSP4,
 230         BPWR_MCBSP5,
 231         BPWR_SSI = 0x20
 232 };
 233
 234 static const u32 bpwr_clkid[] = {
 235         (u32) BPWR_GP_TIMER5,
 236         (u32) BPWR_GP_TIMER6,
 237         (u32) BPWR_GP_TIMER7,
 238         (u32) BPWR_GP_TIMER8,
 239         (u32) BPWR_WD_TIMER3,
 240         (u32) BPWR_MCBSP1,
 241         (u32) BPWR_MCBSP2,
 242         (u32) BPWR_MCBSP3,
 243         (u32) BPWR_MCBSP4,
 244         (u32) BPWR_MCBSP5,
 245         (u32) BPWR_SSI
 246 };
 247
 248 struct bpwr_clk_t {
 249         u32 clk_id;
 250         enum dsp_clk_id clk;
 251 };
 252
 253 static const struct bpwr_clk_t bpwr_clks[] = {
 254         {(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5},
 255         {(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6},
 256         {(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7},
 257         {(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8},
 258         {(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3},
 259         {(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1},
 260         {(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2},
 261         {(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3},
 262         {(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4},
 263         {(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5},
 264         {(u32) BPWR_SSI, DSP_CLK_SSI}
 265 };
 266
 267 /* Interrupt Register Offsets */
 268 #define INTH_IT_REG_OFFSET              0x00    /* Interrupt register offset */
 269 #define INTH_MASK_IT_REG_OFFSET         0x04    /* Mask Interrupt reg offset */
 270
 271 #define   DSP_MAILBOX1_INT              10
 272 /*
 273  *  Bit definition of  Interrupt  Level  Registers
 274  */
 275
 276 /* Mail Box defines */
 277 #define MB_ARM2DSP1_REG_OFFSET          0x00
 278
 279 #define MB_ARM2DSP1B_REG_OFFSET         0x04
 280
 281 #define MB_DSP2ARM1B_REG_OFFSET         0x0C
 282
 283 #define MB_ARM2DSP1_FLAG_REG_OFFSET     0x18
 284
 285 #define MB_ARM2DSP_FLAG                 0x0001
 286
 287 #define MBOX_ARM2DSP HW_MBOX_ID0
 288 #define MBOX_DSP2ARM HW_MBOX_ID1
 289 #define MBOX_ARM HW_MBOX_U0_ARM
 290 #define MBOX_DSP HW_MBOX_U1_DSP1
 291
 292 #define ENABLE                          true
 293 #define DISABLE                         false
 294
 295 #define HIGH_LEVEL                      true
 296 #define LOW_LEVEL                       false
 297
 298 /* Macro's */
 299 #define CLEAR_BIT(reg, mask)             (reg &= ~mask)
 300 #define SET_BIT(reg, mask)               (reg |= mask)
 301
 302 #define SET_GROUP_BITS16(reg, position, width, value) \
 303         do {\
 304                 reg &= ~((0xFFFF >> (16 - (width))) << (position)) ; \
 305                 reg |= ((value & (0xFFFF >> (16 - (width)))) << (position)); \
 306         } while (0);
 307
 308 #define CLEAR_BIT_INDEX(reg, index)   (reg &= ~(1 << (index)))
 309
 310 struct shm_segs {
 311         u32 seg0_da;
 312         u32 seg0_pa;
 313         u32 seg0_va;
 314         u32 seg0_size;
 315         u32 seg1_da;
 316         u32 seg1_pa;
 317         u32 seg1_va;
 318         u32 seg1_size;
 319 };
 320
 321
 322 /* This Bridge driver's device context: */
 323 struct bridge_dev_context {
 324         struct dev_object *hdev_obj;    /* Handle to Bridge device object. */
 325         u32 dw_dsp_base_addr;   /* Arm's API to DSP virt base addr */
 326         /*
 327          * DSP External memory prog address as seen virtually by the OS on
 328          * the host side.
 329          */
 330         u32 dw_dsp_ext_base_addr;       /* See the comment above */
 331         u32 dw_api_reg_base;    /* API mem map'd registers */
 332         u32 dw_api_clk_base;    /* CLK Registers */
 333         u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */
 334         u32 dw_public_rhea;     /* Pub Rhea */
 335         u32 dw_int_addr;        /* MB INTR reg */
 336         u32 dw_tc_endianism;    /* TC Endianism register */
 337         u32 dw_test_base;       /* DSP MMU Mapped registers */
 338         u32 dw_self_loop;       /* Pointer to the selfloop */
 339         u32 dw_dsp_start_add;   /* API Boot vector */
 340         u32 dw_internal_size;   /* Internal memory size */
 341
 342         struct omap_mbox *mbox;         /* Mail box handle */
 343         struct iommu *dsp_mmu;      /* iommu for iva2 handler */
 344         struct shm_segs sh_s;
 345         struct cfg_hostres *resources;  /* Host Resources */
 346
 347         /*
 348          * Processor specific info is set when prog loaded and read from DCD.
 349          * [See bridge_dev_ctrl()]  PROC info contains DSP-MMU TLB entries.
 350          */
 351         /* DMMU TLB entries */
 352         struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];
 353         u32 dw_brd_state;       /* Last known board state. */
 354
 355         /* TC Settings */
 356         bool tc_word_swap_on;   /* Traffic Controller Word Swap */
 357         u32 dsp_per_clks;
 358 };
 359
 360 /*
 361  * If dsp_debug is true, do not branch to the DSP entry
 362  * point and wait for DSP to boot.
 363  */
 364 extern s32 dsp_debug;
 365
 366 /*
 367  *  ======== sm_interrupt_dsp ========
 368  *  Purpose:
 369  *      Set interrupt value & send an interrupt to the DSP processor(s).
 370  *      This is typicaly used when mailbox interrupt mechanisms allow data
 371  *      to be associated with interrupt such as for OMAP's CMD/DATA regs.
 372  *  Parameters:
 373  *      dev_context:    Handle to Bridge driver defined device info.
 374  *      mb_val:         Value associated with interrupt(e.g. mailbox value).
 375  *  Returns:
 376  *      0:        Interrupt sent;
 377  *      else:           Unable to send interrupt.
 378  *  Requires:
 379  *  Ensures:
 380  */
 381 int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val);
 382
 383 /**
 384  * user_to_dsp_map() - maps user to dsp virtual address
 385  * @mmu:        Pointer to iommu handle.
 386  * @uva:                Virtual user space address.
 387  * @da          DSP address
 388  * @size                Buffer size to map.
 389  * @usr_pgs     struct page array pointer where the user pages will be stored
 390  *
 391  * This function maps a user space buffer into DSP virtual address.
 392  *
 393  */
 394 u32 user_to_dsp_map(struct iommu *mmu, u32 uva, u32 da, u32 size,
 395                                                 struct page **usr_pgs);
 396
 397 /**
 398  * user_to_dsp_unmap() - unmaps DSP virtual buffer.
 399  * @mmu:        Pointer to iommu handle.
 400  * @da          DSP address
 401  *
 402  * This function unmaps a user space buffer into DSP virtual address.
 403  *
 404  */
 405 int user_to_dsp_unmap(struct iommu *mmu, u32 da);
 406
 407 #endif /* _TIOMAP_ */