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ARM: 5726/1: at91/USB: at91sam9g45 series USB host integration
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-at91 / at91sam9g45_devices.c
blob003f4f91fa526f0df4e431092ffb51869619e3eb
1 /*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <linux/fb.h>
20 #include <video/atmel_lcdc.h>
21
22 #include <mach/board.h>
23 #include <mach/gpio.h>
24 #include <mach/at91sam9g45.h>
25 #include <mach/at91sam9g45_matrix.h>
26 #include <mach/at91sam9_smc.h>
27 #include <mach/at_hdmac.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33 * HDMAC - AHB DMA Controller
34 * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
37 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
38
39 static struct at_dma_platform_data atdma_pdata = {
40 .nr_channels = 8,
41 };
42
43 static struct resource hdmac_resources[] = {
44 [0] = {
45 .start = AT91_BASE_SYS + AT91_DMA,
46 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
47 .flags = IORESOURCE_MEM,
48 },
49 [2] = {
50 .start = AT91SAM9G45_ID_DMA,
51 .end = AT91SAM9G45_ID_DMA,
52 .flags = IORESOURCE_IRQ,
53 },
54 };
55
56 static struct platform_device at_hdmac_device = {
57 .name = "at_hdmac",
58 .id = -1,
59 .dev = {
60 .dma_mask = &hdmac_dmamask,
61 .coherent_dma_mask = DMA_BIT_MASK(32),
62 .platform_data = &atdma_pdata,
63 },
64 .resource = hdmac_resources,
65 .num_resources = ARRAY_SIZE(hdmac_resources),
66 };
67
68 void __init at91_add_device_hdmac(void)
69 {
70 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
71 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
72 platform_device_register(&at_hdmac_device);
73 }
74 #else
75 void __init at91_add_device_hdmac(void) {}
76 #endif
77
78
79 /* --------------------------------------------------------------------
80 * USB Host (OHCI)
81 * -------------------------------------------------------------------- */
82
83 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
84 static u64 ohci_dmamask = DMA_BIT_MASK(32);
85 static struct at91_usbh_data usbh_ohci_data;
86
87 static struct resource usbh_ohci_resources[] = {
88 [0] = {
89 .start = AT91SAM9G45_OHCI_BASE,
90 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = AT91SAM9G45_ID_UHPHS,
95 .end = AT91SAM9G45_ID_UHPHS,
96 .flags = IORESOURCE_IRQ,
97 },
98 };
99
100 static struct platform_device at91_usbh_ohci_device = {
101 .name = "at91_ohci",
102 .id = -1,
103 .dev = {
104 .dma_mask = &ohci_dmamask,
105 .coherent_dma_mask = DMA_BIT_MASK(32),
106 .platform_data = &usbh_ohci_data,
107 },
108 .resource = usbh_ohci_resources,
109 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
110 };
111
112 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
113 {
114 int i;
115
116 if (!data)
117 return;
118
119 /* Enable VBus control for UHP ports */
120 for (i = 0; i < data->ports; i++) {
121 if (data->vbus_pin[i])
122 at91_set_gpio_output(data->vbus_pin[i], 0);
123 }
124
125 usbh_ohci_data = *data;
126 platform_device_register(&at91_usbh_ohci_device);
127 }
128 #else
129 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
130 #endif
131
132
133 /* --------------------------------------------------------------------
134 * USB Host HS (EHCI)
135 * Needs an OHCI host for low and full speed management
136 * -------------------------------------------------------------------- */
137
138 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
139 static u64 ehci_dmamask = DMA_BIT_MASK(32);
140 static struct at91_usbh_data usbh_ehci_data;
141
142 static struct resource usbh_ehci_resources[] = {
143 [0] = {
144 .start = AT91SAM9G45_EHCI_BASE,
145 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 [1] = {
149 .start = AT91SAM9G45_ID_UHPHS,
150 .end = AT91SAM9G45_ID_UHPHS,
151 .flags = IORESOURCE_IRQ,
152 },
153 };
154
155 static struct platform_device at91_usbh_ehci_device = {
156 .name = "atmel-ehci",
157 .id = -1,
158 .dev = {
159 .dma_mask = &ehci_dmamask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 .platform_data = &usbh_ehci_data,
162 },
163 .resource = usbh_ehci_resources,
164 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
165 };
166
167 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
168 {
169 int i;
170
171 if (!data)
172 return;
173
174 /* Enable VBus control for UHP ports */
175 for (i = 0; i < data->ports; i++) {
176 if (data->vbus_pin[i])
177 at91_set_gpio_output(data->vbus_pin[i], 0);
178 }
179
180 usbh_ehci_data = *data;
181 at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
182 platform_device_register(&at91_usbh_ehci_device);
183 }
184 #else
185 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
186 #endif
187
188
189 /* --------------------------------------------------------------------
190 * USB HS Device (Gadget)
191 * -------------------------------------------------------------------- */
192
193 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
194 static struct resource usba_udc_resources[] = {
195 [0] = {
196 .start = AT91SAM9G45_UDPHS_FIFO,
197 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
198 .flags = IORESOURCE_MEM,
199 },
200 [1] = {
201 .start = AT91SAM9G45_BASE_UDPHS,
202 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
203 .flags = IORESOURCE_MEM,
204 },
205 [2] = {
206 .start = AT91SAM9G45_ID_UDPHS,
207 .end = AT91SAM9G45_ID_UDPHS,
208 .flags = IORESOURCE_IRQ,
209 },
210 };
211
212 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
213 [idx] = { \
214 .name = nam, \
215 .index = idx, \
216 .fifo_size = maxpkt, \
217 .nr_banks = maxbk, \
218 .can_dma = dma, \
219 .can_isoc = isoc, \
220 }
221
222 static struct usba_ep_data usba_udc_ep[] __initdata = {
223 EP("ep0", 0, 64, 1, 0, 0),
224 EP("ep1", 1, 1024, 2, 1, 1),
225 EP("ep2", 2, 1024, 2, 1, 1),
226 EP("ep3", 3, 1024, 3, 1, 0),
227 EP("ep4", 4, 1024, 3, 1, 0),
228 EP("ep5", 5, 1024, 3, 1, 1),
229 EP("ep6", 6, 1024, 3, 1, 1),
230 };
231
232 #undef EP
233
234 /*
235 * pdata doesn't have room for any endpoints, so we need to
236 * append room for the ones we need right after it.
237 */
238 static struct {
239 struct usba_platform_data pdata;
240 struct usba_ep_data ep[7];
241 } usba_udc_data;
242
243 static struct platform_device at91_usba_udc_device = {
244 .name = "atmel_usba_udc",
245 .id = -1,
246 .dev = {
247 .platform_data = &usba_udc_data.pdata,
248 },
249 .resource = usba_udc_resources,
250 .num_resources = ARRAY_SIZE(usba_udc_resources),
251 };
252
253 void __init at91_add_device_usba(struct usba_platform_data *data)
254 {
255 usba_udc_data.pdata.vbus_pin = -EINVAL;
256 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
257 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
258
259 if (data && data->vbus_pin > 0) {
260 at91_set_gpio_input(data->vbus_pin, 0);
261 at91_set_deglitch(data->vbus_pin, 1);
262 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
263 }
264
265 /* Pullup pin is handled internally by USB device peripheral */
266
267 /* Clocks */
268 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
269 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
270
271 platform_device_register(&at91_usba_udc_device);
272 }
273 #else
274 void __init at91_add_device_usba(struct usba_platform_data *data) {}
275 #endif
276
277
278 /* --------------------------------------------------------------------
279 * Ethernet
280 * -------------------------------------------------------------------- */
281
282 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
283 static u64 eth_dmamask = DMA_BIT_MASK(32);
284 static struct at91_eth_data eth_data;
285
286 static struct resource eth_resources[] = {
287 [0] = {
288 .start = AT91SAM9G45_BASE_EMAC,
289 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
290 .flags = IORESOURCE_MEM,
291 },
292 [1] = {
293 .start = AT91SAM9G45_ID_EMAC,
294 .end = AT91SAM9G45_ID_EMAC,
295 .flags = IORESOURCE_IRQ,
296 },
297 };
298
299 static struct platform_device at91sam9g45_eth_device = {
300 .name = "macb",
301 .id = -1,
302 .dev = {
303 .dma_mask = &eth_dmamask,
304 .coherent_dma_mask = DMA_BIT_MASK(32),
305 .platform_data = &eth_data,
306 },
307 .resource = eth_resources,
308 .num_resources = ARRAY_SIZE(eth_resources),
309 };
310
311 void __init at91_add_device_eth(struct at91_eth_data *data)
312 {
313 if (!data)
314 return;
315
316 if (data->phy_irq_pin) {
317 at91_set_gpio_input(data->phy_irq_pin, 0);
318 at91_set_deglitch(data->phy_irq_pin, 1);
319 }
320
321 /* Pins used for MII and RMII */
322 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
323 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
324 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
325 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
326 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
327 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
328 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
329 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
330 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
331 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
332
333 if (!data->is_rmii) {
334 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
335 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
336 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
337 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
338 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
339 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
340 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
341 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
342 }
343
344 eth_data = *data;
345 platform_device_register(&at91sam9g45_eth_device);
346 }
347 #else
348 void __init at91_add_device_eth(struct at91_eth_data *data) {}
349 #endif
350
351
352 /* --------------------------------------------------------------------
353 * NAND / SmartMedia
354 * -------------------------------------------------------------------- */
355
356 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
357 static struct atmel_nand_data nand_data;
358
359 #define NAND_BASE AT91_CHIPSELECT_3
360
361 static struct resource nand_resources[] = {
362 [0] = {
363 .start = NAND_BASE,
364 .end = NAND_BASE + SZ_256M - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 [1] = {
368 .start = AT91_BASE_SYS + AT91_ECC,
369 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
370 .flags = IORESOURCE_MEM,
371 }
372 };
373
374 static struct platform_device at91sam9g45_nand_device = {
375 .name = "atmel_nand",
376 .id = -1,
377 .dev = {
378 .platform_data = &nand_data,
379 },
380 .resource = nand_resources,
381 .num_resources = ARRAY_SIZE(nand_resources),
382 };
383
384 void __init at91_add_device_nand(struct atmel_nand_data *data)
385 {
386 unsigned long csa;
387
388 if (!data)
389 return;
390
391 csa = at91_sys_read(AT91_MATRIX_EBICSA);
392 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
393
394 /* enable pin */
395 if (data->enable_pin)
396 at91_set_gpio_output(data->enable_pin, 1);
397
398 /* ready/busy pin */
399 if (data->rdy_pin)
400 at91_set_gpio_input(data->rdy_pin, 1);
401
402 /* card detect pin */
403 if (data->det_pin)
404 at91_set_gpio_input(data->det_pin, 1);
405
406 nand_data = *data;
407 platform_device_register(&at91sam9g45_nand_device);
408 }
409 #else
410 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
411 #endif
412
413
414 /* --------------------------------------------------------------------
415 * TWI (i2c)
416 * -------------------------------------------------------------------- */
417
418 /*
419 * Prefer the GPIO code since the TWI controller isn't robust
420 * (gets overruns and underruns under load) and can only issue
421 * repeated STARTs in one scenario (the driver doesn't yet handle them).
422 */
423 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
424 static struct i2c_gpio_platform_data pdata_i2c0 = {
425 .sda_pin = AT91_PIN_PA20,
426 .sda_is_open_drain = 1,
427 .scl_pin = AT91_PIN_PA21,
428 .scl_is_open_drain = 1,
429 .udelay = 2, /* ~100 kHz */
430 };
431
432 static struct platform_device at91sam9g45_twi0_device = {
433 .name = "i2c-gpio",
434 .id = 0,
435 .dev.platform_data = &pdata_i2c0,
436 };
437
438 static struct i2c_gpio_platform_data pdata_i2c1 = {
439 .sda_pin = AT91_PIN_PB10,
440 .sda_is_open_drain = 1,
441 .scl_pin = AT91_PIN_PB11,
442 .scl_is_open_drain = 1,
443 .udelay = 2, /* ~100 kHz */
444 };
445
446 static struct platform_device at91sam9g45_twi1_device = {
447 .name = "i2c-gpio",
448 .id = 1,
449 .dev.platform_data = &pdata_i2c1,
450 };
451
452 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
453 {
454 i2c_register_board_info(i2c_id, devices, nr_devices);
455
456 if (i2c_id == 0) {
457 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
458 at91_set_multi_drive(AT91_PIN_PA20, 1);
459
460 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
461 at91_set_multi_drive(AT91_PIN_PA21, 1);
462
463 platform_device_register(&at91sam9g45_twi0_device);
464 } else {
465 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
466 at91_set_multi_drive(AT91_PIN_PB10, 1);
467
468 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
469 at91_set_multi_drive(AT91_PIN_PB11, 1);
470
471 platform_device_register(&at91sam9g45_twi1_device);
472 }
473 }
474
475 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
476 static struct resource twi0_resources[] = {
477 [0] = {
478 .start = AT91SAM9G45_BASE_TWI0,
479 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
480 .flags = IORESOURCE_MEM,
481 },
482 [1] = {
483 .start = AT91SAM9G45_ID_TWI0,
484 .end = AT91SAM9G45_ID_TWI0,
485 .flags = IORESOURCE_IRQ,
486 },
487 };
488
489 static struct platform_device at91sam9g45_twi0_device = {
490 .name = "at91_i2c",
491 .id = 0,
492 .resource = twi0_resources,
493 .num_resources = ARRAY_SIZE(twi0_resources),
494 };
495
496 static struct resource twi1_resources[] = {
497 [0] = {
498 .start = AT91SAM9G45_BASE_TWI1,
499 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
500 .flags = IORESOURCE_MEM,
501 },
502 [1] = {
503 .start = AT91SAM9G45_ID_TWI1,
504 .end = AT91SAM9G45_ID_TWI1,
505 .flags = IORESOURCE_IRQ,
506 },
507 };
508
509 static struct platform_device at91sam9g45_twi1_device = {
510 .name = "at91_i2c",
511 .id = 1,
512 .resource = twi1_resources,
513 .num_resources = ARRAY_SIZE(twi1_resources),
514 };
515
516 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
517 {
518 i2c_register_board_info(i2c_id, devices, nr_devices);
519
520 /* pins used for TWI interface */
521 if (i2c_id == 0) {
522 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
523 at91_set_multi_drive(AT91_PIN_PA20, 1);
524
525 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
526 at91_set_multi_drive(AT91_PIN_PA21, 1);
527
528 platform_device_register(&at91sam9g45_twi0_device);
529 } else {
530 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
531 at91_set_multi_drive(AT91_PIN_PB10, 1);
532
533 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
534 at91_set_multi_drive(AT91_PIN_PB11, 1);
535
536 platform_device_register(&at91sam9g45_twi1_device);
537 }
538 }
539 #else
540 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
541 #endif
542
543
544 /* --------------------------------------------------------------------
545 * SPI
546 * -------------------------------------------------------------------- */
547
548 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
549 static u64 spi_dmamask = DMA_BIT_MASK(32);
550
551 static struct resource spi0_resources[] = {
552 [0] = {
553 .start = AT91SAM9G45_BASE_SPI0,
554 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
555 .flags = IORESOURCE_MEM,
556 },
557 [1] = {
558 .start = AT91SAM9G45_ID_SPI0,
559 .end = AT91SAM9G45_ID_SPI0,
560 .flags = IORESOURCE_IRQ,
561 },
562 };
563
564 static struct platform_device at91sam9g45_spi0_device = {
565 .name = "atmel_spi",
566 .id = 0,
567 .dev = {
568 .dma_mask = &spi_dmamask,
569 .coherent_dma_mask = DMA_BIT_MASK(32),
570 },
571 .resource = spi0_resources,
572 .num_resources = ARRAY_SIZE(spi0_resources),
573 };
574
575 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
576
577 static struct resource spi1_resources[] = {
578 [0] = {
579 .start = AT91SAM9G45_BASE_SPI1,
580 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
581 .flags = IORESOURCE_MEM,
582 },
583 [1] = {
584 .start = AT91SAM9G45_ID_SPI1,
585 .end = AT91SAM9G45_ID_SPI1,
586 .flags = IORESOURCE_IRQ,
587 },
588 };
589
590 static struct platform_device at91sam9g45_spi1_device = {
591 .name = "atmel_spi",
592 .id = 1,
593 .dev = {
594 .dma_mask = &spi_dmamask,
595 .coherent_dma_mask = DMA_BIT_MASK(32),
596 },
597 .resource = spi1_resources,
598 .num_resources = ARRAY_SIZE(spi1_resources),
599 };
600
601 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
602
603 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
604 {
605 int i;
606 unsigned long cs_pin;
607 short enable_spi0 = 0;
608 short enable_spi1 = 0;
609
610 /* Choose SPI chip-selects */
611 for (i = 0; i < nr_devices; i++) {
612 if (devices[i].controller_data)
613 cs_pin = (unsigned long) devices[i].controller_data;
614 else if (devices[i].bus_num == 0)
615 cs_pin = spi0_standard_cs[devices[i].chip_select];
616 else
617 cs_pin = spi1_standard_cs[devices[i].chip_select];
618
619 if (devices[i].bus_num == 0)
620 enable_spi0 = 1;
621 else
622 enable_spi1 = 1;
623
624 /* enable chip-select pin */
625 at91_set_gpio_output(cs_pin, 1);
626
627 /* pass chip-select pin to driver */
628 devices[i].controller_data = (void *) cs_pin;
629 }
630
631 spi_register_board_info(devices, nr_devices);
632
633 /* Configure SPI bus(es) */
634 if (enable_spi0) {
635 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
636 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
637 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
638
639 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
640 platform_device_register(&at91sam9g45_spi0_device);
641 }
642 if (enable_spi1) {
643 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
644 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
645 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
646
647 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
648 platform_device_register(&at91sam9g45_spi1_device);
649 }
650 }
651 #else
652 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
653 #endif
654
655
656 /* --------------------------------------------------------------------
657 * AC97
658 * -------------------------------------------------------------------- */
659
660 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
661 static u64 ac97_dmamask = DMA_BIT_MASK(32);
662 static struct ac97c_platform_data ac97_data;
663
664 static struct resource ac97_resources[] = {
665 [0] = {
666 .start = AT91SAM9G45_BASE_AC97C,
667 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
668 .flags = IORESOURCE_MEM,
669 },
670 [1] = {
671 .start = AT91SAM9G45_ID_AC97C,
672 .end = AT91SAM9G45_ID_AC97C,
673 .flags = IORESOURCE_IRQ,
674 },
675 };
676
677 static struct platform_device at91sam9g45_ac97_device = {
678 .name = "atmel_ac97c",
679 .id = 0,
680 .dev = {
681 .dma_mask = &ac97_dmamask,
682 .coherent_dma_mask = DMA_BIT_MASK(32),
683 .platform_data = &ac97_data,
684 },
685 .resource = ac97_resources,
686 .num_resources = ARRAY_SIZE(ac97_resources),
687 };
688
689 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
690 {
691 if (!data)
692 return;
693
694 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
695 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
696 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
697 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
698
699 /* reset */
700 if (data->reset_pin)
701 at91_set_gpio_output(data->reset_pin, 0);
702
703 ac97_data = *data;
704 platform_device_register(&at91sam9g45_ac97_device);
705 }
706 #else
707 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
708 #endif
709
710
711 /* --------------------------------------------------------------------
712 * LCD Controller
713 * -------------------------------------------------------------------- */
714
715 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
716 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
717 static struct atmel_lcdfb_info lcdc_data;
718
719 static struct resource lcdc_resources[] = {
720 [0] = {
721 .start = AT91SAM9G45_LCDC_BASE,
722 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
723 .flags = IORESOURCE_MEM,
724 },
725 [1] = {
726 .start = AT91SAM9G45_ID_LCDC,
727 .end = AT91SAM9G45_ID_LCDC,
728 .flags = IORESOURCE_IRQ,
729 },
730 };
731
732 static struct platform_device at91_lcdc_device = {
733 .name = "atmel_lcdfb",
734 .id = 0,
735 .dev = {
736 .dma_mask = &lcdc_dmamask,
737 .coherent_dma_mask = DMA_BIT_MASK(32),
738 .platform_data = &lcdc_data,
739 },
740 .resource = lcdc_resources,
741 .num_resources = ARRAY_SIZE(lcdc_resources),
742 };
743
744 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
745 {
746 if (!data)
747 return;
748
749 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
750
751 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
752 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
753 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
754 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
755 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
756 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
757 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
758 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
759 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
760 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
761 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
762 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
763 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
764 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
765 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
766 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
767 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
768 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
769 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
770 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
771 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
772 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
773 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
774 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
775 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
776 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
777 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
778 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
779 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
780
781 lcdc_data = *data;
782 platform_device_register(&at91_lcdc_device);
783 }
784 #else
785 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
786 #endif
787
788
789 /* --------------------------------------------------------------------
790 * Timer/Counter block
791 * -------------------------------------------------------------------- */
792
793 #ifdef CONFIG_ATMEL_TCLIB
794 static struct resource tcb0_resources[] = {
795 [0] = {
796 .start = AT91SAM9G45_BASE_TCB0,
797 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
798 .flags = IORESOURCE_MEM,
799 },
800 [1] = {
801 .start = AT91SAM9G45_ID_TCB,
802 .end = AT91SAM9G45_ID_TCB,
803 .flags = IORESOURCE_IRQ,
804 },
805 };
806
807 static struct platform_device at91sam9g45_tcb0_device = {
808 .name = "atmel_tcb",
809 .id = 0,
810 .resource = tcb0_resources,
811 .num_resources = ARRAY_SIZE(tcb0_resources),
812 };
813
814 /* TCB1 begins with TC3 */
815 static struct resource tcb1_resources[] = {
816 [0] = {
817 .start = AT91SAM9G45_BASE_TCB1,
818 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
819 .flags = IORESOURCE_MEM,
820 },
821 [1] = {
822 .start = AT91SAM9G45_ID_TCB,
823 .end = AT91SAM9G45_ID_TCB,
824 .flags = IORESOURCE_IRQ,
825 },
826 };
827
828 static struct platform_device at91sam9g45_tcb1_device = {
829 .name = "atmel_tcb",
830 .id = 1,
831 .resource = tcb1_resources,
832 .num_resources = ARRAY_SIZE(tcb1_resources),
833 };
834
835 static void __init at91_add_device_tc(void)
836 {
837 /* this chip has one clock and irq for all six TC channels */
838 at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
839 platform_device_register(&at91sam9g45_tcb0_device);
840 at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
841 platform_device_register(&at91sam9g45_tcb1_device);
842 }
843 #else
844 static void __init at91_add_device_tc(void) { }
845 #endif
846
847
848 /* --------------------------------------------------------------------
849 * RTC
850 * -------------------------------------------------------------------- */
851
852 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
853 static struct platform_device at91sam9g45_rtc_device = {
854 .name = "at91_rtc",
855 .id = -1,
856 .num_resources = 0,
857 };
858
859 static void __init at91_add_device_rtc(void)
860 {
861 platform_device_register(&at91sam9g45_rtc_device);
862 }
863 #else
864 static void __init at91_add_device_rtc(void) {}
865 #endif
866
867
868 /* --------------------------------------------------------------------
869 * RTT
870 * -------------------------------------------------------------------- */
871
872 static struct resource rtt_resources[] = {
873 {
874 .start = AT91_BASE_SYS + AT91_RTT,
875 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
876 .flags = IORESOURCE_MEM,
877 }
878 };
879
880 static struct platform_device at91sam9g45_rtt_device = {
881 .name = "at91_rtt",
882 .id = 0,
883 .resource = rtt_resources,
884 .num_resources = ARRAY_SIZE(rtt_resources),
885 };
886
887 static void __init at91_add_device_rtt(void)
888 {
889 platform_device_register(&at91sam9g45_rtt_device);
890 }
891
892
893 /* --------------------------------------------------------------------
894 * Watchdog
895 * -------------------------------------------------------------------- */
896
897 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
898 static struct platform_device at91sam9g45_wdt_device = {
899 .name = "at91_wdt",
900 .id = -1,
901 .num_resources = 0,
902 };
903
904 static void __init at91_add_device_watchdog(void)
905 {
906 platform_device_register(&at91sam9g45_wdt_device);
907 }
908 #else
909 static void __init at91_add_device_watchdog(void) {}
910 #endif
911
912
913 /* --------------------------------------------------------------------
914 * PWM
915 * --------------------------------------------------------------------*/
916
917 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
918 static u32 pwm_mask;
919
920 static struct resource pwm_resources[] = {
921 [0] = {
922 .start = AT91SAM9G45_BASE_PWMC,
923 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
924 .flags = IORESOURCE_MEM,
925 },
926 [1] = {
927 .start = AT91SAM9G45_ID_PWMC,
928 .end = AT91SAM9G45_ID_PWMC,
929 .flags = IORESOURCE_IRQ,
930 },
931 };
932
933 static struct platform_device at91sam9g45_pwm0_device = {
934 .name = "atmel_pwm",
935 .id = -1,
936 .dev = {
937 .platform_data = &pwm_mask,
938 },
939 .resource = pwm_resources,
940 .num_resources = ARRAY_SIZE(pwm_resources),
941 };
942
943 void __init at91_add_device_pwm(u32 mask)
944 {
945 if (mask & (1 << AT91_PWM0))
946 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
947
948 if (mask & (1 << AT91_PWM1))
949 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
950
951 if (mask & (1 << AT91_PWM2))
952 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
953
954 if (mask & (1 << AT91_PWM3))
955 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
956
957 pwm_mask = mask;
958
959 platform_device_register(&at91sam9g45_pwm0_device);
960 }
961 #else
962 void __init at91_add_device_pwm(u32 mask) {}
963 #endif
964
965
966 /* --------------------------------------------------------------------
967 * SSC -- Synchronous Serial Controller
968 * -------------------------------------------------------------------- */
969
970 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
971 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
972
973 static struct resource ssc0_resources[] = {
974 [0] = {
975 .start = AT91SAM9G45_BASE_SSC0,
976 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
977 .flags = IORESOURCE_MEM,
978 },
979 [1] = {
980 .start = AT91SAM9G45_ID_SSC0,
981 .end = AT91SAM9G45_ID_SSC0,
982 .flags = IORESOURCE_IRQ,
983 },
984 };
985
986 static struct platform_device at91sam9g45_ssc0_device = {
987 .name = "ssc",
988 .id = 0,
989 .dev = {
990 .dma_mask = &ssc0_dmamask,
991 .coherent_dma_mask = DMA_BIT_MASK(32),
992 },
993 .resource = ssc0_resources,
994 .num_resources = ARRAY_SIZE(ssc0_resources),
995 };
996
997 static inline void configure_ssc0_pins(unsigned pins)
998 {
999 if (pins & ATMEL_SSC_TF)
1000 at91_set_A_periph(AT91_PIN_PD1, 1);
1001 if (pins & ATMEL_SSC_TK)
1002 at91_set_A_periph(AT91_PIN_PD0, 1);
1003 if (pins & ATMEL_SSC_TD)
1004 at91_set_A_periph(AT91_PIN_PD2, 1);
1005 if (pins & ATMEL_SSC_RD)
1006 at91_set_A_periph(AT91_PIN_PD3, 1);
1007 if (pins & ATMEL_SSC_RK)
1008 at91_set_A_periph(AT91_PIN_PD4, 1);
1009 if (pins & ATMEL_SSC_RF)
1010 at91_set_A_periph(AT91_PIN_PD5, 1);
1011 }
1012
1013 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1014
1015 static struct resource ssc1_resources[] = {
1016 [0] = {
1017 .start = AT91SAM9G45_BASE_SSC1,
1018 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1019 .flags = IORESOURCE_MEM,
1020 },
1021 [1] = {
1022 .start = AT91SAM9G45_ID_SSC1,
1023 .end = AT91SAM9G45_ID_SSC1,
1024 .flags = IORESOURCE_IRQ,
1025 },
1026 };
1027
1028 static struct platform_device at91sam9g45_ssc1_device = {
1029 .name = "ssc",
1030 .id = 1,
1031 .dev = {
1032 .dma_mask = &ssc1_dmamask,
1033 .coherent_dma_mask = DMA_BIT_MASK(32),
1034 },
1035 .resource = ssc1_resources,
1036 .num_resources = ARRAY_SIZE(ssc1_resources),
1037 };
1038
1039 static inline void configure_ssc1_pins(unsigned pins)
1040 {
1041 if (pins & ATMEL_SSC_TF)
1042 at91_set_A_periph(AT91_PIN_PD14, 1);
1043 if (pins & ATMEL_SSC_TK)
1044 at91_set_A_periph(AT91_PIN_PD12, 1);
1045 if (pins & ATMEL_SSC_TD)
1046 at91_set_A_periph(AT91_PIN_PD10, 1);
1047 if (pins & ATMEL_SSC_RD)
1048 at91_set_A_periph(AT91_PIN_PD11, 1);
1049 if (pins & ATMEL_SSC_RK)
1050 at91_set_A_periph(AT91_PIN_PD13, 1);
1051 if (pins & ATMEL_SSC_RF)
1052 at91_set_A_periph(AT91_PIN_PD15, 1);
1053 }
1054
1055 /*
1056 * SSC controllers are accessed through library code, instead of any
1057 * kind of all-singing/all-dancing driver. For example one could be
1058 * used by a particular I2S audio codec's driver, while another one
1059 * on the same system might be used by a custom data capture driver.
1060 */
1061 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1062 {
1063 struct platform_device *pdev;
1064
1065 /*
1066 * NOTE: caller is responsible for passing information matching
1067 * "pins" to whatever will be using each particular controller.
1068 */
1069 switch (id) {
1070 case AT91SAM9G45_ID_SSC0:
1071 pdev = &at91sam9g45_ssc0_device;
1072 configure_ssc0_pins(pins);
1073 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
1074 break;
1075 case AT91SAM9G45_ID_SSC1:
1076 pdev = &at91sam9g45_ssc1_device;
1077 configure_ssc1_pins(pins);
1078 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
1079 break;
1080 default:
1081 return;
1082 }
1083
1084 platform_device_register(pdev);
1085 }
1086
1087 #else
1088 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1089 #endif
1090
1091
1092 /* --------------------------------------------------------------------
1093 * UART
1094 * -------------------------------------------------------------------- */
1095
1096 #if defined(CONFIG_SERIAL_ATMEL)
1097 static struct resource dbgu_resources[] = {
1098 [0] = {
1099 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1100 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1101 .flags = IORESOURCE_MEM,
1102 },
1103 [1] = {
1104 .start = AT91_ID_SYS,
1105 .end = AT91_ID_SYS,
1106 .flags = IORESOURCE_IRQ,
1107 },
1108 };
1109
1110 static struct atmel_uart_data dbgu_data = {
1111 .use_dma_tx = 0,
1112 .use_dma_rx = 0,
1113 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1114 };
1115
1116 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1117
1118 static struct platform_device at91sam9g45_dbgu_device = {
1119 .name = "atmel_usart",
1120 .id = 0,
1121 .dev = {
1122 .dma_mask = &dbgu_dmamask,
1123 .coherent_dma_mask = DMA_BIT_MASK(32),
1124 .platform_data = &dbgu_data,
1125 },
1126 .resource = dbgu_resources,
1127 .num_resources = ARRAY_SIZE(dbgu_resources),
1128 };
1129
1130 static inline void configure_dbgu_pins(void)
1131 {
1132 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1133 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1134 }
1135
1136 static struct resource uart0_resources[] = {
1137 [0] = {
1138 .start = AT91SAM9G45_BASE_US0,
1139 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1140 .flags = IORESOURCE_MEM,
1141 },
1142 [1] = {
1143 .start = AT91SAM9G45_ID_US0,
1144 .end = AT91SAM9G45_ID_US0,
1145 .flags = IORESOURCE_IRQ,
1146 },
1147 };
1148
1149 static struct atmel_uart_data uart0_data = {
1150 .use_dma_tx = 1,
1151 .use_dma_rx = 1,
1152 };
1153
1154 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1155
1156 static struct platform_device at91sam9g45_uart0_device = {
1157 .name = "atmel_usart",
1158 .id = 1,
1159 .dev = {
1160 .dma_mask = &uart0_dmamask,
1161 .coherent_dma_mask = DMA_BIT_MASK(32),
1162 .platform_data = &uart0_data,
1163 },
1164 .resource = uart0_resources,
1165 .num_resources = ARRAY_SIZE(uart0_resources),
1166 };
1167
1168 static inline void configure_usart0_pins(unsigned pins)
1169 {
1170 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1171 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1172
1173 if (pins & ATMEL_UART_RTS)
1174 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1175 if (pins & ATMEL_UART_CTS)
1176 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1177 }
1178
1179 static struct resource uart1_resources[] = {
1180 [0] = {
1181 .start = AT91SAM9G45_BASE_US1,
1182 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1183 .flags = IORESOURCE_MEM,
1184 },
1185 [1] = {
1186 .start = AT91SAM9G45_ID_US1,
1187 .end = AT91SAM9G45_ID_US1,
1188 .flags = IORESOURCE_IRQ,
1189 },
1190 };
1191
1192 static struct atmel_uart_data uart1_data = {
1193 .use_dma_tx = 1,
1194 .use_dma_rx = 1,
1195 };
1196
1197 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1198
1199 static struct platform_device at91sam9g45_uart1_device = {
1200 .name = "atmel_usart",
1201 .id = 2,
1202 .dev = {
1203 .dma_mask = &uart1_dmamask,
1204 .coherent_dma_mask = DMA_BIT_MASK(32),
1205 .platform_data = &uart1_data,
1206 },
1207 .resource = uart1_resources,
1208 .num_resources = ARRAY_SIZE(uart1_resources),
1209 };
1210
1211 static inline void configure_usart1_pins(unsigned pins)
1212 {
1213 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1214 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1215
1216 if (pins & ATMEL_UART_RTS)
1217 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1218 if (pins & ATMEL_UART_CTS)
1219 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1220 }
1221
1222 static struct resource uart2_resources[] = {
1223 [0] = {
1224 .start = AT91SAM9G45_BASE_US2,
1225 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1226 .flags = IORESOURCE_MEM,
1227 },
1228 [1] = {
1229 .start = AT91SAM9G45_ID_US2,
1230 .end = AT91SAM9G45_ID_US2,
1231 .flags = IORESOURCE_IRQ,
1232 },
1233 };
1234
1235 static struct atmel_uart_data uart2_data = {
1236 .use_dma_tx = 1,
1237 .use_dma_rx = 1,
1238 };
1239
1240 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1241
1242 static struct platform_device at91sam9g45_uart2_device = {
1243 .name = "atmel_usart",
1244 .id = 3,
1245 .dev = {
1246 .dma_mask = &uart2_dmamask,
1247 .coherent_dma_mask = DMA_BIT_MASK(32),
1248 .platform_data = &uart2_data,
1249 },
1250 .resource = uart2_resources,
1251 .num_resources = ARRAY_SIZE(uart2_resources),
1252 };
1253
1254 static inline void configure_usart2_pins(unsigned pins)
1255 {
1256 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1257 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1258
1259 if (pins & ATMEL_UART_RTS)
1260 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1261 if (pins & ATMEL_UART_CTS)
1262 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1263 }
1264
1265 static struct resource uart3_resources[] = {
1266 [0] = {
1267 .start = AT91SAM9G45_BASE_US3,
1268 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1269 .flags = IORESOURCE_MEM,
1270 },
1271 [1] = {
1272 .start = AT91SAM9G45_ID_US3,
1273 .end = AT91SAM9G45_ID_US3,
1274 .flags = IORESOURCE_IRQ,
1275 },
1276 };
1277
1278 static struct atmel_uart_data uart3_data = {
1279 .use_dma_tx = 1,
1280 .use_dma_rx = 1,
1281 };
1282
1283 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1284
1285 static struct platform_device at91sam9g45_uart3_device = {
1286 .name = "atmel_usart",
1287 .id = 4,
1288 .dev = {
1289 .dma_mask = &uart3_dmamask,
1290 .coherent_dma_mask = DMA_BIT_MASK(32),
1291 .platform_data = &uart3_data,
1292 },
1293 .resource = uart3_resources,
1294 .num_resources = ARRAY_SIZE(uart3_resources),
1295 };
1296
1297 static inline void configure_usart3_pins(unsigned pins)
1298 {
1299 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1300 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1301
1302 if (pins & ATMEL_UART_RTS)
1303 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1304 if (pins & ATMEL_UART_CTS)
1305 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1306 }
1307
1308 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1309 struct platform_device *atmel_default_console_device; /* the serial console device */
1310
1311 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1312 {
1313 struct platform_device *pdev;
1314
1315 switch (id) {
1316 case 0: /* DBGU */
1317 pdev = &at91sam9g45_dbgu_device;
1318 configure_dbgu_pins();
1319 at91_clock_associate("mck", &pdev->dev, "usart");
1320 break;
1321 case AT91SAM9G45_ID_US0:
1322 pdev = &at91sam9g45_uart0_device;
1323 configure_usart0_pins(pins);
1324 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1325 break;
1326 case AT91SAM9G45_ID_US1:
1327 pdev = &at91sam9g45_uart1_device;
1328 configure_usart1_pins(pins);
1329 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1330 break;
1331 case AT91SAM9G45_ID_US2:
1332 pdev = &at91sam9g45_uart2_device;
1333 configure_usart2_pins(pins);
1334 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1335 break;
1336 case AT91SAM9G45_ID_US3:
1337 pdev = &at91sam9g45_uart3_device;
1338 configure_usart3_pins(pins);
1339 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1340 break;
1341 default:
1342 return;
1343 }
1344 pdev->id = portnr; /* update to mapped ID */
1345
1346 if (portnr < ATMEL_MAX_UART)
1347 at91_uarts[portnr] = pdev;
1348 }
1349
1350 void __init at91_set_serial_console(unsigned portnr)
1351 {
1352 if (portnr < ATMEL_MAX_UART)
1353 atmel_default_console_device = at91_uarts[portnr];
1354 }
1355
1356 void __init at91_add_device_serial(void)
1357 {
1358 int i;
1359
1360 for (i = 0; i < ATMEL_MAX_UART; i++) {
1361 if (at91_uarts[i])
1362 platform_device_register(at91_uarts[i]);
1363 }
1364
1365 if (!atmel_default_console_device)
1366 printk(KERN_INFO "AT91: No default serial console defined.\n");
1367 }
1368 #else
1369 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1370 void __init at91_set_serial_console(unsigned portnr) {}
1371 void __init at91_add_device_serial(void) {}
1372 #endif
1373
1374
1375 /* -------------------------------------------------------------------- */
1376 /*
1377 * These devices are always present and don't need any board-specific
1378 * setup.
1379 */
1380 static int __init at91_add_standard_devices(void)
1381 {
1382 at91_add_device_hdmac();
1383 at91_add_device_rtc();
1384 at91_add_device_rtt();
1385 at91_add_device_watchdog();
1386 at91_add_device_tc();
1387 return 0;
1388 }
1389
1390 arch_initcall(at91_add_standard_devices);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree