2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/version.h>
44 #define NVME_Q_DEPTH 1024
45 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
46 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
47 #define NVME_MINORS 64
48 #define NVME_IO_TIMEOUT (5 * HZ)
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major
;
52 module_param(nvme_major
, int, 0);
54 static int use_threaded_interrupts
;
55 module_param(use_threaded_interrupts
, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock
);
58 static LIST_HEAD(dev_list
);
59 static struct task_struct
*nvme_thread
;
62 * Represents an NVM Express device. Each nvme_dev is a PCI function.
65 struct list_head node
;
66 struct nvme_queue
**queues
;
68 struct pci_dev
*pci_dev
;
69 struct dma_pool
*prp_page_pool
;
70 struct dma_pool
*prp_small_pool
;
75 struct msix_entry
*entry
;
76 struct nvme_bar __iomem
*bar
;
77 struct list_head namespaces
;
84 * An NVM Express namespace is equivalent to a SCSI LUN
87 struct list_head list
;
90 struct request_queue
*queue
;
98 * An NVM Express queue. Each device has at least two (one for admin
99 * commands and one for I/O commands).
102 struct device
*q_dmadev
;
103 struct nvme_dev
*dev
;
105 struct nvme_command
*sq_cmds
;
106 volatile struct nvme_completion
*cqes
;
107 dma_addr_t sq_dma_addr
;
108 dma_addr_t cq_dma_addr
;
109 wait_queue_head_t sq_full
;
110 wait_queue_t sq_cong_wait
;
111 struct bio_list sq_cong
;
119 unsigned long cmdid_data
[];
123 * Check we didin't inadvertently grow the command struct
125 static inline void _nvme_check_size(void)
127 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
138 typedef void (*nvme_completion_fn
)(struct nvme_dev
*, void *,
139 struct nvme_completion
*);
141 struct nvme_cmd_info
{
142 nvme_completion_fn fn
;
144 unsigned long timeout
;
147 static struct nvme_cmd_info
*nvme_cmd_info(struct nvme_queue
*nvmeq
)
149 return (void *)&nvmeq
->cmdid_data
[BITS_TO_LONGS(nvmeq
->q_depth
)];
153 * alloc_cmdid() - Allocate a Command ID
154 * @nvmeq: The queue that will be used for this command
155 * @ctx: A pointer that will be passed to the handler
156 * @handler: The function to call on completion
158 * Allocate a Command ID for a queue. The data passed in will
159 * be passed to the completion handler. This is implemented by using
160 * the bottom two bits of the ctx pointer to store the handler ID.
161 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
162 * We can change this if it becomes a problem.
164 * May be called with local interrupts disabled and the q_lock held,
165 * or with interrupts enabled and no locks held.
167 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
,
168 nvme_completion_fn handler
, unsigned timeout
)
170 int depth
= nvmeq
->q_depth
- 1;
171 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
175 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
178 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
180 info
[cmdid
].fn
= handler
;
181 info
[cmdid
].ctx
= ctx
;
182 info
[cmdid
].timeout
= jiffies
+ timeout
;
186 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
187 nvme_completion_fn handler
, unsigned timeout
)
190 wait_event_killable(nvmeq
->sq_full
,
191 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
, timeout
)) >= 0);
192 return (cmdid
< 0) ? -EINTR
: cmdid
;
195 /* Special values must be less than 0x1000 */
196 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
197 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
198 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
199 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
200 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
202 static void special_completion(struct nvme_dev
*dev
, void *ctx
,
203 struct nvme_completion
*cqe
)
205 if (ctx
== CMD_CTX_CANCELLED
)
207 if (ctx
== CMD_CTX_FLUSH
)
209 if (ctx
== CMD_CTX_COMPLETED
) {
210 dev_warn(&dev
->pci_dev
->dev
,
211 "completed id %d twice on queue %d\n",
212 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
215 if (ctx
== CMD_CTX_INVALID
) {
216 dev_warn(&dev
->pci_dev
->dev
,
217 "invalid id %d completed on queue %d\n",
218 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
222 dev_warn(&dev
->pci_dev
->dev
, "Unknown special completion %p\n", ctx
);
226 * Called with local interrupts disabled and the q_lock held. May not sleep.
228 static void *free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
229 nvme_completion_fn
*fn
)
232 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
234 if (cmdid
>= nvmeq
->q_depth
) {
235 *fn
= special_completion
;
236 return CMD_CTX_INVALID
;
238 *fn
= info
[cmdid
].fn
;
239 ctx
= info
[cmdid
].ctx
;
240 info
[cmdid
].fn
= special_completion
;
241 info
[cmdid
].ctx
= CMD_CTX_COMPLETED
;
242 clear_bit(cmdid
, nvmeq
->cmdid_data
);
243 wake_up(&nvmeq
->sq_full
);
247 static void *cancel_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
248 nvme_completion_fn
*fn
)
251 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
253 *fn
= info
[cmdid
].fn
;
254 ctx
= info
[cmdid
].ctx
;
255 info
[cmdid
].fn
= special_completion
;
256 info
[cmdid
].ctx
= CMD_CTX_CANCELLED
;
260 static struct nvme_queue
*get_nvmeq(struct nvme_dev
*dev
)
262 return dev
->queues
[get_cpu() + 1];
265 static void put_nvmeq(struct nvme_queue
*nvmeq
)
271 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
272 * @nvmeq: The queue to use
273 * @cmd: The command to send
275 * Safe to use from interrupt context
277 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
281 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
282 tail
= nvmeq
->sq_tail
;
283 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
284 if (++tail
== nvmeq
->q_depth
)
286 writel(tail
, nvmeq
->q_db
);
287 nvmeq
->sq_tail
= tail
;
288 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
294 * The nvme_iod describes the data in an I/O, including the list of PRP
295 * entries. You can't see it in this data structure because C doesn't let
296 * me express that. Use nvme_alloc_iod to ensure there's enough space
297 * allocated to store the PRP list.
300 void *private; /* For the use of the submitter of the I/O */
301 int npages
; /* In the PRP list. 0 means small pool in use */
302 int offset
; /* Of PRP list */
303 int nents
; /* Used in scatterlist */
304 int length
; /* Of data, in bytes */
305 dma_addr_t first_dma
;
306 struct scatterlist sg
[0];
309 static __le64
**iod_list(struct nvme_iod
*iod
)
311 return ((void *)iod
) + iod
->offset
;
315 * Will slightly overestimate the number of pages needed. This is OK
316 * as it only leads to a small amount of wasted memory for the lifetime of
319 static int nvme_npages(unsigned size
)
321 unsigned nprps
= DIV_ROUND_UP(size
+ PAGE_SIZE
, PAGE_SIZE
);
322 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
325 static struct nvme_iod
*
326 nvme_alloc_iod(unsigned nseg
, unsigned nbytes
, gfp_t gfp
)
328 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
329 sizeof(__le64
*) * nvme_npages(nbytes
) +
330 sizeof(struct scatterlist
) * nseg
, gfp
);
333 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
335 iod
->length
= nbytes
;
341 static void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
343 const int last_prp
= PAGE_SIZE
/ 8 - 1;
345 __le64
**list
= iod_list(iod
);
346 dma_addr_t prp_dma
= iod
->first_dma
;
348 if (iod
->npages
== 0)
349 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
350 for (i
= 0; i
< iod
->npages
; i
++) {
351 __le64
*prp_list
= list
[i
];
352 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
353 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
354 prp_dma
= next_prp_dma
;
359 static void requeue_bio(struct nvme_dev
*dev
, struct bio
*bio
)
361 struct nvme_queue
*nvmeq
= get_nvmeq(dev
);
362 if (bio_list_empty(&nvmeq
->sq_cong
))
363 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
364 bio_list_add(&nvmeq
->sq_cong
, bio
);
366 wake_up_process(nvme_thread
);
369 static void bio_completion(struct nvme_dev
*dev
, void *ctx
,
370 struct nvme_completion
*cqe
)
372 struct nvme_iod
*iod
= ctx
;
373 struct bio
*bio
= iod
->private;
374 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
376 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
377 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
378 nvme_free_iod(dev
, iod
);
380 bio_endio(bio
, -EIO
);
381 } else if (bio
->bi_vcnt
> bio
->bi_idx
) {
382 requeue_bio(dev
, bio
);
388 /* length is in bytes. gfp flags indicates whether we may sleep. */
389 static int nvme_setup_prps(struct nvme_dev
*dev
,
390 struct nvme_common_command
*cmd
, struct nvme_iod
*iod
,
391 int total_len
, gfp_t gfp
)
393 struct dma_pool
*pool
;
394 int length
= total_len
;
395 struct scatterlist
*sg
= iod
->sg
;
396 int dma_len
= sg_dma_len(sg
);
397 u64 dma_addr
= sg_dma_address(sg
);
398 int offset
= offset_in_page(dma_addr
);
400 __le64
**list
= iod_list(iod
);
404 cmd
->prp1
= cpu_to_le64(dma_addr
);
405 length
-= (PAGE_SIZE
- offset
);
409 dma_len
-= (PAGE_SIZE
- offset
);
411 dma_addr
+= (PAGE_SIZE
- offset
);
414 dma_addr
= sg_dma_address(sg
);
415 dma_len
= sg_dma_len(sg
);
418 if (length
<= PAGE_SIZE
) {
419 cmd
->prp2
= cpu_to_le64(dma_addr
);
423 nprps
= DIV_ROUND_UP(length
, PAGE_SIZE
);
424 if (nprps
<= (256 / 8)) {
425 pool
= dev
->prp_small_pool
;
428 pool
= dev
->prp_page_pool
;
432 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
434 cmd
->prp2
= cpu_to_le64(dma_addr
);
436 return (total_len
- length
) + PAGE_SIZE
;
439 iod
->first_dma
= prp_dma
;
440 cmd
->prp2
= cpu_to_le64(prp_dma
);
443 if (i
== PAGE_SIZE
/ 8) {
444 __le64
*old_prp_list
= prp_list
;
445 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
447 return total_len
- length
;
448 list
[iod
->npages
++] = prp_list
;
449 prp_list
[0] = old_prp_list
[i
- 1];
450 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
453 prp_list
[i
++] = cpu_to_le64(dma_addr
);
454 dma_len
-= PAGE_SIZE
;
455 dma_addr
+= PAGE_SIZE
;
463 dma_addr
= sg_dma_address(sg
);
464 dma_len
= sg_dma_len(sg
);
470 /* NVMe scatterlists require no holes in the virtual address */
471 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
472 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
474 static int nvme_map_bio(struct device
*dev
, struct nvme_iod
*iod
,
475 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
477 struct bio_vec
*bvec
, *bvprv
= NULL
;
478 struct scatterlist
*sg
= NULL
;
479 int i
, old_idx
, length
= 0, nsegs
= 0;
481 sg_init_table(iod
->sg
, psegs
);
482 old_idx
= bio
->bi_idx
;
483 bio_for_each_segment(bvec
, bio
, i
) {
484 if (bvprv
&& BIOVEC_PHYS_MERGEABLE(bvprv
, bvec
)) {
485 sg
->length
+= bvec
->bv_len
;
487 if (bvprv
&& BIOVEC_NOT_VIRT_MERGEABLE(bvprv
, bvec
))
489 sg
= sg
? sg
+ 1 : iod
->sg
;
490 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
,
494 length
+= bvec
->bv_len
;
500 if (dma_map_sg(dev
, iod
->sg
, iod
->nents
, dma_dir
) == 0) {
501 bio
->bi_idx
= old_idx
;
507 static int nvme_submit_flush(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
510 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
512 memset(cmnd
, 0, sizeof(*cmnd
));
513 cmnd
->common
.opcode
= nvme_cmd_flush
;
514 cmnd
->common
.command_id
= cmdid
;
515 cmnd
->common
.nsid
= cpu_to_le32(ns
->ns_id
);
517 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
519 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
524 static int nvme_submit_flush_data(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
)
526 int cmdid
= alloc_cmdid(nvmeq
, (void *)CMD_CTX_FLUSH
,
527 special_completion
, NVME_IO_TIMEOUT
);
528 if (unlikely(cmdid
< 0))
531 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
535 * Called with local interrupts disabled and the q_lock held. May not sleep.
537 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
540 struct nvme_command
*cmnd
;
541 struct nvme_iod
*iod
;
542 enum dma_data_direction dma_dir
;
543 int cmdid
, length
, result
= -ENOMEM
;
546 int psegs
= bio_phys_segments(ns
->queue
, bio
);
548 if ((bio
->bi_rw
& REQ_FLUSH
) && psegs
) {
549 result
= nvme_submit_flush_data(nvmeq
, ns
);
554 iod
= nvme_alloc_iod(psegs
, bio
->bi_size
, GFP_ATOMIC
);
560 cmdid
= alloc_cmdid(nvmeq
, iod
, bio_completion
, NVME_IO_TIMEOUT
);
561 if (unlikely(cmdid
< 0))
564 if ((bio
->bi_rw
& REQ_FLUSH
) && !psegs
)
565 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
568 if (bio
->bi_rw
& REQ_FUA
)
569 control
|= NVME_RW_FUA
;
570 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
571 control
|= NVME_RW_LR
;
574 if (bio
->bi_rw
& REQ_RAHEAD
)
575 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
577 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
579 memset(cmnd
, 0, sizeof(*cmnd
));
580 if (bio_data_dir(bio
)) {
581 cmnd
->rw
.opcode
= nvme_cmd_write
;
582 dma_dir
= DMA_TO_DEVICE
;
584 cmnd
->rw
.opcode
= nvme_cmd_read
;
585 dma_dir
= DMA_FROM_DEVICE
;
588 result
= nvme_map_bio(nvmeq
->q_dmadev
, iod
, bio
, dma_dir
, psegs
);
593 cmnd
->rw
.command_id
= cmdid
;
594 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
595 length
= nvme_setup_prps(nvmeq
->dev
, &cmnd
->common
, iod
, length
,
597 cmnd
->rw
.slba
= cpu_to_le64(bio
->bi_sector
>> (ns
->lba_shift
- 9));
598 cmnd
->rw
.length
= cpu_to_le16((length
>> ns
->lba_shift
) - 1);
599 cmnd
->rw
.control
= cpu_to_le16(control
);
600 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
602 bio
->bi_sector
+= length
>> 9;
604 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
606 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
611 nvme_free_iod(nvmeq
->dev
, iod
);
616 static void nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
618 struct nvme_ns
*ns
= q
->queuedata
;
619 struct nvme_queue
*nvmeq
= get_nvmeq(ns
->dev
);
622 spin_lock_irq(&nvmeq
->q_lock
);
623 if (bio_list_empty(&nvmeq
->sq_cong
))
624 result
= nvme_submit_bio_queue(nvmeq
, ns
, bio
);
625 if (unlikely(result
)) {
626 if (bio_list_empty(&nvmeq
->sq_cong
))
627 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
628 bio_list_add(&nvmeq
->sq_cong
, bio
);
631 spin_unlock_irq(&nvmeq
->q_lock
);
635 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
639 head
= nvmeq
->cq_head
;
640 phase
= nvmeq
->cq_phase
;
644 nvme_completion_fn fn
;
645 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
646 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
648 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
649 if (++head
== nvmeq
->q_depth
) {
654 ctx
= free_cmdid(nvmeq
, cqe
.command_id
, &fn
);
655 fn(nvmeq
->dev
, ctx
, &cqe
);
658 /* If the controller ignores the cq head doorbell and continuously
659 * writes to the queue, it is theoretically possible to wrap around
660 * the queue twice and mistakenly return IRQ_NONE. Linux only
661 * requires that 0.1% of your interrupts are handled, so this isn't
664 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
667 writel(head
, nvmeq
->q_db
+ (1 << nvmeq
->dev
->db_stride
));
668 nvmeq
->cq_head
= head
;
669 nvmeq
->cq_phase
= phase
;
674 static irqreturn_t
nvme_irq(int irq
, void *data
)
677 struct nvme_queue
*nvmeq
= data
;
678 spin_lock(&nvmeq
->q_lock
);
679 result
= nvme_process_cq(nvmeq
);
680 spin_unlock(&nvmeq
->q_lock
);
684 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
686 struct nvme_queue
*nvmeq
= data
;
687 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
688 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
690 return IRQ_WAKE_THREAD
;
693 static void nvme_abort_command(struct nvme_queue
*nvmeq
, int cmdid
)
695 spin_lock_irq(&nvmeq
->q_lock
);
696 cancel_cmdid(nvmeq
, cmdid
, NULL
);
697 spin_unlock_irq(&nvmeq
->q_lock
);
700 struct sync_cmd_info
{
701 struct task_struct
*task
;
706 static void sync_completion(struct nvme_dev
*dev
, void *ctx
,
707 struct nvme_completion
*cqe
)
709 struct sync_cmd_info
*cmdinfo
= ctx
;
710 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
711 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
712 wake_up_process(cmdinfo
->task
);
716 * Returns 0 on success. If the result is negative, it's a Linux error code;
717 * if the result is positive, it's an NVM Express status code
719 static int nvme_submit_sync_cmd(struct nvme_queue
*nvmeq
,
720 struct nvme_command
*cmd
, u32
*result
, unsigned timeout
)
723 struct sync_cmd_info cmdinfo
;
725 cmdinfo
.task
= current
;
726 cmdinfo
.status
= -EINTR
;
728 cmdid
= alloc_cmdid_killable(nvmeq
, &cmdinfo
, sync_completion
,
732 cmd
->common
.command_id
= cmdid
;
734 set_current_state(TASK_KILLABLE
);
735 nvme_submit_cmd(nvmeq
, cmd
);
738 if (cmdinfo
.status
== -EINTR
) {
739 nvme_abort_command(nvmeq
, cmdid
);
744 *result
= cmdinfo
.result
;
746 return cmdinfo
.status
;
749 static int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
752 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
, ADMIN_TIMEOUT
);
755 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
758 struct nvme_command c
;
760 memset(&c
, 0, sizeof(c
));
761 c
.delete_queue
.opcode
= opcode
;
762 c
.delete_queue
.qid
= cpu_to_le16(id
);
764 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
770 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
771 struct nvme_queue
*nvmeq
)
774 struct nvme_command c
;
775 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
777 memset(&c
, 0, sizeof(c
));
778 c
.create_cq
.opcode
= nvme_admin_create_cq
;
779 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
780 c
.create_cq
.cqid
= cpu_to_le16(qid
);
781 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
782 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
783 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
785 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
791 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
792 struct nvme_queue
*nvmeq
)
795 struct nvme_command c
;
796 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
798 memset(&c
, 0, sizeof(c
));
799 c
.create_sq
.opcode
= nvme_admin_create_sq
;
800 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
801 c
.create_sq
.sqid
= cpu_to_le16(qid
);
802 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
803 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
804 c
.create_sq
.cqid
= cpu_to_le16(qid
);
806 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
812 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
814 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
817 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
819 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
822 static int nvme_identify(struct nvme_dev
*dev
, unsigned nsid
, unsigned cns
,
825 struct nvme_command c
;
827 memset(&c
, 0, sizeof(c
));
828 c
.identify
.opcode
= nvme_admin_identify
;
829 c
.identify
.nsid
= cpu_to_le32(nsid
);
830 c
.identify
.prp1
= cpu_to_le64(dma_addr
);
831 c
.identify
.cns
= cpu_to_le32(cns
);
833 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
836 static int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
,
837 unsigned dword11
, dma_addr_t dma_addr
)
839 struct nvme_command c
;
841 memset(&c
, 0, sizeof(c
));
842 c
.features
.opcode
= nvme_admin_get_features
;
843 c
.features
.prp1
= cpu_to_le64(dma_addr
);
844 c
.features
.fid
= cpu_to_le32(fid
);
845 c
.features
.dword11
= cpu_to_le32(dword11
);
847 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
850 static int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
,
851 unsigned dword11
, dma_addr_t dma_addr
, u32
*result
)
853 struct nvme_command c
;
855 memset(&c
, 0, sizeof(c
));
856 c
.features
.opcode
= nvme_admin_set_features
;
857 c
.features
.prp1
= cpu_to_le64(dma_addr
);
858 c
.features
.fid
= cpu_to_le32(fid
);
859 c
.features
.dword11
= cpu_to_le32(dword11
);
861 return nvme_submit_admin_cmd(dev
, &c
, result
);
864 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
866 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
867 int vector
= dev
->entry
[nvmeq
->cq_vector
].vector
;
869 irq_set_affinity_hint(vector
, NULL
);
870 free_irq(vector
, nvmeq
);
872 /* Don't tell the adapter to delete the admin queue */
874 adapter_delete_sq(dev
, qid
);
875 adapter_delete_cq(dev
, qid
);
878 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
879 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
880 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
881 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
885 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
886 int depth
, int vector
)
888 struct device
*dmadev
= &dev
->pci_dev
->dev
;
889 unsigned extra
= (depth
/ 8) + (depth
* sizeof(struct nvme_cmd_info
));
890 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
894 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
895 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
898 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
900 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
901 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
905 nvmeq
->q_dmadev
= dmadev
;
907 spin_lock_init(&nvmeq
->q_lock
);
910 init_waitqueue_head(&nvmeq
->sq_full
);
911 init_waitqueue_entry(&nvmeq
->sq_cong_wait
, nvme_thread
);
912 bio_list_init(&nvmeq
->sq_cong
);
913 nvmeq
->q_db
= &dev
->dbs
[qid
<< (dev
->db_stride
+ 1)];
914 nvmeq
->q_depth
= depth
;
915 nvmeq
->cq_vector
= vector
;
920 dma_free_coherent(dmadev
, CQ_SIZE(nvmeq
->q_depth
), (void *)nvmeq
->cqes
,
927 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
930 if (use_threaded_interrupts
)
931 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
932 nvme_irq_check
, nvme_irq
,
933 IRQF_DISABLED
| IRQF_SHARED
,
935 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
936 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
939 static __devinit
struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
,
940 int qid
, int cq_size
, int vector
)
943 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
946 return ERR_PTR(-ENOMEM
);
948 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
952 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
956 result
= queue_request_irq(dev
, nvmeq
, "nvme");
963 adapter_delete_sq(dev
, qid
);
965 adapter_delete_cq(dev
, qid
);
967 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
968 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
969 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
970 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
972 return ERR_PTR(result
);
975 static int __devinit
nvme_configure_admin_queue(struct nvme_dev
*dev
)
980 unsigned long timeout
;
981 struct nvme_queue
*nvmeq
;
983 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
985 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
989 aqa
= nvmeq
->q_depth
- 1;
992 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
993 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
994 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
995 dev
->ctrl_config
|= NVME_CC_IOSQES
| NVME_CC_IOCQES
;
997 writel(0, &dev
->bar
->cc
);
998 writel(aqa
, &dev
->bar
->aqa
);
999 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
1000 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
1001 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
1003 cap
= readq(&dev
->bar
->cap
);
1004 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
1005 dev
->db_stride
= NVME_CAP_STRIDE(cap
);
1007 while (!(readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
)) {
1009 if (fatal_signal_pending(current
))
1011 if (time_after(jiffies
, timeout
)) {
1012 dev_err(&dev
->pci_dev
->dev
,
1013 "Device not ready; aborting initialisation\n");
1018 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
1019 dev
->queues
[0] = nvmeq
;
1023 static struct nvme_iod
*nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
1024 unsigned long addr
, unsigned length
)
1026 int i
, err
, count
, nents
, offset
;
1027 struct scatterlist
*sg
;
1028 struct page
**pages
;
1029 struct nvme_iod
*iod
;
1032 return ERR_PTR(-EINVAL
);
1034 return ERR_PTR(-EINVAL
);
1036 offset
= offset_in_page(addr
);
1037 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
1038 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
1040 err
= get_user_pages_fast(addr
, count
, 1, pages
);
1047 iod
= nvme_alloc_iod(count
, length
, GFP_KERNEL
);
1049 sg_init_table(sg
, count
);
1050 for (i
= 0; i
< count
; i
++) {
1051 sg_set_page(&sg
[i
], pages
[i
],
1052 min_t(int, length
, PAGE_SIZE
- offset
), offset
);
1053 length
-= (PAGE_SIZE
- offset
);
1056 sg_mark_end(&sg
[i
- 1]);
1060 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
1061 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1071 for (i
= 0; i
< count
; i
++)
1074 return ERR_PTR(err
);
1077 static void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
1078 struct nvme_iod
*iod
)
1082 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
1083 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1085 for (i
= 0; i
< iod
->nents
; i
++)
1086 put_page(sg_page(&iod
->sg
[i
]));
1089 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
1091 struct nvme_dev
*dev
= ns
->dev
;
1092 struct nvme_queue
*nvmeq
;
1093 struct nvme_user_io io
;
1094 struct nvme_command c
;
1097 struct nvme_iod
*iod
;
1099 if (copy_from_user(&io
, uio
, sizeof(io
)))
1101 length
= (io
.nblocks
+ 1) << ns
->lba_shift
;
1103 switch (io
.opcode
) {
1104 case nvme_cmd_write
:
1106 case nvme_cmd_compare
:
1107 iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
);
1114 return PTR_ERR(iod
);
1116 memset(&c
, 0, sizeof(c
));
1117 c
.rw
.opcode
= io
.opcode
;
1118 c
.rw
.flags
= io
.flags
;
1119 c
.rw
.nsid
= cpu_to_le32(ns
->ns_id
);
1120 c
.rw
.slba
= cpu_to_le64(io
.slba
);
1121 c
.rw
.length
= cpu_to_le16(io
.nblocks
);
1122 c
.rw
.control
= cpu_to_le16(io
.control
);
1123 c
.rw
.dsmgmt
= cpu_to_le16(io
.dsmgmt
);
1124 c
.rw
.reftag
= io
.reftag
;
1125 c
.rw
.apptag
= io
.apptag
;
1126 c
.rw
.appmask
= io
.appmask
;
1128 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
, GFP_KERNEL
);
1130 nvmeq
= get_nvmeq(dev
);
1132 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1133 * disabled. We may be preempted at any point, and be rescheduled
1134 * to a different CPU. That will cause cacheline bouncing, but no
1135 * additional races since q_lock already protects against other CPUs.
1138 if (length
!= (io
.nblocks
+ 1) << ns
->lba_shift
)
1141 status
= nvme_submit_sync_cmd(nvmeq
, &c
, NULL
, NVME_IO_TIMEOUT
);
1143 nvme_unmap_user_pages(dev
, io
.opcode
& 1, iod
);
1144 nvme_free_iod(dev
, iod
);
1148 static int nvme_user_admin_cmd(struct nvme_ns
*ns
,
1149 struct nvme_admin_cmd __user
*ucmd
)
1151 struct nvme_dev
*dev
= ns
->dev
;
1152 struct nvme_admin_cmd cmd
;
1153 struct nvme_command c
;
1155 struct nvme_iod
*iod
;
1157 if (!capable(CAP_SYS_ADMIN
))
1159 if (copy_from_user(&cmd
, ucmd
, sizeof(cmd
)))
1162 memset(&c
, 0, sizeof(c
));
1163 c
.common
.opcode
= cmd
.opcode
;
1164 c
.common
.flags
= cmd
.flags
;
1165 c
.common
.nsid
= cpu_to_le32(cmd
.nsid
);
1166 c
.common
.cdw2
[0] = cpu_to_le32(cmd
.cdw2
);
1167 c
.common
.cdw2
[1] = cpu_to_le32(cmd
.cdw3
);
1168 c
.common
.cdw10
[0] = cpu_to_le32(cmd
.cdw10
);
1169 c
.common
.cdw10
[1] = cpu_to_le32(cmd
.cdw11
);
1170 c
.common
.cdw10
[2] = cpu_to_le32(cmd
.cdw12
);
1171 c
.common
.cdw10
[3] = cpu_to_le32(cmd
.cdw13
);
1172 c
.common
.cdw10
[4] = cpu_to_le32(cmd
.cdw14
);
1173 c
.common
.cdw10
[5] = cpu_to_le32(cmd
.cdw15
);
1175 length
= cmd
.data_len
;
1177 iod
= nvme_map_user_pages(dev
, cmd
.opcode
& 1, cmd
.addr
,
1180 return PTR_ERR(iod
);
1181 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
,
1185 if (length
!= cmd
.data_len
)
1188 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
1191 nvme_unmap_user_pages(dev
, cmd
.opcode
& 1, iod
);
1192 nvme_free_iod(dev
, iod
);
1197 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
1200 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
1205 case NVME_IOCTL_ADMIN_CMD
:
1206 return nvme_user_admin_cmd(ns
, (void __user
*)arg
);
1207 case NVME_IOCTL_SUBMIT_IO
:
1208 return nvme_submit_io(ns
, (void __user
*)arg
);
1214 static const struct block_device_operations nvme_fops
= {
1215 .owner
= THIS_MODULE
,
1216 .ioctl
= nvme_ioctl
,
1217 .compat_ioctl
= nvme_ioctl
,
1220 static void nvme_timeout_ios(struct nvme_queue
*nvmeq
)
1222 int depth
= nvmeq
->q_depth
- 1;
1223 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
1224 unsigned long now
= jiffies
;
1227 for_each_set_bit(cmdid
, nvmeq
->cmdid_data
, depth
) {
1229 nvme_completion_fn fn
;
1230 static struct nvme_completion cqe
= { .status
= cpu_to_le16(NVME_SC_ABORT_REQ
) << 1, };
1232 if (!time_after(now
, info
[cmdid
].timeout
))
1234 dev_warn(nvmeq
->q_dmadev
, "Timing out I/O %d\n", cmdid
);
1235 ctx
= cancel_cmdid(nvmeq
, cmdid
, &fn
);
1236 fn(nvmeq
->dev
, ctx
, &cqe
);
1240 static void nvme_resubmit_bios(struct nvme_queue
*nvmeq
)
1242 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1243 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1244 struct nvme_ns
*ns
= bio
->bi_bdev
->bd_disk
->private_data
;
1245 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
1246 bio_list_add_head(&nvmeq
->sq_cong
, bio
);
1249 if (bio_list_empty(&nvmeq
->sq_cong
))
1250 remove_wait_queue(&nvmeq
->sq_full
,
1251 &nvmeq
->sq_cong_wait
);
1255 static int nvme_kthread(void *data
)
1257 struct nvme_dev
*dev
;
1259 while (!kthread_should_stop()) {
1260 __set_current_state(TASK_RUNNING
);
1261 spin_lock(&dev_list_lock
);
1262 list_for_each_entry(dev
, &dev_list
, node
) {
1264 for (i
= 0; i
< dev
->queue_count
; i
++) {
1265 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1268 spin_lock_irq(&nvmeq
->q_lock
);
1269 if (nvme_process_cq(nvmeq
))
1270 printk("process_cq did something\n");
1271 nvme_timeout_ios(nvmeq
);
1272 nvme_resubmit_bios(nvmeq
);
1273 spin_unlock_irq(&nvmeq
->q_lock
);
1276 spin_unlock(&dev_list_lock
);
1277 set_current_state(TASK_INTERRUPTIBLE
);
1278 schedule_timeout(HZ
);
1283 static DEFINE_IDA(nvme_index_ida
);
1285 static int nvme_get_ns_idx(void)
1290 if (!ida_pre_get(&nvme_index_ida
, GFP_KERNEL
))
1293 spin_lock(&dev_list_lock
);
1294 error
= ida_get_new(&nvme_index_ida
, &index
);
1295 spin_unlock(&dev_list_lock
);
1296 } while (error
== -EAGAIN
);
1303 static void nvme_put_ns_idx(int index
)
1305 spin_lock(&dev_list_lock
);
1306 ida_remove(&nvme_index_ida
, index
);
1307 spin_unlock(&dev_list_lock
);
1310 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int nsid
,
1311 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
1314 struct gendisk
*disk
;
1317 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
1320 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
1323 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
1326 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
;
1327 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES
, ns
->queue
);
1328 queue_flag_set_unlocked(QUEUE_FLAG_NONROT
, ns
->queue
);
1329 /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1330 blk_queue_make_request(ns
->queue
, nvme_make_request
);
1332 ns
->queue
->queuedata
= ns
;
1334 disk
= alloc_disk(NVME_MINORS
);
1336 goto out_free_queue
;
1339 lbaf
= id
->flbas
& 0xf;
1340 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
1342 disk
->major
= nvme_major
;
1343 disk
->minors
= NVME_MINORS
;
1344 disk
->first_minor
= NVME_MINORS
* nvme_get_ns_idx();
1345 disk
->fops
= &nvme_fops
;
1346 disk
->private_data
= ns
;
1347 disk
->queue
= ns
->queue
;
1348 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
1349 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, nsid
);
1350 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
1355 blk_cleanup_queue(ns
->queue
);
1361 static void nvme_ns_free(struct nvme_ns
*ns
)
1363 int index
= ns
->disk
->first_minor
/ NVME_MINORS
;
1365 nvme_put_ns_idx(index
);
1366 blk_cleanup_queue(ns
->queue
);
1370 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1374 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1376 status
= nvme_set_features(dev
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1380 return min(result
& 0xffff, result
>> 16) + 1;
1383 static int __devinit
nvme_setup_io_queues(struct nvme_dev
*dev
)
1385 int result
, cpu
, i
, nr_io_queues
, db_bar_size
;
1387 nr_io_queues
= num_online_cpus();
1388 result
= set_queue_count(dev
, nr_io_queues
);
1391 if (result
< nr_io_queues
)
1392 nr_io_queues
= result
;
1394 /* Deregister the admin queue's interrupt */
1395 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
1397 db_bar_size
= 4096 + ((nr_io_queues
+ 1) << (dev
->db_stride
+ 3));
1398 if (db_bar_size
> 8192) {
1400 dev
->bar
= ioremap(pci_resource_start(dev
->pci_dev
, 0),
1402 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1403 dev
->queues
[0]->q_db
= dev
->dbs
;
1406 for (i
= 0; i
< nr_io_queues
; i
++)
1407 dev
->entry
[i
].entry
= i
;
1409 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
,
1413 } else if (result
> 0) {
1414 nr_io_queues
= result
;
1422 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1423 /* XXX: handle failure here */
1425 cpu
= cpumask_first(cpu_online_mask
);
1426 for (i
= 0; i
< nr_io_queues
; i
++) {
1427 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1428 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1431 for (i
= 0; i
< nr_io_queues
; i
++) {
1432 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1,
1434 if (IS_ERR(dev
->queues
[i
+ 1]))
1435 return PTR_ERR(dev
->queues
[i
+ 1]);
1439 for (; i
< num_possible_cpus(); i
++) {
1440 int target
= i
% rounddown_pow_of_two(dev
->queue_count
- 1);
1441 dev
->queues
[i
+ 1] = dev
->queues
[target
+ 1];
1447 static void nvme_free_queues(struct nvme_dev
*dev
)
1451 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1452 nvme_free_queue(dev
, i
);
1455 static int __devinit
nvme_dev_add(struct nvme_dev
*dev
)
1458 struct nvme_ns
*ns
, *next
;
1459 struct nvme_id_ctrl
*ctrl
;
1460 struct nvme_id_ns
*id_ns
;
1462 dma_addr_t dma_addr
;
1464 res
= nvme_setup_io_queues(dev
);
1468 mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1471 res
= nvme_identify(dev
, 0, 1, dma_addr
);
1478 nn
= le32_to_cpup(&ctrl
->nn
);
1479 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1480 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1481 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1484 for (i
= 1; i
<= nn
; i
++) {
1485 res
= nvme_identify(dev
, i
, 0, dma_addr
);
1489 if (id_ns
->ncap
== 0)
1492 res
= nvme_get_features(dev
, NVME_FEAT_LBA_RANGE
, i
,
1497 ns
= nvme_alloc_ns(dev
, i
, mem
, mem
+ 4096);
1499 list_add_tail(&ns
->list
, &dev
->namespaces
);
1501 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1507 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1508 list_del(&ns
->list
);
1513 dma_free_coherent(&dev
->pci_dev
->dev
, 8192, mem
, dma_addr
);
1517 static int nvme_dev_remove(struct nvme_dev
*dev
)
1519 struct nvme_ns
*ns
, *next
;
1521 spin_lock(&dev_list_lock
);
1522 list_del(&dev
->node
);
1523 spin_unlock(&dev_list_lock
);
1525 /* TODO: wait all I/O finished or cancel them */
1527 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1528 list_del(&ns
->list
);
1529 del_gendisk(ns
->disk
);
1533 nvme_free_queues(dev
);
1538 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1540 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1541 dev
->prp_page_pool
= dma_pool_create("prp list page", dmadev
,
1542 PAGE_SIZE
, PAGE_SIZE
, 0);
1543 if (!dev
->prp_page_pool
)
1546 /* Optimisation for I/Os between 4k and 128k */
1547 dev
->prp_small_pool
= dma_pool_create("prp list 256", dmadev
,
1549 if (!dev
->prp_small_pool
) {
1550 dma_pool_destroy(dev
->prp_page_pool
);
1556 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1558 dma_pool_destroy(dev
->prp_page_pool
);
1559 dma_pool_destroy(dev
->prp_small_pool
);
1562 /* XXX: Use an ida or something to let remove / add work correctly */
1563 static void nvme_set_instance(struct nvme_dev
*dev
)
1565 static int instance
;
1566 dev
->instance
= instance
++;
1569 static void nvme_release_instance(struct nvme_dev
*dev
)
1573 static int __devinit
nvme_probe(struct pci_dev
*pdev
,
1574 const struct pci_device_id
*id
)
1576 int bars
, result
= -ENOMEM
;
1577 struct nvme_dev
*dev
;
1579 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1582 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1586 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1591 if (pci_enable_device_mem(pdev
))
1593 pci_set_master(pdev
);
1594 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1595 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1598 INIT_LIST_HEAD(&dev
->namespaces
);
1599 dev
->pci_dev
= pdev
;
1600 pci_set_drvdata(pdev
, dev
);
1601 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1602 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1603 nvme_set_instance(dev
);
1604 dev
->entry
[0].vector
= pdev
->irq
;
1606 result
= nvme_setup_prp_pools(dev
);
1610 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1616 result
= nvme_configure_admin_queue(dev
);
1621 spin_lock(&dev_list_lock
);
1622 list_add(&dev
->node
, &dev_list
);
1623 spin_unlock(&dev_list_lock
);
1625 result
= nvme_dev_add(dev
);
1632 spin_lock(&dev_list_lock
);
1633 list_del(&dev
->node
);
1634 spin_unlock(&dev_list_lock
);
1636 nvme_free_queues(dev
);
1640 pci_disable_msix(pdev
);
1641 nvme_release_instance(dev
);
1642 nvme_release_prp_pools(dev
);
1644 pci_disable_device(pdev
);
1645 pci_release_regions(pdev
);
1653 static void __devexit
nvme_remove(struct pci_dev
*pdev
)
1655 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1656 nvme_dev_remove(dev
);
1657 pci_disable_msix(pdev
);
1659 nvme_release_instance(dev
);
1660 nvme_release_prp_pools(dev
);
1661 pci_disable_device(pdev
);
1662 pci_release_regions(pdev
);
1668 /* These functions are yet to be implemented */
1669 #define nvme_error_detected NULL
1670 #define nvme_dump_registers NULL
1671 #define nvme_link_reset NULL
1672 #define nvme_slot_reset NULL
1673 #define nvme_error_resume NULL
1674 #define nvme_suspend NULL
1675 #define nvme_resume NULL
1677 static struct pci_error_handlers nvme_err_handler
= {
1678 .error_detected
= nvme_error_detected
,
1679 .mmio_enabled
= nvme_dump_registers
,
1680 .link_reset
= nvme_link_reset
,
1681 .slot_reset
= nvme_slot_reset
,
1682 .resume
= nvme_error_resume
,
1685 /* Move to pci_ids.h later */
1686 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1688 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
1689 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
1692 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
1694 static struct pci_driver nvme_driver
= {
1696 .id_table
= nvme_id_table
,
1697 .probe
= nvme_probe
,
1698 .remove
= __devexit_p(nvme_remove
),
1699 .suspend
= nvme_suspend
,
1700 .resume
= nvme_resume
,
1701 .err_handler
= &nvme_err_handler
,
1704 static int __init
nvme_init(void)
1706 int result
= -EBUSY
;
1708 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1709 if (IS_ERR(nvme_thread
))
1710 return PTR_ERR(nvme_thread
);
1712 nvme_major
= register_blkdev(nvme_major
, "nvme");
1713 if (nvme_major
<= 0)
1716 result
= pci_register_driver(&nvme_driver
);
1718 goto unregister_blkdev
;
1722 unregister_blkdev(nvme_major
, "nvme");
1724 kthread_stop(nvme_thread
);
1728 static void __exit
nvme_exit(void)
1730 pci_unregister_driver(&nvme_driver
);
1731 unregister_blkdev(nvme_major
, "nvme");
1732 kthread_stop(nvme_thread
);
1735 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1736 MODULE_LICENSE("GPL");
1737 MODULE_VERSION("0.8");
1738 module_init(nvme_init
);
1739 module_exit(nvme_exit
);