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sfc: Move Falcon NIC operations to efx_nic_type
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sfc / falcon.c
blobf6d10213d0b7fcde5053d23e9248ee3751a72267
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include "net_driver.h"
19 #include "bitfield.h"
20 #include "efx.h"
21 #include "mac.h"
22 #include "spi.h"
23 #include "falcon.h"
24 #include "regs.h"
25 #include "io.h"
26 #include "mdio_10g.h"
27 #include "phy.h"
28 #include "workarounds.h"
29
30 /* Hardware control for SFC4000 (aka Falcon). */
31
32 /**************************************************************************
33 *
34 * Configurable values
35 *
36 **************************************************************************
37 */
38
39 /* This is set to 16 for a good reason. In summary, if larger than
40 * 16, the descriptor cache holds more than a default socket
41 * buffer's worth of packets (for UDP we can only have at most one
42 * socket buffer's worth outstanding). This combined with the fact
43 * that we only get 1 TX event per descriptor cache means the NIC
44 * goes idle.
45 */
46 #define TX_DC_ENTRIES 16
47 #define TX_DC_ENTRIES_ORDER 1
48
49 #define RX_DC_ENTRIES 64
50 #define RX_DC_ENTRIES_ORDER 3
51
52 static const unsigned int
53 /* "Large" EEPROM device: Atmel AT25640 or similar
54 * 8 KB, 16-bit address, 32 B write block */
55 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
56 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
57 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
58 /* Default flash device: Atmel AT25F1024
59 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
60 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
61 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
62 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
63 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
64 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
65
66 /* RX FIFO XOFF watermark
67 *
68 * When the amount of the RX FIFO increases used increases past this
69 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
70 * This also has an effect on RX/TX arbitration
71 */
72 static int rx_xoff_thresh_bytes = -1;
73 module_param(rx_xoff_thresh_bytes, int, 0644);
74 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
75
76 /* RX FIFO XON watermark
77 *
78 * When the amount of the RX FIFO used decreases below this
79 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
80 * This also has an effect on RX/TX arbitration
81 */
82 static int rx_xon_thresh_bytes = -1;
83 module_param(rx_xon_thresh_bytes, int, 0644);
84 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
85
86 /* If FALCON_MAX_INT_ERRORS internal errors occur within
87 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
88 * disable it.
89 */
90 #define FALCON_INT_ERROR_EXPIRE 3600
91 #define FALCON_MAX_INT_ERRORS 5
92
93 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
94 */
95 #define FALCON_FLUSH_INTERVAL 10
96 #define FALCON_FLUSH_POLL_COUNT 100
97
98 /**************************************************************************
99 *
100 * Falcon constants
101 *
102 **************************************************************************
103 */
104
105 /* Size and alignment of special buffers (4KB) */
106 #define FALCON_BUF_SIZE 4096
107
108 /* Depth of RX flush request fifo */
109 #define FALCON_RX_FLUSH_COUNT 4
110
111 #define FALCON_IS_DUAL_FUNC(efx) \
112 (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
113
114 /**************************************************************************
115 *
116 * Falcon hardware access
117 *
118 **************************************************************************/
119
120 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
121 unsigned int index)
122 {
123 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
124 value, index);
125 }
126
127 /* Read the current event from the event queue */
128 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
129 unsigned int index)
130 {
131 return (((efx_qword_t *) (channel->eventq.addr)) + index);
132 }
133
134 /* See if an event is present
135 *
136 * We check both the high and low dword of the event for all ones. We
137 * wrote all ones when we cleared the event, and no valid event can
138 * have all ones in either its high or low dwords. This approach is
139 * robust against reordering.
140 *
141 * Note that using a single 64-bit comparison is incorrect; even
142 * though the CPU read will be atomic, the DMA write may not be.
143 */
144 static inline int falcon_event_present(efx_qword_t *event)
145 {
146 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
147 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
148 }
149
150 /**************************************************************************
151 *
152 * I2C bus - this is a bit-bashing interface using GPIO pins
153 * Note that it uses the output enables to tristate the outputs
154 * SDA is the data pin and SCL is the clock
155 *
156 **************************************************************************
157 */
158 static void falcon_setsda(void *data, int state)
159 {
160 struct efx_nic *efx = (struct efx_nic *)data;
161 efx_oword_t reg;
162
163 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
164 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
165 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
166 }
167
168 static void falcon_setscl(void *data, int state)
169 {
170 struct efx_nic *efx = (struct efx_nic *)data;
171 efx_oword_t reg;
172
173 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
174 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
175 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
176 }
177
178 static int falcon_getsda(void *data)
179 {
180 struct efx_nic *efx = (struct efx_nic *)data;
181 efx_oword_t reg;
182
183 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
184 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
185 }
186
187 static int falcon_getscl(void *data)
188 {
189 struct efx_nic *efx = (struct efx_nic *)data;
190 efx_oword_t reg;
191
192 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
193 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
194 }
195
196 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
197 .setsda = falcon_setsda,
198 .setscl = falcon_setscl,
199 .getsda = falcon_getsda,
200 .getscl = falcon_getscl,
201 .udelay = 5,
202 /* Wait up to 50 ms for slave to let us pull SCL high */
203 .timeout = DIV_ROUND_UP(HZ, 20),
204 };
205
206 /**************************************************************************
207 *
208 * Falcon special buffer handling
209 * Special buffers are used for event queues and the TX and RX
210 * descriptor rings.
211 *
212 *************************************************************************/
213
214 /*
215 * Initialise a Falcon special buffer
216 *
217 * This will define a buffer (previously allocated via
218 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
219 * it to be used for event queues, descriptor rings etc.
220 */
221 static void
222 falcon_init_special_buffer(struct efx_nic *efx,
223 struct efx_special_buffer *buffer)
224 {
225 efx_qword_t buf_desc;
226 int index;
227 dma_addr_t dma_addr;
228 int i;
229
230 EFX_BUG_ON_PARANOID(!buffer->addr);
231
232 /* Write buffer descriptors to NIC */
233 for (i = 0; i < buffer->entries; i++) {
234 index = buffer->index + i;
235 dma_addr = buffer->dma_addr + (i * 4096);
236 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
237 index, (unsigned long long)dma_addr);
238 EFX_POPULATE_QWORD_3(buf_desc,
239 FRF_AZ_BUF_ADR_REGION, 0,
240 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
241 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
242 falcon_write_buf_tbl(efx, &buf_desc, index);
243 }
244 }
245
246 /* Unmaps a buffer from Falcon and clears the buffer table entries */
247 static void
248 falcon_fini_special_buffer(struct efx_nic *efx,
249 struct efx_special_buffer *buffer)
250 {
251 efx_oword_t buf_tbl_upd;
252 unsigned int start = buffer->index;
253 unsigned int end = (buffer->index + buffer->entries - 1);
254
255 if (!buffer->entries)
256 return;
257
258 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
259 buffer->index, buffer->index + buffer->entries - 1);
260
261 EFX_POPULATE_OWORD_4(buf_tbl_upd,
262 FRF_AZ_BUF_UPD_CMD, 0,
263 FRF_AZ_BUF_CLR_CMD, 1,
264 FRF_AZ_BUF_CLR_END_ID, end,
265 FRF_AZ_BUF_CLR_START_ID, start);
266 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
267 }
268
269 /*
270 * Allocate a new Falcon special buffer
271 *
272 * This allocates memory for a new buffer, clears it and allocates a
273 * new buffer ID range. It does not write into Falcon's buffer table.
274 *
275 * This call will allocate 4KB buffers, since Falcon can't use 8KB
276 * buffers for event queues and descriptor rings.
277 */
278 static int falcon_alloc_special_buffer(struct efx_nic *efx,
279 struct efx_special_buffer *buffer,
280 unsigned int len)
281 {
282 len = ALIGN(len, FALCON_BUF_SIZE);
283
284 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
285 &buffer->dma_addr);
286 if (!buffer->addr)
287 return -ENOMEM;
288 buffer->len = len;
289 buffer->entries = len / FALCON_BUF_SIZE;
290 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
291
292 /* All zeros is a potentially valid event so memset to 0xff */
293 memset(buffer->addr, 0xff, len);
294
295 /* Select new buffer ID */
296 buffer->index = efx->next_buffer_table;
297 efx->next_buffer_table += buffer->entries;
298
299 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
300 "(virt %p phys %llx)\n", buffer->index,
301 buffer->index + buffer->entries - 1,
302 (u64)buffer->dma_addr, len,
303 buffer->addr, (u64)virt_to_phys(buffer->addr));
304
305 return 0;
306 }
307
308 static void falcon_free_special_buffer(struct efx_nic *efx,
309 struct efx_special_buffer *buffer)
310 {
311 if (!buffer->addr)
312 return;
313
314 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
315 "(virt %p phys %llx)\n", buffer->index,
316 buffer->index + buffer->entries - 1,
317 (u64)buffer->dma_addr, buffer->len,
318 buffer->addr, (u64)virt_to_phys(buffer->addr));
319
320 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
321 buffer->dma_addr);
322 buffer->addr = NULL;
323 buffer->entries = 0;
324 }
325
326 /**************************************************************************
327 *
328 * Falcon generic buffer handling
329 * These buffers are used for interrupt status and MAC stats
330 *
331 **************************************************************************/
332
333 static int falcon_alloc_buffer(struct efx_nic *efx,
334 struct efx_buffer *buffer, unsigned int len)
335 {
336 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
337 &buffer->dma_addr);
338 if (!buffer->addr)
339 return -ENOMEM;
340 buffer->len = len;
341 memset(buffer->addr, 0, len);
342 return 0;
343 }
344
345 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
346 {
347 if (buffer->addr) {
348 pci_free_consistent(efx->pci_dev, buffer->len,
349 buffer->addr, buffer->dma_addr);
350 buffer->addr = NULL;
351 }
352 }
353
354 /**************************************************************************
355 *
356 * Falcon TX path
357 *
358 **************************************************************************/
359
360 /* Returns a pointer to the specified transmit descriptor in the TX
361 * descriptor queue belonging to the specified channel.
362 */
363 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
364 unsigned int index)
365 {
366 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
367 }
368
369 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
370 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
371 {
372 unsigned write_ptr;
373 efx_dword_t reg;
374
375 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
376 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
377 efx_writed_page(tx_queue->efx, &reg,
378 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
379 }
380
381
382 /* For each entry inserted into the software descriptor ring, create a
383 * descriptor in the hardware TX descriptor ring (in host memory), and
384 * write a doorbell.
385 */
386 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
387 {
388
389 struct efx_tx_buffer *buffer;
390 efx_qword_t *txd;
391 unsigned write_ptr;
392
393 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
394
395 do {
396 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
397 buffer = &tx_queue->buffer[write_ptr];
398 txd = falcon_tx_desc(tx_queue, write_ptr);
399 ++tx_queue->write_count;
400
401 /* Create TX descriptor ring entry */
402 EFX_POPULATE_QWORD_4(*txd,
403 FSF_AZ_TX_KER_CONT, buffer->continuation,
404 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
405 FSF_AZ_TX_KER_BUF_REGION, 0,
406 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
407 } while (tx_queue->write_count != tx_queue->insert_count);
408
409 wmb(); /* Ensure descriptors are written before they are fetched */
410 falcon_notify_tx_desc(tx_queue);
411 }
412
413 /* Allocate hardware resources for a TX queue */
414 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
415 {
416 struct efx_nic *efx = tx_queue->efx;
417 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
418 EFX_TXQ_SIZE & EFX_TXQ_MASK);
419 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
420 EFX_TXQ_SIZE * sizeof(efx_qword_t));
421 }
422
423 void falcon_init_tx(struct efx_tx_queue *tx_queue)
424 {
425 efx_oword_t tx_desc_ptr;
426 struct efx_nic *efx = tx_queue->efx;
427
428 tx_queue->flushed = FLUSH_NONE;
429
430 /* Pin TX descriptor ring */
431 falcon_init_special_buffer(efx, &tx_queue->txd);
432
433 /* Push TX descriptor ring to card */
434 EFX_POPULATE_OWORD_10(tx_desc_ptr,
435 FRF_AZ_TX_DESCQ_EN, 1,
436 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
437 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
438 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
439 FRF_AZ_TX_DESCQ_EVQ_ID,
440 tx_queue->channel->channel,
441 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
442 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
443 FRF_AZ_TX_DESCQ_SIZE,
444 __ffs(tx_queue->txd.entries),
445 FRF_AZ_TX_DESCQ_TYPE, 0,
446 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
447
448 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
449 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
450 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
451 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
452 !csum);
453 }
454
455 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
456 tx_queue->queue);
457
458 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
459 efx_oword_t reg;
460
461 /* Only 128 bits in this register */
462 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
463
464 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
465 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
466 clear_bit_le(tx_queue->queue, (void *)&reg);
467 else
468 set_bit_le(tx_queue->queue, (void *)&reg);
469 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
470 }
471 }
472
473 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
474 {
475 struct efx_nic *efx = tx_queue->efx;
476 efx_oword_t tx_flush_descq;
477
478 tx_queue->flushed = FLUSH_PENDING;
479
480 /* Post a flush command */
481 EFX_POPULATE_OWORD_2(tx_flush_descq,
482 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
483 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
484 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
485 }
486
487 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
488 {
489 struct efx_nic *efx = tx_queue->efx;
490 efx_oword_t tx_desc_ptr;
491
492 /* The queue should have been flushed */
493 WARN_ON(tx_queue->flushed != FLUSH_DONE);
494
495 /* Remove TX descriptor ring from card */
496 EFX_ZERO_OWORD(tx_desc_ptr);
497 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
498 tx_queue->queue);
499
500 /* Unpin TX descriptor ring */
501 falcon_fini_special_buffer(efx, &tx_queue->txd);
502 }
503
504 /* Free buffers backing TX queue */
505 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
506 {
507 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
508 }
509
510 /**************************************************************************
511 *
512 * Falcon RX path
513 *
514 **************************************************************************/
515
516 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
517 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
518 unsigned int index)
519 {
520 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
521 }
522
523 /* This creates an entry in the RX descriptor queue */
524 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
525 unsigned index)
526 {
527 struct efx_rx_buffer *rx_buf;
528 efx_qword_t *rxd;
529
530 rxd = falcon_rx_desc(rx_queue, index);
531 rx_buf = efx_rx_buffer(rx_queue, index);
532 EFX_POPULATE_QWORD_3(*rxd,
533 FSF_AZ_RX_KER_BUF_SIZE,
534 rx_buf->len -
535 rx_queue->efx->type->rx_buffer_padding,
536 FSF_AZ_RX_KER_BUF_REGION, 0,
537 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
538 }
539
540 /* This writes to the RX_DESC_WPTR register for the specified receive
541 * descriptor ring.
542 */
543 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
544 {
545 efx_dword_t reg;
546 unsigned write_ptr;
547
548 while (rx_queue->notified_count != rx_queue->added_count) {
549 falcon_build_rx_desc(rx_queue,
550 rx_queue->notified_count &
551 EFX_RXQ_MASK);
552 ++rx_queue->notified_count;
553 }
554
555 wmb();
556 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
557 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
558 efx_writed_page(rx_queue->efx, &reg,
559 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
560 }
561
562 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
563 {
564 struct efx_nic *efx = rx_queue->efx;
565 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
566 EFX_RXQ_SIZE & EFX_RXQ_MASK);
567 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
568 EFX_RXQ_SIZE * sizeof(efx_qword_t));
569 }
570
571 void falcon_init_rx(struct efx_rx_queue *rx_queue)
572 {
573 efx_oword_t rx_desc_ptr;
574 struct efx_nic *efx = rx_queue->efx;
575 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
576 bool iscsi_digest_en = is_b0;
577
578 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
579 rx_queue->queue, rx_queue->rxd.index,
580 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
581
582 rx_queue->flushed = FLUSH_NONE;
583
584 /* Pin RX descriptor ring */
585 falcon_init_special_buffer(efx, &rx_queue->rxd);
586
587 /* Push RX descriptor ring to card */
588 EFX_POPULATE_OWORD_10(rx_desc_ptr,
589 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
590 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
591 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
592 FRF_AZ_RX_DESCQ_EVQ_ID,
593 rx_queue->channel->channel,
594 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
595 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
596 FRF_AZ_RX_DESCQ_SIZE,
597 __ffs(rx_queue->rxd.entries),
598 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
599 /* For >=B0 this is scatter so disable */
600 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
601 FRF_AZ_RX_DESCQ_EN, 1);
602 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
603 rx_queue->queue);
604 }
605
606 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
607 {
608 struct efx_nic *efx = rx_queue->efx;
609 efx_oword_t rx_flush_descq;
610
611 rx_queue->flushed = FLUSH_PENDING;
612
613 /* Post a flush command */
614 EFX_POPULATE_OWORD_2(rx_flush_descq,
615 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
616 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
617 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
618 }
619
620 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
621 {
622 efx_oword_t rx_desc_ptr;
623 struct efx_nic *efx = rx_queue->efx;
624
625 /* The queue should already have been flushed */
626 WARN_ON(rx_queue->flushed != FLUSH_DONE);
627
628 /* Remove RX descriptor ring from card */
629 EFX_ZERO_OWORD(rx_desc_ptr);
630 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
631 rx_queue->queue);
632
633 /* Unpin RX descriptor ring */
634 falcon_fini_special_buffer(efx, &rx_queue->rxd);
635 }
636
637 /* Free buffers backing RX queue */
638 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
639 {
640 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
641 }
642
643 /**************************************************************************
644 *
645 * Falcon event queue processing
646 * Event queues are processed by per-channel tasklets.
647 *
648 **************************************************************************/
649
650 /* Update a channel's event queue's read pointer (RPTR) register
651 *
652 * This writes the EVQ_RPTR_REG register for the specified channel's
653 * event queue.
654 *
655 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
656 * whereas channel->eventq_read_ptr contains the index of the "next to
657 * read" event.
658 */
659 void falcon_eventq_read_ack(struct efx_channel *channel)
660 {
661 efx_dword_t reg;
662 struct efx_nic *efx = channel->efx;
663
664 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
665 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
666 channel->channel);
667 }
668
669 /* Use HW to insert a SW defined event */
670 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
671 {
672 efx_oword_t drv_ev_reg;
673
674 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
675 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
676 drv_ev_reg.u32[0] = event->u32[0];
677 drv_ev_reg.u32[1] = event->u32[1];
678 drv_ev_reg.u32[2] = 0;
679 drv_ev_reg.u32[3] = 0;
680 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
681 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
682 }
683
684 /* Handle a transmit completion event
685 *
686 * Falcon batches TX completion events; the message we receive is of
687 * the form "complete all TX events up to this index".
688 */
689 static void falcon_handle_tx_event(struct efx_channel *channel,
690 efx_qword_t *event)
691 {
692 unsigned int tx_ev_desc_ptr;
693 unsigned int tx_ev_q_label;
694 struct efx_tx_queue *tx_queue;
695 struct efx_nic *efx = channel->efx;
696
697 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
698 /* Transmit completion */
699 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
700 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
701 tx_queue = &efx->tx_queue[tx_ev_q_label];
702 channel->irq_mod_score +=
703 (tx_ev_desc_ptr - tx_queue->read_count) &
704 EFX_TXQ_MASK;
705 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
706 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
707 /* Rewrite the FIFO write pointer */
708 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
709 tx_queue = &efx->tx_queue[tx_ev_q_label];
710
711 if (efx_dev_registered(efx))
712 netif_tx_lock(efx->net_dev);
713 falcon_notify_tx_desc(tx_queue);
714 if (efx_dev_registered(efx))
715 netif_tx_unlock(efx->net_dev);
716 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
717 EFX_WORKAROUND_10727(efx)) {
718 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
719 } else {
720 EFX_ERR(efx, "channel %d unexpected TX event "
721 EFX_QWORD_FMT"\n", channel->channel,
722 EFX_QWORD_VAL(*event));
723 }
724 }
725
726 /* Detect errors included in the rx_evt_pkt_ok bit. */
727 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
728 const efx_qword_t *event,
729 bool *rx_ev_pkt_ok,
730 bool *discard)
731 {
732 struct efx_nic *efx = rx_queue->efx;
733 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
734 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
735 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
736 bool rx_ev_other_err, rx_ev_pause_frm;
737 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
738 unsigned rx_ev_pkt_type;
739
740 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
741 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
742 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
743 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
744 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
745 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
746 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
747 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
748 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
749 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
750 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
751 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
752 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
753 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
754 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
755
756 /* Every error apart from tobe_disc and pause_frm */
757 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
758 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
759 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
760
761 /* Count errors that are not in MAC stats. Ignore expected
762 * checksum errors during self-test. */
763 if (rx_ev_frm_trunc)
764 ++rx_queue->channel->n_rx_frm_trunc;
765 else if (rx_ev_tobe_disc)
766 ++rx_queue->channel->n_rx_tobe_disc;
767 else if (!efx->loopback_selftest) {
768 if (rx_ev_ip_hdr_chksum_err)
769 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
770 else if (rx_ev_tcp_udp_chksum_err)
771 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
772 }
773
774 /* The frame must be discarded if any of these are true. */
775 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
776 rx_ev_tobe_disc | rx_ev_pause_frm);
777
778 /* TOBE_DISC is expected on unicast mismatches; don't print out an
779 * error message. FRM_TRUNC indicates RXDP dropped the packet due
780 * to a FIFO overflow.
781 */
782 #ifdef EFX_ENABLE_DEBUG
783 if (rx_ev_other_err) {
784 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
785 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
786 rx_queue->queue, EFX_QWORD_VAL(*event),
787 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
788 rx_ev_ip_hdr_chksum_err ?
789 " [IP_HDR_CHKSUM_ERR]" : "",
790 rx_ev_tcp_udp_chksum_err ?
791 " [TCP_UDP_CHKSUM_ERR]" : "",
792 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
793 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
794 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
795 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
796 rx_ev_pause_frm ? " [PAUSE]" : "");
797 }
798 #endif
799 }
800
801 /* Handle receive events that are not in-order. */
802 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
803 unsigned index)
804 {
805 struct efx_nic *efx = rx_queue->efx;
806 unsigned expected, dropped;
807
808 expected = rx_queue->removed_count & EFX_RXQ_MASK;
809 dropped = (index - expected) & EFX_RXQ_MASK;
810 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
811 dropped, index, expected);
812
813 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
814 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
815 }
816
817 /* Handle a packet received event
818 *
819 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
820 * wrong destination address
821 * Also "is multicast" and "matches multicast filter" flags can be used to
822 * discard non-matching multicast packets.
823 */
824 static void falcon_handle_rx_event(struct efx_channel *channel,
825 const efx_qword_t *event)
826 {
827 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
828 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
829 unsigned expected_ptr;
830 bool rx_ev_pkt_ok, discard = false, checksummed;
831 struct efx_rx_queue *rx_queue;
832 struct efx_nic *efx = channel->efx;
833
834 /* Basic packet information */
835 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
836 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
837 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
838 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
839 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
840 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
841 channel->channel);
842
843 rx_queue = &efx->rx_queue[channel->channel];
844
845 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
846 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
847 if (unlikely(rx_ev_desc_ptr != expected_ptr))
848 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
849
850 if (likely(rx_ev_pkt_ok)) {
851 /* If packet is marked as OK and packet type is TCP/IPv4 or
852 * UDP/IPv4, then we can rely on the hardware checksum.
853 */
854 checksummed =
855 likely(efx->rx_checksum_enabled) &&
856 (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
857 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
858 } else {
859 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
860 &discard);
861 checksummed = false;
862 }
863
864 /* Detect multicast packets that didn't match the filter */
865 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
866 if (rx_ev_mcast_pkt) {
867 unsigned int rx_ev_mcast_hash_match =
868 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
869
870 if (unlikely(!rx_ev_mcast_hash_match)) {
871 ++channel->n_rx_mcast_mismatch;
872 discard = true;
873 }
874 }
875
876 channel->irq_mod_score += 2;
877
878 /* Handle received packet */
879 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
880 checksummed, discard);
881 }
882
883 /* Global events are basically PHY events */
884 static void falcon_handle_global_event(struct efx_channel *channel,
885 efx_qword_t *event)
886 {
887 struct efx_nic *efx = channel->efx;
888 bool handled = false;
889
890 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
891 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
892 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
893 /* Ignored */
894 handled = true;
895 }
896
897 if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
898 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
899 efx->xmac_poll_required = true;
900 handled = true;
901 }
902
903 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
904 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
905 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
906 EFX_ERR(efx, "channel %d seen global RX_RESET "
907 "event. Resetting.\n", channel->channel);
908
909 atomic_inc(&efx->rx_reset);
910 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
911 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
912 handled = true;
913 }
914
915 if (!handled)
916 EFX_ERR(efx, "channel %d unknown global event "
917 EFX_QWORD_FMT "\n", channel->channel,
918 EFX_QWORD_VAL(*event));
919 }
920
921 static void falcon_handle_driver_event(struct efx_channel *channel,
922 efx_qword_t *event)
923 {
924 struct efx_nic *efx = channel->efx;
925 unsigned int ev_sub_code;
926 unsigned int ev_sub_data;
927
928 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
929 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
930
931 switch (ev_sub_code) {
932 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
933 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
934 channel->channel, ev_sub_data);
935 break;
936 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
937 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
938 channel->channel, ev_sub_data);
939 break;
940 case FSE_AZ_EVQ_INIT_DONE_EV:
941 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
942 channel->channel, ev_sub_data);
943 break;
944 case FSE_AZ_SRM_UPD_DONE_EV:
945 EFX_TRACE(efx, "channel %d SRAM update done\n",
946 channel->channel);
947 break;
948 case FSE_AZ_WAKE_UP_EV:
949 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
950 channel->channel, ev_sub_data);
951 break;
952 case FSE_AZ_TIMER_EV:
953 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
954 channel->channel, ev_sub_data);
955 break;
956 case FSE_AA_RX_RECOVER_EV:
957 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
958 "Resetting.\n", channel->channel);
959 atomic_inc(&efx->rx_reset);
960 efx_schedule_reset(efx,
961 EFX_WORKAROUND_6555(efx) ?
962 RESET_TYPE_RX_RECOVERY :
963 RESET_TYPE_DISABLE);
964 break;
965 case FSE_BZ_RX_DSC_ERROR_EV:
966 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
967 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
968 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
969 break;
970 case FSE_BZ_TX_DSC_ERROR_EV:
971 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
972 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
973 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
974 break;
975 default:
976 EFX_TRACE(efx, "channel %d unknown driver event code %d "
977 "data %04x\n", channel->channel, ev_sub_code,
978 ev_sub_data);
979 break;
980 }
981 }
982
983 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
984 {
985 unsigned int read_ptr;
986 efx_qword_t event, *p_event;
987 int ev_code;
988 int rx_packets = 0;
989
990 read_ptr = channel->eventq_read_ptr;
991
992 do {
993 p_event = falcon_event(channel, read_ptr);
994 event = *p_event;
995
996 if (!falcon_event_present(&event))
997 /* End of events */
998 break;
999
1000 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1001 channel->channel, EFX_QWORD_VAL(event));
1002
1003 /* Clear this event by marking it all ones */
1004 EFX_SET_QWORD(*p_event);
1005
1006 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1007
1008 switch (ev_code) {
1009 case FSE_AZ_EV_CODE_RX_EV:
1010 falcon_handle_rx_event(channel, &event);
1011 ++rx_packets;
1012 break;
1013 case FSE_AZ_EV_CODE_TX_EV:
1014 falcon_handle_tx_event(channel, &event);
1015 break;
1016 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1017 channel->eventq_magic = EFX_QWORD_FIELD(
1018 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1019 EFX_LOG(channel->efx, "channel %d received generated "
1020 "event "EFX_QWORD_FMT"\n", channel->channel,
1021 EFX_QWORD_VAL(event));
1022 break;
1023 case FSE_AZ_EV_CODE_GLOBAL_EV:
1024 falcon_handle_global_event(channel, &event);
1025 break;
1026 case FSE_AZ_EV_CODE_DRIVER_EV:
1027 falcon_handle_driver_event(channel, &event);
1028 break;
1029 default:
1030 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1031 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1032 ev_code, EFX_QWORD_VAL(event));
1033 }
1034
1035 /* Increment read pointer */
1036 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1037
1038 } while (rx_packets < rx_quota);
1039
1040 channel->eventq_read_ptr = read_ptr;
1041 return rx_packets;
1042 }
1043
1044 static void falcon_push_irq_moderation(struct efx_channel *channel)
1045 {
1046 efx_dword_t timer_cmd;
1047 struct efx_nic *efx = channel->efx;
1048
1049 /* Set timer register */
1050 if (channel->irq_moderation) {
1051 EFX_POPULATE_DWORD_2(timer_cmd,
1052 FRF_AB_TC_TIMER_MODE,
1053 FFE_BB_TIMER_MODE_INT_HLDOFF,
1054 FRF_AB_TC_TIMER_VAL,
1055 channel->irq_moderation - 1);
1056 } else {
1057 EFX_POPULATE_DWORD_2(timer_cmd,
1058 FRF_AB_TC_TIMER_MODE,
1059 FFE_BB_TIMER_MODE_DIS,
1060 FRF_AB_TC_TIMER_VAL, 0);
1061 }
1062 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1063 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1064 channel->channel);
1065
1066 }
1067
1068 /* Allocate buffer table entries for event queue */
1069 int falcon_probe_eventq(struct efx_channel *channel)
1070 {
1071 struct efx_nic *efx = channel->efx;
1072 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1073 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1074 return falcon_alloc_special_buffer(efx, &channel->eventq,
1075 EFX_EVQ_SIZE * sizeof(efx_qword_t));
1076 }
1077
1078 void falcon_init_eventq(struct efx_channel *channel)
1079 {
1080 efx_oword_t evq_ptr;
1081 struct efx_nic *efx = channel->efx;
1082
1083 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1084 channel->channel, channel->eventq.index,
1085 channel->eventq.index + channel->eventq.entries - 1);
1086
1087 /* Pin event queue buffer */
1088 falcon_init_special_buffer(efx, &channel->eventq);
1089
1090 /* Fill event queue with all ones (i.e. empty events) */
1091 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1092
1093 /* Push event queue to card */
1094 EFX_POPULATE_OWORD_3(evq_ptr,
1095 FRF_AZ_EVQ_EN, 1,
1096 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1097 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1098 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1099 channel->channel);
1100
1101 falcon_push_irq_moderation(channel);
1102 }
1103
1104 void falcon_fini_eventq(struct efx_channel *channel)
1105 {
1106 efx_oword_t eventq_ptr;
1107 struct efx_nic *efx = channel->efx;
1108
1109 /* Remove event queue from card */
1110 EFX_ZERO_OWORD(eventq_ptr);
1111 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1112 channel->channel);
1113
1114 /* Unpin event queue */
1115 falcon_fini_special_buffer(efx, &channel->eventq);
1116 }
1117
1118 /* Free buffers backing event queue */
1119 void falcon_remove_eventq(struct efx_channel *channel)
1120 {
1121 falcon_free_special_buffer(channel->efx, &channel->eventq);
1122 }
1123
1124
1125 /* Generates a test event on the event queue. A subsequent call to
1126 * process_eventq() should pick up the event and place the value of
1127 * "magic" into channel->eventq_magic;
1128 */
1129 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1130 {
1131 efx_qword_t test_event;
1132
1133 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1134 FSE_AZ_EV_CODE_DRV_GEN_EV,
1135 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1136 falcon_generate_event(channel, &test_event);
1137 }
1138
1139 /**************************************************************************
1140 *
1141 * Flush handling
1142 *
1143 **************************************************************************/
1144
1145
1146 static void falcon_poll_flush_events(struct efx_nic *efx)
1147 {
1148 struct efx_channel *channel = &efx->channel[0];
1149 struct efx_tx_queue *tx_queue;
1150 struct efx_rx_queue *rx_queue;
1151 unsigned int read_ptr = channel->eventq_read_ptr;
1152 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1153
1154 do {
1155 efx_qword_t *event = falcon_event(channel, read_ptr);
1156 int ev_code, ev_sub_code, ev_queue;
1157 bool ev_failed;
1158
1159 if (!falcon_event_present(event))
1160 break;
1161
1162 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1163 ev_sub_code = EFX_QWORD_FIELD(*event,
1164 FSF_AZ_DRIVER_EV_SUBCODE);
1165 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1166 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1167 ev_queue = EFX_QWORD_FIELD(*event,
1168 FSF_AZ_DRIVER_EV_SUBDATA);
1169 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1170 tx_queue = efx->tx_queue + ev_queue;
1171 tx_queue->flushed = FLUSH_DONE;
1172 }
1173 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1174 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1175 ev_queue = EFX_QWORD_FIELD(
1176 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1177 ev_failed = EFX_QWORD_FIELD(
1178 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1179 if (ev_queue < efx->n_rx_queues) {
1180 rx_queue = efx->rx_queue + ev_queue;
1181 rx_queue->flushed =
1182 ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1183 }
1184 }
1185
1186 /* We're about to destroy the queue anyway, so
1187 * it's ok to throw away every non-flush event */
1188 EFX_SET_QWORD(*event);
1189
1190 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1191 } while (read_ptr != end_ptr);
1192
1193 channel->eventq_read_ptr = read_ptr;
1194 }
1195
1196 static void falcon_prepare_flush(struct efx_nic *efx)
1197 {
1198 falcon_deconfigure_mac_wrapper(efx);
1199
1200 /* Wait for the tx and rx fifo's to get to the next packet boundary
1201 * (~1ms without back-pressure), then to drain the remainder of the
1202 * fifo's at data path speeds (negligible), with a healthy margin. */
1203 msleep(10);
1204 }
1205
1206 /* Handle tx and rx flushes at the same time, since they run in
1207 * parallel in the hardware and there's no reason for us to
1208 * serialise them */
1209 int falcon_flush_queues(struct efx_nic *efx)
1210 {
1211 struct efx_rx_queue *rx_queue;
1212 struct efx_tx_queue *tx_queue;
1213 int i, tx_pending, rx_pending;
1214
1215 /* If necessary prepare the hardware for flushing */
1216 efx->type->prepare_flush(efx);
1217
1218 /* Flush all tx queues in parallel */
1219 efx_for_each_tx_queue(tx_queue, efx)
1220 falcon_flush_tx_queue(tx_queue);
1221
1222 /* The hardware supports four concurrent rx flushes, each of which may
1223 * need to be retried if there is an outstanding descriptor fetch */
1224 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1225 rx_pending = tx_pending = 0;
1226 efx_for_each_rx_queue(rx_queue, efx) {
1227 if (rx_queue->flushed == FLUSH_PENDING)
1228 ++rx_pending;
1229 }
1230 efx_for_each_rx_queue(rx_queue, efx) {
1231 if (rx_pending == FALCON_RX_FLUSH_COUNT)
1232 break;
1233 if (rx_queue->flushed == FLUSH_FAILED ||
1234 rx_queue->flushed == FLUSH_NONE) {
1235 falcon_flush_rx_queue(rx_queue);
1236 ++rx_pending;
1237 }
1238 }
1239 efx_for_each_tx_queue(tx_queue, efx) {
1240 if (tx_queue->flushed != FLUSH_DONE)
1241 ++tx_pending;
1242 }
1243
1244 if (rx_pending == 0 && tx_pending == 0)
1245 return 0;
1246
1247 msleep(FALCON_FLUSH_INTERVAL);
1248 falcon_poll_flush_events(efx);
1249 }
1250
1251 /* Mark the queues as all flushed. We're going to return failure
1252 * leading to a reset, or fake up success anyway */
1253 efx_for_each_tx_queue(tx_queue, efx) {
1254 if (tx_queue->flushed != FLUSH_DONE)
1255 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1256 tx_queue->queue);
1257 tx_queue->flushed = FLUSH_DONE;
1258 }
1259 efx_for_each_rx_queue(rx_queue, efx) {
1260 if (rx_queue->flushed != FLUSH_DONE)
1261 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1262 rx_queue->queue);
1263 rx_queue->flushed = FLUSH_DONE;
1264 }
1265
1266 if (EFX_WORKAROUND_7803(efx))
1267 return 0;
1268
1269 return -ETIMEDOUT;
1270 }
1271
1272 /**************************************************************************
1273 *
1274 * Falcon hardware interrupts
1275 * The hardware interrupt handler does very little work; all the event
1276 * queue processing is carried out by per-channel tasklets.
1277 *
1278 **************************************************************************/
1279
1280 /* Enable/disable/generate Falcon interrupts */
1281 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1282 int force)
1283 {
1284 efx_oword_t int_en_reg_ker;
1285
1286 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1287 FRF_AZ_KER_INT_KER, force,
1288 FRF_AZ_DRV_INT_EN_KER, enabled);
1289 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1290 }
1291
1292 void falcon_enable_interrupts(struct efx_nic *efx)
1293 {
1294 struct efx_channel *channel;
1295
1296 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1297 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1298
1299 /* Enable interrupts */
1300 falcon_interrupts(efx, 1, 0);
1301
1302 /* Force processing of all the channels to get the EVQ RPTRs up to
1303 date */
1304 efx_for_each_channel(channel, efx)
1305 efx_schedule_channel(channel);
1306 }
1307
1308 void falcon_disable_interrupts(struct efx_nic *efx)
1309 {
1310 /* Disable interrupts */
1311 falcon_interrupts(efx, 0, 0);
1312 }
1313
1314 /* Generate a Falcon test interrupt
1315 * Interrupt must already have been enabled, otherwise nasty things
1316 * may happen.
1317 */
1318 void falcon_generate_interrupt(struct efx_nic *efx)
1319 {
1320 falcon_interrupts(efx, 1, 1);
1321 }
1322
1323 /* Acknowledge a legacy interrupt from Falcon
1324 *
1325 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1326 *
1327 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1328 * BIU. Interrupt acknowledge is read sensitive so must write instead
1329 * (then read to ensure the BIU collector is flushed)
1330 *
1331 * NB most hardware supports MSI interrupts
1332 */
1333 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1334 {
1335 efx_dword_t reg;
1336
1337 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1338 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1339 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1340 }
1341
1342 /* Process a fatal interrupt
1343 * Disable bus mastering ASAP and schedule a reset
1344 */
1345 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1346 {
1347 struct falcon_nic_data *nic_data = efx->nic_data;
1348 efx_oword_t *int_ker = efx->irq_status.addr;
1349 efx_oword_t fatal_intr;
1350 int error, mem_perr;
1351
1352 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1353 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1354
1355 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1356 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1357 EFX_OWORD_VAL(fatal_intr),
1358 error ? "disabling bus mastering" : "no recognised error");
1359 if (error == 0)
1360 goto out;
1361
1362 /* If this is a memory parity error dump which blocks are offending */
1363 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1364 if (mem_perr) {
1365 efx_oword_t reg;
1366 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1367 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1368 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1369 }
1370
1371 /* Disable both devices */
1372 pci_clear_master(efx->pci_dev);
1373 if (FALCON_IS_DUAL_FUNC(efx))
1374 pci_clear_master(nic_data->pci_dev2);
1375 falcon_disable_interrupts(efx);
1376
1377 /* Count errors and reset or disable the NIC accordingly */
1378 if (efx->int_error_count == 0 ||
1379 time_after(jiffies, efx->int_error_expire)) {
1380 efx->int_error_count = 0;
1381 efx->int_error_expire =
1382 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1383 }
1384 if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
1385 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1386 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1387 } else {
1388 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1389 "NIC will be disabled\n");
1390 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1391 }
1392 out:
1393 return IRQ_HANDLED;
1394 }
1395
1396 /* Handle a legacy interrupt from Falcon
1397 * Acknowledges the interrupt and schedule event queue processing.
1398 */
1399 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1400 {
1401 struct efx_nic *efx = dev_id;
1402 efx_oword_t *int_ker = efx->irq_status.addr;
1403 irqreturn_t result = IRQ_NONE;
1404 struct efx_channel *channel;
1405 efx_dword_t reg;
1406 u32 queues;
1407 int syserr;
1408
1409 /* Read the ISR which also ACKs the interrupts */
1410 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1411 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1412
1413 /* Check to see if we have a serious error condition */
1414 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1415 if (unlikely(syserr))
1416 return falcon_fatal_interrupt(efx);
1417
1418 /* Schedule processing of any interrupting queues */
1419 efx_for_each_channel(channel, efx) {
1420 if ((queues & 1) ||
1421 falcon_event_present(
1422 falcon_event(channel, channel->eventq_read_ptr))) {
1423 efx_schedule_channel(channel);
1424 result = IRQ_HANDLED;
1425 }
1426 queues >>= 1;
1427 }
1428
1429 if (result == IRQ_HANDLED) {
1430 efx->last_irq_cpu = raw_smp_processor_id();
1431 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1432 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1433 }
1434
1435 return result;
1436 }
1437
1438
1439 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1440 {
1441 struct efx_nic *efx = dev_id;
1442 efx_oword_t *int_ker = efx->irq_status.addr;
1443 struct efx_channel *channel;
1444 int syserr;
1445 int queues;
1446
1447 /* Check to see if this is our interrupt. If it isn't, we
1448 * exit without having touched the hardware.
1449 */
1450 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1451 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1452 raw_smp_processor_id());
1453 return IRQ_NONE;
1454 }
1455 efx->last_irq_cpu = raw_smp_processor_id();
1456 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1457 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1458
1459 /* Check to see if we have a serious error condition */
1460 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1461 if (unlikely(syserr))
1462 return falcon_fatal_interrupt(efx);
1463
1464 /* Determine interrupting queues, clear interrupt status
1465 * register and acknowledge the device interrupt.
1466 */
1467 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
1468 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
1469 EFX_ZERO_OWORD(*int_ker);
1470 wmb(); /* Ensure the vector is cleared before interrupt ack */
1471 falcon_irq_ack_a1(efx);
1472
1473 /* Schedule processing of any interrupting queues */
1474 channel = &efx->channel[0];
1475 while (queues) {
1476 if (queues & 0x01)
1477 efx_schedule_channel(channel);
1478 channel++;
1479 queues >>= 1;
1480 }
1481
1482 return IRQ_HANDLED;
1483 }
1484
1485 /* Handle an MSI interrupt from Falcon
1486 *
1487 * Handle an MSI hardware interrupt. This routine schedules event
1488 * queue processing. No interrupt acknowledgement cycle is necessary.
1489 * Also, we never need to check that the interrupt is for us, since
1490 * MSI interrupts cannot be shared.
1491 */
1492 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1493 {
1494 struct efx_channel *channel = dev_id;
1495 struct efx_nic *efx = channel->efx;
1496 efx_oword_t *int_ker = efx->irq_status.addr;
1497 int syserr;
1498
1499 efx->last_irq_cpu = raw_smp_processor_id();
1500 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1501 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1502
1503 /* Check to see if we have a serious error condition */
1504 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1505 if (unlikely(syserr))
1506 return falcon_fatal_interrupt(efx);
1507
1508 /* Schedule processing of the channel */
1509 efx_schedule_channel(channel);
1510
1511 return IRQ_HANDLED;
1512 }
1513
1514
1515 /* Setup RSS indirection table.
1516 * This maps from the hash value of the packet to RXQ
1517 */
1518 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1519 {
1520 int i = 0;
1521 unsigned long offset;
1522 efx_dword_t dword;
1523
1524 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1525 return;
1526
1527 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1528 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1529 offset += 0x10) {
1530 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1531 i % efx->n_rx_queues);
1532 efx_writed(efx, &dword, offset);
1533 i++;
1534 }
1535 }
1536
1537 /* Hook interrupt handler(s)
1538 * Try MSI and then legacy interrupts.
1539 */
1540 int falcon_init_interrupt(struct efx_nic *efx)
1541 {
1542 struct efx_channel *channel;
1543 int rc;
1544
1545 if (!EFX_INT_MODE_USE_MSI(efx)) {
1546 irq_handler_t handler;
1547 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1548 handler = falcon_legacy_interrupt_b0;
1549 else
1550 handler = falcon_legacy_interrupt_a1;
1551
1552 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1553 efx->name, efx);
1554 if (rc) {
1555 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1556 efx->pci_dev->irq);
1557 goto fail1;
1558 }
1559 return 0;
1560 }
1561
1562 /* Hook MSI or MSI-X interrupt */
1563 efx_for_each_channel(channel, efx) {
1564 rc = request_irq(channel->irq, falcon_msi_interrupt,
1565 IRQF_PROBE_SHARED, /* Not shared */
1566 channel->name, channel);
1567 if (rc) {
1568 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1569 goto fail2;
1570 }
1571 }
1572
1573 return 0;
1574
1575 fail2:
1576 efx_for_each_channel(channel, efx)
1577 free_irq(channel->irq, channel);
1578 fail1:
1579 return rc;
1580 }
1581
1582 void falcon_fini_interrupt(struct efx_nic *efx)
1583 {
1584 struct efx_channel *channel;
1585 efx_oword_t reg;
1586
1587 /* Disable MSI/MSI-X interrupts */
1588 efx_for_each_channel(channel, efx) {
1589 if (channel->irq)
1590 free_irq(channel->irq, channel);
1591 }
1592
1593 /* ACK legacy interrupt */
1594 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1595 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1596 else
1597 falcon_irq_ack_a1(efx);
1598
1599 /* Disable legacy interrupt */
1600 if (efx->legacy_irq)
1601 free_irq(efx->legacy_irq, efx);
1602 }
1603
1604 /**************************************************************************
1605 *
1606 * EEPROM/flash
1607 *
1608 **************************************************************************
1609 */
1610
1611 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1612
1613 static int falcon_spi_poll(struct efx_nic *efx)
1614 {
1615 efx_oword_t reg;
1616 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1617 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1618 }
1619
1620 /* Wait for SPI command completion */
1621 static int falcon_spi_wait(struct efx_nic *efx)
1622 {
1623 /* Most commands will finish quickly, so we start polling at
1624 * very short intervals. Sometimes the command may have to
1625 * wait for VPD or expansion ROM access outside of our
1626 * control, so we allow up to 100 ms. */
1627 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1628 int i;
1629
1630 for (i = 0; i < 10; i++) {
1631 if (!falcon_spi_poll(efx))
1632 return 0;
1633 udelay(10);
1634 }
1635
1636 for (;;) {
1637 if (!falcon_spi_poll(efx))
1638 return 0;
1639 if (time_after_eq(jiffies, timeout)) {
1640 EFX_ERR(efx, "timed out waiting for SPI\n");
1641 return -ETIMEDOUT;
1642 }
1643 schedule_timeout_uninterruptible(1);
1644 }
1645 }
1646
1647 int falcon_spi_cmd(const struct efx_spi_device *spi,
1648 unsigned int command, int address,
1649 const void *in, void *out, size_t len)
1650 {
1651 struct efx_nic *efx = spi->efx;
1652 bool addressed = (address >= 0);
1653 bool reading = (out != NULL);
1654 efx_oword_t reg;
1655 int rc;
1656
1657 /* Input validation */
1658 if (len > FALCON_SPI_MAX_LEN)
1659 return -EINVAL;
1660 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1661
1662 /* Check that previous command is not still running */
1663 rc = falcon_spi_poll(efx);
1664 if (rc)
1665 return rc;
1666
1667 /* Program address register, if we have an address */
1668 if (addressed) {
1669 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1670 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1671 }
1672
1673 /* Program data register, if we have data */
1674 if (in != NULL) {
1675 memcpy(&reg, in, len);
1676 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1677 }
1678
1679 /* Issue read/write command */
1680 EFX_POPULATE_OWORD_7(reg,
1681 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1682 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1683 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1684 FRF_AB_EE_SPI_HCMD_READ, reading,
1685 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1686 FRF_AB_EE_SPI_HCMD_ADBCNT,
1687 (addressed ? spi->addr_len : 0),
1688 FRF_AB_EE_SPI_HCMD_ENC, command);
1689 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1690
1691 /* Wait for read/write to complete */
1692 rc = falcon_spi_wait(efx);
1693 if (rc)
1694 return rc;
1695
1696 /* Read data */
1697 if (out != NULL) {
1698 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1699 memcpy(out, &reg, len);
1700 }
1701
1702 return 0;
1703 }
1704
1705 static size_t
1706 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1707 {
1708 return min(FALCON_SPI_MAX_LEN,
1709 (spi->block_size - (start & (spi->block_size - 1))));
1710 }
1711
1712 static inline u8
1713 efx_spi_munge_command(const struct efx_spi_device *spi,
1714 const u8 command, const unsigned int address)
1715 {
1716 return command | (((address >> 8) & spi->munge_address) << 3);
1717 }
1718
1719 /* Wait up to 10 ms for buffered write completion */
1720 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1721 {
1722 struct efx_nic *efx = spi->efx;
1723 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1724 u8 status;
1725 int rc;
1726
1727 for (;;) {
1728 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1729 &status, sizeof(status));
1730 if (rc)
1731 return rc;
1732 if (!(status & SPI_STATUS_NRDY))
1733 return 0;
1734 if (time_after_eq(jiffies, timeout)) {
1735 EFX_ERR(efx, "SPI write timeout on device %d"
1736 " last status=0x%02x\n",
1737 spi->device_id, status);
1738 return -ETIMEDOUT;
1739 }
1740 schedule_timeout_uninterruptible(1);
1741 }
1742 }
1743
1744 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1745 size_t len, size_t *retlen, u8 *buffer)
1746 {
1747 size_t block_len, pos = 0;
1748 unsigned int command;
1749 int rc = 0;
1750
1751 while (pos < len) {
1752 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1753
1754 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1755 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1756 buffer + pos, block_len);
1757 if (rc)
1758 break;
1759 pos += block_len;
1760
1761 /* Avoid locking up the system */
1762 cond_resched();
1763 if (signal_pending(current)) {
1764 rc = -EINTR;
1765 break;
1766 }
1767 }
1768
1769 if (retlen)
1770 *retlen = pos;
1771 return rc;
1772 }
1773
1774 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1775 size_t len, size_t *retlen, const u8 *buffer)
1776 {
1777 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1778 size_t block_len, pos = 0;
1779 unsigned int command;
1780 int rc = 0;
1781
1782 while (pos < len) {
1783 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1784 if (rc)
1785 break;
1786
1787 block_len = min(len - pos,
1788 falcon_spi_write_limit(spi, start + pos));
1789 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1790 rc = falcon_spi_cmd(spi, command, start + pos,
1791 buffer + pos, NULL, block_len);
1792 if (rc)
1793 break;
1794
1795 rc = falcon_spi_wait_write(spi);
1796 if (rc)
1797 break;
1798
1799 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1800 rc = falcon_spi_cmd(spi, command, start + pos,
1801 NULL, verify_buffer, block_len);
1802 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1803 rc = -EIO;
1804 break;
1805 }
1806
1807 pos += block_len;
1808
1809 /* Avoid locking up the system */
1810 cond_resched();
1811 if (signal_pending(current)) {
1812 rc = -EINTR;
1813 break;
1814 }
1815 }
1816
1817 if (retlen)
1818 *retlen = pos;
1819 return rc;
1820 }
1821
1822 /**************************************************************************
1823 *
1824 * MAC wrapper
1825 *
1826 **************************************************************************
1827 */
1828
1829 static void falcon_push_multicast_hash(struct efx_nic *efx)
1830 {
1831 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1832
1833 WARN_ON(!mutex_is_locked(&efx->mac_lock));
1834
1835 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1836 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1837 }
1838
1839 static int falcon_reset_macs(struct efx_nic *efx)
1840 {
1841 efx_oword_t reg;
1842 int count;
1843
1844 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1845 /* It's not safe to use GLB_CTL_REG to reset the
1846 * macs, so instead use the internal MAC resets
1847 */
1848 if (!EFX_IS10G(efx)) {
1849 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1850 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1851 udelay(1000);
1852
1853 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1854 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1855 udelay(1000);
1856 return 0;
1857 } else {
1858 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1859 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1860
1861 for (count = 0; count < 10000; count++) {
1862 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1863 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1864 0)
1865 return 0;
1866 udelay(10);
1867 }
1868
1869 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1870 return -ETIMEDOUT;
1871 }
1872 }
1873
1874 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1875 * the drain sequence with the statistics fetch */
1876 falcon_stop_nic_stats(efx);
1877
1878 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1879 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1880 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1881
1882 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1883 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1884 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1885 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1886 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1887
1888 count = 0;
1889 while (1) {
1890 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1891 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1892 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1893 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1894 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1895 count);
1896 break;
1897 }
1898 if (count > 20) {
1899 EFX_ERR(efx, "MAC reset failed\n");
1900 break;
1901 }
1902 count++;
1903 udelay(10);
1904 }
1905
1906 /* If we've reset the EM block and the link is up, then
1907 * we'll have to kick the XAUI link so the PHY can recover */
1908 if (efx->link_state.up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1909 falcon_reset_xaui(efx);
1910
1911 falcon_start_nic_stats(efx);
1912
1913 return 0;
1914 }
1915
1916 void falcon_drain_tx_fifo(struct efx_nic *efx)
1917 {
1918 efx_oword_t reg;
1919
1920 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1921 (efx->loopback_mode != LOOPBACK_NONE))
1922 return;
1923
1924 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1925 /* There is no point in draining more than once */
1926 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1927 return;
1928
1929 falcon_reset_macs(efx);
1930 }
1931
1932 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1933 {
1934 efx_oword_t reg;
1935
1936 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1937 return;
1938
1939 /* Isolate the MAC -> RX */
1940 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1941 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1942 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1943
1944 if (!efx->link_state.up)
1945 falcon_drain_tx_fifo(efx);
1946 }
1947
1948 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1949 {
1950 struct efx_link_state *link_state = &efx->link_state;
1951 efx_oword_t reg;
1952 int link_speed;
1953
1954 switch (link_state->speed) {
1955 case 10000: link_speed = 3; break;
1956 case 1000: link_speed = 2; break;
1957 case 100: link_speed = 1; break;
1958 default: link_speed = 0; break;
1959 }
1960 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1961 * as advertised. Disable to ensure packets are not
1962 * indefinitely held and TX queue can be flushed at any point
1963 * while the link is down. */
1964 EFX_POPULATE_OWORD_5(reg,
1965 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1966 FRF_AB_MAC_BCAD_ACPT, 1,
1967 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1968 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1969 FRF_AB_MAC_SPEED, link_speed);
1970 /* On B0, MAC backpressure can be disabled and packets get
1971 * discarded. */
1972 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1973 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1974 !link_state->up);
1975 }
1976
1977 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1978
1979 /* Restore the multicast hash registers. */
1980 falcon_push_multicast_hash(efx);
1981
1982 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1983 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1984 * initialisation but it may read back as 0) */
1985 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1986 /* Unisolate the MAC -> RX */
1987 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1988 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1989 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1990 }
1991
1992 static void falcon_stats_request(struct efx_nic *efx)
1993 {
1994 struct falcon_nic_data *nic_data = efx->nic_data;
1995 efx_oword_t reg;
1996
1997 WARN_ON(nic_data->stats_pending);
1998 WARN_ON(nic_data->stats_disable_count);
1999
2000 if (nic_data->stats_dma_done == NULL)
2001 return; /* no mac selected */
2002
2003 *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
2004 nic_data->stats_pending = true;
2005 wmb(); /* ensure done flag is clear */
2006
2007 /* Initiate DMA transfer of stats */
2008 EFX_POPULATE_OWORD_2(reg,
2009 FRF_AB_MAC_STAT_DMA_CMD, 1,
2010 FRF_AB_MAC_STAT_DMA_ADR,
2011 efx->stats_buffer.dma_addr);
2012 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2013
2014 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
2015 }
2016
2017 static void falcon_stats_complete(struct efx_nic *efx)
2018 {
2019 struct falcon_nic_data *nic_data = efx->nic_data;
2020
2021 if (!nic_data->stats_pending)
2022 return;
2023
2024 nic_data->stats_pending = 0;
2025 if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
2026 rmb(); /* read the done flag before the stats */
2027 efx->mac_op->update_stats(efx);
2028 } else {
2029 EFX_ERR(efx, "timed out waiting for statistics\n");
2030 }
2031 }
2032
2033 static void falcon_stats_timer_func(unsigned long context)
2034 {
2035 struct efx_nic *efx = (struct efx_nic *)context;
2036 struct falcon_nic_data *nic_data = efx->nic_data;
2037
2038 spin_lock(&efx->stats_lock);
2039
2040 falcon_stats_complete(efx);
2041 if (nic_data->stats_disable_count == 0)
2042 falcon_stats_request(efx);
2043
2044 spin_unlock(&efx->stats_lock);
2045 }
2046
2047 static bool falcon_loopback_link_poll(struct efx_nic *efx)
2048 {
2049 struct efx_link_state old_state = efx->link_state;
2050
2051 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2052 WARN_ON(!LOOPBACK_INTERNAL(efx));
2053
2054 efx->link_state.fd = true;
2055 efx->link_state.fc = efx->wanted_fc;
2056 efx->link_state.up = true;
2057
2058 if (efx->loopback_mode == LOOPBACK_GMAC)
2059 efx->link_state.speed = 1000;
2060 else
2061 efx->link_state.speed = 10000;
2062
2063 return !efx_link_state_equal(&efx->link_state, &old_state);
2064 }
2065
2066 /**************************************************************************
2067 *
2068 * PHY access via GMII
2069 *
2070 **************************************************************************
2071 */
2072
2073 /* Wait for GMII access to complete */
2074 static int falcon_gmii_wait(struct efx_nic *efx)
2075 {
2076 efx_oword_t md_stat;
2077 int count;
2078
2079 /* wait upto 50ms - taken max from datasheet */
2080 for (count = 0; count < 5000; count++) {
2081 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
2082 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2083 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2084 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2085 EFX_ERR(efx, "error from GMII access "
2086 EFX_OWORD_FMT"\n",
2087 EFX_OWORD_VAL(md_stat));
2088 return -EIO;
2089 }
2090 return 0;
2091 }
2092 udelay(10);
2093 }
2094 EFX_ERR(efx, "timed out waiting for GMII\n");
2095 return -ETIMEDOUT;
2096 }
2097
2098 /* Write an MDIO register of a PHY connected to Falcon. */
2099 static int falcon_mdio_write(struct net_device *net_dev,
2100 int prtad, int devad, u16 addr, u16 value)
2101 {
2102 struct efx_nic *efx = netdev_priv(net_dev);
2103 efx_oword_t reg;
2104 int rc;
2105
2106 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2107 prtad, devad, addr, value);
2108
2109 mutex_lock(&efx->mdio_lock);
2110
2111 /* Check MDIO not currently being accessed */
2112 rc = falcon_gmii_wait(efx);
2113 if (rc)
2114 goto out;
2115
2116 /* Write the address/ID register */
2117 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2118 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2119
2120 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2121 FRF_AB_MD_DEV_ADR, devad);
2122 efx_writeo(efx, &reg, FR_AB_MD_ID);
2123
2124 /* Write data */
2125 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2126 efx_writeo(efx, &reg, FR_AB_MD_TXD);
2127
2128 EFX_POPULATE_OWORD_2(reg,
2129 FRF_AB_MD_WRC, 1,
2130 FRF_AB_MD_GC, 0);
2131 efx_writeo(efx, &reg, FR_AB_MD_CS);
2132
2133 /* Wait for data to be written */
2134 rc = falcon_gmii_wait(efx);
2135 if (rc) {
2136 /* Abort the write operation */
2137 EFX_POPULATE_OWORD_2(reg,
2138 FRF_AB_MD_WRC, 0,
2139 FRF_AB_MD_GC, 1);
2140 efx_writeo(efx, &reg, FR_AB_MD_CS);
2141 udelay(10);
2142 }
2143
2144 out:
2145 mutex_unlock(&efx->mdio_lock);
2146 return rc;
2147 }
2148
2149 /* Read an MDIO register of a PHY connected to Falcon. */
2150 static int falcon_mdio_read(struct net_device *net_dev,
2151 int prtad, int devad, u16 addr)
2152 {
2153 struct efx_nic *efx = netdev_priv(net_dev);
2154 efx_oword_t reg;
2155 int rc;
2156
2157 mutex_lock(&efx->mdio_lock);
2158
2159 /* Check MDIO not currently being accessed */
2160 rc = falcon_gmii_wait(efx);
2161 if (rc)
2162 goto out;
2163
2164 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2165 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2166
2167 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2168 FRF_AB_MD_DEV_ADR, devad);
2169 efx_writeo(efx, &reg, FR_AB_MD_ID);
2170
2171 /* Request data to be read */
2172 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2173 efx_writeo(efx, &reg, FR_AB_MD_CS);
2174
2175 /* Wait for data to become available */
2176 rc = falcon_gmii_wait(efx);
2177 if (rc == 0) {
2178 efx_reado(efx, &reg, FR_AB_MD_RXD);
2179 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2180 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2181 prtad, devad, addr, rc);
2182 } else {
2183 /* Abort the read operation */
2184 EFX_POPULATE_OWORD_2(reg,
2185 FRF_AB_MD_RIC, 0,
2186 FRF_AB_MD_GC, 1);
2187 efx_writeo(efx, &reg, FR_AB_MD_CS);
2188
2189 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2190 prtad, devad, addr, rc);
2191 }
2192
2193 out:
2194 mutex_unlock(&efx->mdio_lock);
2195 return rc;
2196 }
2197
2198 static void falcon_clock_mac(struct efx_nic *efx)
2199 {
2200 unsigned strap_val;
2201 efx_oword_t nic_stat;
2202
2203 /* Configure the NIC generated MAC clock correctly */
2204 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2205 strap_val = EFX_IS10G(efx) ? 5 : 3;
2206 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2207 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2208 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2209 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2210 } else {
2211 /* Falcon A1 does not support 1G/10G speed switching
2212 * and must not be used with a PHY that does. */
2213 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2214 strap_val);
2215 }
2216 }
2217
2218 int falcon_switch_mac(struct efx_nic *efx)
2219 {
2220 struct efx_mac_operations *old_mac_op = efx->mac_op;
2221 struct falcon_nic_data *nic_data = efx->nic_data;
2222 unsigned int stats_done_offset;
2223 int rc = 0;
2224
2225 /* Don't try to fetch MAC stats while we're switching MACs */
2226 falcon_stop_nic_stats(efx);
2227
2228 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2229 efx->mac_op = (EFX_IS10G(efx) ?
2230 &falcon_xmac_operations : &falcon_gmac_operations);
2231
2232 if (EFX_IS10G(efx))
2233 stats_done_offset = XgDmaDone_offset;
2234 else
2235 stats_done_offset = GDmaDone_offset;
2236 nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
2237
2238 if (old_mac_op == efx->mac_op)
2239 goto out;
2240
2241 falcon_clock_mac(efx);
2242
2243 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2244 /* Not all macs support a mac-level link state */
2245 efx->xmac_poll_required = false;
2246
2247 rc = falcon_reset_macs(efx);
2248 out:
2249 falcon_start_nic_stats(efx);
2250 return rc;
2251 }
2252
2253 /* This call is responsible for hooking in the MAC and PHY operations */
2254 static int falcon_probe_port(struct efx_nic *efx)
2255 {
2256 int rc;
2257
2258 switch (efx->phy_type) {
2259 case PHY_TYPE_SFX7101:
2260 efx->phy_op = &falcon_sfx7101_phy_ops;
2261 break;
2262 case PHY_TYPE_SFT9001A:
2263 case PHY_TYPE_SFT9001B:
2264 efx->phy_op = &falcon_sft9001_phy_ops;
2265 break;
2266 case PHY_TYPE_QT2022C2:
2267 case PHY_TYPE_QT2025C:
2268 efx->phy_op = &falcon_qt202x_phy_ops;
2269 break;
2270 default:
2271 EFX_ERR(efx, "Unknown PHY type %d\n",
2272 efx->phy_type);
2273 return -ENODEV;
2274 }
2275
2276 if (efx->phy_op->macs & EFX_XMAC)
2277 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2278 (1 << LOOPBACK_XGXS) |
2279 (1 << LOOPBACK_XAUI));
2280 if (efx->phy_op->macs & EFX_GMAC)
2281 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2282 efx->loopback_modes |= efx->phy_op->loopbacks;
2283
2284 /* Set up MDIO structure for PHY */
2285 efx->mdio.mmds = efx->phy_op->mmds;
2286 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2287 efx->mdio.mdio_read = falcon_mdio_read;
2288 efx->mdio.mdio_write = falcon_mdio_write;
2289
2290 /* Initial assumption */
2291 efx->link_state.speed = 10000;
2292 efx->link_state.fd = true;
2293
2294 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2295 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
2296 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2297 else
2298 efx->wanted_fc = EFX_FC_RX;
2299
2300 /* Allocate buffer for stats */
2301 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2302 FALCON_MAC_STATS_SIZE);
2303 if (rc)
2304 return rc;
2305 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2306 (u64)efx->stats_buffer.dma_addr,
2307 efx->stats_buffer.addr,
2308 (u64)virt_to_phys(efx->stats_buffer.addr));
2309
2310 return 0;
2311 }
2312
2313 static void falcon_remove_port(struct efx_nic *efx)
2314 {
2315 falcon_free_buffer(efx, &efx->stats_buffer);
2316 }
2317
2318 /**************************************************************************
2319 *
2320 * Falcon test code
2321 *
2322 **************************************************************************/
2323
2324 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2325 {
2326 struct falcon_nvconfig *nvconfig;
2327 struct efx_spi_device *spi;
2328 void *region;
2329 int rc, magic_num, struct_ver;
2330 __le16 *word, *limit;
2331 u32 csum;
2332
2333 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2334 if (!spi)
2335 return -EINVAL;
2336
2337 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2338 if (!region)
2339 return -ENOMEM;
2340 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2341
2342 mutex_lock(&efx->spi_lock);
2343 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2344 mutex_unlock(&efx->spi_lock);
2345 if (rc) {
2346 EFX_ERR(efx, "Failed to read %s\n",
2347 efx->spi_flash ? "flash" : "EEPROM");
2348 rc = -EIO;
2349 goto out;
2350 }
2351
2352 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2353 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2354
2355 rc = -EINVAL;
2356 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2357 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2358 goto out;
2359 }
2360 if (struct_ver < 2) {
2361 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2362 goto out;
2363 } else if (struct_ver < 4) {
2364 word = &nvconfig->board_magic_num;
2365 limit = (__le16 *) (nvconfig + 1);
2366 } else {
2367 word = region;
2368 limit = region + FALCON_NVCONFIG_END;
2369 }
2370 for (csum = 0; word < limit; ++word)
2371 csum += le16_to_cpu(*word);
2372
2373 if (~csum & 0xffff) {
2374 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2375 goto out;
2376 }
2377
2378 rc = 0;
2379 if (nvconfig_out)
2380 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2381
2382 out:
2383 kfree(region);
2384 return rc;
2385 }
2386
2387 /* Registers tested in the falcon register test */
2388 static struct {
2389 unsigned address;
2390 efx_oword_t mask;
2391 } efx_test_registers[] = {
2392 { FR_AZ_ADR_REGION,
2393 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2394 { FR_AZ_RX_CFG,
2395 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2396 { FR_AZ_TX_CFG,
2397 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2398 { FR_AZ_TX_RESERVED,
2399 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2400 { FR_AB_MAC_CTRL,
2401 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2402 { FR_AZ_SRM_TX_DC_CFG,
2403 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2404 { FR_AZ_RX_DC_CFG,
2405 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2406 { FR_AZ_RX_DC_PF_WM,
2407 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2408 { FR_BZ_DP_CTRL,
2409 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2410 { FR_AB_GM_CFG2,
2411 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2412 { FR_AB_GMF_CFG0,
2413 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2414 { FR_AB_XM_GLB_CFG,
2415 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2416 { FR_AB_XM_TX_CFG,
2417 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2418 { FR_AB_XM_RX_CFG,
2419 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2420 { FR_AB_XM_RX_PARAM,
2421 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2422 { FR_AB_XM_FC,
2423 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2424 { FR_AB_XM_ADR_LO,
2425 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2426 { FR_AB_XX_SD_CTL,
2427 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2428 };
2429
2430 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2431 const efx_oword_t *mask)
2432 {
2433 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2434 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2435 }
2436
2437 int falcon_test_registers(struct efx_nic *efx)
2438 {
2439 unsigned address = 0, i, j;
2440 efx_oword_t mask, imask, original, reg, buf;
2441
2442 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2443 WARN_ON(!LOOPBACK_INTERNAL(efx));
2444
2445 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2446 address = efx_test_registers[i].address;
2447 mask = imask = efx_test_registers[i].mask;
2448 EFX_INVERT_OWORD(imask);
2449
2450 efx_reado(efx, &original, address);
2451
2452 /* bit sweep on and off */
2453 for (j = 0; j < 128; j++) {
2454 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2455 continue;
2456
2457 /* Test this testable bit can be set in isolation */
2458 EFX_AND_OWORD(reg, original, mask);
2459 EFX_SET_OWORD32(reg, j, j, 1);
2460
2461 efx_writeo(efx, &reg, address);
2462 efx_reado(efx, &buf, address);
2463
2464 if (efx_masked_compare_oword(&reg, &buf, &mask))
2465 goto fail;
2466
2467 /* Test this testable bit can be cleared in isolation */
2468 EFX_OR_OWORD(reg, original, mask);
2469 EFX_SET_OWORD32(reg, j, j, 0);
2470
2471 efx_writeo(efx, &reg, address);
2472 efx_reado(efx, &buf, address);
2473
2474 if (efx_masked_compare_oword(&reg, &buf, &mask))
2475 goto fail;
2476 }
2477
2478 efx_writeo(efx, &original, address);
2479 }
2480
2481 return 0;
2482
2483 fail:
2484 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2485 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2486 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2487 return -EIO;
2488 }
2489
2490 /**************************************************************************
2491 *
2492 * Device reset
2493 *
2494 **************************************************************************
2495 */
2496
2497 /* Resets NIC to known state. This routine must be called in process
2498 * context and is allowed to sleep. */
2499 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2500 {
2501 struct falcon_nic_data *nic_data = efx->nic_data;
2502 efx_oword_t glb_ctl_reg_ker;
2503 int rc;
2504
2505 EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
2506
2507 /* Initiate device reset */
2508 if (method == RESET_TYPE_WORLD) {
2509 rc = pci_save_state(efx->pci_dev);
2510 if (rc) {
2511 EFX_ERR(efx, "failed to backup PCI state of primary "
2512 "function prior to hardware reset\n");
2513 goto fail1;
2514 }
2515 if (FALCON_IS_DUAL_FUNC(efx)) {
2516 rc = pci_save_state(nic_data->pci_dev2);
2517 if (rc) {
2518 EFX_ERR(efx, "failed to backup PCI state of "
2519 "secondary function prior to "
2520 "hardware reset\n");
2521 goto fail2;
2522 }
2523 }
2524
2525 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2526 FRF_AB_EXT_PHY_RST_DUR,
2527 FFE_AB_EXT_PHY_RST_DUR_10240US,
2528 FRF_AB_SWRST, 1);
2529 } else {
2530 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2531 /* exclude PHY from "invisible" reset */
2532 FRF_AB_EXT_PHY_RST_CTL,
2533 method == RESET_TYPE_INVISIBLE,
2534 /* exclude EEPROM/flash and PCIe */
2535 FRF_AB_PCIE_CORE_RST_CTL, 1,
2536 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2537 FRF_AB_PCIE_SD_RST_CTL, 1,
2538 FRF_AB_EE_RST_CTL, 1,
2539 FRF_AB_EXT_PHY_RST_DUR,
2540 FFE_AB_EXT_PHY_RST_DUR_10240US,
2541 FRF_AB_SWRST, 1);
2542 }
2543 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2544
2545 EFX_LOG(efx, "waiting for hardware reset\n");
2546 schedule_timeout_uninterruptible(HZ / 20);
2547
2548 /* Restore PCI configuration if needed */
2549 if (method == RESET_TYPE_WORLD) {
2550 if (FALCON_IS_DUAL_FUNC(efx)) {
2551 rc = pci_restore_state(nic_data->pci_dev2);
2552 if (rc) {
2553 EFX_ERR(efx, "failed to restore PCI config for "
2554 "the secondary function\n");
2555 goto fail3;
2556 }
2557 }
2558 rc = pci_restore_state(efx->pci_dev);
2559 if (rc) {
2560 EFX_ERR(efx, "failed to restore PCI config for the "
2561 "primary function\n");
2562 goto fail4;
2563 }
2564 EFX_LOG(efx, "successfully restored PCI config\n");
2565 }
2566
2567 /* Assert that reset complete */
2568 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2569 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2570 rc = -ETIMEDOUT;
2571 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2572 goto fail5;
2573 }
2574 EFX_LOG(efx, "hardware reset complete\n");
2575
2576 return 0;
2577
2578 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2579 fail2:
2580 fail3:
2581 pci_restore_state(efx->pci_dev);
2582 fail1:
2583 fail4:
2584 fail5:
2585 return rc;
2586 }
2587
2588 static void falcon_monitor(struct efx_nic *efx)
2589 {
2590 bool link_changed;
2591 int rc;
2592
2593 BUG_ON(!mutex_is_locked(&efx->mac_lock));
2594
2595 rc = falcon_board(efx)->type->monitor(efx);
2596 if (rc) {
2597 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
2598 (rc == -ERANGE) ? "reported fault" : "failed");
2599 efx->phy_mode |= PHY_MODE_LOW_POWER;
2600 __efx_reconfigure_port(efx);
2601 }
2602
2603 if (LOOPBACK_INTERNAL(efx))
2604 link_changed = falcon_loopback_link_poll(efx);
2605 else
2606 link_changed = efx->phy_op->poll(efx);
2607
2608 if (link_changed) {
2609 falcon_stop_nic_stats(efx);
2610 falcon_deconfigure_mac_wrapper(efx);
2611
2612 falcon_switch_mac(efx);
2613 efx->mac_op->reconfigure(efx);
2614
2615 falcon_start_nic_stats(efx);
2616
2617 efx_link_status_changed(efx);
2618 }
2619
2620 if (EFX_IS10G(efx))
2621 falcon_poll_xmac(efx);
2622 }
2623
2624 /* Zeroes out the SRAM contents. This routine must be called in
2625 * process context and is allowed to sleep.
2626 */
2627 static int falcon_reset_sram(struct efx_nic *efx)
2628 {
2629 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2630 int count;
2631
2632 /* Set the SRAM wake/sleep GPIO appropriately. */
2633 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2634 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2635 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2636 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2637
2638 /* Initiate SRAM reset */
2639 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2640 FRF_AZ_SRM_INIT_EN, 1,
2641 FRF_AZ_SRM_NB_SZ, 0);
2642 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2643
2644 /* Wait for SRAM reset to complete */
2645 count = 0;
2646 do {
2647 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2648
2649 /* SRAM reset is slow; expect around 16ms */
2650 schedule_timeout_uninterruptible(HZ / 50);
2651
2652 /* Check for reset complete */
2653 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2654 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2655 EFX_LOG(efx, "SRAM reset complete\n");
2656
2657 return 0;
2658 }
2659 } while (++count < 20); /* wait upto 0.4 sec */
2660
2661 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2662 return -ETIMEDOUT;
2663 }
2664
2665 static int falcon_spi_device_init(struct efx_nic *efx,
2666 struct efx_spi_device **spi_device_ret,
2667 unsigned int device_id, u32 device_type)
2668 {
2669 struct efx_spi_device *spi_device;
2670
2671 if (device_type != 0) {
2672 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2673 if (!spi_device)
2674 return -ENOMEM;
2675 spi_device->device_id = device_id;
2676 spi_device->size =
2677 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2678 spi_device->addr_len =
2679 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2680 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2681 spi_device->addr_len == 1);
2682 spi_device->erase_command =
2683 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2684 spi_device->erase_size =
2685 1 << SPI_DEV_TYPE_FIELD(device_type,
2686 SPI_DEV_TYPE_ERASE_SIZE);
2687 spi_device->block_size =
2688 1 << SPI_DEV_TYPE_FIELD(device_type,
2689 SPI_DEV_TYPE_BLOCK_SIZE);
2690
2691 spi_device->efx = efx;
2692 } else {
2693 spi_device = NULL;
2694 }
2695
2696 kfree(*spi_device_ret);
2697 *spi_device_ret = spi_device;
2698 return 0;
2699 }
2700
2701
2702 static void falcon_remove_spi_devices(struct efx_nic *efx)
2703 {
2704 kfree(efx->spi_eeprom);
2705 efx->spi_eeprom = NULL;
2706 kfree(efx->spi_flash);
2707 efx->spi_flash = NULL;
2708 }
2709
2710 /* Extract non-volatile configuration */
2711 static int falcon_probe_nvconfig(struct efx_nic *efx)
2712 {
2713 struct falcon_nvconfig *nvconfig;
2714 int board_rev;
2715 int rc;
2716
2717 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2718 if (!nvconfig)
2719 return -ENOMEM;
2720
2721 rc = falcon_read_nvram(efx, nvconfig);
2722 if (rc == -EINVAL) {
2723 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2724 efx->phy_type = PHY_TYPE_NONE;
2725 efx->mdio.prtad = MDIO_PRTAD_NONE;
2726 board_rev = 0;
2727 rc = 0;
2728 } else if (rc) {
2729 goto fail1;
2730 } else {
2731 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2732 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2733
2734 efx->phy_type = v2->port0_phy_type;
2735 efx->mdio.prtad = v2->port0_phy_addr;
2736 board_rev = le16_to_cpu(v2->board_revision);
2737
2738 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2739 rc = falcon_spi_device_init(
2740 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2741 le32_to_cpu(v3->spi_device_type
2742 [FFE_AB_SPI_DEVICE_FLASH]));
2743 if (rc)
2744 goto fail2;
2745 rc = falcon_spi_device_init(
2746 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2747 le32_to_cpu(v3->spi_device_type
2748 [FFE_AB_SPI_DEVICE_EEPROM]));
2749 if (rc)
2750 goto fail2;
2751 }
2752 }
2753
2754 /* Read the MAC addresses */
2755 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2756
2757 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2758
2759 falcon_probe_board(efx, board_rev);
2760
2761 kfree(nvconfig);
2762 return 0;
2763
2764 fail2:
2765 falcon_remove_spi_devices(efx);
2766 fail1:
2767 kfree(nvconfig);
2768 return rc;
2769 }
2770
2771 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2772 * count, port speed). Set workaround and feature flags accordingly.
2773 */
2774 static int falcon_probe_nic_variant(struct efx_nic *efx)
2775 {
2776 efx_oword_t altera_build;
2777 efx_oword_t nic_stat;
2778
2779 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2780 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2781 EFX_ERR(efx, "Falcon FPGA not supported\n");
2782 return -ENODEV;
2783 }
2784
2785 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2786
2787 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2788 u8 pci_rev = efx->pci_dev->revision;
2789
2790 if ((pci_rev == 0xff) || (pci_rev == 0)) {
2791 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2792 return -ENODEV;
2793 }
2794 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
2795 EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
2796 return -ENODEV;
2797 }
2798 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2799 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2800 return -ENODEV;
2801 }
2802 }
2803
2804 return 0;
2805 }
2806
2807 /* Probe all SPI devices on the NIC */
2808 static void falcon_probe_spi_devices(struct efx_nic *efx)
2809 {
2810 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2811 int boot_dev;
2812
2813 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2814 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2815 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2816
2817 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2818 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2819 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2820 EFX_LOG(efx, "Booted from %s\n",
2821 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2822 } else {
2823 /* Disable VPD and set clock dividers to safe
2824 * values for initial programming. */
2825 boot_dev = -1;
2826 EFX_LOG(efx, "Booted from internal ASIC settings;"
2827 " setting SPI config\n");
2828 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2829 /* 125 MHz / 7 ~= 20 MHz */
2830 FRF_AB_EE_SF_CLOCK_DIV, 7,
2831 /* 125 MHz / 63 ~= 2 MHz */
2832 FRF_AB_EE_EE_CLOCK_DIV, 63);
2833 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2834 }
2835
2836 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2837 falcon_spi_device_init(efx, &efx->spi_flash,
2838 FFE_AB_SPI_DEVICE_FLASH,
2839 default_flash_type);
2840 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2841 falcon_spi_device_init(efx, &efx->spi_eeprom,
2842 FFE_AB_SPI_DEVICE_EEPROM,
2843 large_eeprom_type);
2844 }
2845
2846 static int falcon_probe_nic(struct efx_nic *efx)
2847 {
2848 struct falcon_nic_data *nic_data;
2849 struct falcon_board *board;
2850 int rc;
2851
2852 /* Allocate storage for hardware specific data */
2853 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2854 if (!nic_data)
2855 return -ENOMEM;
2856 efx->nic_data = nic_data;
2857
2858 /* Determine number of ports etc. */
2859 rc = falcon_probe_nic_variant(efx);
2860 if (rc)
2861 goto fail1;
2862
2863 /* Probe secondary function if expected */
2864 if (FALCON_IS_DUAL_FUNC(efx)) {
2865 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2866
2867 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2868 dev))) {
2869 if (dev->bus == efx->pci_dev->bus &&
2870 dev->devfn == efx->pci_dev->devfn + 1) {
2871 nic_data->pci_dev2 = dev;
2872 break;
2873 }
2874 }
2875 if (!nic_data->pci_dev2) {
2876 EFX_ERR(efx, "failed to find secondary function\n");
2877 rc = -ENODEV;
2878 goto fail2;
2879 }
2880 }
2881
2882 /* Now we can reset the NIC */
2883 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2884 if (rc) {
2885 EFX_ERR(efx, "failed to reset NIC\n");
2886 goto fail3;
2887 }
2888
2889 /* Allocate memory for INT_KER */
2890 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2891 if (rc)
2892 goto fail4;
2893 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2894
2895 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2896 (u64)efx->irq_status.dma_addr,
2897 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2898
2899 falcon_probe_spi_devices(efx);
2900
2901 /* Read in the non-volatile configuration */
2902 rc = falcon_probe_nvconfig(efx);
2903 if (rc)
2904 goto fail5;
2905
2906 /* Initialise I2C adapter */
2907 board = falcon_board(efx);
2908 board->i2c_adap.owner = THIS_MODULE;
2909 board->i2c_data = falcon_i2c_bit_operations;
2910 board->i2c_data.data = efx;
2911 board->i2c_adap.algo_data = &board->i2c_data;
2912 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2913 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2914 sizeof(board->i2c_adap.name));
2915 rc = i2c_bit_add_bus(&board->i2c_adap);
2916 if (rc)
2917 goto fail5;
2918
2919 rc = falcon_board(efx)->type->init(efx);
2920 if (rc) {
2921 EFX_ERR(efx, "failed to initialise board\n");
2922 goto fail6;
2923 }
2924
2925 nic_data->stats_disable_count = 1;
2926 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
2927 (unsigned long)efx);
2928
2929 return 0;
2930
2931 fail6:
2932 BUG_ON(i2c_del_adapter(&board->i2c_adap));
2933 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2934 fail5:
2935 falcon_remove_spi_devices(efx);
2936 falcon_free_buffer(efx, &efx->irq_status);
2937 fail4:
2938 fail3:
2939 if (nic_data->pci_dev2) {
2940 pci_dev_put(nic_data->pci_dev2);
2941 nic_data->pci_dev2 = NULL;
2942 }
2943 fail2:
2944 fail1:
2945 kfree(efx->nic_data);
2946 return rc;
2947 }
2948
2949 static void falcon_init_rx_cfg(struct efx_nic *efx)
2950 {
2951 /* Prior to Siena the RX DMA engine will split each frame at
2952 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2953 * be so large that that never happens. */
2954 const unsigned huge_buf_size = (3 * 4096) >> 5;
2955 /* RX control FIFO thresholds (32 entries) */
2956 const unsigned ctrl_xon_thr = 20;
2957 const unsigned ctrl_xoff_thr = 25;
2958 /* RX data FIFO thresholds (256-byte units; size varies) */
2959 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2960 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2961 efx_oword_t reg;
2962
2963 efx_reado(efx, &reg, FR_AZ_RX_CFG);
2964 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2965 /* Data FIFO size is 5.5K */
2966 if (data_xon_thr < 0)
2967 data_xon_thr = 512 >> 8;
2968 if (data_xoff_thr < 0)
2969 data_xoff_thr = 2048 >> 8;
2970 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2971 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2972 huge_buf_size);
2973 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2974 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2975 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2976 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2977 } else {
2978 /* Data FIFO size is 80K; register fields moved */
2979 if (data_xon_thr < 0)
2980 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2981 if (data_xoff_thr < 0)
2982 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2983 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2984 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2985 huge_buf_size);
2986 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2987 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2988 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2989 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2990 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2991 }
2992 /* Always enable XOFF signal from RX FIFO. We enable
2993 * or disable transmission of pause frames at the MAC. */
2994 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
2995 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2996 }
2997
2998 /* This call performs hardware-specific global initialisation, such as
2999 * defining the descriptor cache sizes and number of RSS channels.
3000 * It does not set up any buffers, descriptor rings or event queues.
3001 */
3002 static int falcon_init_nic(struct efx_nic *efx)
3003 {
3004 efx_oword_t temp;
3005 int rc;
3006
3007 /* Use on-chip SRAM */
3008 efx_reado(efx, &temp, FR_AB_NIC_STAT);
3009 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
3010 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
3011
3012 /* Set the source of the GMAC clock */
3013 if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
3014 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
3015 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
3016 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
3017 }
3018
3019 /* Select the correct MAC */
3020 falcon_clock_mac(efx);
3021
3022 rc = falcon_reset_sram(efx);
3023 if (rc)
3024 return rc;
3025
3026 /* Set positions of descriptor caches in SRAM. */
3027 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
3028 efx->type->tx_dc_base / 8);
3029 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3030 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
3031 efx->type->rx_dc_base / 8);
3032 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3033
3034 /* Set TX descriptor cache size. */
3035 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
3036 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3037 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3038
3039 /* Set RX descriptor cache size. Set low watermark to size-8, as
3040 * this allows most efficient prefetching.
3041 */
3042 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
3043 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3044 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3045 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3046 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3047
3048 /* Program INT_KER address */
3049 EFX_POPULATE_OWORD_2(temp,
3050 FRF_AZ_NORM_INT_VEC_DIS_KER,
3051 EFX_INT_MODE_USE_MSI(efx),
3052 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
3053 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
3054
3055 /* Clear the parity enables on the TX data fifos as
3056 * they produce false parity errors because of timing issues
3057 */
3058 if (EFX_WORKAROUND_5129(efx)) {
3059 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3060 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3061 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3062 }
3063
3064 /* Enable all the genuinely fatal interrupts. (They are still
3065 * masked by the overall interrupt mask, controlled by
3066 * falcon_interrupts()).
3067 *
3068 * Note: All other fatal interrupts are enabled
3069 */
3070 EFX_POPULATE_OWORD_3(temp,
3071 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3072 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3073 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3074 EFX_INVERT_OWORD(temp);
3075 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3076
3077 if (EFX_WORKAROUND_7244(efx)) {
3078 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3079 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3080 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3081 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3082 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3083 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3084 }
3085
3086 falcon_setup_rss_indir_table(efx);
3087
3088 /* XXX This is documented only for Falcon A0/A1 */
3089 /* Setup RX. Wait for descriptor is broken and must
3090 * be disabled. RXDP recovery shouldn't be needed, but is.
3091 */
3092 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3093 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3094 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3095 if (EFX_WORKAROUND_5583(efx))
3096 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3097 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3098
3099 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3100 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3101 */
3102 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3103 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3104 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3105 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3106 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3107 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3108 /* Enable SW_EV to inherit in char driver - assume harmless here */
3109 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3110 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3111 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3112 /* Squash TX of packets of 16 bytes or less */
3113 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
3114 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3115 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3116
3117 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3118 * descriptors (which is bad).
3119 */
3120 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3121 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3122 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3123
3124 falcon_init_rx_cfg(efx);
3125
3126 /* Set destination of both TX and RX Flush events */
3127 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
3128 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3129 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3130 }
3131
3132 return 0;
3133 }
3134
3135 static void falcon_remove_nic(struct efx_nic *efx)
3136 {
3137 struct falcon_nic_data *nic_data = efx->nic_data;
3138 struct falcon_board *board = falcon_board(efx);
3139 int rc;
3140
3141 board->type->fini(efx);
3142
3143 /* Remove I2C adapter and clear it in preparation for a retry */
3144 rc = i2c_del_adapter(&board->i2c_adap);
3145 BUG_ON(rc);
3146 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
3147
3148 falcon_remove_spi_devices(efx);
3149 falcon_free_buffer(efx, &efx->irq_status);
3150
3151 falcon_reset_hw(efx, RESET_TYPE_ALL);
3152
3153 /* Release the second function after the reset */
3154 if (nic_data->pci_dev2) {
3155 pci_dev_put(nic_data->pci_dev2);
3156 nic_data->pci_dev2 = NULL;
3157 }
3158
3159 /* Tear down the private nic state */
3160 kfree(efx->nic_data);
3161 efx->nic_data = NULL;
3162 }
3163
3164 static void falcon_update_nic_stats(struct efx_nic *efx)
3165 {
3166 struct falcon_nic_data *nic_data = efx->nic_data;
3167 efx_oword_t cnt;
3168
3169 if (nic_data->stats_disable_count)
3170 return;
3171
3172 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3173 efx->n_rx_nodesc_drop_cnt +=
3174 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3175
3176 if (nic_data->stats_pending &&
3177 *nic_data->stats_dma_done == FALCON_STATS_DONE) {
3178 nic_data->stats_pending = false;
3179 rmb(); /* read the done flag before the stats */
3180 efx->mac_op->update_stats(efx);
3181 }
3182 }
3183
3184 void falcon_start_nic_stats(struct efx_nic *efx)
3185 {
3186 struct falcon_nic_data *nic_data = efx->nic_data;
3187
3188 spin_lock_bh(&efx->stats_lock);
3189 if (--nic_data->stats_disable_count == 0)
3190 falcon_stats_request(efx);
3191 spin_unlock_bh(&efx->stats_lock);
3192 }
3193
3194 void falcon_stop_nic_stats(struct efx_nic *efx)
3195 {
3196 struct falcon_nic_data *nic_data = efx->nic_data;
3197 int i;
3198
3199 might_sleep();
3200
3201 spin_lock_bh(&efx->stats_lock);
3202 ++nic_data->stats_disable_count;
3203 spin_unlock_bh(&efx->stats_lock);
3204
3205 del_timer_sync(&nic_data->stats_timer);
3206
3207 /* Wait enough time for the most recent transfer to
3208 * complete. */
3209 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
3210 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
3211 break;
3212 msleep(1);
3213 }
3214
3215 spin_lock_bh(&efx->stats_lock);
3216 falcon_stats_complete(efx);
3217 spin_unlock_bh(&efx->stats_lock);
3218 }
3219
3220 /**************************************************************************
3221 *
3222 * Revision-dependent attributes used by efx.c
3223 *
3224 **************************************************************************
3225 */
3226
3227 struct efx_nic_type falcon_a1_nic_type = {
3228 .probe = falcon_probe_nic,
3229 .remove = falcon_remove_nic,
3230 .init = falcon_init_nic,
3231 .fini = efx_port_dummy_op_void,
3232 .monitor = falcon_monitor,
3233 .reset = falcon_reset_hw,
3234 .probe_port = falcon_probe_port,
3235 .remove_port = falcon_remove_port,
3236 .prepare_flush = falcon_prepare_flush,
3237 .update_stats = falcon_update_nic_stats,
3238 .start_stats = falcon_start_nic_stats,
3239 .stop_stats = falcon_stop_nic_stats,
3240 .push_irq_moderation = falcon_push_irq_moderation,
3241 .push_multicast_hash = falcon_push_multicast_hash,
3242 .default_mac_ops = &falcon_xmac_operations,
3243
3244 .revision = EFX_REV_FALCON_A1,
3245 .mem_map_size = 0x20000,
3246 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3247 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3248 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3249 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3250 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3251 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3252 .rx_buffer_padding = 0x24,
3253 .max_interrupt_mode = EFX_INT_MODE_MSI,
3254 .phys_addr_channels = 4,
3255 .tx_dc_base = 0x130000,
3256 .rx_dc_base = 0x100000,
3257 };
3258
3259 struct efx_nic_type falcon_b0_nic_type = {
3260 .probe = falcon_probe_nic,
3261 .remove = falcon_remove_nic,
3262 .init = falcon_init_nic,
3263 .fini = efx_port_dummy_op_void,
3264 .monitor = falcon_monitor,
3265 .reset = falcon_reset_hw,
3266 .probe_port = falcon_probe_port,
3267 .remove_port = falcon_remove_port,
3268 .prepare_flush = falcon_prepare_flush,
3269 .update_stats = falcon_update_nic_stats,
3270 .start_stats = falcon_start_nic_stats,
3271 .stop_stats = falcon_stop_nic_stats,
3272 .push_irq_moderation = falcon_push_irq_moderation,
3273 .push_multicast_hash = falcon_push_multicast_hash,
3274 .default_mac_ops = &falcon_xmac_operations,
3275
3276 .revision = EFX_REV_FALCON_B0,
3277 /* Map everything up to and including the RSS indirection
3278 * table. Don't map MSI-X table, MSI-X PBA since Linux
3279 * requires that they not be mapped. */
3280 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3281 FR_BZ_RX_INDIRECTION_TBL_STEP *
3282 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3283 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3284 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3285 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3286 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3287 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3288 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3289 .rx_buffer_padding = 0,
3290 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3291 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3292 * interrupt handler only supports 32
3293 * channels */
3294 .tx_dc_base = 0x130000,
3295 .rx_dc_base = 0x100000,
3296 };
3297
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree