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ALSA: hda - Add support for 92HD65 / 92HD66 family of codecs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / firewire / ohci.c
blobee76c8ec72f6814aa4810974b6ee47f54c09c039
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45
46 #include <asm/byteorder.h>
47 #include <asm/page.h>
48 #include <asm/system.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define DESCRIPTOR_OUTPUT_MORE 0
58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59 #define DESCRIPTOR_INPUT_MORE (2 << 12)
60 #define DESCRIPTOR_INPUT_LAST (3 << 12)
61 #define DESCRIPTOR_STATUS (1 << 11)
62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63 #define DESCRIPTOR_PING (1 << 7)
64 #define DESCRIPTOR_YY (1 << 6)
65 #define DESCRIPTOR_NO_IRQ (0 << 4)
66 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69 #define DESCRIPTOR_WAIT (3 << 0)
70
71 struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78 } __attribute__((aligned(16)));
79
80 #define CONTROL_SET(regs) (regs)
81 #define CONTROL_CLEAR(regs) ((regs) + 4)
82 #define COMMAND_PTR(regs) ((regs) + 12)
83 #define CONTEXT_MATCH(regs) ((regs) + 16)
84
85 #define AR_BUFFER_SIZE (32*1024)
86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87 /* we need at least two pages for proper list management */
88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90 #define MAX_ASYNC_PAYLOAD 4096
91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
93
94 struct ar_context {
95 struct fw_ohci *ohci;
96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
100 void *pointer;
101 unsigned int last_buffer_index;
102 u32 regs;
103 struct tasklet_struct tasklet;
104 };
105
106 struct context;
107
108 typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
111
112 /*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116 struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122 };
123
124 struct context {
125 struct fw_ohci *ohci;
126 u32 regs;
127 int total_allocation;
128 bool running;
129 bool flushing;
130
131 /*
132 * List of page-sized buffers for storing DMA descriptors.
133 * Head of list contains buffers in use and tail of list contains
134 * free buffers.
135 */
136 struct list_head buffer_list;
137
138 /*
139 * Pointer to a buffer inside buffer_list that contains the tail
140 * end of the current DMA program.
141 */
142 struct descriptor_buffer *buffer_tail;
143
144 /*
145 * The descriptor containing the branch address of the first
146 * descriptor that has not yet been filled by the device.
147 */
148 struct descriptor *last;
149
150 /*
151 * The last descriptor in the DMA program. It contains the branch
152 * address that must be updated upon appending a new descriptor.
153 */
154 struct descriptor *prev;
155
156 descriptor_callback_t callback;
157
158 struct tasklet_struct tasklet;
159 };
160
161 #define IT_HEADER_SY(v) ((v) << 0)
162 #define IT_HEADER_TCODE(v) ((v) << 4)
163 #define IT_HEADER_CHANNEL(v) ((v) << 8)
164 #define IT_HEADER_TAG(v) ((v) << 14)
165 #define IT_HEADER_SPEED(v) ((v) << 16)
166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
167
168 struct iso_context {
169 struct fw_iso_context base;
170 struct context context;
171 int excess_bytes;
172 void *header;
173 size_t header_length;
174
175 u8 sync;
176 u8 tags;
177 };
178
179 #define CONFIG_ROM_SIZE 1024
180
181 struct fw_ohci {
182 struct fw_card card;
183
184 __iomem char *registers;
185 int node_id;
186 int generation;
187 int request_generation; /* for timestamping incoming requests */
188 unsigned quirks;
189 unsigned int pri_req_max;
190 u32 bus_time;
191 bool is_root;
192 bool csr_state_setclear_abdicate;
193 int n_ir;
194 int n_it;
195 /*
196 * Spinlock for accessing fw_ohci data. Never call out of
197 * this driver with this lock held.
198 */
199 spinlock_t lock;
200
201 struct mutex phy_reg_mutex;
202
203 void *misc_buffer;
204 dma_addr_t misc_buffer_bus;
205
206 struct ar_context ar_request_ctx;
207 struct ar_context ar_response_ctx;
208 struct context at_request_ctx;
209 struct context at_response_ctx;
210
211 u32 it_context_support;
212 u32 it_context_mask; /* unoccupied IT contexts */
213 struct iso_context *it_context_list;
214 u64 ir_context_channels; /* unoccupied channels */
215 u32 ir_context_support;
216 u32 ir_context_mask; /* unoccupied IR contexts */
217 struct iso_context *ir_context_list;
218 u64 mc_channels; /* channels in use by the multichannel IR context */
219 bool mc_allocated;
220
221 __be32 *config_rom;
222 dma_addr_t config_rom_bus;
223 __be32 *next_config_rom;
224 dma_addr_t next_config_rom_bus;
225 __be32 next_header;
226
227 __le32 *self_id_cpu;
228 dma_addr_t self_id_bus;
229 struct tasklet_struct bus_reset_tasklet;
230
231 u32 self_id_buffer[512];
232 };
233
234 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
235 {
236 return container_of(card, struct fw_ohci, card);
237 }
238
239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
240 #define IR_CONTEXT_BUFFER_FILL 0x80000000
241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
245
246 #define CONTEXT_RUN 0x8000
247 #define CONTEXT_WAKE 0x1000
248 #define CONTEXT_DEAD 0x0800
249 #define CONTEXT_ACTIVE 0x0400
250
251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
254
255 #define OHCI1394_REGISTER_SIZE 0x800
256 #define OHCI_LOOP_COUNT 500
257 #define OHCI1394_PCI_HCI_Control 0x40
258 #define SELF_ID_BUF_SIZE 0x800
259 #define OHCI_TCODE_PHY_PACKET 0x0e
260 #define OHCI_VERSION_1_1 0x010010
261
262 static char ohci_driver_name[] = KBUILD_MODNAME;
263
264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
265 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
266 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
267 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
268
269 #define QUIRK_CYCLE_TIMER 1
270 #define QUIRK_RESET_PACKET 2
271 #define QUIRK_BE_HEADERS 4
272 #define QUIRK_NO_1394A 8
273 #define QUIRK_NO_MSI 16
274
275 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
276 static const struct {
277 unsigned short vendor, device, revision, flags;
278 } ohci_quirks[] = {
279 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
280 QUIRK_CYCLE_TIMER},
281
282 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
283 QUIRK_BE_HEADERS},
284
285 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
286 QUIRK_NO_MSI},
287
288 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
289 QUIRK_NO_MSI},
290
291 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
292 QUIRK_CYCLE_TIMER},
293
294 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
295 QUIRK_NO_MSI},
296
297 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
298 QUIRK_CYCLE_TIMER},
299
300 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
301 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
302
303 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
304 QUIRK_RESET_PACKET},
305
306 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
307 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
308 };
309
310 /* This overrides anything that was found in ohci_quirks[]. */
311 static int param_quirks;
312 module_param_named(quirks, param_quirks, int, 0644);
313 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
314 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
315 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
316 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
317 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
318 ", disable MSI = " __stringify(QUIRK_NO_MSI)
319 ")");
320
321 #define OHCI_PARAM_DEBUG_AT_AR 1
322 #define OHCI_PARAM_DEBUG_SELFIDS 2
323 #define OHCI_PARAM_DEBUG_IRQS 4
324 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
325
326 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
327
328 static int param_debug;
329 module_param_named(debug, param_debug, int, 0644);
330 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
331 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
332 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
333 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
334 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
335 ", or a combination, or all = -1)");
336
337 static void log_irqs(u32 evt)
338 {
339 if (likely(!(param_debug &
340 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
341 return;
342
343 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
344 !(evt & OHCI1394_busReset))
345 return;
346
347 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
348 evt & OHCI1394_selfIDComplete ? " selfID" : "",
349 evt & OHCI1394_RQPkt ? " AR_req" : "",
350 evt & OHCI1394_RSPkt ? " AR_resp" : "",
351 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
352 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
353 evt & OHCI1394_isochRx ? " IR" : "",
354 evt & OHCI1394_isochTx ? " IT" : "",
355 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
356 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
357 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
358 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
359 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
360 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
361 evt & OHCI1394_busReset ? " busReset" : "",
362 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
363 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
364 OHCI1394_respTxComplete | OHCI1394_isochRx |
365 OHCI1394_isochTx | OHCI1394_postedWriteErr |
366 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
367 OHCI1394_cycleInconsistent |
368 OHCI1394_regAccessFail | OHCI1394_busReset)
369 ? " ?" : "");
370 }
371
372 static const char *speed[] = {
373 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
374 };
375 static const char *power[] = {
376 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
377 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
378 };
379 static const char port[] = { '.', '-', 'p', 'c', };
380
381 static char _p(u32 *s, int shift)
382 {
383 return port[*s >> shift & 3];
384 }
385
386 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
387 {
388 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
389 return;
390
391 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
392 self_id_count, generation, node_id);
393
394 for (; self_id_count--; ++s)
395 if ((*s & 1 << 23) == 0)
396 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
397 "%s gc=%d %s %s%s%s\n",
398 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
399 speed[*s >> 14 & 3], *s >> 16 & 63,
400 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
401 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
402 else
403 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
404 *s, *s >> 24 & 63,
405 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
406 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
407 }
408
409 static const char *evts[] = {
410 [0x00] = "evt_no_status", [0x01] = "-reserved-",
411 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
412 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
413 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
414 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
415 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
416 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
417 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
418 [0x10] = "-reserved-", [0x11] = "ack_complete",
419 [0x12] = "ack_pending ", [0x13] = "-reserved-",
420 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
421 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
422 [0x18] = "-reserved-", [0x19] = "-reserved-",
423 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
424 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
425 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
426 [0x20] = "pending/cancelled",
427 };
428 static const char *tcodes[] = {
429 [0x0] = "QW req", [0x1] = "BW req",
430 [0x2] = "W resp", [0x3] = "-reserved-",
431 [0x4] = "QR req", [0x5] = "BR req",
432 [0x6] = "QR resp", [0x7] = "BR resp",
433 [0x8] = "cycle start", [0x9] = "Lk req",
434 [0xa] = "async stream packet", [0xb] = "Lk resp",
435 [0xc] = "-reserved-", [0xd] = "-reserved-",
436 [0xe] = "link internal", [0xf] = "-reserved-",
437 };
438
439 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
440 {
441 int tcode = header[0] >> 4 & 0xf;
442 char specific[12];
443
444 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
445 return;
446
447 if (unlikely(evt >= ARRAY_SIZE(evts)))
448 evt = 0x1f;
449
450 if (evt == OHCI1394_evt_bus_reset) {
451 fw_notify("A%c evt_bus_reset, generation %d\n",
452 dir, (header[2] >> 16) & 0xff);
453 return;
454 }
455
456 switch (tcode) {
457 case 0x0: case 0x6: case 0x8:
458 snprintf(specific, sizeof(specific), " = %08x",
459 be32_to_cpu((__force __be32)header[3]));
460 break;
461 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
462 snprintf(specific, sizeof(specific), " %x,%x",
463 header[3] >> 16, header[3] & 0xffff);
464 break;
465 default:
466 specific[0] = '\0';
467 }
468
469 switch (tcode) {
470 case 0xa:
471 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
472 break;
473 case 0xe:
474 fw_notify("A%c %s, PHY %08x %08x\n",
475 dir, evts[evt], header[1], header[2]);
476 break;
477 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
478 fw_notify("A%c spd %x tl %02x, "
479 "%04x -> %04x, %s, "
480 "%s, %04x%08x%s\n",
481 dir, speed, header[0] >> 10 & 0x3f,
482 header[1] >> 16, header[0] >> 16, evts[evt],
483 tcodes[tcode], header[1] & 0xffff, header[2], specific);
484 break;
485 default:
486 fw_notify("A%c spd %x tl %02x, "
487 "%04x -> %04x, %s, "
488 "%s%s\n",
489 dir, speed, header[0] >> 10 & 0x3f,
490 header[1] >> 16, header[0] >> 16, evts[evt],
491 tcodes[tcode], specific);
492 }
493 }
494
495 #else
496
497 #define param_debug 0
498 static inline void log_irqs(u32 evt) {}
499 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
500 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
501
502 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
503
504 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
505 {
506 writel(data, ohci->registers + offset);
507 }
508
509 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
510 {
511 return readl(ohci->registers + offset);
512 }
513
514 static inline void flush_writes(const struct fw_ohci *ohci)
515 {
516 /* Do a dummy read to flush writes. */
517 reg_read(ohci, OHCI1394_Version);
518 }
519
520 static int read_phy_reg(struct fw_ohci *ohci, int addr)
521 {
522 u32 val;
523 int i;
524
525 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
526 for (i = 0; i < 3 + 100; i++) {
527 val = reg_read(ohci, OHCI1394_PhyControl);
528 if (val & OHCI1394_PhyControl_ReadDone)
529 return OHCI1394_PhyControl_ReadData(val);
530
531 /*
532 * Try a few times without waiting. Sleeping is necessary
533 * only when the link/PHY interface is busy.
534 */
535 if (i >= 3)
536 msleep(1);
537 }
538 fw_error("failed to read phy reg\n");
539
540 return -EBUSY;
541 }
542
543 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
544 {
545 int i;
546
547 reg_write(ohci, OHCI1394_PhyControl,
548 OHCI1394_PhyControl_Write(addr, val));
549 for (i = 0; i < 3 + 100; i++) {
550 val = reg_read(ohci, OHCI1394_PhyControl);
551 if (!(val & OHCI1394_PhyControl_WritePending))
552 return 0;
553
554 if (i >= 3)
555 msleep(1);
556 }
557 fw_error("failed to write phy reg\n");
558
559 return -EBUSY;
560 }
561
562 static int update_phy_reg(struct fw_ohci *ohci, int addr,
563 int clear_bits, int set_bits)
564 {
565 int ret = read_phy_reg(ohci, addr);
566 if (ret < 0)
567 return ret;
568
569 /*
570 * The interrupt status bits are cleared by writing a one bit.
571 * Avoid clearing them unless explicitly requested in set_bits.
572 */
573 if (addr == 5)
574 clear_bits |= PHY_INT_STATUS_BITS;
575
576 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
577 }
578
579 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
580 {
581 int ret;
582
583 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
584 if (ret < 0)
585 return ret;
586
587 return read_phy_reg(ohci, addr);
588 }
589
590 static int ohci_read_phy_reg(struct fw_card *card, int addr)
591 {
592 struct fw_ohci *ohci = fw_ohci(card);
593 int ret;
594
595 mutex_lock(&ohci->phy_reg_mutex);
596 ret = read_phy_reg(ohci, addr);
597 mutex_unlock(&ohci->phy_reg_mutex);
598
599 return ret;
600 }
601
602 static int ohci_update_phy_reg(struct fw_card *card, int addr,
603 int clear_bits, int set_bits)
604 {
605 struct fw_ohci *ohci = fw_ohci(card);
606 int ret;
607
608 mutex_lock(&ohci->phy_reg_mutex);
609 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
610 mutex_unlock(&ohci->phy_reg_mutex);
611
612 return ret;
613 }
614
615 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
616 {
617 return page_private(ctx->pages[i]);
618 }
619
620 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
621 {
622 struct descriptor *d;
623
624 d = &ctx->descriptors[index];
625 d->branch_address &= cpu_to_le32(~0xf);
626 d->res_count = cpu_to_le16(PAGE_SIZE);
627 d->transfer_status = 0;
628
629 wmb(); /* finish init of new descriptors before branch_address update */
630 d = &ctx->descriptors[ctx->last_buffer_index];
631 d->branch_address |= cpu_to_le32(1);
632
633 ctx->last_buffer_index = index;
634
635 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
636 flush_writes(ctx->ohci);
637 }
638
639 static void ar_context_release(struct ar_context *ctx)
640 {
641 unsigned int i;
642
643 if (ctx->buffer)
644 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
645
646 for (i = 0; i < AR_BUFFERS; i++)
647 if (ctx->pages[i]) {
648 dma_unmap_page(ctx->ohci->card.device,
649 ar_buffer_bus(ctx, i),
650 PAGE_SIZE, DMA_FROM_DEVICE);
651 __free_page(ctx->pages[i]);
652 }
653 }
654
655 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
656 {
657 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
658 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
659 flush_writes(ctx->ohci);
660
661 fw_error("AR error: %s; DMA stopped\n", error_msg);
662 }
663 /* FIXME: restart? */
664 }
665
666 static inline unsigned int ar_next_buffer_index(unsigned int index)
667 {
668 return (index + 1) % AR_BUFFERS;
669 }
670
671 static inline unsigned int ar_prev_buffer_index(unsigned int index)
672 {
673 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
674 }
675
676 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
677 {
678 return ar_next_buffer_index(ctx->last_buffer_index);
679 }
680
681 /*
682 * We search for the buffer that contains the last AR packet DMA data written
683 * by the controller.
684 */
685 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
686 unsigned int *buffer_offset)
687 {
688 unsigned int i, next_i, last = ctx->last_buffer_index;
689 __le16 res_count, next_res_count;
690
691 i = ar_first_buffer_index(ctx);
692 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
693
694 /* A buffer that is not yet completely filled must be the last one. */
695 while (i != last && res_count == 0) {
696
697 /* Peek at the next descriptor. */
698 next_i = ar_next_buffer_index(i);
699 rmb(); /* read descriptors in order */
700 next_res_count = ACCESS_ONCE(
701 ctx->descriptors[next_i].res_count);
702 /*
703 * If the next descriptor is still empty, we must stop at this
704 * descriptor.
705 */
706 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
707 /*
708 * The exception is when the DMA data for one packet is
709 * split over three buffers; in this case, the middle
710 * buffer's descriptor might be never updated by the
711 * controller and look still empty, and we have to peek
712 * at the third one.
713 */
714 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
715 next_i = ar_next_buffer_index(next_i);
716 rmb();
717 next_res_count = ACCESS_ONCE(
718 ctx->descriptors[next_i].res_count);
719 if (next_res_count != cpu_to_le16(PAGE_SIZE))
720 goto next_buffer_is_active;
721 }
722
723 break;
724 }
725
726 next_buffer_is_active:
727 i = next_i;
728 res_count = next_res_count;
729 }
730
731 rmb(); /* read res_count before the DMA data */
732
733 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
734 if (*buffer_offset > PAGE_SIZE) {
735 *buffer_offset = 0;
736 ar_context_abort(ctx, "corrupted descriptor");
737 }
738
739 return i;
740 }
741
742 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
743 unsigned int end_buffer_index,
744 unsigned int end_buffer_offset)
745 {
746 unsigned int i;
747
748 i = ar_first_buffer_index(ctx);
749 while (i != end_buffer_index) {
750 dma_sync_single_for_cpu(ctx->ohci->card.device,
751 ar_buffer_bus(ctx, i),
752 PAGE_SIZE, DMA_FROM_DEVICE);
753 i = ar_next_buffer_index(i);
754 }
755 if (end_buffer_offset > 0)
756 dma_sync_single_for_cpu(ctx->ohci->card.device,
757 ar_buffer_bus(ctx, i),
758 end_buffer_offset, DMA_FROM_DEVICE);
759 }
760
761 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
762 #define cond_le32_to_cpu(v) \
763 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
764 #else
765 #define cond_le32_to_cpu(v) le32_to_cpu(v)
766 #endif
767
768 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
769 {
770 struct fw_ohci *ohci = ctx->ohci;
771 struct fw_packet p;
772 u32 status, length, tcode;
773 int evt;
774
775 p.header[0] = cond_le32_to_cpu(buffer[0]);
776 p.header[1] = cond_le32_to_cpu(buffer[1]);
777 p.header[2] = cond_le32_to_cpu(buffer[2]);
778
779 tcode = (p.header[0] >> 4) & 0x0f;
780 switch (tcode) {
781 case TCODE_WRITE_QUADLET_REQUEST:
782 case TCODE_READ_QUADLET_RESPONSE:
783 p.header[3] = (__force __u32) buffer[3];
784 p.header_length = 16;
785 p.payload_length = 0;
786 break;
787
788 case TCODE_READ_BLOCK_REQUEST :
789 p.header[3] = cond_le32_to_cpu(buffer[3]);
790 p.header_length = 16;
791 p.payload_length = 0;
792 break;
793
794 case TCODE_WRITE_BLOCK_REQUEST:
795 case TCODE_READ_BLOCK_RESPONSE:
796 case TCODE_LOCK_REQUEST:
797 case TCODE_LOCK_RESPONSE:
798 p.header[3] = cond_le32_to_cpu(buffer[3]);
799 p.header_length = 16;
800 p.payload_length = p.header[3] >> 16;
801 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
802 ar_context_abort(ctx, "invalid packet length");
803 return NULL;
804 }
805 break;
806
807 case TCODE_WRITE_RESPONSE:
808 case TCODE_READ_QUADLET_REQUEST:
809 case OHCI_TCODE_PHY_PACKET:
810 p.header_length = 12;
811 p.payload_length = 0;
812 break;
813
814 default:
815 ar_context_abort(ctx, "invalid tcode");
816 return NULL;
817 }
818
819 p.payload = (void *) buffer + p.header_length;
820
821 /* FIXME: What to do about evt_* errors? */
822 length = (p.header_length + p.payload_length + 3) / 4;
823 status = cond_le32_to_cpu(buffer[length]);
824 evt = (status >> 16) & 0x1f;
825
826 p.ack = evt - 16;
827 p.speed = (status >> 21) & 0x7;
828 p.timestamp = status & 0xffff;
829 p.generation = ohci->request_generation;
830
831 log_ar_at_event('R', p.speed, p.header, evt);
832
833 /*
834 * Several controllers, notably from NEC and VIA, forget to
835 * write ack_complete status at PHY packet reception.
836 */
837 if (evt == OHCI1394_evt_no_status &&
838 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
839 p.ack = ACK_COMPLETE;
840
841 /*
842 * The OHCI bus reset handler synthesizes a PHY packet with
843 * the new generation number when a bus reset happens (see
844 * section 8.4.2.3). This helps us determine when a request
845 * was received and make sure we send the response in the same
846 * generation. We only need this for requests; for responses
847 * we use the unique tlabel for finding the matching
848 * request.
849 *
850 * Alas some chips sometimes emit bus reset packets with a
851 * wrong generation. We set the correct generation for these
852 * at a slightly incorrect time (in bus_reset_tasklet).
853 */
854 if (evt == OHCI1394_evt_bus_reset) {
855 if (!(ohci->quirks & QUIRK_RESET_PACKET))
856 ohci->request_generation = (p.header[2] >> 16) & 0xff;
857 } else if (ctx == &ohci->ar_request_ctx) {
858 fw_core_handle_request(&ohci->card, &p);
859 } else {
860 fw_core_handle_response(&ohci->card, &p);
861 }
862
863 return buffer + length + 1;
864 }
865
866 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
867 {
868 void *next;
869
870 while (p < end) {
871 next = handle_ar_packet(ctx, p);
872 if (!next)
873 return p;
874 p = next;
875 }
876
877 return p;
878 }
879
880 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
881 {
882 unsigned int i;
883
884 i = ar_first_buffer_index(ctx);
885 while (i != end_buffer) {
886 dma_sync_single_for_device(ctx->ohci->card.device,
887 ar_buffer_bus(ctx, i),
888 PAGE_SIZE, DMA_FROM_DEVICE);
889 ar_context_link_page(ctx, i);
890 i = ar_next_buffer_index(i);
891 }
892 }
893
894 static void ar_context_tasklet(unsigned long data)
895 {
896 struct ar_context *ctx = (struct ar_context *)data;
897 unsigned int end_buffer_index, end_buffer_offset;
898 void *p, *end;
899
900 p = ctx->pointer;
901 if (!p)
902 return;
903
904 end_buffer_index = ar_search_last_active_buffer(ctx,
905 &end_buffer_offset);
906 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
907 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
908
909 if (end_buffer_index < ar_first_buffer_index(ctx)) {
910 /*
911 * The filled part of the overall buffer wraps around; handle
912 * all packets up to the buffer end here. If the last packet
913 * wraps around, its tail will be visible after the buffer end
914 * because the buffer start pages are mapped there again.
915 */
916 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
917 p = handle_ar_packets(ctx, p, buffer_end);
918 if (p < buffer_end)
919 goto error;
920 /* adjust p to point back into the actual buffer */
921 p -= AR_BUFFERS * PAGE_SIZE;
922 }
923
924 p = handle_ar_packets(ctx, p, end);
925 if (p != end) {
926 if (p > end)
927 ar_context_abort(ctx, "inconsistent descriptor");
928 goto error;
929 }
930
931 ctx->pointer = p;
932 ar_recycle_buffers(ctx, end_buffer_index);
933
934 return;
935
936 error:
937 ctx->pointer = NULL;
938 }
939
940 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
941 unsigned int descriptors_offset, u32 regs)
942 {
943 unsigned int i;
944 dma_addr_t dma_addr;
945 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
946 struct descriptor *d;
947
948 ctx->regs = regs;
949 ctx->ohci = ohci;
950 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
951
952 for (i = 0; i < AR_BUFFERS; i++) {
953 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
954 if (!ctx->pages[i])
955 goto out_of_memory;
956 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
957 0, PAGE_SIZE, DMA_FROM_DEVICE);
958 if (dma_mapping_error(ohci->card.device, dma_addr)) {
959 __free_page(ctx->pages[i]);
960 ctx->pages[i] = NULL;
961 goto out_of_memory;
962 }
963 set_page_private(ctx->pages[i], dma_addr);
964 }
965
966 for (i = 0; i < AR_BUFFERS; i++)
967 pages[i] = ctx->pages[i];
968 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
969 pages[AR_BUFFERS + i] = ctx->pages[i];
970 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
971 -1, PAGE_KERNEL);
972 if (!ctx->buffer)
973 goto out_of_memory;
974
975 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
976 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
977
978 for (i = 0; i < AR_BUFFERS; i++) {
979 d = &ctx->descriptors[i];
980 d->req_count = cpu_to_le16(PAGE_SIZE);
981 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
982 DESCRIPTOR_STATUS |
983 DESCRIPTOR_BRANCH_ALWAYS);
984 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
985 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
986 ar_next_buffer_index(i) * sizeof(struct descriptor));
987 }
988
989 return 0;
990
991 out_of_memory:
992 ar_context_release(ctx);
993
994 return -ENOMEM;
995 }
996
997 static void ar_context_run(struct ar_context *ctx)
998 {
999 unsigned int i;
1000
1001 for (i = 0; i < AR_BUFFERS; i++)
1002 ar_context_link_page(ctx, i);
1003
1004 ctx->pointer = ctx->buffer;
1005
1006 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1007 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1008 flush_writes(ctx->ohci);
1009 }
1010
1011 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1012 {
1013 __le16 branch;
1014
1015 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1016
1017 /* figure out which descriptor the branch address goes in */
1018 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1019 return d;
1020 else
1021 return d + z - 1;
1022 }
1023
1024 static void context_tasklet(unsigned long data)
1025 {
1026 struct context *ctx = (struct context *) data;
1027 struct descriptor *d, *last;
1028 u32 address;
1029 int z;
1030 struct descriptor_buffer *desc;
1031
1032 desc = list_entry(ctx->buffer_list.next,
1033 struct descriptor_buffer, list);
1034 last = ctx->last;
1035 while (last->branch_address != 0) {
1036 struct descriptor_buffer *old_desc = desc;
1037 address = le32_to_cpu(last->branch_address);
1038 z = address & 0xf;
1039 address &= ~0xf;
1040
1041 /* If the branch address points to a buffer outside of the
1042 * current buffer, advance to the next buffer. */
1043 if (address < desc->buffer_bus ||
1044 address >= desc->buffer_bus + desc->used)
1045 desc = list_entry(desc->list.next,
1046 struct descriptor_buffer, list);
1047 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1048 last = find_branch_descriptor(d, z);
1049
1050 if (!ctx->callback(ctx, d, last))
1051 break;
1052
1053 if (old_desc != desc) {
1054 /* If we've advanced to the next buffer, move the
1055 * previous buffer to the free list. */
1056 unsigned long flags;
1057 old_desc->used = 0;
1058 spin_lock_irqsave(&ctx->ohci->lock, flags);
1059 list_move_tail(&old_desc->list, &ctx->buffer_list);
1060 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1061 }
1062 ctx->last = last;
1063 }
1064 }
1065
1066 /*
1067 * Allocate a new buffer and add it to the list of free buffers for this
1068 * context. Must be called with ohci->lock held.
1069 */
1070 static int context_add_buffer(struct context *ctx)
1071 {
1072 struct descriptor_buffer *desc;
1073 dma_addr_t uninitialized_var(bus_addr);
1074 int offset;
1075
1076 /*
1077 * 16MB of descriptors should be far more than enough for any DMA
1078 * program. This will catch run-away userspace or DoS attacks.
1079 */
1080 if (ctx->total_allocation >= 16*1024*1024)
1081 return -ENOMEM;
1082
1083 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1084 &bus_addr, GFP_ATOMIC);
1085 if (!desc)
1086 return -ENOMEM;
1087
1088 offset = (void *)&desc->buffer - (void *)desc;
1089 desc->buffer_size = PAGE_SIZE - offset;
1090 desc->buffer_bus = bus_addr + offset;
1091 desc->used = 0;
1092
1093 list_add_tail(&desc->list, &ctx->buffer_list);
1094 ctx->total_allocation += PAGE_SIZE;
1095
1096 return 0;
1097 }
1098
1099 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1100 u32 regs, descriptor_callback_t callback)
1101 {
1102 ctx->ohci = ohci;
1103 ctx->regs = regs;
1104 ctx->total_allocation = 0;
1105
1106 INIT_LIST_HEAD(&ctx->buffer_list);
1107 if (context_add_buffer(ctx) < 0)
1108 return -ENOMEM;
1109
1110 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1111 struct descriptor_buffer, list);
1112
1113 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1114 ctx->callback = callback;
1115
1116 /*
1117 * We put a dummy descriptor in the buffer that has a NULL
1118 * branch address and looks like it's been sent. That way we
1119 * have a descriptor to append DMA programs to.
1120 */
1121 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1122 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1123 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1124 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1125 ctx->last = ctx->buffer_tail->buffer;
1126 ctx->prev = ctx->buffer_tail->buffer;
1127
1128 return 0;
1129 }
1130
1131 static void context_release(struct context *ctx)
1132 {
1133 struct fw_card *card = &ctx->ohci->card;
1134 struct descriptor_buffer *desc, *tmp;
1135
1136 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1137 dma_free_coherent(card->device, PAGE_SIZE, desc,
1138 desc->buffer_bus -
1139 ((void *)&desc->buffer - (void *)desc));
1140 }
1141
1142 /* Must be called with ohci->lock held */
1143 static struct descriptor *context_get_descriptors(struct context *ctx,
1144 int z, dma_addr_t *d_bus)
1145 {
1146 struct descriptor *d = NULL;
1147 struct descriptor_buffer *desc = ctx->buffer_tail;
1148
1149 if (z * sizeof(*d) > desc->buffer_size)
1150 return NULL;
1151
1152 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1153 /* No room for the descriptor in this buffer, so advance to the
1154 * next one. */
1155
1156 if (desc->list.next == &ctx->buffer_list) {
1157 /* If there is no free buffer next in the list,
1158 * allocate one. */
1159 if (context_add_buffer(ctx) < 0)
1160 return NULL;
1161 }
1162 desc = list_entry(desc->list.next,
1163 struct descriptor_buffer, list);
1164 ctx->buffer_tail = desc;
1165 }
1166
1167 d = desc->buffer + desc->used / sizeof(*d);
1168 memset(d, 0, z * sizeof(*d));
1169 *d_bus = desc->buffer_bus + desc->used;
1170
1171 return d;
1172 }
1173
1174 static void context_run(struct context *ctx, u32 extra)
1175 {
1176 struct fw_ohci *ohci = ctx->ohci;
1177
1178 reg_write(ohci, COMMAND_PTR(ctx->regs),
1179 le32_to_cpu(ctx->last->branch_address));
1180 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1181 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1182 ctx->running = true;
1183 flush_writes(ohci);
1184 }
1185
1186 static void context_append(struct context *ctx,
1187 struct descriptor *d, int z, int extra)
1188 {
1189 dma_addr_t d_bus;
1190 struct descriptor_buffer *desc = ctx->buffer_tail;
1191
1192 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1193
1194 desc->used += (z + extra) * sizeof(*d);
1195
1196 wmb(); /* finish init of new descriptors before branch_address update */
1197 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1198 ctx->prev = find_branch_descriptor(d, z);
1199 }
1200
1201 static void context_stop(struct context *ctx)
1202 {
1203 u32 reg;
1204 int i;
1205
1206 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1207 ctx->running = false;
1208 flush_writes(ctx->ohci);
1209
1210 for (i = 0; i < 10; i++) {
1211 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1212 if ((reg & CONTEXT_ACTIVE) == 0)
1213 return;
1214
1215 mdelay(1);
1216 }
1217 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1218 }
1219
1220 struct driver_data {
1221 u8 inline_data[8];
1222 struct fw_packet *packet;
1223 };
1224
1225 /*
1226 * This function apppends a packet to the DMA queue for transmission.
1227 * Must always be called with the ochi->lock held to ensure proper
1228 * generation handling and locking around packet queue manipulation.
1229 */
1230 static int at_context_queue_packet(struct context *ctx,
1231 struct fw_packet *packet)
1232 {
1233 struct fw_ohci *ohci = ctx->ohci;
1234 dma_addr_t d_bus, uninitialized_var(payload_bus);
1235 struct driver_data *driver_data;
1236 struct descriptor *d, *last;
1237 __le32 *header;
1238 int z, tcode;
1239
1240 d = context_get_descriptors(ctx, 4, &d_bus);
1241 if (d == NULL) {
1242 packet->ack = RCODE_SEND_ERROR;
1243 return -1;
1244 }
1245
1246 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1247 d[0].res_count = cpu_to_le16(packet->timestamp);
1248
1249 /*
1250 * The DMA format for asyncronous link packets is different
1251 * from the IEEE1394 layout, so shift the fields around
1252 * accordingly.
1253 */
1254
1255 tcode = (packet->header[0] >> 4) & 0x0f;
1256 header = (__le32 *) &d[1];
1257 switch (tcode) {
1258 case TCODE_WRITE_QUADLET_REQUEST:
1259 case TCODE_WRITE_BLOCK_REQUEST:
1260 case TCODE_WRITE_RESPONSE:
1261 case TCODE_READ_QUADLET_REQUEST:
1262 case TCODE_READ_BLOCK_REQUEST:
1263 case TCODE_READ_QUADLET_RESPONSE:
1264 case TCODE_READ_BLOCK_RESPONSE:
1265 case TCODE_LOCK_REQUEST:
1266 case TCODE_LOCK_RESPONSE:
1267 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1268 (packet->speed << 16));
1269 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1270 (packet->header[0] & 0xffff0000));
1271 header[2] = cpu_to_le32(packet->header[2]);
1272
1273 if (TCODE_IS_BLOCK_PACKET(tcode))
1274 header[3] = cpu_to_le32(packet->header[3]);
1275 else
1276 header[3] = (__force __le32) packet->header[3];
1277
1278 d[0].req_count = cpu_to_le16(packet->header_length);
1279 break;
1280
1281 case TCODE_LINK_INTERNAL:
1282 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1283 (packet->speed << 16));
1284 header[1] = cpu_to_le32(packet->header[1]);
1285 header[2] = cpu_to_le32(packet->header[2]);
1286 d[0].req_count = cpu_to_le16(12);
1287
1288 if (is_ping_packet(&packet->header[1]))
1289 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1290 break;
1291
1292 case TCODE_STREAM_DATA:
1293 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1294 (packet->speed << 16));
1295 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1296 d[0].req_count = cpu_to_le16(8);
1297 break;
1298
1299 default:
1300 /* BUG(); */
1301 packet->ack = RCODE_SEND_ERROR;
1302 return -1;
1303 }
1304
1305 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1306 driver_data = (struct driver_data *) &d[3];
1307 driver_data->packet = packet;
1308 packet->driver_data = driver_data;
1309
1310 if (packet->payload_length > 0) {
1311 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1312 payload_bus = dma_map_single(ohci->card.device,
1313 packet->payload,
1314 packet->payload_length,
1315 DMA_TO_DEVICE);
1316 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1317 packet->ack = RCODE_SEND_ERROR;
1318 return -1;
1319 }
1320 packet->payload_bus = payload_bus;
1321 packet->payload_mapped = true;
1322 } else {
1323 memcpy(driver_data->inline_data, packet->payload,
1324 packet->payload_length);
1325 payload_bus = d_bus + 3 * sizeof(*d);
1326 }
1327
1328 d[2].req_count = cpu_to_le16(packet->payload_length);
1329 d[2].data_address = cpu_to_le32(payload_bus);
1330 last = &d[2];
1331 z = 3;
1332 } else {
1333 last = &d[0];
1334 z = 2;
1335 }
1336
1337 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1338 DESCRIPTOR_IRQ_ALWAYS |
1339 DESCRIPTOR_BRANCH_ALWAYS);
1340
1341 /* FIXME: Document how the locking works. */
1342 if (ohci->generation != packet->generation) {
1343 if (packet->payload_mapped)
1344 dma_unmap_single(ohci->card.device, payload_bus,
1345 packet->payload_length, DMA_TO_DEVICE);
1346 packet->ack = RCODE_GENERATION;
1347 return -1;
1348 }
1349
1350 context_append(ctx, d, z, 4 - z);
1351
1352 if (ctx->running) {
1353 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1354 flush_writes(ohci);
1355 } else {
1356 context_run(ctx, 0);
1357 }
1358
1359 return 0;
1360 }
1361
1362 static void at_context_flush(struct context *ctx)
1363 {
1364 tasklet_disable(&ctx->tasklet);
1365
1366 ctx->flushing = true;
1367 context_tasklet((unsigned long)ctx);
1368 ctx->flushing = false;
1369
1370 tasklet_enable(&ctx->tasklet);
1371 }
1372
1373 static int handle_at_packet(struct context *context,
1374 struct descriptor *d,
1375 struct descriptor *last)
1376 {
1377 struct driver_data *driver_data;
1378 struct fw_packet *packet;
1379 struct fw_ohci *ohci = context->ohci;
1380 int evt;
1381
1382 if (last->transfer_status == 0 && !context->flushing)
1383 /* This descriptor isn't done yet, stop iteration. */
1384 return 0;
1385
1386 driver_data = (struct driver_data *) &d[3];
1387 packet = driver_data->packet;
1388 if (packet == NULL)
1389 /* This packet was cancelled, just continue. */
1390 return 1;
1391
1392 if (packet->payload_mapped)
1393 dma_unmap_single(ohci->card.device, packet->payload_bus,
1394 packet->payload_length, DMA_TO_DEVICE);
1395
1396 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1397 packet->timestamp = le16_to_cpu(last->res_count);
1398
1399 log_ar_at_event('T', packet->speed, packet->header, evt);
1400
1401 switch (evt) {
1402 case OHCI1394_evt_timeout:
1403 /* Async response transmit timed out. */
1404 packet->ack = RCODE_CANCELLED;
1405 break;
1406
1407 case OHCI1394_evt_flushed:
1408 /*
1409 * The packet was flushed should give same error as
1410 * when we try to use a stale generation count.
1411 */
1412 packet->ack = RCODE_GENERATION;
1413 break;
1414
1415 case OHCI1394_evt_missing_ack:
1416 if (context->flushing)
1417 packet->ack = RCODE_GENERATION;
1418 else {
1419 /*
1420 * Using a valid (current) generation count, but the
1421 * node is not on the bus or not sending acks.
1422 */
1423 packet->ack = RCODE_NO_ACK;
1424 }
1425 break;
1426
1427 case ACK_COMPLETE + 0x10:
1428 case ACK_PENDING + 0x10:
1429 case ACK_BUSY_X + 0x10:
1430 case ACK_BUSY_A + 0x10:
1431 case ACK_BUSY_B + 0x10:
1432 case ACK_DATA_ERROR + 0x10:
1433 case ACK_TYPE_ERROR + 0x10:
1434 packet->ack = evt - 0x10;
1435 break;
1436
1437 case OHCI1394_evt_no_status:
1438 if (context->flushing) {
1439 packet->ack = RCODE_GENERATION;
1440 break;
1441 }
1442 /* fall through */
1443
1444 default:
1445 packet->ack = RCODE_SEND_ERROR;
1446 break;
1447 }
1448
1449 packet->callback(packet, &ohci->card, packet->ack);
1450
1451 return 1;
1452 }
1453
1454 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1455 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1456 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1457 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1458 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1459
1460 static void handle_local_rom(struct fw_ohci *ohci,
1461 struct fw_packet *packet, u32 csr)
1462 {
1463 struct fw_packet response;
1464 int tcode, length, i;
1465
1466 tcode = HEADER_GET_TCODE(packet->header[0]);
1467 if (TCODE_IS_BLOCK_PACKET(tcode))
1468 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1469 else
1470 length = 4;
1471
1472 i = csr - CSR_CONFIG_ROM;
1473 if (i + length > CONFIG_ROM_SIZE) {
1474 fw_fill_response(&response, packet->header,
1475 RCODE_ADDRESS_ERROR, NULL, 0);
1476 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1477 fw_fill_response(&response, packet->header,
1478 RCODE_TYPE_ERROR, NULL, 0);
1479 } else {
1480 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1481 (void *) ohci->config_rom + i, length);
1482 }
1483
1484 fw_core_handle_response(&ohci->card, &response);
1485 }
1486
1487 static void handle_local_lock(struct fw_ohci *ohci,
1488 struct fw_packet *packet, u32 csr)
1489 {
1490 struct fw_packet response;
1491 int tcode, length, ext_tcode, sel, try;
1492 __be32 *payload, lock_old;
1493 u32 lock_arg, lock_data;
1494
1495 tcode = HEADER_GET_TCODE(packet->header[0]);
1496 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1497 payload = packet->payload;
1498 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1499
1500 if (tcode == TCODE_LOCK_REQUEST &&
1501 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1502 lock_arg = be32_to_cpu(payload[0]);
1503 lock_data = be32_to_cpu(payload[1]);
1504 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1505 lock_arg = 0;
1506 lock_data = 0;
1507 } else {
1508 fw_fill_response(&response, packet->header,
1509 RCODE_TYPE_ERROR, NULL, 0);
1510 goto out;
1511 }
1512
1513 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1514 reg_write(ohci, OHCI1394_CSRData, lock_data);
1515 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1516 reg_write(ohci, OHCI1394_CSRControl, sel);
1517
1518 for (try = 0; try < 20; try++)
1519 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1520 lock_old = cpu_to_be32(reg_read(ohci,
1521 OHCI1394_CSRData));
1522 fw_fill_response(&response, packet->header,
1523 RCODE_COMPLETE,
1524 &lock_old, sizeof(lock_old));
1525 goto out;
1526 }
1527
1528 fw_error("swap not done (CSR lock timeout)\n");
1529 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1530
1531 out:
1532 fw_core_handle_response(&ohci->card, &response);
1533 }
1534
1535 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1536 {
1537 u64 offset, csr;
1538
1539 if (ctx == &ctx->ohci->at_request_ctx) {
1540 packet->ack = ACK_PENDING;
1541 packet->callback(packet, &ctx->ohci->card, packet->ack);
1542 }
1543
1544 offset =
1545 ((unsigned long long)
1546 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1547 packet->header[2];
1548 csr = offset - CSR_REGISTER_BASE;
1549
1550 /* Handle config rom reads. */
1551 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1552 handle_local_rom(ctx->ohci, packet, csr);
1553 else switch (csr) {
1554 case CSR_BUS_MANAGER_ID:
1555 case CSR_BANDWIDTH_AVAILABLE:
1556 case CSR_CHANNELS_AVAILABLE_HI:
1557 case CSR_CHANNELS_AVAILABLE_LO:
1558 handle_local_lock(ctx->ohci, packet, csr);
1559 break;
1560 default:
1561 if (ctx == &ctx->ohci->at_request_ctx)
1562 fw_core_handle_request(&ctx->ohci->card, packet);
1563 else
1564 fw_core_handle_response(&ctx->ohci->card, packet);
1565 break;
1566 }
1567
1568 if (ctx == &ctx->ohci->at_response_ctx) {
1569 packet->ack = ACK_COMPLETE;
1570 packet->callback(packet, &ctx->ohci->card, packet->ack);
1571 }
1572 }
1573
1574 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1575 {
1576 unsigned long flags;
1577 int ret;
1578
1579 spin_lock_irqsave(&ctx->ohci->lock, flags);
1580
1581 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1582 ctx->ohci->generation == packet->generation) {
1583 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1584 handle_local_request(ctx, packet);
1585 return;
1586 }
1587
1588 ret = at_context_queue_packet(ctx, packet);
1589 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1590
1591 if (ret < 0)
1592 packet->callback(packet, &ctx->ohci->card, packet->ack);
1593
1594 }
1595
1596 static void detect_dead_context(struct fw_ohci *ohci,
1597 const char *name, unsigned int regs)
1598 {
1599 u32 ctl;
1600
1601 ctl = reg_read(ohci, CONTROL_SET(regs));
1602 if (ctl & CONTEXT_DEAD) {
1603 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1604 fw_error("DMA context %s has stopped, error code: %s\n",
1605 name, evts[ctl & 0x1f]);
1606 #else
1607 fw_error("DMA context %s has stopped, error code: %#x\n",
1608 name, ctl & 0x1f);
1609 #endif
1610 }
1611 }
1612
1613 static void handle_dead_contexts(struct fw_ohci *ohci)
1614 {
1615 unsigned int i;
1616 char name[8];
1617
1618 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1619 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1620 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1621 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1622 for (i = 0; i < 32; ++i) {
1623 if (!(ohci->it_context_support & (1 << i)))
1624 continue;
1625 sprintf(name, "IT%u", i);
1626 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1627 }
1628 for (i = 0; i < 32; ++i) {
1629 if (!(ohci->ir_context_support & (1 << i)))
1630 continue;
1631 sprintf(name, "IR%u", i);
1632 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1633 }
1634 /* TODO: maybe try to flush and restart the dead contexts */
1635 }
1636
1637 static u32 cycle_timer_ticks(u32 cycle_timer)
1638 {
1639 u32 ticks;
1640
1641 ticks = cycle_timer & 0xfff;
1642 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1643 ticks += (3072 * 8000) * (cycle_timer >> 25);
1644
1645 return ticks;
1646 }
1647
1648 /*
1649 * Some controllers exhibit one or more of the following bugs when updating the
1650 * iso cycle timer register:
1651 * - When the lowest six bits are wrapping around to zero, a read that happens
1652 * at the same time will return garbage in the lowest ten bits.
1653 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1654 * not incremented for about 60 ns.
1655 * - Occasionally, the entire register reads zero.
1656 *
1657 * To catch these, we read the register three times and ensure that the
1658 * difference between each two consecutive reads is approximately the same, i.e.
1659 * less than twice the other. Furthermore, any negative difference indicates an
1660 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1661 * execute, so we have enough precision to compute the ratio of the differences.)
1662 */
1663 static u32 get_cycle_time(struct fw_ohci *ohci)
1664 {
1665 u32 c0, c1, c2;
1666 u32 t0, t1, t2;
1667 s32 diff01, diff12;
1668 int i;
1669
1670 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1671
1672 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1673 i = 0;
1674 c1 = c2;
1675 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1676 do {
1677 c0 = c1;
1678 c1 = c2;
1679 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1680 t0 = cycle_timer_ticks(c0);
1681 t1 = cycle_timer_ticks(c1);
1682 t2 = cycle_timer_ticks(c2);
1683 diff01 = t1 - t0;
1684 diff12 = t2 - t1;
1685 } while ((diff01 <= 0 || diff12 <= 0 ||
1686 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1687 && i++ < 20);
1688 }
1689
1690 return c2;
1691 }
1692
1693 /*
1694 * This function has to be called at least every 64 seconds. The bus_time
1695 * field stores not only the upper 25 bits of the BUS_TIME register but also
1696 * the most significant bit of the cycle timer in bit 6 so that we can detect
1697 * changes in this bit.
1698 */
1699 static u32 update_bus_time(struct fw_ohci *ohci)
1700 {
1701 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1702
1703 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1704 ohci->bus_time += 0x40;
1705
1706 return ohci->bus_time | cycle_time_seconds;
1707 }
1708
1709 static void bus_reset_tasklet(unsigned long data)
1710 {
1711 struct fw_ohci *ohci = (struct fw_ohci *)data;
1712 int self_id_count, i, j, reg;
1713 int generation, new_generation;
1714 unsigned long flags;
1715 void *free_rom = NULL;
1716 dma_addr_t free_rom_bus = 0;
1717 bool is_new_root;
1718
1719 reg = reg_read(ohci, OHCI1394_NodeID);
1720 if (!(reg & OHCI1394_NodeID_idValid)) {
1721 fw_notify("node ID not valid, new bus reset in progress\n");
1722 return;
1723 }
1724 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1725 fw_notify("malconfigured bus\n");
1726 return;
1727 }
1728 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1729 OHCI1394_NodeID_nodeNumber);
1730
1731 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1732 if (!(ohci->is_root && is_new_root))
1733 reg_write(ohci, OHCI1394_LinkControlSet,
1734 OHCI1394_LinkControl_cycleMaster);
1735 ohci->is_root = is_new_root;
1736
1737 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1738 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1739 fw_notify("inconsistent self IDs\n");
1740 return;
1741 }
1742 /*
1743 * The count in the SelfIDCount register is the number of
1744 * bytes in the self ID receive buffer. Since we also receive
1745 * the inverted quadlets and a header quadlet, we shift one
1746 * bit extra to get the actual number of self IDs.
1747 */
1748 self_id_count = (reg >> 3) & 0xff;
1749 if (self_id_count == 0 || self_id_count > 252) {
1750 fw_notify("inconsistent self IDs\n");
1751 return;
1752 }
1753 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1754 rmb();
1755
1756 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1757 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1758 fw_notify("inconsistent self IDs\n");
1759 return;
1760 }
1761 ohci->self_id_buffer[j] =
1762 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1763 }
1764 rmb();
1765
1766 /*
1767 * Check the consistency of the self IDs we just read. The
1768 * problem we face is that a new bus reset can start while we
1769 * read out the self IDs from the DMA buffer. If this happens,
1770 * the DMA buffer will be overwritten with new self IDs and we
1771 * will read out inconsistent data. The OHCI specification
1772 * (section 11.2) recommends a technique similar to
1773 * linux/seqlock.h, where we remember the generation of the
1774 * self IDs in the buffer before reading them out and compare
1775 * it to the current generation after reading them out. If
1776 * the two generations match we know we have a consistent set
1777 * of self IDs.
1778 */
1779
1780 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1781 if (new_generation != generation) {
1782 fw_notify("recursive bus reset detected, "
1783 "discarding self ids\n");
1784 return;
1785 }
1786
1787 /* FIXME: Document how the locking works. */
1788 spin_lock_irqsave(&ohci->lock, flags);
1789
1790 ohci->generation = -1; /* prevent AT packet queueing */
1791 context_stop(&ohci->at_request_ctx);
1792 context_stop(&ohci->at_response_ctx);
1793
1794 spin_unlock_irqrestore(&ohci->lock, flags);
1795
1796 /*
1797 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1798 * packets in the AT queues and software needs to drain them.
1799 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1800 */
1801 at_context_flush(&ohci->at_request_ctx);
1802 at_context_flush(&ohci->at_response_ctx);
1803
1804 spin_lock_irqsave(&ohci->lock, flags);
1805
1806 ohci->generation = generation;
1807 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1808
1809 if (ohci->quirks & QUIRK_RESET_PACKET)
1810 ohci->request_generation = generation;
1811
1812 /*
1813 * This next bit is unrelated to the AT context stuff but we
1814 * have to do it under the spinlock also. If a new config rom
1815 * was set up before this reset, the old one is now no longer
1816 * in use and we can free it. Update the config rom pointers
1817 * to point to the current config rom and clear the
1818 * next_config_rom pointer so a new update can take place.
1819 */
1820
1821 if (ohci->next_config_rom != NULL) {
1822 if (ohci->next_config_rom != ohci->config_rom) {
1823 free_rom = ohci->config_rom;
1824 free_rom_bus = ohci->config_rom_bus;
1825 }
1826 ohci->config_rom = ohci->next_config_rom;
1827 ohci->config_rom_bus = ohci->next_config_rom_bus;
1828 ohci->next_config_rom = NULL;
1829
1830 /*
1831 * Restore config_rom image and manually update
1832 * config_rom registers. Writing the header quadlet
1833 * will indicate that the config rom is ready, so we
1834 * do that last.
1835 */
1836 reg_write(ohci, OHCI1394_BusOptions,
1837 be32_to_cpu(ohci->config_rom[2]));
1838 ohci->config_rom[0] = ohci->next_header;
1839 reg_write(ohci, OHCI1394_ConfigROMhdr,
1840 be32_to_cpu(ohci->next_header));
1841 }
1842
1843 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1844 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1845 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1846 #endif
1847
1848 spin_unlock_irqrestore(&ohci->lock, flags);
1849
1850 if (free_rom)
1851 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1852 free_rom, free_rom_bus);
1853
1854 log_selfids(ohci->node_id, generation,
1855 self_id_count, ohci->self_id_buffer);
1856
1857 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1858 self_id_count, ohci->self_id_buffer,
1859 ohci->csr_state_setclear_abdicate);
1860 ohci->csr_state_setclear_abdicate = false;
1861 }
1862
1863 static irqreturn_t irq_handler(int irq, void *data)
1864 {
1865 struct fw_ohci *ohci = data;
1866 u32 event, iso_event;
1867 int i;
1868
1869 event = reg_read(ohci, OHCI1394_IntEventClear);
1870
1871 if (!event || !~event)
1872 return IRQ_NONE;
1873
1874 /*
1875 * busReset and postedWriteErr must not be cleared yet
1876 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1877 */
1878 reg_write(ohci, OHCI1394_IntEventClear,
1879 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1880 log_irqs(event);
1881
1882 if (event & OHCI1394_selfIDComplete)
1883 tasklet_schedule(&ohci->bus_reset_tasklet);
1884
1885 if (event & OHCI1394_RQPkt)
1886 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1887
1888 if (event & OHCI1394_RSPkt)
1889 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1890
1891 if (event & OHCI1394_reqTxComplete)
1892 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1893
1894 if (event & OHCI1394_respTxComplete)
1895 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1896
1897 if (event & OHCI1394_isochRx) {
1898 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1899 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1900
1901 while (iso_event) {
1902 i = ffs(iso_event) - 1;
1903 tasklet_schedule(
1904 &ohci->ir_context_list[i].context.tasklet);
1905 iso_event &= ~(1 << i);
1906 }
1907 }
1908
1909 if (event & OHCI1394_isochTx) {
1910 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1911 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1912
1913 while (iso_event) {
1914 i = ffs(iso_event) - 1;
1915 tasklet_schedule(
1916 &ohci->it_context_list[i].context.tasklet);
1917 iso_event &= ~(1 << i);
1918 }
1919 }
1920
1921 if (unlikely(event & OHCI1394_regAccessFail))
1922 fw_error("Register access failure - "
1923 "please notify linux1394-devel@lists.sf.net\n");
1924
1925 if (unlikely(event & OHCI1394_postedWriteErr)) {
1926 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1927 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1928 reg_write(ohci, OHCI1394_IntEventClear,
1929 OHCI1394_postedWriteErr);
1930 fw_error("PCI posted write error\n");
1931 }
1932
1933 if (unlikely(event & OHCI1394_cycleTooLong)) {
1934 if (printk_ratelimit())
1935 fw_notify("isochronous cycle too long\n");
1936 reg_write(ohci, OHCI1394_LinkControlSet,
1937 OHCI1394_LinkControl_cycleMaster);
1938 }
1939
1940 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1941 /*
1942 * We need to clear this event bit in order to make
1943 * cycleMatch isochronous I/O work. In theory we should
1944 * stop active cycleMatch iso contexts now and restart
1945 * them at least two cycles later. (FIXME?)
1946 */
1947 if (printk_ratelimit())
1948 fw_notify("isochronous cycle inconsistent\n");
1949 }
1950
1951 if (unlikely(event & OHCI1394_unrecoverableError))
1952 handle_dead_contexts(ohci);
1953
1954 if (event & OHCI1394_cycle64Seconds) {
1955 spin_lock(&ohci->lock);
1956 update_bus_time(ohci);
1957 spin_unlock(&ohci->lock);
1958 } else
1959 flush_writes(ohci);
1960
1961 return IRQ_HANDLED;
1962 }
1963
1964 static int software_reset(struct fw_ohci *ohci)
1965 {
1966 int i;
1967
1968 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1969
1970 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1971 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1972 OHCI1394_HCControl_softReset) == 0)
1973 return 0;
1974 msleep(1);
1975 }
1976
1977 return -EBUSY;
1978 }
1979
1980 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1981 {
1982 size_t size = length * 4;
1983
1984 memcpy(dest, src, size);
1985 if (size < CONFIG_ROM_SIZE)
1986 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1987 }
1988
1989 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1990 {
1991 bool enable_1394a;
1992 int ret, clear, set, offset;
1993
1994 /* Check if the driver should configure link and PHY. */
1995 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1996 OHCI1394_HCControl_programPhyEnable))
1997 return 0;
1998
1999 /* Paranoia: check whether the PHY supports 1394a, too. */
2000 enable_1394a = false;
2001 ret = read_phy_reg(ohci, 2);
2002 if (ret < 0)
2003 return ret;
2004 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2005 ret = read_paged_phy_reg(ohci, 1, 8);
2006 if (ret < 0)
2007 return ret;
2008 if (ret >= 1)
2009 enable_1394a = true;
2010 }
2011
2012 if (ohci->quirks & QUIRK_NO_1394A)
2013 enable_1394a = false;
2014
2015 /* Configure PHY and link consistently. */
2016 if (enable_1394a) {
2017 clear = 0;
2018 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2019 } else {
2020 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2021 set = 0;
2022 }
2023 ret = update_phy_reg(ohci, 5, clear, set);
2024 if (ret < 0)
2025 return ret;
2026
2027 if (enable_1394a)
2028 offset = OHCI1394_HCControlSet;
2029 else
2030 offset = OHCI1394_HCControlClear;
2031 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2032
2033 /* Clean up: configuration has been taken care of. */
2034 reg_write(ohci, OHCI1394_HCControlClear,
2035 OHCI1394_HCControl_programPhyEnable);
2036
2037 return 0;
2038 }
2039
2040 static int ohci_enable(struct fw_card *card,
2041 const __be32 *config_rom, size_t length)
2042 {
2043 struct fw_ohci *ohci = fw_ohci(card);
2044 struct pci_dev *dev = to_pci_dev(card->device);
2045 u32 lps, seconds, version, irqs;
2046 int i, ret;
2047
2048 if (software_reset(ohci)) {
2049 fw_error("Failed to reset ohci card.\n");
2050 return -EBUSY;
2051 }
2052
2053 /*
2054 * Now enable LPS, which we need in order to start accessing
2055 * most of the registers. In fact, on some cards (ALI M5251),
2056 * accessing registers in the SClk domain without LPS enabled
2057 * will lock up the machine. Wait 50msec to make sure we have
2058 * full link enabled. However, with some cards (well, at least
2059 * a JMicron PCIe card), we have to try again sometimes.
2060 */
2061 reg_write(ohci, OHCI1394_HCControlSet,
2062 OHCI1394_HCControl_LPS |
2063 OHCI1394_HCControl_postedWriteEnable);
2064 flush_writes(ohci);
2065
2066 for (lps = 0, i = 0; !lps && i < 3; i++) {
2067 msleep(50);
2068 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2069 OHCI1394_HCControl_LPS;
2070 }
2071
2072 if (!lps) {
2073 fw_error("Failed to set Link Power Status\n");
2074 return -EIO;
2075 }
2076
2077 reg_write(ohci, OHCI1394_HCControlClear,
2078 OHCI1394_HCControl_noByteSwapData);
2079
2080 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2081 reg_write(ohci, OHCI1394_LinkControlSet,
2082 OHCI1394_LinkControl_cycleTimerEnable |
2083 OHCI1394_LinkControl_cycleMaster);
2084
2085 reg_write(ohci, OHCI1394_ATRetries,
2086 OHCI1394_MAX_AT_REQ_RETRIES |
2087 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2088 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2089 (200 << 16));
2090
2091 seconds = lower_32_bits(get_seconds());
2092 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2093 ohci->bus_time = seconds & ~0x3f;
2094
2095 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2096 if (version >= OHCI_VERSION_1_1) {
2097 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2098 0xfffffffe);
2099 card->broadcast_channel_auto_allocated = true;
2100 }
2101
2102 /* Get implemented bits of the priority arbitration request counter. */
2103 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2104 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2105 reg_write(ohci, OHCI1394_FairnessControl, 0);
2106 card->priority_budget_implemented = ohci->pri_req_max != 0;
2107
2108 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2109 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2110 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2111
2112 ret = configure_1394a_enhancements(ohci);
2113 if (ret < 0)
2114 return ret;
2115
2116 /* Activate link_on bit and contender bit in our self ID packets.*/
2117 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2118 if (ret < 0)
2119 return ret;
2120
2121 /*
2122 * When the link is not yet enabled, the atomic config rom
2123 * update mechanism described below in ohci_set_config_rom()
2124 * is not active. We have to update ConfigRomHeader and
2125 * BusOptions manually, and the write to ConfigROMmap takes
2126 * effect immediately. We tie this to the enabling of the
2127 * link, so we have a valid config rom before enabling - the
2128 * OHCI requires that ConfigROMhdr and BusOptions have valid
2129 * values before enabling.
2130 *
2131 * However, when the ConfigROMmap is written, some controllers
2132 * always read back quadlets 0 and 2 from the config rom to
2133 * the ConfigRomHeader and BusOptions registers on bus reset.
2134 * They shouldn't do that in this initial case where the link
2135 * isn't enabled. This means we have to use the same
2136 * workaround here, setting the bus header to 0 and then write
2137 * the right values in the bus reset tasklet.
2138 */
2139
2140 if (config_rom) {
2141 ohci->next_config_rom =
2142 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2143 &ohci->next_config_rom_bus,
2144 GFP_KERNEL);
2145 if (ohci->next_config_rom == NULL)
2146 return -ENOMEM;
2147
2148 copy_config_rom(ohci->next_config_rom, config_rom, length);
2149 } else {
2150 /*
2151 * In the suspend case, config_rom is NULL, which
2152 * means that we just reuse the old config rom.
2153 */
2154 ohci->next_config_rom = ohci->config_rom;
2155 ohci->next_config_rom_bus = ohci->config_rom_bus;
2156 }
2157
2158 ohci->next_header = ohci->next_config_rom[0];
2159 ohci->next_config_rom[0] = 0;
2160 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2161 reg_write(ohci, OHCI1394_BusOptions,
2162 be32_to_cpu(ohci->next_config_rom[2]));
2163 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2164
2165 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2166
2167 if (!(ohci->quirks & QUIRK_NO_MSI))
2168 pci_enable_msi(dev);
2169 if (request_irq(dev->irq, irq_handler,
2170 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2171 ohci_driver_name, ohci)) {
2172 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2173 pci_disable_msi(dev);
2174 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2175 ohci->config_rom, ohci->config_rom_bus);
2176 return -EIO;
2177 }
2178
2179 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2180 OHCI1394_RQPkt | OHCI1394_RSPkt |
2181 OHCI1394_isochTx | OHCI1394_isochRx |
2182 OHCI1394_postedWriteErr |
2183 OHCI1394_selfIDComplete |
2184 OHCI1394_regAccessFail |
2185 OHCI1394_cycle64Seconds |
2186 OHCI1394_cycleInconsistent |
2187 OHCI1394_unrecoverableError |
2188 OHCI1394_cycleTooLong |
2189 OHCI1394_masterIntEnable;
2190 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2191 irqs |= OHCI1394_busReset;
2192 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2193
2194 reg_write(ohci, OHCI1394_HCControlSet,
2195 OHCI1394_HCControl_linkEnable |
2196 OHCI1394_HCControl_BIBimageValid);
2197
2198 reg_write(ohci, OHCI1394_LinkControlSet,
2199 OHCI1394_LinkControl_rcvSelfID |
2200 OHCI1394_LinkControl_rcvPhyPkt);
2201
2202 ar_context_run(&ohci->ar_request_ctx);
2203 ar_context_run(&ohci->ar_response_ctx); /* also flushes writes */
2204
2205 /* We are ready to go, reset bus to finish initialization. */
2206 fw_schedule_bus_reset(&ohci->card, false, true);
2207
2208 return 0;
2209 }
2210
2211 static int ohci_set_config_rom(struct fw_card *card,
2212 const __be32 *config_rom, size_t length)
2213 {
2214 struct fw_ohci *ohci;
2215 unsigned long flags;
2216 __be32 *next_config_rom;
2217 dma_addr_t uninitialized_var(next_config_rom_bus);
2218
2219 ohci = fw_ohci(card);
2220
2221 /*
2222 * When the OHCI controller is enabled, the config rom update
2223 * mechanism is a bit tricky, but easy enough to use. See
2224 * section 5.5.6 in the OHCI specification.
2225 *
2226 * The OHCI controller caches the new config rom address in a
2227 * shadow register (ConfigROMmapNext) and needs a bus reset
2228 * for the changes to take place. When the bus reset is
2229 * detected, the controller loads the new values for the
2230 * ConfigRomHeader and BusOptions registers from the specified
2231 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2232 * shadow register. All automatically and atomically.
2233 *
2234 * Now, there's a twist to this story. The automatic load of
2235 * ConfigRomHeader and BusOptions doesn't honor the
2236 * noByteSwapData bit, so with a be32 config rom, the
2237 * controller will load be32 values in to these registers
2238 * during the atomic update, even on litte endian
2239 * architectures. The workaround we use is to put a 0 in the
2240 * header quadlet; 0 is endian agnostic and means that the
2241 * config rom isn't ready yet. In the bus reset tasklet we
2242 * then set up the real values for the two registers.
2243 *
2244 * We use ohci->lock to avoid racing with the code that sets
2245 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2246 */
2247
2248 next_config_rom =
2249 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2250 &next_config_rom_bus, GFP_KERNEL);
2251 if (next_config_rom == NULL)
2252 return -ENOMEM;
2253
2254 spin_lock_irqsave(&ohci->lock, flags);
2255
2256 /*
2257 * If there is not an already pending config_rom update,
2258 * push our new allocation into the ohci->next_config_rom
2259 * and then mark the local variable as null so that we
2260 * won't deallocate the new buffer.
2261 *
2262 * OTOH, if there is a pending config_rom update, just
2263 * use that buffer with the new config_rom data, and
2264 * let this routine free the unused DMA allocation.
2265 */
2266
2267 if (ohci->next_config_rom == NULL) {
2268 ohci->next_config_rom = next_config_rom;
2269 ohci->next_config_rom_bus = next_config_rom_bus;
2270 next_config_rom = NULL;
2271 }
2272
2273 copy_config_rom(ohci->next_config_rom, config_rom, length);
2274
2275 ohci->next_header = config_rom[0];
2276 ohci->next_config_rom[0] = 0;
2277
2278 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2279
2280 spin_unlock_irqrestore(&ohci->lock, flags);
2281
2282 /* If we didn't use the DMA allocation, delete it. */
2283 if (next_config_rom != NULL)
2284 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2285 next_config_rom, next_config_rom_bus);
2286
2287 /*
2288 * Now initiate a bus reset to have the changes take
2289 * effect. We clean up the old config rom memory and DMA
2290 * mappings in the bus reset tasklet, since the OHCI
2291 * controller could need to access it before the bus reset
2292 * takes effect.
2293 */
2294
2295 fw_schedule_bus_reset(&ohci->card, true, true);
2296
2297 return 0;
2298 }
2299
2300 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2301 {
2302 struct fw_ohci *ohci = fw_ohci(card);
2303
2304 at_context_transmit(&ohci->at_request_ctx, packet);
2305 }
2306
2307 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2308 {
2309 struct fw_ohci *ohci = fw_ohci(card);
2310
2311 at_context_transmit(&ohci->at_response_ctx, packet);
2312 }
2313
2314 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2315 {
2316 struct fw_ohci *ohci = fw_ohci(card);
2317 struct context *ctx = &ohci->at_request_ctx;
2318 struct driver_data *driver_data = packet->driver_data;
2319 int ret = -ENOENT;
2320
2321 tasklet_disable(&ctx->tasklet);
2322
2323 if (packet->ack != 0)
2324 goto out;
2325
2326 if (packet->payload_mapped)
2327 dma_unmap_single(ohci->card.device, packet->payload_bus,
2328 packet->payload_length, DMA_TO_DEVICE);
2329
2330 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2331 driver_data->packet = NULL;
2332 packet->ack = RCODE_CANCELLED;
2333 packet->callback(packet, &ohci->card, packet->ack);
2334 ret = 0;
2335 out:
2336 tasklet_enable(&ctx->tasklet);
2337
2338 return ret;
2339 }
2340
2341 static int ohci_enable_phys_dma(struct fw_card *card,
2342 int node_id, int generation)
2343 {
2344 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2345 return 0;
2346 #else
2347 struct fw_ohci *ohci = fw_ohci(card);
2348 unsigned long flags;
2349 int n, ret = 0;
2350
2351 /*
2352 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2353 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2354 */
2355
2356 spin_lock_irqsave(&ohci->lock, flags);
2357
2358 if (ohci->generation != generation) {
2359 ret = -ESTALE;
2360 goto out;
2361 }
2362
2363 /*
2364 * Note, if the node ID contains a non-local bus ID, physical DMA is
2365 * enabled for _all_ nodes on remote buses.
2366 */
2367
2368 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2369 if (n < 32)
2370 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2371 else
2372 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2373
2374 flush_writes(ohci);
2375 out:
2376 spin_unlock_irqrestore(&ohci->lock, flags);
2377
2378 return ret;
2379 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2380 }
2381
2382 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2383 {
2384 struct fw_ohci *ohci = fw_ohci(card);
2385 unsigned long flags;
2386 u32 value;
2387
2388 switch (csr_offset) {
2389 case CSR_STATE_CLEAR:
2390 case CSR_STATE_SET:
2391 if (ohci->is_root &&
2392 (reg_read(ohci, OHCI1394_LinkControlSet) &
2393 OHCI1394_LinkControl_cycleMaster))
2394 value = CSR_STATE_BIT_CMSTR;
2395 else
2396 value = 0;
2397 if (ohci->csr_state_setclear_abdicate)
2398 value |= CSR_STATE_BIT_ABDICATE;
2399
2400 return value;
2401
2402 case CSR_NODE_IDS:
2403 return reg_read(ohci, OHCI1394_NodeID) << 16;
2404
2405 case CSR_CYCLE_TIME:
2406 return get_cycle_time(ohci);
2407
2408 case CSR_BUS_TIME:
2409 /*
2410 * We might be called just after the cycle timer has wrapped
2411 * around but just before the cycle64Seconds handler, so we
2412 * better check here, too, if the bus time needs to be updated.
2413 */
2414 spin_lock_irqsave(&ohci->lock, flags);
2415 value = update_bus_time(ohci);
2416 spin_unlock_irqrestore(&ohci->lock, flags);
2417 return value;
2418
2419 case CSR_BUSY_TIMEOUT:
2420 value = reg_read(ohci, OHCI1394_ATRetries);
2421 return (value >> 4) & 0x0ffff00f;
2422
2423 case CSR_PRIORITY_BUDGET:
2424 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2425 (ohci->pri_req_max << 8);
2426
2427 default:
2428 WARN_ON(1);
2429 return 0;
2430 }
2431 }
2432
2433 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2434 {
2435 struct fw_ohci *ohci = fw_ohci(card);
2436 unsigned long flags;
2437
2438 switch (csr_offset) {
2439 case CSR_STATE_CLEAR:
2440 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2441 reg_write(ohci, OHCI1394_LinkControlClear,
2442 OHCI1394_LinkControl_cycleMaster);
2443 flush_writes(ohci);
2444 }
2445 if (value & CSR_STATE_BIT_ABDICATE)
2446 ohci->csr_state_setclear_abdicate = false;
2447 break;
2448
2449 case CSR_STATE_SET:
2450 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2451 reg_write(ohci, OHCI1394_LinkControlSet,
2452 OHCI1394_LinkControl_cycleMaster);
2453 flush_writes(ohci);
2454 }
2455 if (value & CSR_STATE_BIT_ABDICATE)
2456 ohci->csr_state_setclear_abdicate = true;
2457 break;
2458
2459 case CSR_NODE_IDS:
2460 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2461 flush_writes(ohci);
2462 break;
2463
2464 case CSR_CYCLE_TIME:
2465 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2466 reg_write(ohci, OHCI1394_IntEventSet,
2467 OHCI1394_cycleInconsistent);
2468 flush_writes(ohci);
2469 break;
2470
2471 case CSR_BUS_TIME:
2472 spin_lock_irqsave(&ohci->lock, flags);
2473 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2474 spin_unlock_irqrestore(&ohci->lock, flags);
2475 break;
2476
2477 case CSR_BUSY_TIMEOUT:
2478 value = (value & 0xf) | ((value & 0xf) << 4) |
2479 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2480 reg_write(ohci, OHCI1394_ATRetries, value);
2481 flush_writes(ohci);
2482 break;
2483
2484 case CSR_PRIORITY_BUDGET:
2485 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2486 flush_writes(ohci);
2487 break;
2488
2489 default:
2490 WARN_ON(1);
2491 break;
2492 }
2493 }
2494
2495 static void copy_iso_headers(struct iso_context *ctx, void *p)
2496 {
2497 int i = ctx->header_length;
2498
2499 if (i + ctx->base.header_size > PAGE_SIZE)
2500 return;
2501
2502 /*
2503 * The iso header is byteswapped to little endian by
2504 * the controller, but the remaining header quadlets
2505 * are big endian. We want to present all the headers
2506 * as big endian, so we have to swap the first quadlet.
2507 */
2508 if (ctx->base.header_size > 0)
2509 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2510 if (ctx->base.header_size > 4)
2511 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2512 if (ctx->base.header_size > 8)
2513 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2514 ctx->header_length += ctx->base.header_size;
2515 }
2516
2517 static int handle_ir_packet_per_buffer(struct context *context,
2518 struct descriptor *d,
2519 struct descriptor *last)
2520 {
2521 struct iso_context *ctx =
2522 container_of(context, struct iso_context, context);
2523 struct descriptor *pd;
2524 __le32 *ir_header;
2525 void *p;
2526
2527 for (pd = d; pd <= last; pd++)
2528 if (pd->transfer_status)
2529 break;
2530 if (pd > last)
2531 /* Descriptor(s) not done yet, stop iteration */
2532 return 0;
2533
2534 p = last + 1;
2535 copy_iso_headers(ctx, p);
2536
2537 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2538 ir_header = (__le32 *) p;
2539 ctx->base.callback.sc(&ctx->base,
2540 le32_to_cpu(ir_header[0]) & 0xffff,
2541 ctx->header_length, ctx->header,
2542 ctx->base.callback_data);
2543 ctx->header_length = 0;
2544 }
2545
2546 return 1;
2547 }
2548
2549 /* d == last because each descriptor block is only a single descriptor. */
2550 static int handle_ir_buffer_fill(struct context *context,
2551 struct descriptor *d,
2552 struct descriptor *last)
2553 {
2554 struct iso_context *ctx =
2555 container_of(context, struct iso_context, context);
2556
2557 if (!last->transfer_status)
2558 /* Descriptor(s) not done yet, stop iteration */
2559 return 0;
2560
2561 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2562 ctx->base.callback.mc(&ctx->base,
2563 le32_to_cpu(last->data_address) +
2564 le16_to_cpu(last->req_count) -
2565 le16_to_cpu(last->res_count),
2566 ctx->base.callback_data);
2567
2568 return 1;
2569 }
2570
2571 static int handle_it_packet(struct context *context,
2572 struct descriptor *d,
2573 struct descriptor *last)
2574 {
2575 struct iso_context *ctx =
2576 container_of(context, struct iso_context, context);
2577 int i;
2578 struct descriptor *pd;
2579
2580 for (pd = d; pd <= last; pd++)
2581 if (pd->transfer_status)
2582 break;
2583 if (pd > last)
2584 /* Descriptor(s) not done yet, stop iteration */
2585 return 0;
2586
2587 i = ctx->header_length;
2588 if (i + 4 < PAGE_SIZE) {
2589 /* Present this value as big-endian to match the receive code */
2590 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2591 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2592 le16_to_cpu(pd->res_count));
2593 ctx->header_length += 4;
2594 }
2595 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2596 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2597 ctx->header_length, ctx->header,
2598 ctx->base.callback_data);
2599 ctx->header_length = 0;
2600 }
2601 return 1;
2602 }
2603
2604 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2605 {
2606 u32 hi = channels >> 32, lo = channels;
2607
2608 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2609 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2610 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2611 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2612 mmiowb();
2613 ohci->mc_channels = channels;
2614 }
2615
2616 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2617 int type, int channel, size_t header_size)
2618 {
2619 struct fw_ohci *ohci = fw_ohci(card);
2620 struct iso_context *uninitialized_var(ctx);
2621 descriptor_callback_t uninitialized_var(callback);
2622 u64 *uninitialized_var(channels);
2623 u32 *uninitialized_var(mask), uninitialized_var(regs);
2624 unsigned long flags;
2625 int index, ret = -EBUSY;
2626
2627 spin_lock_irqsave(&ohci->lock, flags);
2628
2629 switch (type) {
2630 case FW_ISO_CONTEXT_TRANSMIT:
2631 mask = &ohci->it_context_mask;
2632 callback = handle_it_packet;
2633 index = ffs(*mask) - 1;
2634 if (index >= 0) {
2635 *mask &= ~(1 << index);
2636 regs = OHCI1394_IsoXmitContextBase(index);
2637 ctx = &ohci->it_context_list[index];
2638 }
2639 break;
2640
2641 case FW_ISO_CONTEXT_RECEIVE:
2642 channels = &ohci->ir_context_channels;
2643 mask = &ohci->ir_context_mask;
2644 callback = handle_ir_packet_per_buffer;
2645 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2646 if (index >= 0) {
2647 *channels &= ~(1ULL << channel);
2648 *mask &= ~(1 << index);
2649 regs = OHCI1394_IsoRcvContextBase(index);
2650 ctx = &ohci->ir_context_list[index];
2651 }
2652 break;
2653
2654 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2655 mask = &ohci->ir_context_mask;
2656 callback = handle_ir_buffer_fill;
2657 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2658 if (index >= 0) {
2659 ohci->mc_allocated = true;
2660 *mask &= ~(1 << index);
2661 regs = OHCI1394_IsoRcvContextBase(index);
2662 ctx = &ohci->ir_context_list[index];
2663 }
2664 break;
2665
2666 default:
2667 index = -1;
2668 ret = -ENOSYS;
2669 }
2670
2671 spin_unlock_irqrestore(&ohci->lock, flags);
2672
2673 if (index < 0)
2674 return ERR_PTR(ret);
2675
2676 memset(ctx, 0, sizeof(*ctx));
2677 ctx->header_length = 0;
2678 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2679 if (ctx->header == NULL) {
2680 ret = -ENOMEM;
2681 goto out;
2682 }
2683 ret = context_init(&ctx->context, ohci, regs, callback);
2684 if (ret < 0)
2685 goto out_with_header;
2686
2687 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2688 set_multichannel_mask(ohci, 0);
2689
2690 return &ctx->base;
2691
2692 out_with_header:
2693 free_page((unsigned long)ctx->header);
2694 out:
2695 spin_lock_irqsave(&ohci->lock, flags);
2696
2697 switch (type) {
2698 case FW_ISO_CONTEXT_RECEIVE:
2699 *channels |= 1ULL << channel;
2700 break;
2701
2702 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2703 ohci->mc_allocated = false;
2704 break;
2705 }
2706 *mask |= 1 << index;
2707
2708 spin_unlock_irqrestore(&ohci->lock, flags);
2709
2710 return ERR_PTR(ret);
2711 }
2712
2713 static int ohci_start_iso(struct fw_iso_context *base,
2714 s32 cycle, u32 sync, u32 tags)
2715 {
2716 struct iso_context *ctx = container_of(base, struct iso_context, base);
2717 struct fw_ohci *ohci = ctx->context.ohci;
2718 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2719 int index;
2720
2721 /* the controller cannot start without any queued packets */
2722 if (ctx->context.last->branch_address == 0)
2723 return -ENODATA;
2724
2725 switch (ctx->base.type) {
2726 case FW_ISO_CONTEXT_TRANSMIT:
2727 index = ctx - ohci->it_context_list;
2728 match = 0;
2729 if (cycle >= 0)
2730 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2731 (cycle & 0x7fff) << 16;
2732
2733 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2734 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2735 context_run(&ctx->context, match);
2736 break;
2737
2738 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2739 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2740 /* fall through */
2741 case FW_ISO_CONTEXT_RECEIVE:
2742 index = ctx - ohci->ir_context_list;
2743 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2744 if (cycle >= 0) {
2745 match |= (cycle & 0x07fff) << 12;
2746 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2747 }
2748
2749 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2750 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2751 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2752 context_run(&ctx->context, control);
2753
2754 ctx->sync = sync;
2755 ctx->tags = tags;
2756
2757 break;
2758 }
2759
2760 return 0;
2761 }
2762
2763 static int ohci_stop_iso(struct fw_iso_context *base)
2764 {
2765 struct fw_ohci *ohci = fw_ohci(base->card);
2766 struct iso_context *ctx = container_of(base, struct iso_context, base);
2767 int index;
2768
2769 switch (ctx->base.type) {
2770 case FW_ISO_CONTEXT_TRANSMIT:
2771 index = ctx - ohci->it_context_list;
2772 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2773 break;
2774
2775 case FW_ISO_CONTEXT_RECEIVE:
2776 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2777 index = ctx - ohci->ir_context_list;
2778 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2779 break;
2780 }
2781 flush_writes(ohci);
2782 context_stop(&ctx->context);
2783 tasklet_kill(&ctx->context.tasklet);
2784
2785 return 0;
2786 }
2787
2788 static void ohci_free_iso_context(struct fw_iso_context *base)
2789 {
2790 struct fw_ohci *ohci = fw_ohci(base->card);
2791 struct iso_context *ctx = container_of(base, struct iso_context, base);
2792 unsigned long flags;
2793 int index;
2794
2795 ohci_stop_iso(base);
2796 context_release(&ctx->context);
2797 free_page((unsigned long)ctx->header);
2798
2799 spin_lock_irqsave(&ohci->lock, flags);
2800
2801 switch (base->type) {
2802 case FW_ISO_CONTEXT_TRANSMIT:
2803 index = ctx - ohci->it_context_list;
2804 ohci->it_context_mask |= 1 << index;
2805 break;
2806
2807 case FW_ISO_CONTEXT_RECEIVE:
2808 index = ctx - ohci->ir_context_list;
2809 ohci->ir_context_mask |= 1 << index;
2810 ohci->ir_context_channels |= 1ULL << base->channel;
2811 break;
2812
2813 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2814 index = ctx - ohci->ir_context_list;
2815 ohci->ir_context_mask |= 1 << index;
2816 ohci->ir_context_channels |= ohci->mc_channels;
2817 ohci->mc_channels = 0;
2818 ohci->mc_allocated = false;
2819 break;
2820 }
2821
2822 spin_unlock_irqrestore(&ohci->lock, flags);
2823 }
2824
2825 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2826 {
2827 struct fw_ohci *ohci = fw_ohci(base->card);
2828 unsigned long flags;
2829 int ret;
2830
2831 switch (base->type) {
2832 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2833
2834 spin_lock_irqsave(&ohci->lock, flags);
2835
2836 /* Don't allow multichannel to grab other contexts' channels. */
2837 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2838 *channels = ohci->ir_context_channels;
2839 ret = -EBUSY;
2840 } else {
2841 set_multichannel_mask(ohci, *channels);
2842 ret = 0;
2843 }
2844
2845 spin_unlock_irqrestore(&ohci->lock, flags);
2846
2847 break;
2848 default:
2849 ret = -EINVAL;
2850 }
2851
2852 return ret;
2853 }
2854
2855 #ifdef CONFIG_PM
2856 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2857 {
2858 int i;
2859 struct iso_context *ctx;
2860
2861 for (i = 0 ; i < ohci->n_ir ; i++) {
2862 ctx = &ohci->ir_context_list[i];
2863 if (ctx->context.running)
2864 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2865 }
2866
2867 for (i = 0 ; i < ohci->n_it ; i++) {
2868 ctx = &ohci->it_context_list[i];
2869 if (ctx->context.running)
2870 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2871 }
2872 }
2873 #endif
2874
2875 static int queue_iso_transmit(struct iso_context *ctx,
2876 struct fw_iso_packet *packet,
2877 struct fw_iso_buffer *buffer,
2878 unsigned long payload)
2879 {
2880 struct descriptor *d, *last, *pd;
2881 struct fw_iso_packet *p;
2882 __le32 *header;
2883 dma_addr_t d_bus, page_bus;
2884 u32 z, header_z, payload_z, irq;
2885 u32 payload_index, payload_end_index, next_page_index;
2886 int page, end_page, i, length, offset;
2887
2888 p = packet;
2889 payload_index = payload;
2890
2891 if (p->skip)
2892 z = 1;
2893 else
2894 z = 2;
2895 if (p->header_length > 0)
2896 z++;
2897
2898 /* Determine the first page the payload isn't contained in. */
2899 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2900 if (p->payload_length > 0)
2901 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2902 else
2903 payload_z = 0;
2904
2905 z += payload_z;
2906
2907 /* Get header size in number of descriptors. */
2908 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2909
2910 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2911 if (d == NULL)
2912 return -ENOMEM;
2913
2914 if (!p->skip) {
2915 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2916 d[0].req_count = cpu_to_le16(8);
2917 /*
2918 * Link the skip address to this descriptor itself. This causes
2919 * a context to skip a cycle whenever lost cycles or FIFO
2920 * overruns occur, without dropping the data. The application
2921 * should then decide whether this is an error condition or not.
2922 * FIXME: Make the context's cycle-lost behaviour configurable?
2923 */
2924 d[0].branch_address = cpu_to_le32(d_bus | z);
2925
2926 header = (__le32 *) &d[1];
2927 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2928 IT_HEADER_TAG(p->tag) |
2929 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2930 IT_HEADER_CHANNEL(ctx->base.channel) |
2931 IT_HEADER_SPEED(ctx->base.speed));
2932 header[1] =
2933 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2934 p->payload_length));
2935 }
2936
2937 if (p->header_length > 0) {
2938 d[2].req_count = cpu_to_le16(p->header_length);
2939 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2940 memcpy(&d[z], p->header, p->header_length);
2941 }
2942
2943 pd = d + z - payload_z;
2944 payload_end_index = payload_index + p->payload_length;
2945 for (i = 0; i < payload_z; i++) {
2946 page = payload_index >> PAGE_SHIFT;
2947 offset = payload_index & ~PAGE_MASK;
2948 next_page_index = (page + 1) << PAGE_SHIFT;
2949 length =
2950 min(next_page_index, payload_end_index) - payload_index;
2951 pd[i].req_count = cpu_to_le16(length);
2952
2953 page_bus = page_private(buffer->pages[page]);
2954 pd[i].data_address = cpu_to_le32(page_bus + offset);
2955
2956 payload_index += length;
2957 }
2958
2959 if (p->interrupt)
2960 irq = DESCRIPTOR_IRQ_ALWAYS;
2961 else
2962 irq = DESCRIPTOR_NO_IRQ;
2963
2964 last = z == 2 ? d : d + z - 1;
2965 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2966 DESCRIPTOR_STATUS |
2967 DESCRIPTOR_BRANCH_ALWAYS |
2968 irq);
2969
2970 context_append(&ctx->context, d, z, header_z);
2971
2972 return 0;
2973 }
2974
2975 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2976 struct fw_iso_packet *packet,
2977 struct fw_iso_buffer *buffer,
2978 unsigned long payload)
2979 {
2980 struct descriptor *d, *pd;
2981 dma_addr_t d_bus, page_bus;
2982 u32 z, header_z, rest;
2983 int i, j, length;
2984 int page, offset, packet_count, header_size, payload_per_buffer;
2985
2986 /*
2987 * The OHCI controller puts the isochronous header and trailer in the
2988 * buffer, so we need at least 8 bytes.
2989 */
2990 packet_count = packet->header_length / ctx->base.header_size;
2991 header_size = max(ctx->base.header_size, (size_t)8);
2992
2993 /* Get header size in number of descriptors. */
2994 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2995 page = payload >> PAGE_SHIFT;
2996 offset = payload & ~PAGE_MASK;
2997 payload_per_buffer = packet->payload_length / packet_count;
2998
2999 for (i = 0; i < packet_count; i++) {
3000 /* d points to the header descriptor */
3001 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3002 d = context_get_descriptors(&ctx->context,
3003 z + header_z, &d_bus);
3004 if (d == NULL)
3005 return -ENOMEM;
3006
3007 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3008 DESCRIPTOR_INPUT_MORE);
3009 if (packet->skip && i == 0)
3010 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3011 d->req_count = cpu_to_le16(header_size);
3012 d->res_count = d->req_count;
3013 d->transfer_status = 0;
3014 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3015
3016 rest = payload_per_buffer;
3017 pd = d;
3018 for (j = 1; j < z; j++) {
3019 pd++;
3020 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3021 DESCRIPTOR_INPUT_MORE);
3022
3023 if (offset + rest < PAGE_SIZE)
3024 length = rest;
3025 else
3026 length = PAGE_SIZE - offset;
3027 pd->req_count = cpu_to_le16(length);
3028 pd->res_count = pd->req_count;
3029 pd->transfer_status = 0;
3030
3031 page_bus = page_private(buffer->pages[page]);
3032 pd->data_address = cpu_to_le32(page_bus + offset);
3033
3034 offset = (offset + length) & ~PAGE_MASK;
3035 rest -= length;
3036 if (offset == 0)
3037 page++;
3038 }
3039 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3040 DESCRIPTOR_INPUT_LAST |
3041 DESCRIPTOR_BRANCH_ALWAYS);
3042 if (packet->interrupt && i == packet_count - 1)
3043 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3044
3045 context_append(&ctx->context, d, z, header_z);
3046 }
3047
3048 return 0;
3049 }
3050
3051 static int queue_iso_buffer_fill(struct iso_context *ctx,
3052 struct fw_iso_packet *packet,
3053 struct fw_iso_buffer *buffer,
3054 unsigned long payload)
3055 {
3056 struct descriptor *d;
3057 dma_addr_t d_bus, page_bus;
3058 int page, offset, rest, z, i, length;
3059
3060 page = payload >> PAGE_SHIFT;
3061 offset = payload & ~PAGE_MASK;
3062 rest = packet->payload_length;
3063
3064 /* We need one descriptor for each page in the buffer. */
3065 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3066
3067 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3068 return -EFAULT;
3069
3070 for (i = 0; i < z; i++) {
3071 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3072 if (d == NULL)
3073 return -ENOMEM;
3074
3075 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3076 DESCRIPTOR_BRANCH_ALWAYS);
3077 if (packet->skip && i == 0)
3078 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3079 if (packet->interrupt && i == z - 1)
3080 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3081
3082 if (offset + rest < PAGE_SIZE)
3083 length = rest;
3084 else
3085 length = PAGE_SIZE - offset;
3086 d->req_count = cpu_to_le16(length);
3087 d->res_count = d->req_count;
3088 d->transfer_status = 0;
3089
3090 page_bus = page_private(buffer->pages[page]);
3091 d->data_address = cpu_to_le32(page_bus + offset);
3092
3093 rest -= length;
3094 offset = 0;
3095 page++;
3096
3097 context_append(&ctx->context, d, 1, 0);
3098 }
3099
3100 return 0;
3101 }
3102
3103 static int ohci_queue_iso(struct fw_iso_context *base,
3104 struct fw_iso_packet *packet,
3105 struct fw_iso_buffer *buffer,
3106 unsigned long payload)
3107 {
3108 struct iso_context *ctx = container_of(base, struct iso_context, base);
3109 unsigned long flags;
3110 int ret = -ENOSYS;
3111
3112 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3113 switch (base->type) {
3114 case FW_ISO_CONTEXT_TRANSMIT:
3115 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3116 break;
3117 case FW_ISO_CONTEXT_RECEIVE:
3118 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3119 break;
3120 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3121 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3122 break;
3123 }
3124 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3125
3126 return ret;
3127 }
3128
3129 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3130 {
3131 struct context *ctx =
3132 &container_of(base, struct iso_context, base)->context;
3133
3134 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3135 flush_writes(ctx->ohci);
3136 }
3137
3138 static const struct fw_card_driver ohci_driver = {
3139 .enable = ohci_enable,
3140 .read_phy_reg = ohci_read_phy_reg,
3141 .update_phy_reg = ohci_update_phy_reg,
3142 .set_config_rom = ohci_set_config_rom,
3143 .send_request = ohci_send_request,
3144 .send_response = ohci_send_response,
3145 .cancel_packet = ohci_cancel_packet,
3146 .enable_phys_dma = ohci_enable_phys_dma,
3147 .read_csr = ohci_read_csr,
3148 .write_csr = ohci_write_csr,
3149
3150 .allocate_iso_context = ohci_allocate_iso_context,
3151 .free_iso_context = ohci_free_iso_context,
3152 .set_iso_channels = ohci_set_iso_channels,
3153 .queue_iso = ohci_queue_iso,
3154 .flush_queue_iso = ohci_flush_queue_iso,
3155 .start_iso = ohci_start_iso,
3156 .stop_iso = ohci_stop_iso,
3157 };
3158
3159 #ifdef CONFIG_PPC_PMAC
3160 static void pmac_ohci_on(struct pci_dev *dev)
3161 {
3162 if (machine_is(powermac)) {
3163 struct device_node *ofn = pci_device_to_OF_node(dev);
3164
3165 if (ofn) {
3166 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3167 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3168 }
3169 }
3170 }
3171
3172 static void pmac_ohci_off(struct pci_dev *dev)
3173 {
3174 if (machine_is(powermac)) {
3175 struct device_node *ofn = pci_device_to_OF_node(dev);
3176
3177 if (ofn) {
3178 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3179 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3180 }
3181 }
3182 }
3183 #else
3184 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3185 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3186 #endif /* CONFIG_PPC_PMAC */
3187
3188 static int __devinit pci_probe(struct pci_dev *dev,
3189 const struct pci_device_id *ent)
3190 {
3191 struct fw_ohci *ohci;
3192 u32 bus_options, max_receive, link_speed, version;
3193 u64 guid;
3194 int i, err;
3195 size_t size;
3196
3197 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3198 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3199 return -ENOSYS;
3200 }
3201
3202 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3203 if (ohci == NULL) {
3204 err = -ENOMEM;
3205 goto fail;
3206 }
3207
3208 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3209
3210 pmac_ohci_on(dev);
3211
3212 err = pci_enable_device(dev);
3213 if (err) {
3214 fw_error("Failed to enable OHCI hardware\n");
3215 goto fail_free;
3216 }
3217
3218 pci_set_master(dev);
3219 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3220 pci_set_drvdata(dev, ohci);
3221
3222 spin_lock_init(&ohci->lock);
3223 mutex_init(&ohci->phy_reg_mutex);
3224
3225 tasklet_init(&ohci->bus_reset_tasklet,
3226 bus_reset_tasklet, (unsigned long)ohci);
3227
3228 err = pci_request_region(dev, 0, ohci_driver_name);
3229 if (err) {
3230 fw_error("MMIO resource unavailable\n");
3231 goto fail_disable;
3232 }
3233
3234 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3235 if (ohci->registers == NULL) {
3236 fw_error("Failed to remap registers\n");
3237 err = -ENXIO;
3238 goto fail_iomem;
3239 }
3240
3241 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3242 if ((ohci_quirks[i].vendor == dev->vendor) &&
3243 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3244 ohci_quirks[i].device == dev->device) &&
3245 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3246 ohci_quirks[i].revision >= dev->revision)) {
3247 ohci->quirks = ohci_quirks[i].flags;
3248 break;
3249 }
3250 if (param_quirks)
3251 ohci->quirks = param_quirks;
3252
3253 /*
3254 * Because dma_alloc_coherent() allocates at least one page,
3255 * we save space by using a common buffer for the AR request/
3256 * response descriptors and the self IDs buffer.
3257 */
3258 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3259 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3260 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3261 PAGE_SIZE,
3262 &ohci->misc_buffer_bus,
3263 GFP_KERNEL);
3264 if (!ohci->misc_buffer) {
3265 err = -ENOMEM;
3266 goto fail_iounmap;
3267 }
3268
3269 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3270 OHCI1394_AsReqRcvContextControlSet);
3271 if (err < 0)
3272 goto fail_misc_buf;
3273
3274 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3275 OHCI1394_AsRspRcvContextControlSet);
3276 if (err < 0)
3277 goto fail_arreq_ctx;
3278
3279 err = context_init(&ohci->at_request_ctx, ohci,
3280 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3281 if (err < 0)
3282 goto fail_arrsp_ctx;
3283
3284 err = context_init(&ohci->at_response_ctx, ohci,
3285 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3286 if (err < 0)
3287 goto fail_atreq_ctx;
3288
3289 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3290 ohci->ir_context_channels = ~0ULL;
3291 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3292 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3293 ohci->ir_context_mask = ohci->ir_context_support;
3294 ohci->n_ir = hweight32(ohci->ir_context_mask);
3295 size = sizeof(struct iso_context) * ohci->n_ir;
3296 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3297
3298 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3299 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3300 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3301 ohci->it_context_mask = ohci->it_context_support;
3302 ohci->n_it = hweight32(ohci->it_context_mask);
3303 size = sizeof(struct iso_context) * ohci->n_it;
3304 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3305
3306 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3307 err = -ENOMEM;
3308 goto fail_contexts;
3309 }
3310
3311 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3312 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3313
3314 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3315 max_receive = (bus_options >> 12) & 0xf;
3316 link_speed = bus_options & 0x7;
3317 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3318 reg_read(ohci, OHCI1394_GUIDLo);
3319
3320 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3321 if (err)
3322 goto fail_contexts;
3323
3324 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3325 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3326 "%d IR + %d IT contexts, quirks 0x%x\n",
3327 dev_name(&dev->dev), version >> 16, version & 0xff,
3328 ohci->n_ir, ohci->n_it, ohci->quirks);
3329
3330 return 0;
3331
3332 fail_contexts:
3333 kfree(ohci->ir_context_list);
3334 kfree(ohci->it_context_list);
3335 context_release(&ohci->at_response_ctx);
3336 fail_atreq_ctx:
3337 context_release(&ohci->at_request_ctx);
3338 fail_arrsp_ctx:
3339 ar_context_release(&ohci->ar_response_ctx);
3340 fail_arreq_ctx:
3341 ar_context_release(&ohci->ar_request_ctx);
3342 fail_misc_buf:
3343 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3344 ohci->misc_buffer, ohci->misc_buffer_bus);
3345 fail_iounmap:
3346 pci_iounmap(dev, ohci->registers);
3347 fail_iomem:
3348 pci_release_region(dev, 0);
3349 fail_disable:
3350 pci_disable_device(dev);
3351 fail_free:
3352 kfree(ohci);
3353 pmac_ohci_off(dev);
3354 fail:
3355 if (err == -ENOMEM)
3356 fw_error("Out of memory\n");
3357
3358 return err;
3359 }
3360
3361 static void pci_remove(struct pci_dev *dev)
3362 {
3363 struct fw_ohci *ohci;
3364
3365 ohci = pci_get_drvdata(dev);
3366 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3367 flush_writes(ohci);
3368 fw_core_remove_card(&ohci->card);
3369
3370 /*
3371 * FIXME: Fail all pending packets here, now that the upper
3372 * layers can't queue any more.
3373 */
3374
3375 software_reset(ohci);
3376 free_irq(dev->irq, ohci);
3377
3378 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3379 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3380 ohci->next_config_rom, ohci->next_config_rom_bus);
3381 if (ohci->config_rom)
3382 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3383 ohci->config_rom, ohci->config_rom_bus);
3384 ar_context_release(&ohci->ar_request_ctx);
3385 ar_context_release(&ohci->ar_response_ctx);
3386 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3387 ohci->misc_buffer, ohci->misc_buffer_bus);
3388 context_release(&ohci->at_request_ctx);
3389 context_release(&ohci->at_response_ctx);
3390 kfree(ohci->it_context_list);
3391 kfree(ohci->ir_context_list);
3392 pci_disable_msi(dev);
3393 pci_iounmap(dev, ohci->registers);
3394 pci_release_region(dev, 0);
3395 pci_disable_device(dev);
3396 kfree(ohci);
3397 pmac_ohci_off(dev);
3398
3399 fw_notify("Removed fw-ohci device.\n");
3400 }
3401
3402 #ifdef CONFIG_PM
3403 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3404 {
3405 struct fw_ohci *ohci = pci_get_drvdata(dev);
3406 int err;
3407
3408 software_reset(ohci);
3409 free_irq(dev->irq, ohci);
3410 pci_disable_msi(dev);
3411 err = pci_save_state(dev);
3412 if (err) {
3413 fw_error("pci_save_state failed\n");
3414 return err;
3415 }
3416 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3417 if (err)
3418 fw_error("pci_set_power_state failed with %d\n", err);
3419 pmac_ohci_off(dev);
3420
3421 return 0;
3422 }
3423
3424 static int pci_resume(struct pci_dev *dev)
3425 {
3426 struct fw_ohci *ohci = pci_get_drvdata(dev);
3427 int err;
3428
3429 pmac_ohci_on(dev);
3430 pci_set_power_state(dev, PCI_D0);
3431 pci_restore_state(dev);
3432 err = pci_enable_device(dev);
3433 if (err) {
3434 fw_error("pci_enable_device failed\n");
3435 return err;
3436 }
3437
3438 /* Some systems don't setup GUID register on resume from ram */
3439 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3440 !reg_read(ohci, OHCI1394_GUIDHi)) {
3441 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3442 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3443 }
3444
3445 err = ohci_enable(&ohci->card, NULL, 0);
3446 if (err)
3447 return err;
3448
3449 ohci_resume_iso_dma(ohci);
3450
3451 return 0;
3452 }
3453 #endif
3454
3455 static const struct pci_device_id pci_table[] = {
3456 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3457 { }
3458 };
3459
3460 MODULE_DEVICE_TABLE(pci, pci_table);
3461
3462 static struct pci_driver fw_ohci_pci_driver = {
3463 .name = ohci_driver_name,
3464 .id_table = pci_table,
3465 .probe = pci_probe,
3466 .remove = pci_remove,
3467 #ifdef CONFIG_PM
3468 .resume = pci_resume,
3469 .suspend = pci_suspend,
3470 #endif
3471 };
3472
3473 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3474 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3475 MODULE_LICENSE("GPL");
3476
3477 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3478 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3479 MODULE_ALIAS("ohci1394");
3480 #endif
3481
3482 static int __init fw_ohci_init(void)
3483 {
3484 return pci_register_driver(&fw_ohci_pci_driver);
3485 }
3486
3487 static void __exit fw_ohci_cleanup(void)
3488 {
3489 pci_unregister_driver(&fw_ohci_pci_driver);
3490 }
3491
3492 module_init(fw_ohci_init);
3493 module_exit(fw_ohci_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree