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drm/radeon: properly program gart on rv740, juniper, cypress, barts, hemlock
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / rv770.c
blob51d20aa63d0398bdc4c0062c65594ab498f16c32
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
35 #include "rv770d.h"
36 #include "atom.h"
37 #include "avivod.h"
38
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
41
42 static void rv770_gpu_init(struct radeon_device *rdev);
43 void rv770_fini(struct radeon_device *rdev);
44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45
46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47 {
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50 int i;
51
52 /* Lock the graphics update lock */
53 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
54 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
55
56 /* update the scanout addresses */
57 if (radeon_crtc->crtc_id) {
58 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
60 } else {
61 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
63 }
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
65 (u32)crtc_base);
66 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
67 (u32)crtc_base);
68
69 /* Wait for update_pending to go high. */
70 for (i = 0; i < rdev->usec_timeout; i++) {
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
72 break;
73 udelay(1);
74 }
75 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
76
77 /* Unlock the lock, so double-buffering can take place inside vblank */
78 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
79 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
80
81 /* Return current update_pending status: */
82 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
83 }
84
85 /* get temperature in millidegrees */
86 int rv770_get_temp(struct radeon_device *rdev)
87 {
88 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
89 ASIC_T_SHIFT;
90 int actual_temp;
91
92 if (temp & 0x400)
93 actual_temp = -256;
94 else if (temp & 0x200)
95 actual_temp = 255;
96 else if (temp & 0x100) {
97 actual_temp = temp & 0x1ff;
98 actual_temp |= ~0x1ff;
99 } else
100 actual_temp = temp & 0xff;
101
102 return (actual_temp * 1000) / 2;
103 }
104
105 void rv770_pm_misc(struct radeon_device *rdev)
106 {
107 int req_ps_idx = rdev->pm.requested_power_state_index;
108 int req_cm_idx = rdev->pm.requested_clock_mode_index;
109 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
110 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
111
112 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
113 /* 0xff01 is a flag rather then an actual voltage */
114 if (voltage->voltage == 0xff01)
115 return;
116 if (voltage->voltage != rdev->pm.current_vddc) {
117 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
118 rdev->pm.current_vddc = voltage->voltage;
119 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
120 }
121 }
122 }
123
124 /*
125 * GART
126 */
127 int rv770_pcie_gart_enable(struct radeon_device *rdev)
128 {
129 u32 tmp;
130 int r, i;
131
132 if (rdev->gart.table.vram.robj == NULL) {
133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
134 return -EINVAL;
135 }
136 r = radeon_gart_table_vram_pin(rdev);
137 if (r)
138 return r;
139 radeon_gart_restore(rdev);
140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
150 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
154 if (rdev->family == CHIP_RV740)
155 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
156 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
157 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
158 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
159 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
160 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
161 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
162 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
163 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
164 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
165 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
166 (u32)(rdev->dummy_page.addr >> 12));
167 for (i = 1; i < 7; i++)
168 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
169
170 r600_pcie_gart_tlb_flush(rdev);
171 rdev->gart.ready = true;
172 return 0;
173 }
174
175 void rv770_pcie_gart_disable(struct radeon_device *rdev)
176 {
177 u32 tmp;
178 int i, r;
179
180 /* Disable all tables */
181 for (i = 0; i < 7; i++)
182 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
183
184 /* Setup L2 cache */
185 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
186 EFFECTIVE_L2_QUEUE_SIZE(7));
187 WREG32(VM_L2_CNTL2, 0);
188 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
189 /* Setup TLB control */
190 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
191 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
192 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
193 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
194 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
195 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
196 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
197 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
198 if (rdev->gart.table.vram.robj) {
199 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
200 if (likely(r == 0)) {
201 radeon_bo_kunmap(rdev->gart.table.vram.robj);
202 radeon_bo_unpin(rdev->gart.table.vram.robj);
203 radeon_bo_unreserve(rdev->gart.table.vram.robj);
204 }
205 }
206 }
207
208 void rv770_pcie_gart_fini(struct radeon_device *rdev)
209 {
210 radeon_gart_fini(rdev);
211 rv770_pcie_gart_disable(rdev);
212 radeon_gart_table_vram_free(rdev);
213 }
214
215
216 void rv770_agp_enable(struct radeon_device *rdev)
217 {
218 u32 tmp;
219 int i;
220
221 /* Setup L2 cache */
222 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
223 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
224 EFFECTIVE_L2_QUEUE_SIZE(7));
225 WREG32(VM_L2_CNTL2, 0);
226 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
227 /* Setup TLB control */
228 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
229 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
230 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
231 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
232 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
233 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
234 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
235 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
236 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
237 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
238 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
239 for (i = 0; i < 7; i++)
240 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
241 }
242
243 static void rv770_mc_program(struct radeon_device *rdev)
244 {
245 struct rv515_mc_save save;
246 u32 tmp;
247 int i, j;
248
249 /* Initialize HDP */
250 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
251 WREG32((0x2c14 + j), 0x00000000);
252 WREG32((0x2c18 + j), 0x00000000);
253 WREG32((0x2c1c + j), 0x00000000);
254 WREG32((0x2c20 + j), 0x00000000);
255 WREG32((0x2c24 + j), 0x00000000);
256 }
257 /* r7xx hw bug. Read from HDP_DEBUG1 rather
258 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
259 */
260 tmp = RREG32(HDP_DEBUG1);
261
262 rv515_mc_stop(rdev, &save);
263 if (r600_mc_wait_for_idle(rdev)) {
264 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
265 }
266 /* Lockout access through VGA aperture*/
267 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
268 /* Update configuration */
269 if (rdev->flags & RADEON_IS_AGP) {
270 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
271 /* VRAM before AGP */
272 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
273 rdev->mc.vram_start >> 12);
274 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
275 rdev->mc.gtt_end >> 12);
276 } else {
277 /* VRAM after AGP */
278 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
279 rdev->mc.gtt_start >> 12);
280 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
281 rdev->mc.vram_end >> 12);
282 }
283 } else {
284 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
285 rdev->mc.vram_start >> 12);
286 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
287 rdev->mc.vram_end >> 12);
288 }
289 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
290 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
291 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
292 WREG32(MC_VM_FB_LOCATION, tmp);
293 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
294 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
295 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
296 if (rdev->flags & RADEON_IS_AGP) {
297 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
298 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
299 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
300 } else {
301 WREG32(MC_VM_AGP_BASE, 0);
302 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
303 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
304 }
305 if (r600_mc_wait_for_idle(rdev)) {
306 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
307 }
308 rv515_mc_resume(rdev, &save);
309 /* we need to own VRAM, so turn off the VGA renderer here
310 * to stop it overwriting our objects */
311 rv515_vga_render_disable(rdev);
312 }
313
314
315 /*
316 * CP.
317 */
318 void r700_cp_stop(struct radeon_device *rdev)
319 {
320 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
321 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
322 WREG32(SCRATCH_UMSK, 0);
323 }
324
325 static int rv770_cp_load_microcode(struct radeon_device *rdev)
326 {
327 const __be32 *fw_data;
328 int i;
329
330 if (!rdev->me_fw || !rdev->pfp_fw)
331 return -EINVAL;
332
333 r700_cp_stop(rdev);
334 WREG32(CP_RB_CNTL,
335 #ifdef __BIG_ENDIAN
336 BUF_SWAP_32BIT |
337 #endif
338 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
339
340 /* Reset cp */
341 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
342 RREG32(GRBM_SOFT_RESET);
343 mdelay(15);
344 WREG32(GRBM_SOFT_RESET, 0);
345
346 fw_data = (const __be32 *)rdev->pfp_fw->data;
347 WREG32(CP_PFP_UCODE_ADDR, 0);
348 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
349 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
350 WREG32(CP_PFP_UCODE_ADDR, 0);
351
352 fw_data = (const __be32 *)rdev->me_fw->data;
353 WREG32(CP_ME_RAM_WADDR, 0);
354 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
355 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
356
357 WREG32(CP_PFP_UCODE_ADDR, 0);
358 WREG32(CP_ME_RAM_WADDR, 0);
359 WREG32(CP_ME_RAM_RADDR, 0);
360 return 0;
361 }
362
363 void r700_cp_fini(struct radeon_device *rdev)
364 {
365 r700_cp_stop(rdev);
366 radeon_ring_fini(rdev);
367 }
368
369 /*
370 * Core functions
371 */
372 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
373 u32 num_tile_pipes,
374 u32 num_backends,
375 u32 backend_disable_mask)
376 {
377 u32 backend_map = 0;
378 u32 enabled_backends_mask;
379 u32 enabled_backends_count;
380 u32 cur_pipe;
381 u32 swizzle_pipe[R7XX_MAX_PIPES];
382 u32 cur_backend;
383 u32 i;
384 bool force_no_swizzle;
385
386 if (num_tile_pipes > R7XX_MAX_PIPES)
387 num_tile_pipes = R7XX_MAX_PIPES;
388 if (num_tile_pipes < 1)
389 num_tile_pipes = 1;
390 if (num_backends > R7XX_MAX_BACKENDS)
391 num_backends = R7XX_MAX_BACKENDS;
392 if (num_backends < 1)
393 num_backends = 1;
394
395 enabled_backends_mask = 0;
396 enabled_backends_count = 0;
397 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
398 if (((backend_disable_mask >> i) & 1) == 0) {
399 enabled_backends_mask |= (1 << i);
400 ++enabled_backends_count;
401 }
402 if (enabled_backends_count == num_backends)
403 break;
404 }
405
406 if (enabled_backends_count == 0) {
407 enabled_backends_mask = 1;
408 enabled_backends_count = 1;
409 }
410
411 if (enabled_backends_count != num_backends)
412 num_backends = enabled_backends_count;
413
414 switch (rdev->family) {
415 case CHIP_RV770:
416 case CHIP_RV730:
417 force_no_swizzle = false;
418 break;
419 case CHIP_RV710:
420 case CHIP_RV740:
421 default:
422 force_no_swizzle = true;
423 break;
424 }
425
426 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
427 switch (num_tile_pipes) {
428 case 1:
429 swizzle_pipe[0] = 0;
430 break;
431 case 2:
432 swizzle_pipe[0] = 0;
433 swizzle_pipe[1] = 1;
434 break;
435 case 3:
436 if (force_no_swizzle) {
437 swizzle_pipe[0] = 0;
438 swizzle_pipe[1] = 1;
439 swizzle_pipe[2] = 2;
440 } else {
441 swizzle_pipe[0] = 0;
442 swizzle_pipe[1] = 2;
443 swizzle_pipe[2] = 1;
444 }
445 break;
446 case 4:
447 if (force_no_swizzle) {
448 swizzle_pipe[0] = 0;
449 swizzle_pipe[1] = 1;
450 swizzle_pipe[2] = 2;
451 swizzle_pipe[3] = 3;
452 } else {
453 swizzle_pipe[0] = 0;
454 swizzle_pipe[1] = 2;
455 swizzle_pipe[2] = 3;
456 swizzle_pipe[3] = 1;
457 }
458 break;
459 case 5:
460 if (force_no_swizzle) {
461 swizzle_pipe[0] = 0;
462 swizzle_pipe[1] = 1;
463 swizzle_pipe[2] = 2;
464 swizzle_pipe[3] = 3;
465 swizzle_pipe[4] = 4;
466 } else {
467 swizzle_pipe[0] = 0;
468 swizzle_pipe[1] = 2;
469 swizzle_pipe[2] = 4;
470 swizzle_pipe[3] = 1;
471 swizzle_pipe[4] = 3;
472 }
473 break;
474 case 6:
475 if (force_no_swizzle) {
476 swizzle_pipe[0] = 0;
477 swizzle_pipe[1] = 1;
478 swizzle_pipe[2] = 2;
479 swizzle_pipe[3] = 3;
480 swizzle_pipe[4] = 4;
481 swizzle_pipe[5] = 5;
482 } else {
483 swizzle_pipe[0] = 0;
484 swizzle_pipe[1] = 2;
485 swizzle_pipe[2] = 4;
486 swizzle_pipe[3] = 5;
487 swizzle_pipe[4] = 3;
488 swizzle_pipe[5] = 1;
489 }
490 break;
491 case 7:
492 if (force_no_swizzle) {
493 swizzle_pipe[0] = 0;
494 swizzle_pipe[1] = 1;
495 swizzle_pipe[2] = 2;
496 swizzle_pipe[3] = 3;
497 swizzle_pipe[4] = 4;
498 swizzle_pipe[5] = 5;
499 swizzle_pipe[6] = 6;
500 } else {
501 swizzle_pipe[0] = 0;
502 swizzle_pipe[1] = 2;
503 swizzle_pipe[2] = 4;
504 swizzle_pipe[3] = 6;
505 swizzle_pipe[4] = 3;
506 swizzle_pipe[5] = 1;
507 swizzle_pipe[6] = 5;
508 }
509 break;
510 case 8:
511 if (force_no_swizzle) {
512 swizzle_pipe[0] = 0;
513 swizzle_pipe[1] = 1;
514 swizzle_pipe[2] = 2;
515 swizzle_pipe[3] = 3;
516 swizzle_pipe[4] = 4;
517 swizzle_pipe[5] = 5;
518 swizzle_pipe[6] = 6;
519 swizzle_pipe[7] = 7;
520 } else {
521 swizzle_pipe[0] = 0;
522 swizzle_pipe[1] = 2;
523 swizzle_pipe[2] = 4;
524 swizzle_pipe[3] = 6;
525 swizzle_pipe[4] = 3;
526 swizzle_pipe[5] = 1;
527 swizzle_pipe[6] = 7;
528 swizzle_pipe[7] = 5;
529 }
530 break;
531 }
532
533 cur_backend = 0;
534 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
535 while (((1 << cur_backend) & enabled_backends_mask) == 0)
536 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
537
538 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
539
540 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
541 }
542
543 return backend_map;
544 }
545
546 static void rv770_gpu_init(struct radeon_device *rdev)
547 {
548 int i, j, num_qd_pipes;
549 u32 ta_aux_cntl;
550 u32 sx_debug_1;
551 u32 smx_dc_ctl0;
552 u32 db_debug3;
553 u32 num_gs_verts_per_thread;
554 u32 vgt_gs_per_es;
555 u32 gs_prim_buffer_depth = 0;
556 u32 sq_ms_fifo_sizes;
557 u32 sq_config;
558 u32 sq_thread_resource_mgmt;
559 u32 hdp_host_path_cntl;
560 u32 sq_dyn_gpr_size_simd_ab_0;
561 u32 backend_map;
562 u32 gb_tiling_config = 0;
563 u32 cc_rb_backend_disable = 0;
564 u32 cc_gc_shader_pipe_config = 0;
565 u32 mc_arb_ramcfg;
566 u32 db_debug4;
567
568 /* setup chip specs */
569 switch (rdev->family) {
570 case CHIP_RV770:
571 rdev->config.rv770.max_pipes = 4;
572 rdev->config.rv770.max_tile_pipes = 8;
573 rdev->config.rv770.max_simds = 10;
574 rdev->config.rv770.max_backends = 4;
575 rdev->config.rv770.max_gprs = 256;
576 rdev->config.rv770.max_threads = 248;
577 rdev->config.rv770.max_stack_entries = 512;
578 rdev->config.rv770.max_hw_contexts = 8;
579 rdev->config.rv770.max_gs_threads = 16 * 2;
580 rdev->config.rv770.sx_max_export_size = 128;
581 rdev->config.rv770.sx_max_export_pos_size = 16;
582 rdev->config.rv770.sx_max_export_smx_size = 112;
583 rdev->config.rv770.sq_num_cf_insts = 2;
584
585 rdev->config.rv770.sx_num_of_sets = 7;
586 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
587 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
588 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
589 break;
590 case CHIP_RV730:
591 rdev->config.rv770.max_pipes = 2;
592 rdev->config.rv770.max_tile_pipes = 4;
593 rdev->config.rv770.max_simds = 8;
594 rdev->config.rv770.max_backends = 2;
595 rdev->config.rv770.max_gprs = 128;
596 rdev->config.rv770.max_threads = 248;
597 rdev->config.rv770.max_stack_entries = 256;
598 rdev->config.rv770.max_hw_contexts = 8;
599 rdev->config.rv770.max_gs_threads = 16 * 2;
600 rdev->config.rv770.sx_max_export_size = 256;
601 rdev->config.rv770.sx_max_export_pos_size = 32;
602 rdev->config.rv770.sx_max_export_smx_size = 224;
603 rdev->config.rv770.sq_num_cf_insts = 2;
604
605 rdev->config.rv770.sx_num_of_sets = 7;
606 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
607 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
608 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
609 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
610 rdev->config.rv770.sx_max_export_pos_size -= 16;
611 rdev->config.rv770.sx_max_export_smx_size += 16;
612 }
613 break;
614 case CHIP_RV710:
615 rdev->config.rv770.max_pipes = 2;
616 rdev->config.rv770.max_tile_pipes = 2;
617 rdev->config.rv770.max_simds = 2;
618 rdev->config.rv770.max_backends = 1;
619 rdev->config.rv770.max_gprs = 256;
620 rdev->config.rv770.max_threads = 192;
621 rdev->config.rv770.max_stack_entries = 256;
622 rdev->config.rv770.max_hw_contexts = 4;
623 rdev->config.rv770.max_gs_threads = 8 * 2;
624 rdev->config.rv770.sx_max_export_size = 128;
625 rdev->config.rv770.sx_max_export_pos_size = 16;
626 rdev->config.rv770.sx_max_export_smx_size = 112;
627 rdev->config.rv770.sq_num_cf_insts = 1;
628
629 rdev->config.rv770.sx_num_of_sets = 7;
630 rdev->config.rv770.sc_prim_fifo_size = 0x40;
631 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
632 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
633 break;
634 case CHIP_RV740:
635 rdev->config.rv770.max_pipes = 4;
636 rdev->config.rv770.max_tile_pipes = 4;
637 rdev->config.rv770.max_simds = 8;
638 rdev->config.rv770.max_backends = 4;
639 rdev->config.rv770.max_gprs = 256;
640 rdev->config.rv770.max_threads = 248;
641 rdev->config.rv770.max_stack_entries = 512;
642 rdev->config.rv770.max_hw_contexts = 8;
643 rdev->config.rv770.max_gs_threads = 16 * 2;
644 rdev->config.rv770.sx_max_export_size = 256;
645 rdev->config.rv770.sx_max_export_pos_size = 32;
646 rdev->config.rv770.sx_max_export_smx_size = 224;
647 rdev->config.rv770.sq_num_cf_insts = 2;
648
649 rdev->config.rv770.sx_num_of_sets = 7;
650 rdev->config.rv770.sc_prim_fifo_size = 0x100;
651 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
652 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
653
654 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
655 rdev->config.rv770.sx_max_export_pos_size -= 16;
656 rdev->config.rv770.sx_max_export_smx_size += 16;
657 }
658 break;
659 default:
660 break;
661 }
662
663 /* Initialize HDP */
664 j = 0;
665 for (i = 0; i < 32; i++) {
666 WREG32((0x2c14 + j), 0x00000000);
667 WREG32((0x2c18 + j), 0x00000000);
668 WREG32((0x2c1c + j), 0x00000000);
669 WREG32((0x2c20 + j), 0x00000000);
670 WREG32((0x2c24 + j), 0x00000000);
671 j += 0x18;
672 }
673
674 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
675
676 /* setup tiling, simd, pipe config */
677 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
678
679 switch (rdev->config.rv770.max_tile_pipes) {
680 case 1:
681 default:
682 gb_tiling_config |= PIPE_TILING(0);
683 break;
684 case 2:
685 gb_tiling_config |= PIPE_TILING(1);
686 break;
687 case 4:
688 gb_tiling_config |= PIPE_TILING(2);
689 break;
690 case 8:
691 gb_tiling_config |= PIPE_TILING(3);
692 break;
693 }
694 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
695
696 if (rdev->family == CHIP_RV770)
697 gb_tiling_config |= BANK_TILING(1);
698 else
699 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
700 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
701 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
702 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
703 rdev->config.rv770.tiling_group_size = 512;
704 else
705 rdev->config.rv770.tiling_group_size = 256;
706 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
707 gb_tiling_config |= ROW_TILING(3);
708 gb_tiling_config |= SAMPLE_SPLIT(3);
709 } else {
710 gb_tiling_config |=
711 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
712 gb_tiling_config |=
713 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
714 }
715
716 gb_tiling_config |= BANK_SWAPS(1);
717
718 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
719 cc_rb_backend_disable |=
720 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
721
722 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
723 cc_gc_shader_pipe_config |=
724 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
725 cc_gc_shader_pipe_config |=
726 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
727
728 if (rdev->family == CHIP_RV740)
729 backend_map = 0x28;
730 else
731 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
732 rdev->config.rv770.max_tile_pipes,
733 (R7XX_MAX_BACKENDS -
734 r600_count_pipe_bits((cc_rb_backend_disable &
735 R7XX_MAX_BACKENDS_MASK) >> 16)),
736 (cc_rb_backend_disable >> 16));
737
738 rdev->config.rv770.tile_config = gb_tiling_config;
739 gb_tiling_config |= BACKEND_MAP(backend_map);
740
741 WREG32(GB_TILING_CONFIG, gb_tiling_config);
742 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
743 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
744
745 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
746 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
747 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
748 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
749
750 WREG32(CGTS_SYS_TCC_DISABLE, 0);
751 WREG32(CGTS_TCC_DISABLE, 0);
752 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
753 WREG32(CGTS_USER_TCC_DISABLE, 0);
754
755 num_qd_pipes =
756 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
757 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
758 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
759
760 /* set HW defaults for 3D engine */
761 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
762 ROQ_IB2_START(0x2b)));
763
764 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
765
766 ta_aux_cntl = RREG32(TA_CNTL_AUX);
767 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
768
769 sx_debug_1 = RREG32(SX_DEBUG_1);
770 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
771 WREG32(SX_DEBUG_1, sx_debug_1);
772
773 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
774 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
775 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
776 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
777
778 if (rdev->family != CHIP_RV740)
779 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
780 GS_FLUSH_CTL(4) |
781 ACK_FLUSH_CTL(3) |
782 SYNC_FLUSH_CTL));
783
784 db_debug3 = RREG32(DB_DEBUG3);
785 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
786 switch (rdev->family) {
787 case CHIP_RV770:
788 case CHIP_RV740:
789 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
790 break;
791 case CHIP_RV710:
792 case CHIP_RV730:
793 default:
794 db_debug3 |= DB_CLK_OFF_DELAY(2);
795 break;
796 }
797 WREG32(DB_DEBUG3, db_debug3);
798
799 if (rdev->family != CHIP_RV770) {
800 db_debug4 = RREG32(DB_DEBUG4);
801 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
802 WREG32(DB_DEBUG4, db_debug4);
803 }
804
805 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
806 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
807 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
808
809 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
810 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
811 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
812
813 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
814
815 WREG32(VGT_NUM_INSTANCES, 1);
816
817 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
818
819 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
820
821 WREG32(CP_PERFMON_CNTL, 0);
822
823 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
824 DONE_FIFO_HIWATER(0xe0) |
825 ALU_UPDATE_FIFO_HIWATER(0x8));
826 switch (rdev->family) {
827 case CHIP_RV770:
828 case CHIP_RV730:
829 case CHIP_RV710:
830 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
831 break;
832 case CHIP_RV740:
833 default:
834 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
835 break;
836 }
837 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
838
839 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
840 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
841 */
842 sq_config = RREG32(SQ_CONFIG);
843 sq_config &= ~(PS_PRIO(3) |
844 VS_PRIO(3) |
845 GS_PRIO(3) |
846 ES_PRIO(3));
847 sq_config |= (DX9_CONSTS |
848 VC_ENABLE |
849 EXPORT_SRC_C |
850 PS_PRIO(0) |
851 VS_PRIO(1) |
852 GS_PRIO(2) |
853 ES_PRIO(3));
854 if (rdev->family == CHIP_RV710)
855 /* no vertex cache */
856 sq_config &= ~VC_ENABLE;
857
858 WREG32(SQ_CONFIG, sq_config);
859
860 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
861 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
862 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
863
864 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
865 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
866
867 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
868 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
869 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
870 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
871 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
872 else
873 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
874 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
875
876 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
877 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
878
879 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
880 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
881
882 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
883 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
884 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
885 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
886
887 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
888 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
889 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
890 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
891 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
892 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
893 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
894 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
895
896 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
897 FORCE_EOV_MAX_REZ_CNT(255)));
898
899 if (rdev->family == CHIP_RV710)
900 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
901 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
902 else
903 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
904 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
905
906 switch (rdev->family) {
907 case CHIP_RV770:
908 case CHIP_RV730:
909 case CHIP_RV740:
910 gs_prim_buffer_depth = 384;
911 break;
912 case CHIP_RV710:
913 gs_prim_buffer_depth = 128;
914 break;
915 default:
916 break;
917 }
918
919 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
920 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
921 /* Max value for this is 256 */
922 if (vgt_gs_per_es > 256)
923 vgt_gs_per_es = 256;
924
925 WREG32(VGT_ES_PER_GS, 128);
926 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
927 WREG32(VGT_GS_PER_VS, 2);
928
929 /* more default values. 2D/3D driver should adjust as needed */
930 WREG32(VGT_GS_VERTEX_REUSE, 16);
931 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
932 WREG32(VGT_STRMOUT_EN, 0);
933 WREG32(SX_MISC, 0);
934 WREG32(PA_SC_MODE_CNTL, 0);
935 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
936 WREG32(PA_SC_AA_CONFIG, 0);
937 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
938 WREG32(PA_SC_LINE_STIPPLE, 0);
939 WREG32(SPI_INPUT_Z, 0);
940 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
941 WREG32(CB_COLOR7_FRAG, 0);
942
943 /* clear render buffer base addresses */
944 WREG32(CB_COLOR0_BASE, 0);
945 WREG32(CB_COLOR1_BASE, 0);
946 WREG32(CB_COLOR2_BASE, 0);
947 WREG32(CB_COLOR3_BASE, 0);
948 WREG32(CB_COLOR4_BASE, 0);
949 WREG32(CB_COLOR5_BASE, 0);
950 WREG32(CB_COLOR6_BASE, 0);
951 WREG32(CB_COLOR7_BASE, 0);
952
953 WREG32(TCP_CNTL, 0);
954
955 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
956 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
957
958 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
959
960 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
961 NUM_CLIP_SEQ(3)));
962
963 }
964
965 static int rv770_vram_scratch_init(struct radeon_device *rdev)
966 {
967 int r;
968 u64 gpu_addr;
969
970 if (rdev->vram_scratch.robj == NULL) {
971 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
972 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
973 &rdev->vram_scratch.robj);
974 if (r) {
975 return r;
976 }
977 }
978
979 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
980 if (unlikely(r != 0))
981 return r;
982 r = radeon_bo_pin(rdev->vram_scratch.robj,
983 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
984 if (r) {
985 radeon_bo_unreserve(rdev->vram_scratch.robj);
986 return r;
987 }
988 r = radeon_bo_kmap(rdev->vram_scratch.robj,
989 (void **)&rdev->vram_scratch.ptr);
990 if (r)
991 radeon_bo_unpin(rdev->vram_scratch.robj);
992 radeon_bo_unreserve(rdev->vram_scratch.robj);
993
994 return r;
995 }
996
997 static void rv770_vram_scratch_fini(struct radeon_device *rdev)
998 {
999 int r;
1000
1001 if (rdev->vram_scratch.robj == NULL) {
1002 return;
1003 }
1004 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1005 if (likely(r == 0)) {
1006 radeon_bo_kunmap(rdev->vram_scratch.robj);
1007 radeon_bo_unpin(rdev->vram_scratch.robj);
1008 radeon_bo_unreserve(rdev->vram_scratch.robj);
1009 }
1010 radeon_bo_unref(&rdev->vram_scratch.robj);
1011 }
1012
1013 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1014 {
1015 u64 size_bf, size_af;
1016
1017 if (mc->mc_vram_size > 0xE0000000) {
1018 /* leave room for at least 512M GTT */
1019 dev_warn(rdev->dev, "limiting VRAM\n");
1020 mc->real_vram_size = 0xE0000000;
1021 mc->mc_vram_size = 0xE0000000;
1022 }
1023 if (rdev->flags & RADEON_IS_AGP) {
1024 size_bf = mc->gtt_start;
1025 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1026 if (size_bf > size_af) {
1027 if (mc->mc_vram_size > size_bf) {
1028 dev_warn(rdev->dev, "limiting VRAM\n");
1029 mc->real_vram_size = size_bf;
1030 mc->mc_vram_size = size_bf;
1031 }
1032 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1033 } else {
1034 if (mc->mc_vram_size > size_af) {
1035 dev_warn(rdev->dev, "limiting VRAM\n");
1036 mc->real_vram_size = size_af;
1037 mc->mc_vram_size = size_af;
1038 }
1039 mc->vram_start = mc->gtt_end;
1040 }
1041 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1042 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1043 mc->mc_vram_size >> 20, mc->vram_start,
1044 mc->vram_end, mc->real_vram_size >> 20);
1045 } else {
1046 radeon_vram_location(rdev, &rdev->mc, 0);
1047 rdev->mc.gtt_base_align = 0;
1048 radeon_gtt_location(rdev, mc);
1049 }
1050 }
1051
1052 int rv770_mc_init(struct radeon_device *rdev)
1053 {
1054 u32 tmp;
1055 int chansize, numchan;
1056
1057 /* Get VRAM informations */
1058 rdev->mc.vram_is_ddr = true;
1059 tmp = RREG32(MC_ARB_RAMCFG);
1060 if (tmp & CHANSIZE_OVERRIDE) {
1061 chansize = 16;
1062 } else if (tmp & CHANSIZE_MASK) {
1063 chansize = 64;
1064 } else {
1065 chansize = 32;
1066 }
1067 tmp = RREG32(MC_SHARED_CHMAP);
1068 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1069 case 0:
1070 default:
1071 numchan = 1;
1072 break;
1073 case 1:
1074 numchan = 2;
1075 break;
1076 case 2:
1077 numchan = 4;
1078 break;
1079 case 3:
1080 numchan = 8;
1081 break;
1082 }
1083 rdev->mc.vram_width = numchan * chansize;
1084 /* Could aper size report 0 ? */
1085 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1086 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1087 /* Setup GPU memory space */
1088 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1089 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1090 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1091 r700_vram_gtt_location(rdev, &rdev->mc);
1092 radeon_update_bandwidth_info(rdev);
1093
1094 return 0;
1095 }
1096
1097 static int rv770_startup(struct radeon_device *rdev)
1098 {
1099 int r;
1100
1101 /* enable pcie gen2 link */
1102 rv770_pcie_gen2_enable(rdev);
1103
1104 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1105 r = r600_init_microcode(rdev);
1106 if (r) {
1107 DRM_ERROR("Failed to load firmware!\n");
1108 return r;
1109 }
1110 }
1111
1112 rv770_mc_program(rdev);
1113 if (rdev->flags & RADEON_IS_AGP) {
1114 rv770_agp_enable(rdev);
1115 } else {
1116 r = rv770_pcie_gart_enable(rdev);
1117 if (r)
1118 return r;
1119 }
1120 r = rv770_vram_scratch_init(rdev);
1121 if (r)
1122 return r;
1123 rv770_gpu_init(rdev);
1124 r = r600_blit_init(rdev);
1125 if (r) {
1126 r600_blit_fini(rdev);
1127 rdev->asic->copy = NULL;
1128 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1129 }
1130
1131 /* allocate wb buffer */
1132 r = radeon_wb_init(rdev);
1133 if (r)
1134 return r;
1135
1136 /* Enable IRQ */
1137 r = r600_irq_init(rdev);
1138 if (r) {
1139 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1140 radeon_irq_kms_fini(rdev);
1141 return r;
1142 }
1143 r600_irq_set(rdev);
1144
1145 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1146 if (r)
1147 return r;
1148 r = rv770_cp_load_microcode(rdev);
1149 if (r)
1150 return r;
1151 r = r600_cp_resume(rdev);
1152 if (r)
1153 return r;
1154
1155 return 0;
1156 }
1157
1158 int rv770_resume(struct radeon_device *rdev)
1159 {
1160 int r;
1161
1162 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1163 * posting will perform necessary task to bring back GPU into good
1164 * shape.
1165 */
1166 /* post card */
1167 atom_asic_init(rdev->mode_info.atom_context);
1168
1169 r = rv770_startup(rdev);
1170 if (r) {
1171 DRM_ERROR("r600 startup failed on resume\n");
1172 return r;
1173 }
1174
1175 r = r600_ib_test(rdev);
1176 if (r) {
1177 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1178 return r;
1179 }
1180
1181 r = r600_audio_init(rdev);
1182 if (r) {
1183 dev_err(rdev->dev, "radeon: audio init failed\n");
1184 return r;
1185 }
1186
1187 return r;
1188
1189 }
1190
1191 int rv770_suspend(struct radeon_device *rdev)
1192 {
1193 int r;
1194
1195 r600_audio_fini(rdev);
1196 /* FIXME: we should wait for ring to be empty */
1197 r700_cp_stop(rdev);
1198 rdev->cp.ready = false;
1199 r600_irq_suspend(rdev);
1200 radeon_wb_disable(rdev);
1201 rv770_pcie_gart_disable(rdev);
1202 /* unpin shaders bo */
1203 if (rdev->r600_blit.shader_obj) {
1204 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1205 if (likely(r == 0)) {
1206 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1207 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1208 }
1209 }
1210 return 0;
1211 }
1212
1213 /* Plan is to move initialization in that function and use
1214 * helper function so that radeon_device_init pretty much
1215 * do nothing more than calling asic specific function. This
1216 * should also allow to remove a bunch of callback function
1217 * like vram_info.
1218 */
1219 int rv770_init(struct radeon_device *rdev)
1220 {
1221 int r;
1222
1223 /* This don't do much */
1224 r = radeon_gem_init(rdev);
1225 if (r)
1226 return r;
1227 /* Read BIOS */
1228 if (!radeon_get_bios(rdev)) {
1229 if (ASIC_IS_AVIVO(rdev))
1230 return -EINVAL;
1231 }
1232 /* Must be an ATOMBIOS */
1233 if (!rdev->is_atom_bios) {
1234 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1235 return -EINVAL;
1236 }
1237 r = radeon_atombios_init(rdev);
1238 if (r)
1239 return r;
1240 /* Post card if necessary */
1241 if (!radeon_card_posted(rdev)) {
1242 if (!rdev->bios) {
1243 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1244 return -EINVAL;
1245 }
1246 DRM_INFO("GPU not posted. posting now...\n");
1247 atom_asic_init(rdev->mode_info.atom_context);
1248 }
1249 /* Initialize scratch registers */
1250 r600_scratch_init(rdev);
1251 /* Initialize surface registers */
1252 radeon_surface_init(rdev);
1253 /* Initialize clocks */
1254 radeon_get_clock_info(rdev->ddev);
1255 /* Fence driver */
1256 r = radeon_fence_driver_init(rdev);
1257 if (r)
1258 return r;
1259 /* initialize AGP */
1260 if (rdev->flags & RADEON_IS_AGP) {
1261 r = radeon_agp_init(rdev);
1262 if (r)
1263 radeon_agp_disable(rdev);
1264 }
1265 r = rv770_mc_init(rdev);
1266 if (r)
1267 return r;
1268 /* Memory manager */
1269 r = radeon_bo_init(rdev);
1270 if (r)
1271 return r;
1272
1273 r = radeon_irq_kms_init(rdev);
1274 if (r)
1275 return r;
1276
1277 rdev->cp.ring_obj = NULL;
1278 r600_ring_init(rdev, 1024 * 1024);
1279
1280 rdev->ih.ring_obj = NULL;
1281 r600_ih_ring_init(rdev, 64 * 1024);
1282
1283 r = r600_pcie_gart_init(rdev);
1284 if (r)
1285 return r;
1286
1287 rdev->accel_working = true;
1288 r = rv770_startup(rdev);
1289 if (r) {
1290 dev_err(rdev->dev, "disabling GPU acceleration\n");
1291 r700_cp_fini(rdev);
1292 r600_irq_fini(rdev);
1293 radeon_wb_fini(rdev);
1294 radeon_irq_kms_fini(rdev);
1295 rv770_pcie_gart_fini(rdev);
1296 rdev->accel_working = false;
1297 }
1298 if (rdev->accel_working) {
1299 r = radeon_ib_pool_init(rdev);
1300 if (r) {
1301 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1302 rdev->accel_working = false;
1303 } else {
1304 r = r600_ib_test(rdev);
1305 if (r) {
1306 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1307 rdev->accel_working = false;
1308 }
1309 }
1310 }
1311
1312 r = r600_audio_init(rdev);
1313 if (r) {
1314 dev_err(rdev->dev, "radeon: audio init failed\n");
1315 return r;
1316 }
1317
1318 return 0;
1319 }
1320
1321 void rv770_fini(struct radeon_device *rdev)
1322 {
1323 r600_blit_fini(rdev);
1324 r700_cp_fini(rdev);
1325 r600_irq_fini(rdev);
1326 radeon_wb_fini(rdev);
1327 radeon_ib_pool_fini(rdev);
1328 radeon_irq_kms_fini(rdev);
1329 rv770_pcie_gart_fini(rdev);
1330 rv770_vram_scratch_fini(rdev);
1331 radeon_gem_fini(rdev);
1332 radeon_fence_driver_fini(rdev);
1333 radeon_agp_fini(rdev);
1334 radeon_bo_fini(rdev);
1335 radeon_atombios_fini(rdev);
1336 kfree(rdev->bios);
1337 rdev->bios = NULL;
1338 }
1339
1340 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1341 {
1342 u32 link_width_cntl, lanes, speed_cntl, tmp;
1343 u16 link_cntl2;
1344
1345 if (radeon_pcie_gen2 == 0)
1346 return;
1347
1348 if (rdev->flags & RADEON_IS_IGP)
1349 return;
1350
1351 if (!(rdev->flags & RADEON_IS_PCIE))
1352 return;
1353
1354 /* x2 cards have a special sequence */
1355 if (ASIC_IS_X2(rdev))
1356 return;
1357
1358 /* advertise upconfig capability */
1359 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1360 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1361 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1362 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1363 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1364 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1365 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1366 LC_RECONFIG_ARC_MISSING_ESCAPE);
1367 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1368 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1369 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1370 } else {
1371 link_width_cntl |= LC_UPCONFIGURE_DIS;
1372 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1373 }
1374
1375 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1376 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1377 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1378
1379 tmp = RREG32(0x541c);
1380 WREG32(0x541c, tmp | 0x8);
1381 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1382 link_cntl2 = RREG16(0x4088);
1383 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1384 link_cntl2 |= 0x2;
1385 WREG16(0x4088, link_cntl2);
1386 WREG32(MM_CFGREGS_CNTL, 0);
1387
1388 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1389 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1390 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1391
1392 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1393 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1394 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1395
1396 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1397 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1398 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1399
1400 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1401 speed_cntl |= LC_GEN2_EN_STRAP;
1402 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1403
1404 } else {
1405 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1406 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1407 if (1)
1408 link_width_cntl |= LC_UPCONFIGURE_DIS;
1409 else
1410 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1411 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1412 }
1413 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree