drivers/tty/serial/mxs-auart.c

   1 /*
   2  * Freescale STMP37XX/STMP378X Application UART driver
   3  *
   4  * Author: dmitry pervushin <dimka@embeddedalley.com>
   5  *
   6  * Copyright 2008-2010 Freescale Semiconductor, Inc.
   7  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/errno.h>
  19 #include <linux/init.h>
  20 #include <linux/console.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/wait.h>
  25 #include <linux/tty.h>
  26 #include <linux/tty_driver.h>
  27 #include <linux/tty_flip.h>
  28 #include <linux/serial.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/device.h>
  32 #include <linux/clk.h>
  33 #include <linux/delay.h>
  34 #include <linux/io.h>
  35
  36 #include <asm/cacheflush.h>
  37
  38 #define MXS_AUART_PORTS 5
  39
  40 #define AUART_CTRL0                     0x00000000
  41 #define AUART_CTRL0_SET                 0x00000004
  42 #define AUART_CTRL0_CLR                 0x00000008
  43 #define AUART_CTRL0_TOG                 0x0000000c
  44 #define AUART_CTRL1                     0x00000010
  45 #define AUART_CTRL1_SET                 0x00000014
  46 #define AUART_CTRL1_CLR                 0x00000018
  47 #define AUART_CTRL1_TOG                 0x0000001c
  48 #define AUART_CTRL2                     0x00000020
  49 #define AUART_CTRL2_SET                 0x00000024
  50 #define AUART_CTRL2_CLR                 0x00000028
  51 #define AUART_CTRL2_TOG                 0x0000002c
  52 #define AUART_LINECTRL                  0x00000030
  53 #define AUART_LINECTRL_SET              0x00000034
  54 #define AUART_LINECTRL_CLR              0x00000038
  55 #define AUART_LINECTRL_TOG              0x0000003c
  56 #define AUART_LINECTRL2                 0x00000040
  57 #define AUART_LINECTRL2_SET             0x00000044
  58 #define AUART_LINECTRL2_CLR             0x00000048
  59 #define AUART_LINECTRL2_TOG             0x0000004c
  60 #define AUART_INTR                      0x00000050
  61 #define AUART_INTR_SET                  0x00000054
  62 #define AUART_INTR_CLR                  0x00000058
  63 #define AUART_INTR_TOG                  0x0000005c
  64 #define AUART_DATA                      0x00000060
  65 #define AUART_STAT                      0x00000070
  66 #define AUART_DEBUG                     0x00000080
  67 #define AUART_VERSION                   0x00000090
  68 #define AUART_AUTOBAUD                  0x000000a0
  69
  70 #define AUART_CTRL0_SFTRST                      (1 << 31)
  71 #define AUART_CTRL0_CLKGATE                     (1 << 30)
  72
  73 #define AUART_CTRL2_CTSEN                       (1 << 15)
  74 #define AUART_CTRL2_RTS                         (1 << 11)
  75 #define AUART_CTRL2_RXE                         (1 << 9)
  76 #define AUART_CTRL2_TXE                         (1 << 8)
  77 #define AUART_CTRL2_UARTEN                      (1 << 0)
  78
  79 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT        16
  80 #define AUART_LINECTRL_BAUD_DIVINT_MASK         0xffff0000
  81 #define AUART_LINECTRL_BAUD_DIVINT(v)           (((v) & 0xffff) << 16)
  82 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT       8
  83 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK        0x00003f00
  84 #define AUART_LINECTRL_BAUD_DIVFRAC(v)          (((v) & 0x3f) << 8)
  85 #define AUART_LINECTRL_WLEN_MASK                0x00000060
  86 #define AUART_LINECTRL_WLEN(v)                  (((v) & 0x3) << 5)
  87 #define AUART_LINECTRL_FEN                      (1 << 4)
  88 #define AUART_LINECTRL_STP2                     (1 << 3)
  89 #define AUART_LINECTRL_EPS                      (1 << 2)
  90 #define AUART_LINECTRL_PEN                      (1 << 1)
  91 #define AUART_LINECTRL_BRK                      (1 << 0)
  92
  93 #define AUART_INTR_RTIEN                        (1 << 22)
  94 #define AUART_INTR_TXIEN                        (1 << 21)
  95 #define AUART_INTR_RXIEN                        (1 << 20)
  96 #define AUART_INTR_CTSMIEN                      (1 << 17)
  97 #define AUART_INTR_RTIS                         (1 << 6)
  98 #define AUART_INTR_TXIS                         (1 << 5)
  99 #define AUART_INTR_RXIS                         (1 << 4)
 100 #define AUART_INTR_CTSMIS                       (1 << 1)
 101
 102 #define AUART_STAT_BUSY                         (1 << 29)
 103 #define AUART_STAT_CTS                          (1 << 28)
 104 #define AUART_STAT_TXFE                         (1 << 27)
 105 #define AUART_STAT_TXFF                         (1 << 25)
 106 #define AUART_STAT_RXFE                         (1 << 24)
 107 #define AUART_STAT_OERR                         (1 << 19)
 108 #define AUART_STAT_BERR                         (1 << 18)
 109 #define AUART_STAT_PERR                         (1 << 17)
 110 #define AUART_STAT_FERR                         (1 << 16)
 111
 112 static struct uart_driver auart_driver;
 113
 114 struct mxs_auart_port {
 115         struct uart_port port;
 116
 117         unsigned int flags;
 118         unsigned int ctrl;
 119
 120         unsigned int irq;
 121
 122         struct clk *clk;
 123         struct device *dev;
 124 };
 125
 126 static void mxs_auart_stop_tx(struct uart_port *u);
 127
 128 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
 129
 130 static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
 131 {
 132         struct circ_buf *xmit = &s->port.state->xmit;
 133
 134         while (!(readl(s->port.membase + AUART_STAT) &
 135                  AUART_STAT_TXFF)) {
 136                 if (s->port.x_char) {
 137                         s->port.icount.tx++;
 138                         writel(s->port.x_char,
 139                                      s->port.membase + AUART_DATA);
 140                         s->port.x_char = 0;
 141                         continue;
 142                 }
 143                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
 144                         s->port.icount.tx++;
 145                         writel(xmit->buf[xmit->tail],
 146                                      s->port.membase + AUART_DATA);
 147                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 148                         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 149                                 uart_write_wakeup(&s->port);
 150                 } else
 151                         break;
 152         }
 153         if (uart_circ_empty(&(s->port.state->xmit)))
 154                 writel(AUART_INTR_TXIEN,
 155                              s->port.membase + AUART_INTR_CLR);
 156         else
 157                 writel(AUART_INTR_TXIEN,
 158                              s->port.membase + AUART_INTR_SET);
 159
 160         if (uart_tx_stopped(&s->port))
 161                 mxs_auart_stop_tx(&s->port);
 162 }
 163
 164 static void mxs_auart_rx_char(struct mxs_auart_port *s)
 165 {
 166         int flag;
 167         u32 stat;
 168         u8 c;
 169
 170         c = readl(s->port.membase + AUART_DATA);
 171         stat = readl(s->port.membase + AUART_STAT);
 172
 173         flag = TTY_NORMAL;
 174         s->port.icount.rx++;
 175
 176         if (stat & AUART_STAT_BERR) {
 177                 s->port.icount.brk++;
 178                 if (uart_handle_break(&s->port))
 179                         goto out;
 180         } else if (stat & AUART_STAT_PERR) {
 181                 s->port.icount.parity++;
 182         } else if (stat & AUART_STAT_FERR) {
 183                 s->port.icount.frame++;
 184         }
 185
 186         /*
 187          * Mask off conditions which should be ingored.
 188          */
 189         stat &= s->port.read_status_mask;
 190
 191         if (stat & AUART_STAT_BERR) {
 192                 flag = TTY_BREAK;
 193         } else if (stat & AUART_STAT_PERR)
 194                 flag = TTY_PARITY;
 195         else if (stat & AUART_STAT_FERR)
 196                 flag = TTY_FRAME;
 197
 198         if (stat & AUART_STAT_OERR)
 199                 s->port.icount.overrun++;
 200
 201         if (uart_handle_sysrq_char(&s->port, c))
 202                 goto out;
 203
 204         uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
 205 out:
 206         writel(stat, s->port.membase + AUART_STAT);
 207 }
 208
 209 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
 210 {
 211         struct tty_struct *tty = s->port.state->port.tty;
 212         u32 stat = 0;
 213
 214         for (;;) {
 215                 stat = readl(s->port.membase + AUART_STAT);
 216                 if (stat & AUART_STAT_RXFE)
 217                         break;
 218                 mxs_auart_rx_char(s);
 219         }
 220
 221         writel(stat, s->port.membase + AUART_STAT);
 222         tty_flip_buffer_push(tty);
 223 }
 224
 225 static int mxs_auart_request_port(struct uart_port *u)
 226 {
 227         return 0;
 228 }
 229
 230 static int mxs_auart_verify_port(struct uart_port *u,
 231                                     struct serial_struct *ser)
 232 {
 233         if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
 234                 return -EINVAL;
 235         return 0;
 236 }
 237
 238 static void mxs_auart_config_port(struct uart_port *u, int flags)
 239 {
 240 }
 241
 242 static const char *mxs_auart_type(struct uart_port *u)
 243 {
 244         struct mxs_auart_port *s = to_auart_port(u);
 245
 246         return dev_name(s->dev);
 247 }
 248
 249 static void mxs_auart_release_port(struct uart_port *u)
 250 {
 251 }
 252
 253 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
 254 {
 255         struct mxs_auart_port *s = to_auart_port(u);
 256
 257         u32 ctrl = readl(u->membase + AUART_CTRL2);
 258
 259         ctrl &= ~AUART_CTRL2_RTS;
 260         if (mctrl & TIOCM_RTS)
 261                 ctrl |= AUART_CTRL2_RTS;
 262         s->ctrl = mctrl;
 263         writel(ctrl, u->membase + AUART_CTRL2);
 264 }
 265
 266 static u32 mxs_auart_get_mctrl(struct uart_port *u)
 267 {
 268         struct mxs_auart_port *s = to_auart_port(u);
 269         u32 stat = readl(u->membase + AUART_STAT);
 270         int ctrl2 = readl(u->membase + AUART_CTRL2);
 271         u32 mctrl = s->ctrl;
 272
 273         mctrl &= ~TIOCM_CTS;
 274         if (stat & AUART_STAT_CTS)
 275                 mctrl |= TIOCM_CTS;
 276
 277         if (ctrl2 & AUART_CTRL2_RTS)
 278                 mctrl |= TIOCM_RTS;
 279
 280         return mctrl;
 281 }
 282
 283 static void mxs_auart_settermios(struct uart_port *u,
 284                                  struct ktermios *termios,
 285                                  struct ktermios *old)
 286 {
 287         u32 bm, ctrl, ctrl2, div;
 288         unsigned int cflag, baud;
 289
 290         cflag = termios->c_cflag;
 291
 292         ctrl = AUART_LINECTRL_FEN;
 293         ctrl2 = readl(u->membase + AUART_CTRL2);
 294
 295         /* byte size */
 296         switch (cflag & CSIZE) {
 297         case CS5:
 298                 bm = 0;
 299                 break;
 300         case CS6:
 301                 bm = 1;
 302                 break;
 303         case CS7:
 304                 bm = 2;
 305                 break;
 306         case CS8:
 307                 bm = 3;
 308                 break;
 309         default:
 310                 return;
 311         }
 312
 313         ctrl |= AUART_LINECTRL_WLEN(bm);
 314
 315         /* parity */
 316         if (cflag & PARENB) {
 317                 ctrl |= AUART_LINECTRL_PEN;
 318                 if ((cflag & PARODD) == 0)
 319                         ctrl |= AUART_LINECTRL_EPS;
 320         }
 321
 322         u->read_status_mask = 0;
 323
 324         if (termios->c_iflag & INPCK)
 325                 u->read_status_mask |= AUART_STAT_PERR;
 326         if (termios->c_iflag & (BRKINT | PARMRK))
 327                 u->read_status_mask |= AUART_STAT_BERR;
 328
 329         /*
 330          * Characters to ignore
 331          */
 332         u->ignore_status_mask = 0;
 333         if (termios->c_iflag & IGNPAR)
 334                 u->ignore_status_mask |= AUART_STAT_PERR;
 335         if (termios->c_iflag & IGNBRK) {
 336                 u->ignore_status_mask |= AUART_STAT_BERR;
 337                 /*
 338                  * If we're ignoring parity and break indicators,
 339                  * ignore overruns too (for real raw support).
 340                  */
 341                 if (termios->c_iflag & IGNPAR)
 342                         u->ignore_status_mask |= AUART_STAT_OERR;
 343         }
 344
 345         /*
 346          * ignore all characters if CREAD is not set
 347          */
 348         if (cflag & CREAD)
 349                 ctrl2 |= AUART_CTRL2_RXE;
 350         else
 351                 ctrl2 &= ~AUART_CTRL2_RXE;
 352
 353         /* figure out the stop bits requested */
 354         if (cflag & CSTOPB)
 355                 ctrl |= AUART_LINECTRL_STP2;
 356
 357         /* figure out the hardware flow control settings */
 358         if (cflag & CRTSCTS)
 359                 ctrl2 |= AUART_CTRL2_CTSEN;
 360         else
 361                 ctrl2 &= ~AUART_CTRL2_CTSEN;
 362
 363         /* set baud rate */
 364         baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
 365         div = u->uartclk * 32 / baud;
 366         ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
 367         ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
 368
 369         writel(ctrl, u->membase + AUART_LINECTRL);
 370         writel(ctrl2, u->membase + AUART_CTRL2);
 371
 372         uart_update_timeout(u, termios->c_cflag, baud);
 373 }
 374
 375 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
 376 {
 377         u32 istatus, istat;
 378         struct mxs_auart_port *s = context;
 379         u32 stat = readl(s->port.membase + AUART_STAT);
 380
 381         istatus = istat = readl(s->port.membase + AUART_INTR);
 382
 383         if (istat & AUART_INTR_CTSMIS) {
 384                 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
 385                 writel(AUART_INTR_CTSMIS,
 386                                 s->port.membase + AUART_INTR_CLR);
 387                 istat &= ~AUART_INTR_CTSMIS;
 388         }
 389
 390         if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
 391                 mxs_auart_rx_chars(s);
 392                 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
 393         }
 394
 395         if (istat & AUART_INTR_TXIS) {
 396                 mxs_auart_tx_chars(s);
 397                 istat &= ~AUART_INTR_TXIS;
 398         }
 399
 400         writel(istatus & (AUART_INTR_RTIS
 401                 | AUART_INTR_TXIS
 402                 | AUART_INTR_RXIS
 403                 | AUART_INTR_CTSMIS),
 404                         s->port.membase + AUART_INTR_CLR);
 405
 406         return IRQ_HANDLED;
 407 }
 408
 409 static void mxs_auart_reset(struct uart_port *u)
 410 {
 411         int i;
 412         unsigned int reg;
 413
 414         writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
 415
 416         for (i = 0; i < 10000; i++) {
 417                 reg = readl(u->membase + AUART_CTRL0);
 418                 if (!(reg & AUART_CTRL0_SFTRST))
 419                         break;
 420                 udelay(3);
 421         }
 422         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
 423 }
 424
 425 static int mxs_auart_startup(struct uart_port *u)
 426 {
 427         struct mxs_auart_port *s = to_auart_port(u);
 428
 429         clk_enable(s->clk);
 430
 431         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
 432
 433         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
 434
 435         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
 436                         u->membase + AUART_INTR);
 437
 438         /*
 439          * Enable fifo so all four bytes of a DMA word are written to
 440          * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
 441          */
 442         writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
 443
 444         return 0;
 445 }
 446
 447 static void mxs_auart_shutdown(struct uart_port *u)
 448 {
 449         struct mxs_auart_port *s = to_auart_port(u);
 450
 451         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
 452
 453         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
 454
 455         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
 456                         u->membase + AUART_INTR_CLR);
 457
 458         clk_disable(s->clk);
 459 }
 460
 461 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
 462 {
 463         if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
 464                 return TIOCSER_TEMT;
 465         else
 466                 return 0;
 467 }
 468
 469 static void mxs_auart_start_tx(struct uart_port *u)
 470 {
 471         struct mxs_auart_port *s = to_auart_port(u);
 472
 473         /* enable transmitter */
 474         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
 475
 476         mxs_auart_tx_chars(s);
 477 }
 478
 479 static void mxs_auart_stop_tx(struct uart_port *u)
 480 {
 481         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
 482 }
 483
 484 static void mxs_auart_stop_rx(struct uart_port *u)
 485 {
 486         writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
 487 }
 488
 489 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
 490 {
 491         if (ctl)
 492                 writel(AUART_LINECTRL_BRK,
 493                              u->membase + AUART_LINECTRL_SET);
 494         else
 495                 writel(AUART_LINECTRL_BRK,
 496                              u->membase + AUART_LINECTRL_CLR);
 497 }
 498
 499 static void mxs_auart_enable_ms(struct uart_port *port)
 500 {
 501         /* just empty */
 502 }
 503
 504 static struct uart_ops mxs_auart_ops = {
 505         .tx_empty       = mxs_auart_tx_empty,
 506         .start_tx       = mxs_auart_start_tx,
 507         .stop_tx        = mxs_auart_stop_tx,
 508         .stop_rx        = mxs_auart_stop_rx,
 509         .enable_ms      = mxs_auart_enable_ms,
 510         .break_ctl      = mxs_auart_break_ctl,
 511         .set_mctrl      = mxs_auart_set_mctrl,
 512         .get_mctrl      = mxs_auart_get_mctrl,
 513         .startup        = mxs_auart_startup,
 514         .shutdown       = mxs_auart_shutdown,
 515         .set_termios    = mxs_auart_settermios,
 516         .type           = mxs_auart_type,
 517         .release_port   = mxs_auart_release_port,
 518         .request_port   = mxs_auart_request_port,
 519         .config_port    = mxs_auart_config_port,
 520         .verify_port    = mxs_auart_verify_port,
 521 };
 522
 523 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
 524
 525 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
 526 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
 527 {
 528         unsigned int to = 1000;
 529
 530         while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
 531                 if (!to--)
 532                         break;
 533                 udelay(1);
 534         }
 535
 536         writel(ch, port->membase + AUART_DATA);
 537 }
 538
 539 static void
 540 auart_console_write(struct console *co, const char *str, unsigned int count)
 541 {
 542         struct mxs_auart_port *s;
 543         struct uart_port *port;
 544         unsigned int old_ctrl0, old_ctrl2;
 545         unsigned int to = 1000;
 546
 547         if (co->index > MXS_AUART_PORTS || co->index < 0)
 548                 return;
 549
 550         s = auart_port[co->index];
 551         port = &s->port;
 552
 553         clk_enable(s->clk);
 554
 555         /* First save the CR then disable the interrupts */
 556         old_ctrl2 = readl(port->membase + AUART_CTRL2);
 557         old_ctrl0 = readl(port->membase + AUART_CTRL0);
 558
 559         writel(AUART_CTRL0_CLKGATE,
 560                      port->membase + AUART_CTRL0_CLR);
 561         writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
 562                      port->membase + AUART_CTRL2_SET);
 563
 564         uart_console_write(port, str, count, mxs_auart_console_putchar);
 565
 566         /*
 567          * Finally, wait for transmitter to become empty
 568          * and restore the TCR
 569          */
 570         while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
 571                 if (!to--)
 572                         break;
 573                 udelay(1);
 574         }
 575
 576         writel(old_ctrl0, port->membase + AUART_CTRL0);
 577         writel(old_ctrl2, port->membase + AUART_CTRL2);
 578
 579         clk_disable(s->clk);
 580 }
 581
 582 static void __init
 583 auart_console_get_options(struct uart_port *port, int *baud,
 584                           int *parity, int *bits)
 585 {
 586         unsigned int lcr_h, quot;
 587
 588         if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
 589                 return;
 590
 591         lcr_h = readl(port->membase + AUART_LINECTRL);
 592
 593         *parity = 'n';
 594         if (lcr_h & AUART_LINECTRL_PEN) {
 595                 if (lcr_h & AUART_LINECTRL_EPS)
 596                         *parity = 'e';
 597                 else
 598                         *parity = 'o';
 599         }
 600
 601         if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
 602                 *bits = 7;
 603         else
 604                 *bits = 8;
 605
 606         quot = ((readl(port->membase + AUART_LINECTRL)
 607                         & AUART_LINECTRL_BAUD_DIVINT_MASK))
 608                             >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
 609         quot |= ((readl(port->membase + AUART_LINECTRL)
 610                         & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
 611                                 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
 612         if (quot == 0)
 613                 quot = 1;
 614
 615         *baud = (port->uartclk << 2) / quot;
 616 }
 617
 618 static int __init
 619 auart_console_setup(struct console *co, char *options)
 620 {
 621         struct mxs_auart_port *s;
 622         int baud = 9600;
 623         int bits = 8;
 624         int parity = 'n';
 625         int flow = 'n';
 626         int ret;
 627
 628         /*
 629          * Check whether an invalid uart number has been specified, and
 630          * if so, search for the first available port that does have
 631          * console support.
 632          */
 633         if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
 634                 co->index = 0;
 635         s = auart_port[co->index];
 636         if (!s)
 637                 return -ENODEV;
 638
 639         clk_enable(s->clk);
 640
 641         if (options)
 642                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 643         else
 644                 auart_console_get_options(&s->port, &baud, &parity, &bits);
 645
 646         ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
 647
 648         clk_disable(s->clk);
 649
 650         return ret;
 651 }
 652
 653 static struct console auart_console = {
 654         .name           = "ttyAPP",
 655         .write          = auart_console_write,
 656         .device         = uart_console_device,
 657         .setup          = auart_console_setup,
 658         .flags          = CON_PRINTBUFFER,
 659         .index          = -1,
 660         .data           = &auart_driver,
 661 };
 662 #endif
 663
 664 static struct uart_driver auart_driver = {
 665         .owner          = THIS_MODULE,
 666         .driver_name    = "ttyAPP",
 667         .dev_name       = "ttyAPP",
 668         .major          = 0,
 669         .minor          = 0,
 670         .nr             = MXS_AUART_PORTS,
 671 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
 672         .cons =         &auart_console,
 673 #endif
 674 };
 675
 676 static int __devinit mxs_auart_probe(struct platform_device *pdev)
 677 {
 678         struct mxs_auart_port *s;
 679         u32 version;
 680         int ret = 0;
 681         struct resource *r;
 682
 683         s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
 684         if (!s) {
 685                 ret = -ENOMEM;
 686                 goto out;
 687         }
 688
 689         s->clk = clk_get(&pdev->dev, NULL);
 690         if (IS_ERR(s->clk)) {
 691                 ret = PTR_ERR(s->clk);
 692                 goto out_free;
 693         }
 694
 695         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 696         if (!r) {
 697                 ret = -ENXIO;
 698                 goto out_free_clk;
 699         }
 700
 701         s->port.mapbase = r->start;
 702         s->port.membase = ioremap(r->start, resource_size(r));
 703         s->port.ops = &mxs_auart_ops;
 704         s->port.iotype = UPIO_MEM;
 705         s->port.line = pdev->id < 0 ? 0 : pdev->id;
 706         s->port.fifosize = 16;
 707         s->port.uartclk = clk_get_rate(s->clk);
 708         s->port.type = PORT_IMX;
 709         s->port.dev = s->dev = get_device(&pdev->dev);
 710
 711         s->flags = 0;
 712         s->ctrl = 0;
 713
 714         s->irq = platform_get_irq(pdev, 0);
 715         s->port.irq = s->irq;
 716         ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
 717         if (ret)
 718                 goto out_free_clk;
 719
 720         platform_set_drvdata(pdev, s);
 721
 722         auart_port[pdev->id] = s;
 723
 724         mxs_auart_reset(&s->port);
 725
 726         ret = uart_add_one_port(&auart_driver, &s->port);
 727         if (ret)
 728                 goto out_free_irq;
 729
 730         version = readl(s->port.membase + AUART_VERSION);
 731         dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
 732                (version >> 24) & 0xff,
 733                (version >> 16) & 0xff, version & 0xffff);
 734
 735         return 0;
 736
 737 out_free_irq:
 738         auart_port[pdev->id] = NULL;
 739         free_irq(s->irq, s);
 740 out_free_clk:
 741         clk_put(s->clk);
 742 out_free:
 743         kfree(s);
 744 out:
 745         return ret;
 746 }
 747
 748 static int __devexit mxs_auart_remove(struct platform_device *pdev)
 749 {
 750         struct mxs_auart_port *s = platform_get_drvdata(pdev);
 751
 752         uart_remove_one_port(&auart_driver, &s->port);
 753
 754         auart_port[pdev->id] = NULL;
 755
 756         clk_put(s->clk);
 757         free_irq(s->irq, s);
 758         kfree(s);
 759
 760         return 0;
 761 }
 762
 763 static struct platform_driver mxs_auart_driver = {
 764         .probe = mxs_auart_probe,
 765         .remove = __devexit_p(mxs_auart_remove),
 766         .driver = {
 767                 .name = "mxs-auart",
 768                 .owner = THIS_MODULE,
 769         },
 770 };
 771
 772 static int __init mxs_auart_init(void)
 773 {
 774         int r;
 775
 776         r = uart_register_driver(&auart_driver);
 777         if (r)
 778                 goto out;
 779
 780         r = platform_driver_register(&mxs_auart_driver);
 781         if (r)
 782                 goto out_err;
 783
 784         return 0;
 785 out_err:
 786         uart_unregister_driver(&auart_driver);
 787 out:
 788         return r;
 789 }
 790
 791 static void __exit mxs_auart_exit(void)
 792 {
 793         platform_driver_unregister(&mxs_auart_driver);
 794         uart_unregister_driver(&auart_driver);
 795 }
 796
 797 module_init(mxs_auart_init);
 798 module_exit(mxs_auart_exit);
 799 MODULE_LICENSE("GPL");
 800 MODULE_DESCRIPTION("Freescale MXS application uart driver");