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x86/amd-iommu: Fix crash when request_mem_region fails
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / amd_iommu_init.c
blob1405346c62b4a183504bc342ab9cb3f90494cc3b
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/x86_init.h>
34
35 /*
36 * definitions for the ACPI scanning code
37 */
38 #define IVRS_HEADER_LENGTH 48
39
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
44
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
53
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
58
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
61
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70
71 /*
72 * ACPI table definitions
73 *
74 * These data structures are laid over the table to parse the important values
75 * out of it.
76 */
77
78 /*
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
81 */
82 struct ivhd_header {
83 u8 type;
84 u8 flags;
85 u16 length;
86 u16 devid;
87 u16 cap_ptr;
88 u64 mmio_phys;
89 u16 pci_seg;
90 u16 info;
91 u32 reserved;
92 } __attribute__((packed));
93
94 /*
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
97 */
98 struct ivhd_entry {
99 u8 type;
100 u16 devid;
101 u8 flags;
102 u32 ext;
103 } __attribute__((packed));
104
105 /*
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
108 */
109 struct ivmd_header {
110 u8 type;
111 u8 flags;
112 u16 length;
113 u16 devid;
114 u16 aux;
115 u64 resv;
116 u64 range_start;
117 u64 range_length;
118 } __attribute__((packed));
119
120 bool amd_iommu_dump;
121
122 static int __initdata amd_iommu_detected;
123 static bool __initdata amd_iommu_disabled;
124
125 u16 amd_iommu_last_bdf; /* largest PCI device id we have
126 to handle */
127 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
128 we find in ACPI */
129 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
130
131 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
132 system */
133
134 /* Array to assign indices to IOMMUs*/
135 struct amd_iommu *amd_iommus[MAX_IOMMUS];
136 int amd_iommus_present;
137
138 /* IOMMUs have a non-present cache? */
139 bool amd_iommu_np_cache __read_mostly;
140
141 /*
142 * The ACPI table parsing functions set this variable on an error
143 */
144 static int __initdata amd_iommu_init_err;
145
146 /*
147 * List of protection domains - used during resume
148 */
149 LIST_HEAD(amd_iommu_pd_list);
150 spinlock_t amd_iommu_pd_lock;
151
152 /*
153 * Pointer to the device table which is shared by all AMD IOMMUs
154 * it is indexed by the PCI device id or the HT unit id and contains
155 * information about the domain the device belongs to as well as the
156 * page table root pointer.
157 */
158 struct dev_table_entry *amd_iommu_dev_table;
159
160 /*
161 * The alias table is a driver specific data structure which contains the
162 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
163 * More than one device can share the same requestor id.
164 */
165 u16 *amd_iommu_alias_table;
166
167 /*
168 * The rlookup table is used to find the IOMMU which is responsible
169 * for a specific device. It is also indexed by the PCI device id.
170 */
171 struct amd_iommu **amd_iommu_rlookup_table;
172
173 /*
174 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
175 * to know which ones are already in use.
176 */
177 unsigned long *amd_iommu_pd_alloc_bitmap;
178
179 static u32 dev_table_size; /* size of the device table */
180 static u32 alias_table_size; /* size of the alias table */
181 static u32 rlookup_table_size; /* size if the rlookup table */
182
183 static inline void update_last_devid(u16 devid)
184 {
185 if (devid > amd_iommu_last_bdf)
186 amd_iommu_last_bdf = devid;
187 }
188
189 static inline unsigned long tbl_size(int entry_size)
190 {
191 unsigned shift = PAGE_SHIFT +
192 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
193
194 return 1UL << shift;
195 }
196
197 /****************************************************************************
198 *
199 * AMD IOMMU MMIO register space handling functions
200 *
201 * These functions are used to program the IOMMU device registers in
202 * MMIO space required for that driver.
203 *
204 ****************************************************************************/
205
206 /*
207 * This function set the exclusion range in the IOMMU. DMA accesses to the
208 * exclusion range are passed through untranslated
209 */
210 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
211 {
212 u64 start = iommu->exclusion_start & PAGE_MASK;
213 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
214 u64 entry;
215
216 if (!iommu->exclusion_start)
217 return;
218
219 entry = start | MMIO_EXCL_ENABLE_MASK;
220 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
221 &entry, sizeof(entry));
222
223 entry = limit;
224 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
225 &entry, sizeof(entry));
226 }
227
228 /* Programs the physical address of the device table into the IOMMU hardware */
229 static void __init iommu_set_device_table(struct amd_iommu *iommu)
230 {
231 u64 entry;
232
233 BUG_ON(iommu->mmio_base == NULL);
234
235 entry = virt_to_phys(amd_iommu_dev_table);
236 entry |= (dev_table_size >> 12) - 1;
237 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
238 &entry, sizeof(entry));
239 }
240
241 /* Generic functions to enable/disable certain features of the IOMMU. */
242 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
243 {
244 u32 ctrl;
245
246 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
247 ctrl |= (1 << bit);
248 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
249 }
250
251 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
252 {
253 u32 ctrl;
254
255 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
256 ctrl &= ~(1 << bit);
257 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
258 }
259
260 /* Function to enable the hardware */
261 static void iommu_enable(struct amd_iommu *iommu)
262 {
263 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
264 dev_name(&iommu->dev->dev), iommu->cap_ptr);
265
266 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
267 }
268
269 static void iommu_disable(struct amd_iommu *iommu)
270 {
271 /* Disable command buffer */
272 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
273
274 /* Disable event logging and event interrupts */
275 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
276 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
277
278 /* Disable IOMMU hardware itself */
279 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
280 }
281
282 /*
283 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
284 * the system has one.
285 */
286 static u8 * __init iommu_map_mmio_space(u64 address)
287 {
288 u8 *ret;
289
290 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
291 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
292 address);
293 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
294 return NULL;
295 }
296
297 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
298 if (ret != NULL)
299 return ret;
300
301 release_mem_region(address, MMIO_REGION_LENGTH);
302
303 return NULL;
304 }
305
306 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
307 {
308 if (iommu->mmio_base)
309 iounmap(iommu->mmio_base);
310 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
311 }
312
313 /****************************************************************************
314 *
315 * The functions below belong to the first pass of AMD IOMMU ACPI table
316 * parsing. In this pass we try to find out the highest device id this
317 * code has to handle. Upon this information the size of the shared data
318 * structures is determined later.
319 *
320 ****************************************************************************/
321
322 /*
323 * This function calculates the length of a given IVHD entry
324 */
325 static inline int ivhd_entry_length(u8 *ivhd)
326 {
327 return 0x04 << (*ivhd >> 6);
328 }
329
330 /*
331 * This function reads the last device id the IOMMU has to handle from the PCI
332 * capability header for this IOMMU
333 */
334 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
335 {
336 u32 cap;
337
338 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
339 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
340
341 return 0;
342 }
343
344 /*
345 * After reading the highest device id from the IOMMU PCI capability header
346 * this function looks if there is a higher device id defined in the ACPI table
347 */
348 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
349 {
350 u8 *p = (void *)h, *end = (void *)h;
351 struct ivhd_entry *dev;
352
353 p += sizeof(*h);
354 end += h->length;
355
356 find_last_devid_on_pci(PCI_BUS(h->devid),
357 PCI_SLOT(h->devid),
358 PCI_FUNC(h->devid),
359 h->cap_ptr);
360
361 while (p < end) {
362 dev = (struct ivhd_entry *)p;
363 switch (dev->type) {
364 case IVHD_DEV_SELECT:
365 case IVHD_DEV_RANGE_END:
366 case IVHD_DEV_ALIAS:
367 case IVHD_DEV_EXT_SELECT:
368 /* all the above subfield types refer to device ids */
369 update_last_devid(dev->devid);
370 break;
371 default:
372 break;
373 }
374 p += ivhd_entry_length(p);
375 }
376
377 WARN_ON(p != end);
378
379 return 0;
380 }
381
382 /*
383 * Iterate over all IVHD entries in the ACPI table and find the highest device
384 * id which we need to handle. This is the first of three functions which parse
385 * the ACPI table. So we check the checksum here.
386 */
387 static int __init find_last_devid_acpi(struct acpi_table_header *table)
388 {
389 int i;
390 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
391 struct ivhd_header *h;
392
393 /*
394 * Validate checksum here so we don't need to do it when
395 * we actually parse the table
396 */
397 for (i = 0; i < table->length; ++i)
398 checksum += p[i];
399 if (checksum != 0) {
400 /* ACPI table corrupt */
401 amd_iommu_init_err = -ENODEV;
402 return 0;
403 }
404
405 p += IVRS_HEADER_LENGTH;
406
407 end += table->length;
408 while (p < end) {
409 h = (struct ivhd_header *)p;
410 switch (h->type) {
411 case ACPI_IVHD_TYPE:
412 find_last_devid_from_ivhd(h);
413 break;
414 default:
415 break;
416 }
417 p += h->length;
418 }
419 WARN_ON(p != end);
420
421 return 0;
422 }
423
424 /****************************************************************************
425 *
426 * The following functions belong the the code path which parses the ACPI table
427 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
428 * data structures, initialize the device/alias/rlookup table and also
429 * basically initialize the hardware.
430 *
431 ****************************************************************************/
432
433 /*
434 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
435 * write commands to that buffer later and the IOMMU will execute them
436 * asynchronously
437 */
438 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
439 {
440 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
441 get_order(CMD_BUFFER_SIZE));
442
443 if (cmd_buf == NULL)
444 return NULL;
445
446 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
447
448 return cmd_buf;
449 }
450
451 /*
452 * This function resets the command buffer if the IOMMU stopped fetching
453 * commands from it.
454 */
455 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
456 {
457 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
458
459 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
460 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
461
462 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
463 }
464
465 /*
466 * This function writes the command buffer address to the hardware and
467 * enables it.
468 */
469 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
470 {
471 u64 entry;
472
473 BUG_ON(iommu->cmd_buf == NULL);
474
475 entry = (u64)virt_to_phys(iommu->cmd_buf);
476 entry |= MMIO_CMD_SIZE_512;
477
478 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
479 &entry, sizeof(entry));
480
481 amd_iommu_reset_cmd_buffer(iommu);
482 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
483 }
484
485 static void __init free_command_buffer(struct amd_iommu *iommu)
486 {
487 free_pages((unsigned long)iommu->cmd_buf,
488 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
489 }
490
491 /* allocates the memory where the IOMMU will log its events to */
492 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
493 {
494 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
495 get_order(EVT_BUFFER_SIZE));
496
497 if (iommu->evt_buf == NULL)
498 return NULL;
499
500 iommu->evt_buf_size = EVT_BUFFER_SIZE;
501
502 return iommu->evt_buf;
503 }
504
505 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
506 {
507 u64 entry;
508
509 BUG_ON(iommu->evt_buf == NULL);
510
511 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
512
513 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
514 &entry, sizeof(entry));
515
516 /* set head and tail to zero manually */
517 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
518 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
519
520 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
521 }
522
523 static void __init free_event_buffer(struct amd_iommu *iommu)
524 {
525 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
526 }
527
528 /* sets a specific bit in the device table entry. */
529 static void set_dev_entry_bit(u16 devid, u8 bit)
530 {
531 int i = (bit >> 5) & 0x07;
532 int _bit = bit & 0x1f;
533
534 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
535 }
536
537 static int get_dev_entry_bit(u16 devid, u8 bit)
538 {
539 int i = (bit >> 5) & 0x07;
540 int _bit = bit & 0x1f;
541
542 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
543 }
544
545
546 void amd_iommu_apply_erratum_63(u16 devid)
547 {
548 int sysmgt;
549
550 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
551 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
552
553 if (sysmgt == 0x01)
554 set_dev_entry_bit(devid, DEV_ENTRY_IW);
555 }
556
557 /* Writes the specific IOMMU for a device into the rlookup table */
558 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
559 {
560 amd_iommu_rlookup_table[devid] = iommu;
561 }
562
563 /*
564 * This function takes the device specific flags read from the ACPI
565 * table and sets up the device table entry with that information
566 */
567 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
568 u16 devid, u32 flags, u32 ext_flags)
569 {
570 if (flags & ACPI_DEVFLAG_INITPASS)
571 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
572 if (flags & ACPI_DEVFLAG_EXTINT)
573 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
574 if (flags & ACPI_DEVFLAG_NMI)
575 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
576 if (flags & ACPI_DEVFLAG_SYSMGT1)
577 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
578 if (flags & ACPI_DEVFLAG_SYSMGT2)
579 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
580 if (flags & ACPI_DEVFLAG_LINT0)
581 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
582 if (flags & ACPI_DEVFLAG_LINT1)
583 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
584
585 amd_iommu_apply_erratum_63(devid);
586
587 set_iommu_for_device(iommu, devid);
588 }
589
590 /*
591 * Reads the device exclusion range from ACPI and initialize IOMMU with
592 * it
593 */
594 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
595 {
596 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
597
598 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
599 return;
600
601 if (iommu) {
602 /*
603 * We only can configure exclusion ranges per IOMMU, not
604 * per device. But we can enable the exclusion range per
605 * device. This is done here
606 */
607 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
608 iommu->exclusion_start = m->range_start;
609 iommu->exclusion_length = m->range_length;
610 }
611 }
612
613 /*
614 * This function reads some important data from the IOMMU PCI space and
615 * initializes the driver data structure with it. It reads the hardware
616 * capabilities and the first/last device entries
617 */
618 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
619 {
620 int cap_ptr = iommu->cap_ptr;
621 u32 range, misc;
622
623 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
624 &iommu->cap);
625 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
626 &range);
627 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
628 &misc);
629
630 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
631 MMIO_GET_FD(range));
632 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
633 MMIO_GET_LD(range));
634 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
635 }
636
637 /*
638 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
639 * initializes the hardware and our data structures with it.
640 */
641 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
642 struct ivhd_header *h)
643 {
644 u8 *p = (u8 *)h;
645 u8 *end = p, flags = 0;
646 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
647 u32 ext_flags = 0;
648 bool alias = false;
649 struct ivhd_entry *e;
650
651 /*
652 * First set the recommended feature enable bits from ACPI
653 * into the IOMMU control registers
654 */
655 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
656 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
657 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
658
659 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
660 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
661 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
662
663 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
664 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
665 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
666
667 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
668 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
669 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
670
671 /*
672 * make IOMMU memory accesses cache coherent
673 */
674 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
675
676 /*
677 * Done. Now parse the device entries
678 */
679 p += sizeof(struct ivhd_header);
680 end += h->length;
681
682
683 while (p < end) {
684 e = (struct ivhd_entry *)p;
685 switch (e->type) {
686 case IVHD_DEV_ALL:
687
688 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
689 " last device %02x:%02x.%x flags: %02x\n",
690 PCI_BUS(iommu->first_device),
691 PCI_SLOT(iommu->first_device),
692 PCI_FUNC(iommu->first_device),
693 PCI_BUS(iommu->last_device),
694 PCI_SLOT(iommu->last_device),
695 PCI_FUNC(iommu->last_device),
696 e->flags);
697
698 for (dev_i = iommu->first_device;
699 dev_i <= iommu->last_device; ++dev_i)
700 set_dev_entry_from_acpi(iommu, dev_i,
701 e->flags, 0);
702 break;
703 case IVHD_DEV_SELECT:
704
705 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
706 "flags: %02x\n",
707 PCI_BUS(e->devid),
708 PCI_SLOT(e->devid),
709 PCI_FUNC(e->devid),
710 e->flags);
711
712 devid = e->devid;
713 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
714 break;
715 case IVHD_DEV_SELECT_RANGE_START:
716
717 DUMP_printk(" DEV_SELECT_RANGE_START\t "
718 "devid: %02x:%02x.%x flags: %02x\n",
719 PCI_BUS(e->devid),
720 PCI_SLOT(e->devid),
721 PCI_FUNC(e->devid),
722 e->flags);
723
724 devid_start = e->devid;
725 flags = e->flags;
726 ext_flags = 0;
727 alias = false;
728 break;
729 case IVHD_DEV_ALIAS:
730
731 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
732 "flags: %02x devid_to: %02x:%02x.%x\n",
733 PCI_BUS(e->devid),
734 PCI_SLOT(e->devid),
735 PCI_FUNC(e->devid),
736 e->flags,
737 PCI_BUS(e->ext >> 8),
738 PCI_SLOT(e->ext >> 8),
739 PCI_FUNC(e->ext >> 8));
740
741 devid = e->devid;
742 devid_to = e->ext >> 8;
743 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
744 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
745 amd_iommu_alias_table[devid] = devid_to;
746 break;
747 case IVHD_DEV_ALIAS_RANGE:
748
749 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
750 "devid: %02x:%02x.%x flags: %02x "
751 "devid_to: %02x:%02x.%x\n",
752 PCI_BUS(e->devid),
753 PCI_SLOT(e->devid),
754 PCI_FUNC(e->devid),
755 e->flags,
756 PCI_BUS(e->ext >> 8),
757 PCI_SLOT(e->ext >> 8),
758 PCI_FUNC(e->ext >> 8));
759
760 devid_start = e->devid;
761 flags = e->flags;
762 devid_to = e->ext >> 8;
763 ext_flags = 0;
764 alias = true;
765 break;
766 case IVHD_DEV_EXT_SELECT:
767
768 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
769 "flags: %02x ext: %08x\n",
770 PCI_BUS(e->devid),
771 PCI_SLOT(e->devid),
772 PCI_FUNC(e->devid),
773 e->flags, e->ext);
774
775 devid = e->devid;
776 set_dev_entry_from_acpi(iommu, devid, e->flags,
777 e->ext);
778 break;
779 case IVHD_DEV_EXT_SELECT_RANGE:
780
781 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
782 "%02x:%02x.%x flags: %02x ext: %08x\n",
783 PCI_BUS(e->devid),
784 PCI_SLOT(e->devid),
785 PCI_FUNC(e->devid),
786 e->flags, e->ext);
787
788 devid_start = e->devid;
789 flags = e->flags;
790 ext_flags = e->ext;
791 alias = false;
792 break;
793 case IVHD_DEV_RANGE_END:
794
795 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
796 PCI_BUS(e->devid),
797 PCI_SLOT(e->devid),
798 PCI_FUNC(e->devid));
799
800 devid = e->devid;
801 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
802 if (alias) {
803 amd_iommu_alias_table[dev_i] = devid_to;
804 set_dev_entry_from_acpi(iommu,
805 devid_to, flags, ext_flags);
806 }
807 set_dev_entry_from_acpi(iommu, dev_i,
808 flags, ext_flags);
809 }
810 break;
811 default:
812 break;
813 }
814
815 p += ivhd_entry_length(p);
816 }
817 }
818
819 /* Initializes the device->iommu mapping for the driver */
820 static int __init init_iommu_devices(struct amd_iommu *iommu)
821 {
822 u16 i;
823
824 for (i = iommu->first_device; i <= iommu->last_device; ++i)
825 set_iommu_for_device(iommu, i);
826
827 return 0;
828 }
829
830 static void __init free_iommu_one(struct amd_iommu *iommu)
831 {
832 free_command_buffer(iommu);
833 free_event_buffer(iommu);
834 iommu_unmap_mmio_space(iommu);
835 }
836
837 static void __init free_iommu_all(void)
838 {
839 struct amd_iommu *iommu, *next;
840
841 for_each_iommu_safe(iommu, next) {
842 list_del(&iommu->list);
843 free_iommu_one(iommu);
844 kfree(iommu);
845 }
846 }
847
848 /*
849 * This function clues the initialization function for one IOMMU
850 * together and also allocates the command buffer and programs the
851 * hardware. It does NOT enable the IOMMU. This is done afterwards.
852 */
853 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
854 {
855 spin_lock_init(&iommu->lock);
856
857 /* Add IOMMU to internal data structures */
858 list_add_tail(&iommu->list, &amd_iommu_list);
859 iommu->index = amd_iommus_present++;
860
861 if (unlikely(iommu->index >= MAX_IOMMUS)) {
862 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
863 return -ENOSYS;
864 }
865
866 /* Index is fine - add IOMMU to the array */
867 amd_iommus[iommu->index] = iommu;
868
869 /*
870 * Copy data from ACPI table entry to the iommu struct
871 */
872 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
873 if (!iommu->dev)
874 return 1;
875
876 iommu->cap_ptr = h->cap_ptr;
877 iommu->pci_seg = h->pci_seg;
878 iommu->mmio_phys = h->mmio_phys;
879 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
880 if (!iommu->mmio_base)
881 return -ENOMEM;
882
883 iommu->cmd_buf = alloc_command_buffer(iommu);
884 if (!iommu->cmd_buf)
885 return -ENOMEM;
886
887 iommu->evt_buf = alloc_event_buffer(iommu);
888 if (!iommu->evt_buf)
889 return -ENOMEM;
890
891 iommu->int_enabled = false;
892
893 init_iommu_from_pci(iommu);
894 init_iommu_from_acpi(iommu, h);
895 init_iommu_devices(iommu);
896
897 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
898 amd_iommu_np_cache = true;
899
900 return pci_enable_device(iommu->dev);
901 }
902
903 /*
904 * Iterates over all IOMMU entries in the ACPI table, allocates the
905 * IOMMU structure and initializes it with init_iommu_one()
906 */
907 static int __init init_iommu_all(struct acpi_table_header *table)
908 {
909 u8 *p = (u8 *)table, *end = (u8 *)table;
910 struct ivhd_header *h;
911 struct amd_iommu *iommu;
912 int ret;
913
914 end += table->length;
915 p += IVRS_HEADER_LENGTH;
916
917 while (p < end) {
918 h = (struct ivhd_header *)p;
919 switch (*p) {
920 case ACPI_IVHD_TYPE:
921
922 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
923 "seg: %d flags: %01x info %04x\n",
924 PCI_BUS(h->devid), PCI_SLOT(h->devid),
925 PCI_FUNC(h->devid), h->cap_ptr,
926 h->pci_seg, h->flags, h->info);
927 DUMP_printk(" mmio-addr: %016llx\n",
928 h->mmio_phys);
929
930 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
931 if (iommu == NULL) {
932 amd_iommu_init_err = -ENOMEM;
933 return 0;
934 }
935
936 ret = init_iommu_one(iommu, h);
937 if (ret) {
938 amd_iommu_init_err = ret;
939 return 0;
940 }
941 break;
942 default:
943 break;
944 }
945 p += h->length;
946
947 }
948 WARN_ON(p != end);
949
950 return 0;
951 }
952
953 /****************************************************************************
954 *
955 * The following functions initialize the MSI interrupts for all IOMMUs
956 * in the system. Its a bit challenging because there could be multiple
957 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
958 * pci_dev.
959 *
960 ****************************************************************************/
961
962 static int iommu_setup_msi(struct amd_iommu *iommu)
963 {
964 int r;
965
966 if (pci_enable_msi(iommu->dev))
967 return 1;
968
969 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
970 IRQF_SAMPLE_RANDOM,
971 "AMD-Vi",
972 NULL);
973
974 if (r) {
975 pci_disable_msi(iommu->dev);
976 return 1;
977 }
978
979 iommu->int_enabled = true;
980 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
981
982 return 0;
983 }
984
985 static int iommu_init_msi(struct amd_iommu *iommu)
986 {
987 if (iommu->int_enabled)
988 return 0;
989
990 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
991 return iommu_setup_msi(iommu);
992
993 return 1;
994 }
995
996 /****************************************************************************
997 *
998 * The next functions belong to the third pass of parsing the ACPI
999 * table. In this last pass the memory mapping requirements are
1000 * gathered (like exclusion and unity mapping reanges).
1001 *
1002 ****************************************************************************/
1003
1004 static void __init free_unity_maps(void)
1005 {
1006 struct unity_map_entry *entry, *next;
1007
1008 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1009 list_del(&entry->list);
1010 kfree(entry);
1011 }
1012 }
1013
1014 /* called when we find an exclusion range definition in ACPI */
1015 static int __init init_exclusion_range(struct ivmd_header *m)
1016 {
1017 int i;
1018
1019 switch (m->type) {
1020 case ACPI_IVMD_TYPE:
1021 set_device_exclusion_range(m->devid, m);
1022 break;
1023 case ACPI_IVMD_TYPE_ALL:
1024 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1025 set_device_exclusion_range(i, m);
1026 break;
1027 case ACPI_IVMD_TYPE_RANGE:
1028 for (i = m->devid; i <= m->aux; ++i)
1029 set_device_exclusion_range(i, m);
1030 break;
1031 default:
1032 break;
1033 }
1034
1035 return 0;
1036 }
1037
1038 /* called for unity map ACPI definition */
1039 static int __init init_unity_map_range(struct ivmd_header *m)
1040 {
1041 struct unity_map_entry *e = 0;
1042 char *s;
1043
1044 e = kzalloc(sizeof(*e), GFP_KERNEL);
1045 if (e == NULL)
1046 return -ENOMEM;
1047
1048 switch (m->type) {
1049 default:
1050 kfree(e);
1051 return 0;
1052 case ACPI_IVMD_TYPE:
1053 s = "IVMD_TYPEi\t\t\t";
1054 e->devid_start = e->devid_end = m->devid;
1055 break;
1056 case ACPI_IVMD_TYPE_ALL:
1057 s = "IVMD_TYPE_ALL\t\t";
1058 e->devid_start = 0;
1059 e->devid_end = amd_iommu_last_bdf;
1060 break;
1061 case ACPI_IVMD_TYPE_RANGE:
1062 s = "IVMD_TYPE_RANGE\t\t";
1063 e->devid_start = m->devid;
1064 e->devid_end = m->aux;
1065 break;
1066 }
1067 e->address_start = PAGE_ALIGN(m->range_start);
1068 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1069 e->prot = m->flags >> 1;
1070
1071 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1072 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1073 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1074 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1075 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1076 e->address_start, e->address_end, m->flags);
1077
1078 list_add_tail(&e->list, &amd_iommu_unity_map);
1079
1080 return 0;
1081 }
1082
1083 /* iterates over all memory definitions we find in the ACPI table */
1084 static int __init init_memory_definitions(struct acpi_table_header *table)
1085 {
1086 u8 *p = (u8 *)table, *end = (u8 *)table;
1087 struct ivmd_header *m;
1088
1089 end += table->length;
1090 p += IVRS_HEADER_LENGTH;
1091
1092 while (p < end) {
1093 m = (struct ivmd_header *)p;
1094 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1095 init_exclusion_range(m);
1096 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1097 init_unity_map_range(m);
1098
1099 p += m->length;
1100 }
1101
1102 return 0;
1103 }
1104
1105 /*
1106 * Init the device table to not allow DMA access for devices and
1107 * suppress all page faults
1108 */
1109 static void init_device_table(void)
1110 {
1111 u16 devid;
1112
1113 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1114 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1115 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1116 }
1117 }
1118
1119 /*
1120 * This function finally enables all IOMMUs found in the system after
1121 * they have been initialized
1122 */
1123 static void enable_iommus(void)
1124 {
1125 struct amd_iommu *iommu;
1126
1127 for_each_iommu(iommu) {
1128 iommu_disable(iommu);
1129 iommu_set_device_table(iommu);
1130 iommu_enable_command_buffer(iommu);
1131 iommu_enable_event_buffer(iommu);
1132 iommu_set_exclusion_range(iommu);
1133 iommu_init_msi(iommu);
1134 iommu_enable(iommu);
1135 }
1136 }
1137
1138 static void disable_iommus(void)
1139 {
1140 struct amd_iommu *iommu;
1141
1142 for_each_iommu(iommu)
1143 iommu_disable(iommu);
1144 }
1145
1146 /*
1147 * Suspend/Resume support
1148 * disable suspend until real resume implemented
1149 */
1150
1151 static int amd_iommu_resume(struct sys_device *dev)
1152 {
1153 /* re-load the hardware */
1154 enable_iommus();
1155
1156 /*
1157 * we have to flush after the IOMMUs are enabled because a
1158 * disabled IOMMU will never execute the commands we send
1159 */
1160 amd_iommu_flush_all_devices();
1161 amd_iommu_flush_all_domains();
1162
1163 return 0;
1164 }
1165
1166 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1167 {
1168 /* disable IOMMUs to go out of the way for BIOS */
1169 disable_iommus();
1170
1171 return 0;
1172 }
1173
1174 static struct sysdev_class amd_iommu_sysdev_class = {
1175 .name = "amd_iommu",
1176 .suspend = amd_iommu_suspend,
1177 .resume = amd_iommu_resume,
1178 };
1179
1180 static struct sys_device device_amd_iommu = {
1181 .id = 0,
1182 .cls = &amd_iommu_sysdev_class,
1183 };
1184
1185 /*
1186 * This is the core init function for AMD IOMMU hardware in the system.
1187 * This function is called from the generic x86 DMA layer initialization
1188 * code.
1189 *
1190 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1191 * three times:
1192 *
1193 * 1 pass) Find the highest PCI device id the driver has to handle.
1194 * Upon this information the size of the data structures is
1195 * determined that needs to be allocated.
1196 *
1197 * 2 pass) Initialize the data structures just allocated with the
1198 * information in the ACPI table about available AMD IOMMUs
1199 * in the system. It also maps the PCI devices in the
1200 * system to specific IOMMUs
1201 *
1202 * 3 pass) After the basic data structures are allocated and
1203 * initialized we update them with information about memory
1204 * remapping requirements parsed out of the ACPI table in
1205 * this last pass.
1206 *
1207 * After that the hardware is initialized and ready to go. In the last
1208 * step we do some Linux specific things like registering the driver in
1209 * the dma_ops interface and initializing the suspend/resume support
1210 * functions. Finally it prints some information about AMD IOMMUs and
1211 * the driver state and enables the hardware.
1212 */
1213 static int __init amd_iommu_init(void)
1214 {
1215 int i, ret = 0;
1216
1217 /*
1218 * First parse ACPI tables to find the largest Bus/Dev/Func
1219 * we need to handle. Upon this information the shared data
1220 * structures for the IOMMUs in the system will be allocated
1221 */
1222 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1223 return -ENODEV;
1224
1225 ret = amd_iommu_init_err;
1226 if (ret)
1227 goto out;
1228
1229 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1230 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1231 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1232
1233 ret = -ENOMEM;
1234
1235 /* Device table - directly used by all IOMMUs */
1236 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1237 get_order(dev_table_size));
1238 if (amd_iommu_dev_table == NULL)
1239 goto out;
1240
1241 /*
1242 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1243 * IOMMU see for that device
1244 */
1245 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1246 get_order(alias_table_size));
1247 if (amd_iommu_alias_table == NULL)
1248 goto free;
1249
1250 /* IOMMU rlookup table - find the IOMMU for a specific device */
1251 amd_iommu_rlookup_table = (void *)__get_free_pages(
1252 GFP_KERNEL | __GFP_ZERO,
1253 get_order(rlookup_table_size));
1254 if (amd_iommu_rlookup_table == NULL)
1255 goto free;
1256
1257 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1258 GFP_KERNEL | __GFP_ZERO,
1259 get_order(MAX_DOMAIN_ID/8));
1260 if (amd_iommu_pd_alloc_bitmap == NULL)
1261 goto free;
1262
1263 /* init the device table */
1264 init_device_table();
1265
1266 /*
1267 * let all alias entries point to itself
1268 */
1269 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1270 amd_iommu_alias_table[i] = i;
1271
1272 /*
1273 * never allocate domain 0 because its used as the non-allocated and
1274 * error value placeholder
1275 */
1276 amd_iommu_pd_alloc_bitmap[0] = 1;
1277
1278 spin_lock_init(&amd_iommu_pd_lock);
1279
1280 /*
1281 * now the data structures are allocated and basically initialized
1282 * start the real acpi table scan
1283 */
1284 ret = -ENODEV;
1285 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1286 goto free;
1287
1288 if (amd_iommu_init_err) {
1289 ret = amd_iommu_init_err;
1290 goto free;
1291 }
1292
1293 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1294 goto free;
1295
1296 if (amd_iommu_init_err) {
1297 ret = amd_iommu_init_err;
1298 goto free;
1299 }
1300
1301 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1302 if (ret)
1303 goto free;
1304
1305 ret = sysdev_register(&device_amd_iommu);
1306 if (ret)
1307 goto free;
1308
1309 ret = amd_iommu_init_devices();
1310 if (ret)
1311 goto free;
1312
1313 enable_iommus();
1314
1315 if (iommu_pass_through)
1316 ret = amd_iommu_init_passthrough();
1317 else
1318 ret = amd_iommu_init_dma_ops();
1319
1320 if (ret)
1321 goto free_disable;
1322
1323 amd_iommu_init_api();
1324
1325 amd_iommu_init_notifier();
1326
1327 if (iommu_pass_through)
1328 goto out;
1329
1330 if (amd_iommu_unmap_flush)
1331 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1332 else
1333 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1334
1335 x86_platform.iommu_shutdown = disable_iommus;
1336 out:
1337 return ret;
1338
1339 free_disable:
1340 disable_iommus();
1341
1342 free:
1343 amd_iommu_uninit_devices();
1344
1345 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1346 get_order(MAX_DOMAIN_ID/8));
1347
1348 free_pages((unsigned long)amd_iommu_rlookup_table,
1349 get_order(rlookup_table_size));
1350
1351 free_pages((unsigned long)amd_iommu_alias_table,
1352 get_order(alias_table_size));
1353
1354 free_pages((unsigned long)amd_iommu_dev_table,
1355 get_order(dev_table_size));
1356
1357 free_iommu_all();
1358
1359 free_unity_maps();
1360
1361 goto out;
1362 }
1363
1364 /****************************************************************************
1365 *
1366 * Early detect code. This code runs at IOMMU detection time in the DMA
1367 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1368 * IOMMUs
1369 *
1370 ****************************************************************************/
1371 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1372 {
1373 return 0;
1374 }
1375
1376 void __init amd_iommu_detect(void)
1377 {
1378 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1379 return;
1380
1381 if (amd_iommu_disabled)
1382 return;
1383
1384 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1385 iommu_detected = 1;
1386 amd_iommu_detected = 1;
1387 x86_init.iommu.iommu_init = amd_iommu_init;
1388
1389 /* Make sure ACS will be enabled */
1390 pci_request_acs();
1391 }
1392 }
1393
1394 /****************************************************************************
1395 *
1396 * Parsing functions for the AMD IOMMU specific kernel command line
1397 * options.
1398 *
1399 ****************************************************************************/
1400
1401 static int __init parse_amd_iommu_dump(char *str)
1402 {
1403 amd_iommu_dump = true;
1404
1405 return 1;
1406 }
1407
1408 static int __init parse_amd_iommu_options(char *str)
1409 {
1410 for (; *str; ++str) {
1411 if (strncmp(str, "fullflush", 9) == 0)
1412 amd_iommu_unmap_flush = true;
1413 if (strncmp(str, "off", 3) == 0)
1414 amd_iommu_disabled = true;
1415 }
1416
1417 return 1;
1418 }
1419
1420 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1421 __setup("amd_iommu=", parse_amd_iommu_options);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree