arch/arm/mach-tegra/include/mach/io.h

   1 /*
   2  * arch/arm/mach-tegra/include/mach/io.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *      Erik Gilling <konkers@google.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #ifndef __MACH_TEGRA_IO_H
  22 #define __MACH_TEGRA_IO_H
  23
  24 #define IO_SPACE_LIMIT 0xffff
  25
  26 /* On TEGRA, many peripherals are very closely packed in
  27  * two 256MB io windows (that actually only use about 64KB
  28  * at the start of each).
  29  *
  30  * We will just map the first 1MB of each window (to minimize
  31  * pt entries needed) and provide a macro to transform physical
  32  * io addresses to an appropriate void __iomem *.
  33  *
  34  */
  35
  36 #ifdef __ASSEMBLY__
  37 #define IOMEM(x)        (x)
  38 #else
  39 #define IOMEM(x)        ((void __force __iomem *)(x))
  40 #endif
  41
  42 #define IO_IRAM_PHYS    0x40000000
  43 #define IO_IRAM_VIRT    IOMEM(0xFE400000)
  44 #define IO_IRAM_SIZE    SZ_256K
  45
  46 #define IO_CPU_PHYS     0x50040000
  47 #define IO_CPU_VIRT     IOMEM(0xFE000000)
  48 #define IO_CPU_SIZE     SZ_16K
  49
  50 #define IO_PPSB_PHYS    0x60000000
  51 #define IO_PPSB_VIRT    IOMEM(0xFE200000)
  52 #define IO_PPSB_SIZE    SZ_1M
  53
  54 #define IO_APB_PHYS     0x70000000
  55 #define IO_APB_VIRT     IOMEM(0xFE300000)
  56 #define IO_APB_SIZE     SZ_1M
  57
  58 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
  59 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
  60
  61 #define IO_TO_VIRT(n) ( \
  62         IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?           \
  63                 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :     \
  64         IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?             \
  65                 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :       \
  66         IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?             \
  67                 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :       \
  68         IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?           \
  69                 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :     \
  70         NULL)
  71
  72 #ifndef __ASSEMBLER__
  73
  74 #define __arch_ioremap          tegra_ioremap
  75 #define __arch_iounmap          tegra_iounmap
  76
  77 void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
  78 void tegra_iounmap(volatile void __iomem *addr);
  79
  80 #define IO_ADDRESS(n) (IO_TO_VIRT(n))
  81
  82 #ifdef CONFIG_TEGRA_PCI
  83 extern void __iomem *tegra_pcie_io_base;
  84
  85 static inline void __iomem *__io(unsigned long addr)
  86 {
  87         return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
  88 }
  89 #else
  90 static inline void __iomem *__io(unsigned long addr)
  91 {
  92         return (void __iomem *)addr;
  93 }
  94 #endif
  95
  96 #define __io(a)         __io(a)
  97 #define __mem_pci(a)    (a)
  98
  99 #endif
 100
 101 #endif