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mmc: sdhci: Check mrq->cmd in sdhci_tasklet_finish
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / spi_mpc8xxx.c
blob3fc4103eb208dfdb086b0181cbb96e81e0db25c7
1 /*
2 * MPC8xxx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/bug.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/irq.h>
29 #include <linux/device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/platform_device.h>
33 #include <linux/fsl_devices.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/mm.h>
36 #include <linux/mutex.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
41 #include <linux/of_spi.h>
42
43 #include <sysdev/fsl_soc.h>
44 #include <asm/cpm.h>
45 #include <asm/qe.h>
46 #include <asm/irq.h>
47
48 /* CPM1 and CPM2 are mutually exclusive. */
49 #ifdef CONFIG_CPM1
50 #include <asm/cpm1.h>
51 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
52 #else
53 #include <asm/cpm2.h>
54 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
55 #endif
56
57 /* SPI Controller registers */
58 struct mpc8xxx_spi_reg {
59 u8 res1[0x20];
60 __be32 mode;
61 __be32 event;
62 __be32 mask;
63 __be32 command;
64 __be32 transmit;
65 __be32 receive;
66 };
67
68 /* SPI Controller mode register definitions */
69 #define SPMODE_LOOP (1 << 30)
70 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
71 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
72 #define SPMODE_DIV16 (1 << 27)
73 #define SPMODE_REV (1 << 26)
74 #define SPMODE_MS (1 << 25)
75 #define SPMODE_ENABLE (1 << 24)
76 #define SPMODE_LEN(x) ((x) << 20)
77 #define SPMODE_PM(x) ((x) << 16)
78 #define SPMODE_OP (1 << 14)
79 #define SPMODE_CG(x) ((x) << 7)
80
81 /*
82 * Default for SPI Mode:
83 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
84 */
85 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
86 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
87
88 /* SPIE register values */
89 #define SPIE_NE 0x00000200 /* Not empty */
90 #define SPIE_NF 0x00000100 /* Not full */
91
92 /* SPIM register values */
93 #define SPIM_NE 0x00000200 /* Not empty */
94 #define SPIM_NF 0x00000100 /* Not full */
95
96 #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
97 #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
98
99 /* SPCOM register values */
100 #define SPCOM_STR (1 << 23) /* Start transmit */
101
102 #define SPI_PRAM_SIZE 0x100
103 #define SPI_MRBLR ((unsigned int)PAGE_SIZE)
104
105 /* SPI Controller driver's private data. */
106 struct mpc8xxx_spi {
107 struct device *dev;
108 struct mpc8xxx_spi_reg __iomem *base;
109
110 /* rx & tx bufs from the spi_transfer */
111 const void *tx;
112 void *rx;
113
114 int subblock;
115 struct spi_pram __iomem *pram;
116 struct cpm_buf_desc __iomem *tx_bd;
117 struct cpm_buf_desc __iomem *rx_bd;
118
119 struct spi_transfer *xfer_in_progress;
120
121 /* dma addresses for CPM transfers */
122 dma_addr_t tx_dma;
123 dma_addr_t rx_dma;
124 bool map_tx_dma;
125 bool map_rx_dma;
126
127 dma_addr_t dma_dummy_tx;
128 dma_addr_t dma_dummy_rx;
129
130 /* functions to deal with different sized buffers */
131 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
132 u32(*get_tx) (struct mpc8xxx_spi *);
133
134 unsigned int count;
135 unsigned int irq;
136
137 unsigned nsecs; /* (clock cycle time)/2 */
138
139 u32 spibrg; /* SPIBRG input clock */
140 u32 rx_shift; /* RX data reg shift when in qe mode */
141 u32 tx_shift; /* TX data reg shift when in qe mode */
142
143 unsigned int flags;
144
145 struct workqueue_struct *workqueue;
146 struct work_struct work;
147
148 struct list_head queue;
149 spinlock_t lock;
150
151 struct completion done;
152 };
153
154 static void *mpc8xxx_dummy_rx;
155 static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
156 static int mpc8xxx_dummy_rx_refcnt;
157
158 struct spi_mpc8xxx_cs {
159 /* functions to deal with different sized buffers */
160 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
161 u32 (*get_tx) (struct mpc8xxx_spi *);
162 u32 rx_shift; /* RX data reg shift when in qe mode */
163 u32 tx_shift; /* TX data reg shift when in qe mode */
164 u32 hw_mode; /* Holds HW mode register settings */
165 };
166
167 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
168 {
169 out_be32(reg, val);
170 }
171
172 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
173 {
174 return in_be32(reg);
175 }
176
177 #define MPC83XX_SPI_RX_BUF(type) \
178 static \
179 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
180 { \
181 type *rx = mpc8xxx_spi->rx; \
182 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
183 mpc8xxx_spi->rx = rx; \
184 }
185
186 #define MPC83XX_SPI_TX_BUF(type) \
187 static \
188 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
189 { \
190 u32 data; \
191 const type *tx = mpc8xxx_spi->tx; \
192 if (!tx) \
193 return 0; \
194 data = *tx++ << mpc8xxx_spi->tx_shift; \
195 mpc8xxx_spi->tx = tx; \
196 return data; \
197 }
198
199 MPC83XX_SPI_RX_BUF(u8)
200 MPC83XX_SPI_RX_BUF(u16)
201 MPC83XX_SPI_RX_BUF(u32)
202 MPC83XX_SPI_TX_BUF(u8)
203 MPC83XX_SPI_TX_BUF(u16)
204 MPC83XX_SPI_TX_BUF(u32)
205
206 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
207 {
208 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
209 struct spi_mpc8xxx_cs *cs = spi->controller_state;
210 __be32 __iomem *mode = &mspi->base->mode;
211 unsigned long flags;
212
213 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
214 return;
215
216 /* Turn off IRQs locally to minimize time that SPI is disabled. */
217 local_irq_save(flags);
218
219 /* Turn off SPI unit prior changing mode */
220 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
221 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
222
223 /* When in CPM mode, we need to reinit tx and rx. */
224 if (mspi->flags & SPI_CPM_MODE) {
225 if (mspi->flags & SPI_QE) {
226 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
227 QE_CR_PROTOCOL_UNSPECIFIED, 0);
228 } else {
229 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
230 if (mspi->flags & SPI_CPM1) {
231 out_be16(&mspi->pram->rbptr,
232 in_be16(&mspi->pram->rbase));
233 out_be16(&mspi->pram->tbptr,
234 in_be16(&mspi->pram->tbase));
235 }
236 }
237 }
238
239 local_irq_restore(flags);
240 }
241
242 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
243 {
244 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
245 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
246 bool pol = spi->mode & SPI_CS_HIGH;
247 struct spi_mpc8xxx_cs *cs = spi->controller_state;
248
249 if (value == BITBANG_CS_INACTIVE) {
250 if (pdata->cs_control)
251 pdata->cs_control(spi, !pol);
252 }
253
254 if (value == BITBANG_CS_ACTIVE) {
255 mpc8xxx_spi->rx_shift = cs->rx_shift;
256 mpc8xxx_spi->tx_shift = cs->tx_shift;
257 mpc8xxx_spi->get_rx = cs->get_rx;
258 mpc8xxx_spi->get_tx = cs->get_tx;
259
260 mpc8xxx_spi_change_mode(spi);
261
262 if (pdata->cs_control)
263 pdata->cs_control(spi, pol);
264 }
265 }
266
267 static
268 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
269 {
270 struct mpc8xxx_spi *mpc8xxx_spi;
271 u8 bits_per_word, pm;
272 u32 hz;
273 struct spi_mpc8xxx_cs *cs = spi->controller_state;
274
275 mpc8xxx_spi = spi_master_get_devdata(spi->master);
276
277 if (t) {
278 bits_per_word = t->bits_per_word;
279 hz = t->speed_hz;
280 } else {
281 bits_per_word = 0;
282 hz = 0;
283 }
284
285 /* spi_transfer level calls that work per-word */
286 if (!bits_per_word)
287 bits_per_word = spi->bits_per_word;
288
289 /* Make sure its a bit width we support [4..16, 32] */
290 if ((bits_per_word < 4)
291 || ((bits_per_word > 16) && (bits_per_word != 32)))
292 return -EINVAL;
293
294 if (!hz)
295 hz = spi->max_speed_hz;
296
297 cs->rx_shift = 0;
298 cs->tx_shift = 0;
299 if (bits_per_word <= 8) {
300 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
301 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
302 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
303 cs->rx_shift = 16;
304 cs->tx_shift = 24;
305 }
306 } else if (bits_per_word <= 16) {
307 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
308 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
309 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
310 cs->rx_shift = 16;
311 cs->tx_shift = 16;
312 }
313 } else if (bits_per_word <= 32) {
314 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
315 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
316 } else
317 return -EINVAL;
318
319 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
320 spi->mode & SPI_LSB_FIRST) {
321 cs->tx_shift = 0;
322 if (bits_per_word <= 8)
323 cs->rx_shift = 8;
324 else
325 cs->rx_shift = 0;
326 }
327
328 mpc8xxx_spi->rx_shift = cs->rx_shift;
329 mpc8xxx_spi->tx_shift = cs->tx_shift;
330 mpc8xxx_spi->get_rx = cs->get_rx;
331 mpc8xxx_spi->get_tx = cs->get_tx;
332
333 if (bits_per_word == 32)
334 bits_per_word = 0;
335 else
336 bits_per_word = bits_per_word - 1;
337
338 /* mask out bits we are going to set */
339 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
340 | SPMODE_PM(0xF));
341
342 cs->hw_mode |= SPMODE_LEN(bits_per_word);
343
344 if ((mpc8xxx_spi->spibrg / hz) > 64) {
345 cs->hw_mode |= SPMODE_DIV16;
346 pm = mpc8xxx_spi->spibrg / (hz * 64);
347
348 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
349 "Will use %d Hz instead.\n", dev_name(&spi->dev),
350 hz, mpc8xxx_spi->spibrg / 1024);
351 if (pm > 16)
352 pm = 16;
353 } else
354 pm = mpc8xxx_spi->spibrg / (hz * 4);
355 if (pm)
356 pm--;
357
358 cs->hw_mode |= SPMODE_PM(pm);
359
360 mpc8xxx_spi_change_mode(spi);
361 return 0;
362 }
363
364 static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
365 {
366 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
367 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
368 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
369 unsigned int xfer_ofs;
370
371 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
372
373 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
374 out_be16(&rx_bd->cbd_datlen, 0);
375 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
376
377 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
378 out_be16(&tx_bd->cbd_datlen, xfer_len);
379 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
380 BD_SC_LAST);
381
382 /* start transfer */
383 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
384 }
385
386 static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
387 struct spi_transfer *t, bool is_dma_mapped)
388 {
389 struct device *dev = mspi->dev;
390
391 if (is_dma_mapped) {
392 mspi->map_tx_dma = 0;
393 mspi->map_rx_dma = 0;
394 } else {
395 mspi->map_tx_dma = 1;
396 mspi->map_rx_dma = 1;
397 }
398
399 if (!t->tx_buf) {
400 mspi->tx_dma = mspi->dma_dummy_tx;
401 mspi->map_tx_dma = 0;
402 }
403
404 if (!t->rx_buf) {
405 mspi->rx_dma = mspi->dma_dummy_rx;
406 mspi->map_rx_dma = 0;
407 }
408
409 if (mspi->map_tx_dma) {
410 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
411
412 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
413 DMA_TO_DEVICE);
414 if (dma_mapping_error(dev, mspi->tx_dma)) {
415 dev_err(dev, "unable to map tx dma\n");
416 return -ENOMEM;
417 }
418 } else {
419 mspi->tx_dma = t->tx_dma;
420 }
421
422 if (mspi->map_rx_dma) {
423 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
424 DMA_FROM_DEVICE);
425 if (dma_mapping_error(dev, mspi->rx_dma)) {
426 dev_err(dev, "unable to map rx dma\n");
427 goto err_rx_dma;
428 }
429 } else {
430 mspi->rx_dma = t->rx_dma;
431 }
432
433 /* enable rx ints */
434 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
435
436 mspi->xfer_in_progress = t;
437 mspi->count = t->len;
438
439 /* start CPM transfers */
440 mpc8xxx_spi_cpm_bufs_start(mspi);
441
442 return 0;
443
444 err_rx_dma:
445 if (mspi->map_tx_dma)
446 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
447 return -ENOMEM;
448 }
449
450 static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
451 {
452 struct device *dev = mspi->dev;
453 struct spi_transfer *t = mspi->xfer_in_progress;
454
455 if (mspi->map_tx_dma)
456 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
457 if (mspi->map_tx_dma)
458 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
459 mspi->xfer_in_progress = NULL;
460 }
461
462 static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
463 struct spi_transfer *t, unsigned int len)
464 {
465 u32 word;
466
467 mspi->count = len;
468
469 /* enable rx ints */
470 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
471
472 /* transmit word */
473 word = mspi->get_tx(mspi);
474 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
475
476 return 0;
477 }
478
479 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
480 bool is_dma_mapped)
481 {
482 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
483 unsigned int len = t->len;
484 u8 bits_per_word;
485 int ret;
486
487 bits_per_word = spi->bits_per_word;
488 if (t->bits_per_word)
489 bits_per_word = t->bits_per_word;
490
491 if (bits_per_word > 8) {
492 /* invalid length? */
493 if (len & 1)
494 return -EINVAL;
495 len /= 2;
496 }
497 if (bits_per_word > 16) {
498 /* invalid length? */
499 if (len & 1)
500 return -EINVAL;
501 len /= 2;
502 }
503
504 mpc8xxx_spi->tx = t->tx_buf;
505 mpc8xxx_spi->rx = t->rx_buf;
506
507 INIT_COMPLETION(mpc8xxx_spi->done);
508
509 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
510 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
511 else
512 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
513 if (ret)
514 return ret;
515
516 wait_for_completion(&mpc8xxx_spi->done);
517
518 /* disable rx ints */
519 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
520
521 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
522 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
523
524 return mpc8xxx_spi->count;
525 }
526
527 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
528 {
529 struct spi_device *spi = m->spi;
530 struct spi_transfer *t;
531 unsigned int cs_change;
532 const int nsecs = 50;
533 int status;
534
535 cs_change = 1;
536 status = 0;
537 list_for_each_entry(t, &m->transfers, transfer_list) {
538 if (t->bits_per_word || t->speed_hz) {
539 /* Don't allow changes if CS is active */
540 status = -EINVAL;
541
542 if (cs_change)
543 status = mpc8xxx_spi_setup_transfer(spi, t);
544 if (status < 0)
545 break;
546 }
547
548 if (cs_change) {
549 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
550 ndelay(nsecs);
551 }
552 cs_change = t->cs_change;
553 if (t->len)
554 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
555 if (status) {
556 status = -EMSGSIZE;
557 break;
558 }
559 m->actual_length += t->len;
560
561 if (t->delay_usecs)
562 udelay(t->delay_usecs);
563
564 if (cs_change) {
565 ndelay(nsecs);
566 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
567 ndelay(nsecs);
568 }
569 }
570
571 m->status = status;
572 m->complete(m->context);
573
574 if (status || !cs_change) {
575 ndelay(nsecs);
576 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
577 }
578
579 mpc8xxx_spi_setup_transfer(spi, NULL);
580 }
581
582 static void mpc8xxx_spi_work(struct work_struct *work)
583 {
584 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
585 work);
586
587 spin_lock_irq(&mpc8xxx_spi->lock);
588 while (!list_empty(&mpc8xxx_spi->queue)) {
589 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
590 struct spi_message, queue);
591
592 list_del_init(&m->queue);
593 spin_unlock_irq(&mpc8xxx_spi->lock);
594
595 mpc8xxx_spi_do_one_msg(m);
596
597 spin_lock_irq(&mpc8xxx_spi->lock);
598 }
599 spin_unlock_irq(&mpc8xxx_spi->lock);
600 }
601
602 static int mpc8xxx_spi_setup(struct spi_device *spi)
603 {
604 struct mpc8xxx_spi *mpc8xxx_spi;
605 int retval;
606 u32 hw_mode;
607 struct spi_mpc8xxx_cs *cs = spi->controller_state;
608
609 if (!spi->max_speed_hz)
610 return -EINVAL;
611
612 if (!cs) {
613 cs = kzalloc(sizeof *cs, GFP_KERNEL);
614 if (!cs)
615 return -ENOMEM;
616 spi->controller_state = cs;
617 }
618 mpc8xxx_spi = spi_master_get_devdata(spi->master);
619
620 hw_mode = cs->hw_mode; /* Save orginal settings */
621 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
622 /* mask out bits we are going to set */
623 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
624 | SPMODE_REV | SPMODE_LOOP);
625
626 if (spi->mode & SPI_CPHA)
627 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
628 if (spi->mode & SPI_CPOL)
629 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
630 if (!(spi->mode & SPI_LSB_FIRST))
631 cs->hw_mode |= SPMODE_REV;
632 if (spi->mode & SPI_LOOP)
633 cs->hw_mode |= SPMODE_LOOP;
634
635 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
636 if (retval < 0) {
637 cs->hw_mode = hw_mode; /* Restore settings */
638 return retval;
639 }
640 return 0;
641 }
642
643 static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
644 {
645 u16 len;
646
647 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
648 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
649
650 len = in_be16(&mspi->rx_bd->cbd_datlen);
651 if (len > mspi->count) {
652 WARN_ON(1);
653 len = mspi->count;
654 }
655
656 /* Clear the events */
657 mpc8xxx_spi_write_reg(&mspi->base->event, events);
658
659 mspi->count -= len;
660 if (mspi->count)
661 mpc8xxx_spi_cpm_bufs_start(mspi);
662 else
663 complete(&mspi->done);
664 }
665
666 static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
667 {
668 /* We need handle RX first */
669 if (events & SPIE_NE) {
670 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
671
672 if (mspi->rx)
673 mspi->get_rx(rx_data, mspi);
674 }
675
676 if ((events & SPIE_NF) == 0)
677 /* spin until TX is done */
678 while (((events =
679 mpc8xxx_spi_read_reg(&mspi->base->event)) &
680 SPIE_NF) == 0)
681 cpu_relax();
682
683 /* Clear the events */
684 mpc8xxx_spi_write_reg(&mspi->base->event, events);
685
686 mspi->count -= 1;
687 if (mspi->count) {
688 u32 word = mspi->get_tx(mspi);
689
690 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
691 } else {
692 complete(&mspi->done);
693 }
694 }
695
696 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
697 {
698 struct mpc8xxx_spi *mspi = context_data;
699 irqreturn_t ret = IRQ_NONE;
700 u32 events;
701
702 /* Get interrupt events(tx/rx) */
703 events = mpc8xxx_spi_read_reg(&mspi->base->event);
704 if (events)
705 ret = IRQ_HANDLED;
706
707 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
708
709 if (mspi->flags & SPI_CPM_MODE)
710 mpc8xxx_spi_cpm_irq(mspi, events);
711 else
712 mpc8xxx_spi_cpu_irq(mspi, events);
713
714 return ret;
715 }
716
717 static int mpc8xxx_spi_transfer(struct spi_device *spi,
718 struct spi_message *m)
719 {
720 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
721 unsigned long flags;
722
723 m->actual_length = 0;
724 m->status = -EINPROGRESS;
725
726 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
727 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
728 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
729 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
730
731 return 0;
732 }
733
734
735 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
736 {
737 kfree(spi->controller_state);
738 }
739
740 static void *mpc8xxx_spi_alloc_dummy_rx(void)
741 {
742 mutex_lock(&mpc8xxx_dummy_rx_lock);
743
744 if (!mpc8xxx_dummy_rx)
745 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
746 if (mpc8xxx_dummy_rx)
747 mpc8xxx_dummy_rx_refcnt++;
748
749 mutex_unlock(&mpc8xxx_dummy_rx_lock);
750
751 return mpc8xxx_dummy_rx;
752 }
753
754 static void mpc8xxx_spi_free_dummy_rx(void)
755 {
756 mutex_lock(&mpc8xxx_dummy_rx_lock);
757
758 switch (mpc8xxx_dummy_rx_refcnt) {
759 case 0:
760 WARN_ON(1);
761 break;
762 case 1:
763 kfree(mpc8xxx_dummy_rx);
764 mpc8xxx_dummy_rx = NULL;
765 /* fall through */
766 default:
767 mpc8xxx_dummy_rx_refcnt--;
768 break;
769 }
770
771 mutex_unlock(&mpc8xxx_dummy_rx_lock);
772 }
773
774 static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
775 {
776 struct device *dev = mspi->dev;
777 struct device_node *np = dev_archdata_get_node(&dev->archdata);
778 const u32 *iprop;
779 int size;
780 unsigned long spi_base_ofs;
781 unsigned long pram_ofs = -ENOMEM;
782
783 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
784 iprop = of_get_property(np, "reg", &size);
785
786 /* QE with a fixed pram location? */
787 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
788 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
789
790 /* QE but with a dynamic pram location? */
791 if (mspi->flags & SPI_QE) {
792 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
793 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
794 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
795 return pram_ofs;
796 }
797
798 /* CPM1 and CPM2 pram must be at a fixed addr. */
799 if (!iprop || size != sizeof(*iprop) * 4)
800 return -ENOMEM;
801
802 spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
803 if (IS_ERR_VALUE(spi_base_ofs))
804 return -ENOMEM;
805
806 if (mspi->flags & SPI_CPM2) {
807 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
808 if (!IS_ERR_VALUE(pram_ofs)) {
809 u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
810
811 out_be16(spi_base, pram_ofs);
812 }
813 } else {
814 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
815 u16 rpbase = in_be16(&pram->rpbase);
816
817 /* Microcode relocation patch applied? */
818 if (rpbase)
819 pram_ofs = rpbase;
820 else
821 return spi_base_ofs;
822 }
823
824 cpm_muram_free(spi_base_ofs);
825 return pram_ofs;
826 }
827
828 static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
829 {
830 struct device *dev = mspi->dev;
831 struct device_node *np = dev_archdata_get_node(&dev->archdata);
832 const u32 *iprop;
833 int size;
834 unsigned long pram_ofs;
835 unsigned long bds_ofs;
836
837 if (!(mspi->flags & SPI_CPM_MODE))
838 return 0;
839
840 if (!mpc8xxx_spi_alloc_dummy_rx())
841 return -ENOMEM;
842
843 if (mspi->flags & SPI_QE) {
844 iprop = of_get_property(np, "cell-index", &size);
845 if (iprop && size == sizeof(*iprop))
846 mspi->subblock = *iprop;
847
848 switch (mspi->subblock) {
849 default:
850 dev_warn(dev, "cell-index unspecified, assuming SPI1");
851 /* fall through */
852 case 0:
853 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
854 break;
855 case 1:
856 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
857 break;
858 }
859 }
860
861 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
862 if (IS_ERR_VALUE(pram_ofs)) {
863 dev_err(dev, "can't allocate spi parameter ram\n");
864 goto err_pram;
865 }
866
867 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
868 sizeof(*mspi->rx_bd), 8);
869 if (IS_ERR_VALUE(bds_ofs)) {
870 dev_err(dev, "can't allocate bds\n");
871 goto err_bds;
872 }
873
874 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
875 DMA_TO_DEVICE);
876 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
877 dev_err(dev, "unable to map dummy tx buffer\n");
878 goto err_dummy_tx;
879 }
880
881 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
882 DMA_FROM_DEVICE);
883 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
884 dev_err(dev, "unable to map dummy rx buffer\n");
885 goto err_dummy_rx;
886 }
887
888 mspi->pram = cpm_muram_addr(pram_ofs);
889
890 mspi->tx_bd = cpm_muram_addr(bds_ofs);
891 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
892
893 /* Initialize parameter ram. */
894 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
895 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
896 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
897 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
898 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
899 out_be32(&mspi->pram->rstate, 0);
900 out_be32(&mspi->pram->rdp, 0);
901 out_be16(&mspi->pram->rbptr, 0);
902 out_be16(&mspi->pram->rbc, 0);
903 out_be32(&mspi->pram->rxtmp, 0);
904 out_be32(&mspi->pram->tstate, 0);
905 out_be32(&mspi->pram->tdp, 0);
906 out_be16(&mspi->pram->tbptr, 0);
907 out_be16(&mspi->pram->tbc, 0);
908 out_be32(&mspi->pram->txtmp, 0);
909
910 return 0;
911
912 err_dummy_rx:
913 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
914 err_dummy_tx:
915 cpm_muram_free(bds_ofs);
916 err_bds:
917 cpm_muram_free(pram_ofs);
918 err_pram:
919 mpc8xxx_spi_free_dummy_rx();
920 return -ENOMEM;
921 }
922
923 static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
924 {
925 struct device *dev = mspi->dev;
926
927 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
928 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
929 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
930 cpm_muram_free(cpm_muram_offset(mspi->pram));
931 mpc8xxx_spi_free_dummy_rx();
932 }
933
934 static const char *mpc8xxx_spi_strmode(unsigned int flags)
935 {
936 if (flags & SPI_QE_CPU_MODE) {
937 return "QE CPU";
938 } else if (flags & SPI_CPM_MODE) {
939 if (flags & SPI_QE)
940 return "QE";
941 else if (flags & SPI_CPM2)
942 return "CPM2";
943 else
944 return "CPM1";
945 }
946 return "CPU";
947 }
948
949 static struct spi_master * __devinit
950 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
951 {
952 struct fsl_spi_platform_data *pdata = dev->platform_data;
953 struct spi_master *master;
954 struct mpc8xxx_spi *mpc8xxx_spi;
955 u32 regval;
956 int ret = 0;
957
958 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
959 if (master == NULL) {
960 ret = -ENOMEM;
961 goto err;
962 }
963
964 dev_set_drvdata(dev, master);
965
966 /* the spi->mode bits understood by this driver: */
967 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
968 | SPI_LSB_FIRST | SPI_LOOP;
969
970 master->setup = mpc8xxx_spi_setup;
971 master->transfer = mpc8xxx_spi_transfer;
972 master->cleanup = mpc8xxx_spi_cleanup;
973
974 mpc8xxx_spi = spi_master_get_devdata(master);
975 mpc8xxx_spi->dev = dev;
976 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
977 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
978 mpc8xxx_spi->flags = pdata->flags;
979 mpc8xxx_spi->spibrg = pdata->sysclk;
980
981 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
982 if (ret)
983 goto err_cpm_init;
984
985 mpc8xxx_spi->rx_shift = 0;
986 mpc8xxx_spi->tx_shift = 0;
987 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
988 mpc8xxx_spi->rx_shift = 16;
989 mpc8xxx_spi->tx_shift = 24;
990 }
991
992 init_completion(&mpc8xxx_spi->done);
993
994 mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
995 if (mpc8xxx_spi->base == NULL) {
996 ret = -ENOMEM;
997 goto err_ioremap;
998 }
999
1000 mpc8xxx_spi->irq = irq;
1001
1002 /* Register for SPI Interrupt */
1003 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1004 0, "mpc8xxx_spi", mpc8xxx_spi);
1005
1006 if (ret != 0)
1007 goto unmap_io;
1008
1009 master->bus_num = pdata->bus_num;
1010 master->num_chipselect = pdata->max_chipselect;
1011
1012 /* SPI controller initializations */
1013 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1014 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1015 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1016 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
1017
1018 /* Enable SPI interface */
1019 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1020 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1021 regval |= SPMODE_OP;
1022
1023 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1024 spin_lock_init(&mpc8xxx_spi->lock);
1025 init_completion(&mpc8xxx_spi->done);
1026 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1027 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1028
1029 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1030 dev_name(master->dev.parent));
1031 if (mpc8xxx_spi->workqueue == NULL) {
1032 ret = -EBUSY;
1033 goto free_irq;
1034 }
1035
1036 ret = spi_register_master(master);
1037 if (ret < 0)
1038 goto unreg_master;
1039
1040 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1041 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1042
1043 return master;
1044
1045 unreg_master:
1046 destroy_workqueue(mpc8xxx_spi->workqueue);
1047 free_irq:
1048 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1049 unmap_io:
1050 iounmap(mpc8xxx_spi->base);
1051 err_ioremap:
1052 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1053 err_cpm_init:
1054 spi_master_put(master);
1055 err:
1056 return ERR_PTR(ret);
1057 }
1058
1059 static int __devexit mpc8xxx_spi_remove(struct device *dev)
1060 {
1061 struct mpc8xxx_spi *mpc8xxx_spi;
1062 struct spi_master *master;
1063
1064 master = dev_get_drvdata(dev);
1065 mpc8xxx_spi = spi_master_get_devdata(master);
1066
1067 flush_workqueue(mpc8xxx_spi->workqueue);
1068 destroy_workqueue(mpc8xxx_spi->workqueue);
1069 spi_unregister_master(master);
1070
1071 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1072 iounmap(mpc8xxx_spi->base);
1073 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1074
1075 return 0;
1076 }
1077
1078 struct mpc8xxx_spi_probe_info {
1079 struct fsl_spi_platform_data pdata;
1080 int *gpios;
1081 bool *alow_flags;
1082 };
1083
1084 static struct mpc8xxx_spi_probe_info *
1085 to_of_pinfo(struct fsl_spi_platform_data *pdata)
1086 {
1087 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1088 }
1089
1090 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1091 {
1092 struct device *dev = spi->dev.parent;
1093 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
1094 u16 cs = spi->chip_select;
1095 int gpio = pinfo->gpios[cs];
1096 bool alow = pinfo->alow_flags[cs];
1097
1098 gpio_set_value(gpio, on ^ alow);
1099 }
1100
1101 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1102 {
1103 struct device_node *np = dev_archdata_get_node(&dev->archdata);
1104 struct fsl_spi_platform_data *pdata = dev->platform_data;
1105 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1106 unsigned int ngpios;
1107 int i = 0;
1108 int ret;
1109
1110 ngpios = of_gpio_count(np);
1111 if (!ngpios) {
1112 /*
1113 * SPI w/o chip-select line. One SPI device is still permitted
1114 * though.
1115 */
1116 pdata->max_chipselect = 1;
1117 return 0;
1118 }
1119
1120 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
1121 if (!pinfo->gpios)
1122 return -ENOMEM;
1123 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
1124
1125 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
1126 GFP_KERNEL);
1127 if (!pinfo->alow_flags) {
1128 ret = -ENOMEM;
1129 goto err_alloc_flags;
1130 }
1131
1132 for (; i < ngpios; i++) {
1133 int gpio;
1134 enum of_gpio_flags flags;
1135
1136 gpio = of_get_gpio_flags(np, i, &flags);
1137 if (!gpio_is_valid(gpio)) {
1138 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
1139 ret = gpio;
1140 goto err_loop;
1141 }
1142
1143 ret = gpio_request(gpio, dev_name(dev));
1144 if (ret) {
1145 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1146 goto err_loop;
1147 }
1148
1149 pinfo->gpios[i] = gpio;
1150 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1151
1152 ret = gpio_direction_output(pinfo->gpios[i],
1153 pinfo->alow_flags[i]);
1154 if (ret) {
1155 dev_err(dev, "can't set output direction for gpio "
1156 "#%d: %d\n", i, ret);
1157 goto err_loop;
1158 }
1159 }
1160
1161 pdata->max_chipselect = ngpios;
1162 pdata->cs_control = mpc8xxx_spi_cs_control;
1163
1164 return 0;
1165
1166 err_loop:
1167 while (i >= 0) {
1168 if (gpio_is_valid(pinfo->gpios[i]))
1169 gpio_free(pinfo->gpios[i]);
1170 i--;
1171 }
1172
1173 kfree(pinfo->alow_flags);
1174 pinfo->alow_flags = NULL;
1175 err_alloc_flags:
1176 kfree(pinfo->gpios);
1177 pinfo->gpios = NULL;
1178 return ret;
1179 }
1180
1181 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1182 {
1183 struct fsl_spi_platform_data *pdata = dev->platform_data;
1184 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1185 int i;
1186
1187 if (!pinfo->gpios)
1188 return 0;
1189
1190 for (i = 0; i < pdata->max_chipselect; i++) {
1191 if (gpio_is_valid(pinfo->gpios[i]))
1192 gpio_free(pinfo->gpios[i]);
1193 }
1194
1195 kfree(pinfo->gpios);
1196 kfree(pinfo->alow_flags);
1197 return 0;
1198 }
1199
1200 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
1201 const struct of_device_id *ofid)
1202 {
1203 struct device *dev = &ofdev->dev;
1204 struct device_node *np = ofdev->node;
1205 struct mpc8xxx_spi_probe_info *pinfo;
1206 struct fsl_spi_platform_data *pdata;
1207 struct spi_master *master;
1208 struct resource mem;
1209 struct resource irq;
1210 const void *prop;
1211 int ret = -ENOMEM;
1212
1213 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1214 if (!pinfo)
1215 return -ENOMEM;
1216
1217 pdata = &pinfo->pdata;
1218 dev->platform_data = pdata;
1219
1220 /* Allocate bus num dynamically. */
1221 pdata->bus_num = -1;
1222
1223 /* SPI controller is either clocked from QE or SoC clock. */
1224 pdata->sysclk = get_brgfreq();
1225 if (pdata->sysclk == -1) {
1226 pdata->sysclk = fsl_get_sys_freq();
1227 if (pdata->sysclk == -1) {
1228 ret = -ENODEV;
1229 goto err_clk;
1230 }
1231 }
1232
1233 prop = of_get_property(np, "mode", NULL);
1234 if (prop && !strcmp(prop, "cpu-qe"))
1235 pdata->flags = SPI_QE_CPU_MODE;
1236 else if (prop && !strcmp(prop, "qe"))
1237 pdata->flags = SPI_CPM_MODE | SPI_QE;
1238 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1239 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1240 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1241 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1242
1243 ret = of_mpc8xxx_spi_get_chipselects(dev);
1244 if (ret)
1245 goto err;
1246
1247 ret = of_address_to_resource(np, 0, &mem);
1248 if (ret)
1249 goto err;
1250
1251 ret = of_irq_to_resource(np, 0, &irq);
1252 if (!ret) {
1253 ret = -EINVAL;
1254 goto err;
1255 }
1256
1257 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1258 if (IS_ERR(master)) {
1259 ret = PTR_ERR(master);
1260 goto err;
1261 }
1262
1263 of_register_spi_devices(master, np);
1264
1265 return 0;
1266
1267 err:
1268 of_mpc8xxx_spi_free_chipselects(dev);
1269 err_clk:
1270 kfree(pinfo);
1271 return ret;
1272 }
1273
1274 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
1275 {
1276 int ret;
1277
1278 ret = mpc8xxx_spi_remove(&ofdev->dev);
1279 if (ret)
1280 return ret;
1281 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1282 return 0;
1283 }
1284
1285 static const struct of_device_id of_mpc8xxx_spi_match[] = {
1286 { .compatible = "fsl,spi" },
1287 {},
1288 };
1289 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1290
1291 static struct of_platform_driver of_mpc8xxx_spi_driver = {
1292 .name = "mpc8xxx_spi",
1293 .match_table = of_mpc8xxx_spi_match,
1294 .probe = of_mpc8xxx_spi_probe,
1295 .remove = __devexit_p(of_mpc8xxx_spi_remove),
1296 };
1297
1298 #ifdef CONFIG_MPC832x_RDB
1299 /*
1300 * XXX XXX XXX
1301 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1302 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1303 * tree can work with OpenFirmware driver. But for now we support old trees
1304 * as well.
1305 */
1306 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1307 {
1308 struct resource *mem;
1309 unsigned int irq;
1310 struct spi_master *master;
1311
1312 if (!pdev->dev.platform_data)
1313 return -EINVAL;
1314
1315 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316 if (!mem)
1317 return -EINVAL;
1318
1319 irq = platform_get_irq(pdev, 0);
1320 if (!irq)
1321 return -EINVAL;
1322
1323 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1324 if (IS_ERR(master))
1325 return PTR_ERR(master);
1326 return 0;
1327 }
1328
1329 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1330 {
1331 return mpc8xxx_spi_remove(&pdev->dev);
1332 }
1333
1334 MODULE_ALIAS("platform:mpc8xxx_spi");
1335 static struct platform_driver mpc8xxx_spi_driver = {
1336 .probe = plat_mpc8xxx_spi_probe,
1337 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
1338 .driver = {
1339 .name = "mpc8xxx_spi",
1340 .owner = THIS_MODULE,
1341 },
1342 };
1343
1344 static bool legacy_driver_failed;
1345
1346 static void __init legacy_driver_register(void)
1347 {
1348 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1349 }
1350
1351 static void __exit legacy_driver_unregister(void)
1352 {
1353 if (legacy_driver_failed)
1354 return;
1355 platform_driver_unregister(&mpc8xxx_spi_driver);
1356 }
1357 #else
1358 static void __init legacy_driver_register(void) {}
1359 static void __exit legacy_driver_unregister(void) {}
1360 #endif /* CONFIG_MPC832x_RDB */
1361
1362 static int __init mpc8xxx_spi_init(void)
1363 {
1364 legacy_driver_register();
1365 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1366 }
1367
1368 static void __exit mpc8xxx_spi_exit(void)
1369 {
1370 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1371 legacy_driver_unregister();
1372 }
1373
1374 module_init(mpc8xxx_spi_init);
1375 module_exit(mpc8xxx_spi_exit);
1376
1377 MODULE_AUTHOR("Kumar Gala");
1378 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1379 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree