2 * File: arch/blackfin/mach-bf561/acvilon.c
3 * Based on: arch/blackfin/mach-bf561/ezkit.c
10 * Copyright 2004-2006 Analog Devices Inc.
11 * Copyright 2009 CJSC "NII STT"
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * For more information about Acvilon BF561 SoM please
32 * go to http://www.niistt.ru/
36 #include <linux/device.h>
37 #include <linux/platform_device.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/mtd/physmap.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/plat-ram.h>
43 #include <linux/spi/spi.h>
44 #include <linux/spi/flash.h>
45 #include <linux/irq.h>
46 #include <linux/interrupt.h>
47 #include <linux/i2c-pca-platform.h>
48 #include <linux/delay.h>
51 #include <asm/bfin5xx_spi.h>
52 #include <asm/portmux.h>
54 #include <asm/cacheflush.h>
55 #include <linux/i2c.h>
58 * Name the Board for the /proc/cpuinfo
60 const char bfin_board_name
[] = "Acvilon board";
62 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
63 #include <linux/usb/isp1760.h>
64 static struct resource bfin_isp1760_resources
[] = {
67 .end
= 0x20000000 + 0x000fffff,
68 .flags
= IORESOURCE_MEM
,
73 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_LOWLEVEL
,
77 static struct isp1760_platform_data isp1760_priv
= {
83 .dack_polarity_high
= 0,
84 .dreq_polarity_high
= 0,
87 static struct platform_device bfin_isp1760_device
= {
88 .name
= "isp1760-hcd",
91 .platform_data
= &isp1760_priv
,
93 .num_resources
= ARRAY_SIZE(bfin_isp1760_resources
),
94 .resource
= bfin_isp1760_resources
,
98 static struct resource bfin_i2c_pca_resources
[] = {
100 .name
= "pca9564-regs",
102 .end
= 0x2C000000 + 16,
103 .flags
= IORESOURCE_MEM
| IORESOURCE_MEM_32BIT
,
108 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_LOWLEVEL
,
112 struct i2c_pca9564_pf_platform_data pca9564_platform_data
= {
114 .i2c_clock_speed
= 330000,
118 /* PCA9564 I2C Bus driver */
119 static struct platform_device bfin_i2c_pca_device
= {
120 .name
= "i2c-pca-platform",
122 .num_resources
= ARRAY_SIZE(bfin_i2c_pca_resources
),
123 .resource
= bfin_i2c_pca_resources
,
125 .platform_data
= &pca9564_platform_data
,
129 /* I2C devices fitted. */
130 static struct i2c_board_info acvilon_i2c_devs
[] __initdata
= {
132 I2C_BOARD_INFO("ds1339", 0x68),
135 I2C_BOARD_INFO("tcn75", 0x49),
139 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
140 static struct platdata_mtd_ram mtd_ram_data
= {
141 .mapname
= "rootfs(RAM)",
145 static struct resource mtd_ram_resource
= {
148 .flags
= IORESOURCE_MEM
,
151 static struct platform_device mtd_ram_device
= {
155 .platform_data
= &mtd_ram_data
,
158 .resource
= &mtd_ram_resource
,
162 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
163 #include <linux/smsc911x.h>
164 static struct resource smsc911x_resources
[] = {
166 .name
= "smsc911x-memory",
168 .end
= 0x28000000 + 0xFF,
169 .flags
= IORESOURCE_MEM
,
174 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_LOWLEVEL
,
178 static struct smsc911x_platform_config smsc911x_config
= {
179 .flags
= SMSC911X_USE_32BIT
| SMSC911X_SAVE_MAC_ADDRESS
,
180 .irq_polarity
= SMSC911X_IRQ_POLARITY_ACTIVE_LOW
,
181 .irq_type
= SMSC911X_IRQ_TYPE_OPEN_DRAIN
,
182 .phy_interface
= PHY_INTERFACE_MODE_MII
,
185 static struct platform_device smsc911x_device
= {
188 .num_resources
= ARRAY_SIZE(smsc911x_resources
),
189 .resource
= smsc911x_resources
,
191 .platform_data
= &smsc911x_config
,
196 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
197 #ifdef CONFIG_SERIAL_BFIN_UART0
198 static struct resource bfin_uart0_resources
[] = {
200 .start
= BFIN_UART_THR
,
201 .end
= BFIN_UART_GCTL
+ 2,
202 .flags
= IORESOURCE_MEM
,
205 .start
= IRQ_UART_RX
,
206 .end
= IRQ_UART_RX
+ 1,
207 .flags
= IORESOURCE_IRQ
,
210 .start
= IRQ_UART_ERROR
,
211 .end
= IRQ_UART_ERROR
,
212 .flags
= IORESOURCE_IRQ
,
217 .flags
= IORESOURCE_DMA
,
222 .flags
= IORESOURCE_DMA
,
226 unsigned short bfin_uart0_peripherals
[] = {
227 P_UART0_TX
, P_UART0_RX
, 0
230 static struct platform_device bfin_uart0_device
= {
233 .num_resources
= ARRAY_SIZE(bfin_uart0_resources
),
234 .resource
= bfin_uart0_resources
,
236 /* Passed to driver */
237 .platform_data
= &bfin_uart0_peripherals
,
243 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
245 #ifdef CONFIG_MTD_PARTITIONS
246 const char *part_probes
[] = { "cmdlinepart", NULL
};
248 static struct mtd_partition bfin_plat_nand_partitions
[] = {
250 .name
= "params(nand)",
251 .size
= 32 * 1024 * 1024,
254 .name
= "userfs(nand)",
255 .size
= MTDPART_SIZ_FULL
,
256 .offset
= MTDPART_OFS_APPEND
,
261 #define BFIN_NAND_PLAT_CLE 2
262 #define BFIN_NAND_PLAT_ALE 3
264 static void bfin_plat_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
267 struct nand_chip
*this = mtd
->priv
;
269 if (cmd
== NAND_CMD_NONE
)
273 writeb(cmd
, this->IO_ADDR_W
+ (1 << BFIN_NAND_PLAT_CLE
));
275 writeb(cmd
, this->IO_ADDR_W
+ (1 << BFIN_NAND_PLAT_ALE
));
278 #define BFIN_NAND_PLAT_READY GPIO_PF10
279 static int bfin_plat_nand_dev_ready(struct mtd_info
*mtd
)
281 return gpio_get_value(BFIN_NAND_PLAT_READY
);
284 static struct platform_nand_data bfin_plat_nand_data
= {
288 #ifdef CONFIG_MTD_PARTITIONS
289 .part_probe_types
= part_probes
,
290 .partitions
= bfin_plat_nand_partitions
,
291 .nr_partitions
= ARRAY_SIZE(bfin_plat_nand_partitions
),
295 .cmd_ctrl
= bfin_plat_nand_cmd_ctrl
,
296 .dev_ready
= bfin_plat_nand_dev_ready
,
300 #define MAX(x, y) (x > y ? x : y)
301 static struct resource bfin_plat_nand_resources
= {
303 .end
= 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE
, BFIN_NAND_PLAT_ALE
)),
304 .flags
= IORESOURCE_IO
,
307 static struct platform_device bfin_async_nand_device
= {
311 .resource
= &bfin_plat_nand_resources
,
313 .platform_data
= &bfin_plat_nand_data
,
317 static void bfin_plat_nand_init(void)
319 gpio_request(BFIN_NAND_PLAT_READY
, "bfin_nand_plat");
322 static void bfin_plat_nand_init(void)
327 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
328 static struct mtd_partition bfin_spi_dataflash_partitions
[] = {
330 .name
= "bootloader",
333 .mask_flags
= MTD_CAP_ROM
},
337 .offset
= MTDPART_OFS_APPEND
,
340 .name
= "u-boot(params)",
342 .offset
= MTDPART_OFS_APPEND
,
347 .offset
= MTDPART_OFS_APPEND
,
352 .offset
= MTDPART_OFS_APPEND
,
356 .size
= MTDPART_SIZ_FULL
,
357 .offset
= MTDPART_OFS_APPEND
,
361 static struct flash_platform_data bfin_spi_dataflash_data
= {
362 .name
= "SPI Dataflash",
363 .parts
= bfin_spi_dataflash_partitions
,
364 .nr_parts
= ARRAY_SIZE(bfin_spi_dataflash_partitions
),
368 static struct bfin5xx_spi_chip data_flash_chip_info
= {
369 .enable_dma
= 0, /* use dma transfer with this chip */
374 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
375 static struct bfin5xx_spi_chip spidev_chip_info
= {
381 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
383 static struct resource bfin_spi0_resource
[] = {
385 .start
= SPI0_REGBASE
,
386 .end
= SPI0_REGBASE
+ 0xFF,
387 .flags
= IORESOURCE_MEM
,
392 .flags
= IORESOURCE_DMA
,
397 .flags
= IORESOURCE_IRQ
,
401 /* SPI controller data */
402 static struct bfin5xx_spi_master bfin_spi0_info
= {
404 .enable_dma
= 1, /* master has the ability to do dma transfer */
405 .pin_req
= {P_SPI0_SCK
, P_SPI0_MISO
, P_SPI0_MOSI
, 0},
408 static struct platform_device bfin_spi0_device
= {
410 .id
= 0, /* Bus number */
411 .num_resources
= ARRAY_SIZE(bfin_spi0_resource
),
412 .resource
= bfin_spi0_resource
,
414 .platform_data
= &bfin_spi0_info
, /* Passed to driver */
419 static struct spi_board_info bfin_spi_board_info
[] __initdata
= {
420 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
422 .modalias
= "spidev",
423 .max_speed_hz
= 3125000, /* max spi clock (SCK) speed in HZ */
426 .controller_data
= &spidev_chip_info
,
429 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
430 { /* DataFlash chip */
431 .modalias
= "mtd_dataflash",
432 .max_speed_hz
= 33250000, /* max spi clock (SCK) speed in HZ */
433 .bus_num
= 0, /* Framework bus number */
434 .chip_select
= 2, /* Framework chip select */
435 .platform_data
= &bfin_spi_dataflash_data
,
436 .controller_data
= &data_flash_chip_info
,
442 static struct resource bfin_gpios_resources
= {
444 /* .end = MAX_BLACKFIN_GPIOS - 1, */
446 .flags
= IORESOURCE_IRQ
,
449 static struct platform_device bfin_gpios_device
= {
450 .name
= "simple-gpio",
453 .resource
= &bfin_gpios_resources
,
456 static const unsigned int cclk_vlev_datasheet
[] = {
457 VRPAIR(VLEV_085
, 250000000),
458 VRPAIR(VLEV_090
, 300000000),
459 VRPAIR(VLEV_095
, 313000000),
460 VRPAIR(VLEV_100
, 350000000),
461 VRPAIR(VLEV_105
, 400000000),
462 VRPAIR(VLEV_110
, 444000000),
463 VRPAIR(VLEV_115
, 450000000),
464 VRPAIR(VLEV_120
, 475000000),
465 VRPAIR(VLEV_125
, 500000000),
466 VRPAIR(VLEV_130
, 600000000),
469 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data
= {
470 .tuple_tab
= cclk_vlev_datasheet
,
471 .tabsize
= ARRAY_SIZE(cclk_vlev_datasheet
),
472 .vr_settling_time
= 25 /* us */ ,
475 static struct platform_device bfin_dpmc
= {
478 .platform_data
= &bfin_dmpc_vreg_data
,
482 static struct platform_device
*acvilon_devices
[] __initdata
= {
485 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
489 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
490 #ifdef CONFIG_SERIAL_BFIN_UART0
497 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
501 &bfin_i2c_pca_device
,
503 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
504 &bfin_async_nand_device
,
507 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
513 static int __init
acvilon_init(void)
517 printk(KERN_INFO
"%s(): registering device resources\n", __func__
);
519 bfin_plat_nand_init();
521 platform_add_devices(acvilon_devices
, ARRAY_SIZE(acvilon_devices
));
525 i2c_register_board_info(0, acvilon_i2c_devs
,
526 ARRAY_SIZE(acvilon_i2c_devs
));
528 bfin_write_FIO0_FLAG_C(1 << 14);
530 bfin_write_FIO0_FLAG_S(1 << 14);
532 spi_register_board_info(bfin_spi_board_info
,
533 ARRAY_SIZE(bfin_spi_board_info
));
537 arch_initcall(acvilon_init
);
539 static struct platform_device
*acvilon_early_devices
[] __initdata
= {
540 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
541 #ifdef CONFIG_SERIAL_BFIN_UART0
547 void __init
native_machine_early_platform_add_devices(void)
549 printk(KERN_INFO
"register early platform devices\n");
550 early_platform_add_devices(acvilon_early_devices
,
551 ARRAY_SIZE(acvilon_early_devices
));