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drm/radeon/kms: fix num_banks tiling config for fusion
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
blob12d2fdc52414463d42cdc0ecb2a66f0b7e1e76e2
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
45 {
46 /* enable the pflip int */
47 radeon_irq_kms_pflip_irq_get(rdev, crtc);
48 }
49
50 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
51 {
52 /* disable the pflip int */
53 radeon_irq_kms_pflip_irq_put(rdev, crtc);
54 }
55
56 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
57 {
58 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
59 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
60
61 /* Lock the graphics update lock */
62 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
63 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
64
65 /* update the scanout addresses */
66 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
67 upper_32_bits(crtc_base));
68 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
69 (u32)crtc_base);
70
71 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
72 upper_32_bits(crtc_base));
73 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
74 (u32)crtc_base);
75
76 /* Wait for update_pending to go high. */
77 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
79
80 /* Unlock the lock, so double-buffering can take place inside vblank */
81 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
82 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
83
84 /* Return current update_pending status: */
85 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
86 }
87
88 /* get temperature in millidegrees */
89 int evergreen_get_temp(struct radeon_device *rdev)
90 {
91 u32 temp, toffset;
92 int actual_temp = 0;
93
94 if (rdev->family == CHIP_JUNIPER) {
95 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
96 TOFFSET_SHIFT;
97 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
98 TS0_ADC_DOUT_SHIFT;
99
100 if (toffset & 0x100)
101 actual_temp = temp / 2 - (0x200 - toffset);
102 else
103 actual_temp = temp / 2 + toffset;
104
105 actual_temp = actual_temp * 1000;
106
107 } else {
108 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
109 ASIC_T_SHIFT;
110
111 if (temp & 0x400)
112 actual_temp = -256;
113 else if (temp & 0x200)
114 actual_temp = 255;
115 else if (temp & 0x100) {
116 actual_temp = temp & 0x1ff;
117 actual_temp |= ~0x1ff;
118 } else
119 actual_temp = temp & 0xff;
120
121 actual_temp = (actual_temp * 1000) / 2;
122 }
123
124 return actual_temp;
125 }
126
127 int sumo_get_temp(struct radeon_device *rdev)
128 {
129 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
130 int actual_temp = temp - 49;
131
132 return actual_temp * 1000;
133 }
134
135 void evergreen_pm_misc(struct radeon_device *rdev)
136 {
137 int req_ps_idx = rdev->pm.requested_power_state_index;
138 int req_cm_idx = rdev->pm.requested_clock_mode_index;
139 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
140 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
141
142 if (voltage->type == VOLTAGE_SW) {
143 /* 0xff01 is a flag rather then an actual voltage */
144 if (voltage->voltage == 0xff01)
145 return;
146 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
147 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
148 rdev->pm.current_vddc = voltage->voltage;
149 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
150 }
151 /* 0xff01 is a flag rather then an actual voltage */
152 if (voltage->vddci == 0xff01)
153 return;
154 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
155 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
156 rdev->pm.current_vddci = voltage->vddci;
157 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
158 }
159 }
160 }
161
162 void evergreen_pm_prepare(struct radeon_device *rdev)
163 {
164 struct drm_device *ddev = rdev->ddev;
165 struct drm_crtc *crtc;
166 struct radeon_crtc *radeon_crtc;
167 u32 tmp;
168
169 /* disable any active CRTCs */
170 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
171 radeon_crtc = to_radeon_crtc(crtc);
172 if (radeon_crtc->enabled) {
173 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
174 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
175 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
176 }
177 }
178 }
179
180 void evergreen_pm_finish(struct radeon_device *rdev)
181 {
182 struct drm_device *ddev = rdev->ddev;
183 struct drm_crtc *crtc;
184 struct radeon_crtc *radeon_crtc;
185 u32 tmp;
186
187 /* enable any active CRTCs */
188 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
189 radeon_crtc = to_radeon_crtc(crtc);
190 if (radeon_crtc->enabled) {
191 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
192 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
193 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
194 }
195 }
196 }
197
198 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
199 {
200 bool connected = false;
201
202 switch (hpd) {
203 case RADEON_HPD_1:
204 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
205 connected = true;
206 break;
207 case RADEON_HPD_2:
208 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
209 connected = true;
210 break;
211 case RADEON_HPD_3:
212 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
213 connected = true;
214 break;
215 case RADEON_HPD_4:
216 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
217 connected = true;
218 break;
219 case RADEON_HPD_5:
220 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
221 connected = true;
222 break;
223 case RADEON_HPD_6:
224 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
225 connected = true;
226 break;
227 default:
228 break;
229 }
230
231 return connected;
232 }
233
234 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
235 enum radeon_hpd_id hpd)
236 {
237 u32 tmp;
238 bool connected = evergreen_hpd_sense(rdev, hpd);
239
240 switch (hpd) {
241 case RADEON_HPD_1:
242 tmp = RREG32(DC_HPD1_INT_CONTROL);
243 if (connected)
244 tmp &= ~DC_HPDx_INT_POLARITY;
245 else
246 tmp |= DC_HPDx_INT_POLARITY;
247 WREG32(DC_HPD1_INT_CONTROL, tmp);
248 break;
249 case RADEON_HPD_2:
250 tmp = RREG32(DC_HPD2_INT_CONTROL);
251 if (connected)
252 tmp &= ~DC_HPDx_INT_POLARITY;
253 else
254 tmp |= DC_HPDx_INT_POLARITY;
255 WREG32(DC_HPD2_INT_CONTROL, tmp);
256 break;
257 case RADEON_HPD_3:
258 tmp = RREG32(DC_HPD3_INT_CONTROL);
259 if (connected)
260 tmp &= ~DC_HPDx_INT_POLARITY;
261 else
262 tmp |= DC_HPDx_INT_POLARITY;
263 WREG32(DC_HPD3_INT_CONTROL, tmp);
264 break;
265 case RADEON_HPD_4:
266 tmp = RREG32(DC_HPD4_INT_CONTROL);
267 if (connected)
268 tmp &= ~DC_HPDx_INT_POLARITY;
269 else
270 tmp |= DC_HPDx_INT_POLARITY;
271 WREG32(DC_HPD4_INT_CONTROL, tmp);
272 break;
273 case RADEON_HPD_5:
274 tmp = RREG32(DC_HPD5_INT_CONTROL);
275 if (connected)
276 tmp &= ~DC_HPDx_INT_POLARITY;
277 else
278 tmp |= DC_HPDx_INT_POLARITY;
279 WREG32(DC_HPD5_INT_CONTROL, tmp);
280 break;
281 case RADEON_HPD_6:
282 tmp = RREG32(DC_HPD6_INT_CONTROL);
283 if (connected)
284 tmp &= ~DC_HPDx_INT_POLARITY;
285 else
286 tmp |= DC_HPDx_INT_POLARITY;
287 WREG32(DC_HPD6_INT_CONTROL, tmp);
288 break;
289 default:
290 break;
291 }
292 }
293
294 void evergreen_hpd_init(struct radeon_device *rdev)
295 {
296 struct drm_device *dev = rdev->ddev;
297 struct drm_connector *connector;
298 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
299 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
300
301 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
302 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
303 switch (radeon_connector->hpd.hpd) {
304 case RADEON_HPD_1:
305 WREG32(DC_HPD1_CONTROL, tmp);
306 rdev->irq.hpd[0] = true;
307 break;
308 case RADEON_HPD_2:
309 WREG32(DC_HPD2_CONTROL, tmp);
310 rdev->irq.hpd[1] = true;
311 break;
312 case RADEON_HPD_3:
313 WREG32(DC_HPD3_CONTROL, tmp);
314 rdev->irq.hpd[2] = true;
315 break;
316 case RADEON_HPD_4:
317 WREG32(DC_HPD4_CONTROL, tmp);
318 rdev->irq.hpd[3] = true;
319 break;
320 case RADEON_HPD_5:
321 WREG32(DC_HPD5_CONTROL, tmp);
322 rdev->irq.hpd[4] = true;
323 break;
324 case RADEON_HPD_6:
325 WREG32(DC_HPD6_CONTROL, tmp);
326 rdev->irq.hpd[5] = true;
327 break;
328 default:
329 break;
330 }
331 }
332 if (rdev->irq.installed)
333 evergreen_irq_set(rdev);
334 }
335
336 void evergreen_hpd_fini(struct radeon_device *rdev)
337 {
338 struct drm_device *dev = rdev->ddev;
339 struct drm_connector *connector;
340
341 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
342 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
343 switch (radeon_connector->hpd.hpd) {
344 case RADEON_HPD_1:
345 WREG32(DC_HPD1_CONTROL, 0);
346 rdev->irq.hpd[0] = false;
347 break;
348 case RADEON_HPD_2:
349 WREG32(DC_HPD2_CONTROL, 0);
350 rdev->irq.hpd[1] = false;
351 break;
352 case RADEON_HPD_3:
353 WREG32(DC_HPD3_CONTROL, 0);
354 rdev->irq.hpd[2] = false;
355 break;
356 case RADEON_HPD_4:
357 WREG32(DC_HPD4_CONTROL, 0);
358 rdev->irq.hpd[3] = false;
359 break;
360 case RADEON_HPD_5:
361 WREG32(DC_HPD5_CONTROL, 0);
362 rdev->irq.hpd[4] = false;
363 break;
364 case RADEON_HPD_6:
365 WREG32(DC_HPD6_CONTROL, 0);
366 rdev->irq.hpd[5] = false;
367 break;
368 default:
369 break;
370 }
371 }
372 }
373
374 /* watermark setup */
375
376 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
377 struct radeon_crtc *radeon_crtc,
378 struct drm_display_mode *mode,
379 struct drm_display_mode *other_mode)
380 {
381 u32 tmp;
382 /*
383 * Line Buffer Setup
384 * There are 3 line buffers, each one shared by 2 display controllers.
385 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
386 * the display controllers. The paritioning is done via one of four
387 * preset allocations specified in bits 2:0:
388 * first display controller
389 * 0 - first half of lb (3840 * 2)
390 * 1 - first 3/4 of lb (5760 * 2)
391 * 2 - whole lb (7680 * 2), other crtc must be disabled
392 * 3 - first 1/4 of lb (1920 * 2)
393 * second display controller
394 * 4 - second half of lb (3840 * 2)
395 * 5 - second 3/4 of lb (5760 * 2)
396 * 6 - whole lb (7680 * 2), other crtc must be disabled
397 * 7 - last 1/4 of lb (1920 * 2)
398 */
399 /* this can get tricky if we have two large displays on a paired group
400 * of crtcs. Ideally for multiple large displays we'd assign them to
401 * non-linked crtcs for maximum line buffer allocation.
402 */
403 if (radeon_crtc->base.enabled && mode) {
404 if (other_mode)
405 tmp = 0; /* 1/2 */
406 else
407 tmp = 2; /* whole */
408 } else
409 tmp = 0;
410
411 /* second controller of the pair uses second half of the lb */
412 if (radeon_crtc->crtc_id % 2)
413 tmp += 4;
414 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
415
416 if (radeon_crtc->base.enabled && mode) {
417 switch (tmp) {
418 case 0:
419 case 4:
420 default:
421 if (ASIC_IS_DCE5(rdev))
422 return 4096 * 2;
423 else
424 return 3840 * 2;
425 case 1:
426 case 5:
427 if (ASIC_IS_DCE5(rdev))
428 return 6144 * 2;
429 else
430 return 5760 * 2;
431 case 2:
432 case 6:
433 if (ASIC_IS_DCE5(rdev))
434 return 8192 * 2;
435 else
436 return 7680 * 2;
437 case 3:
438 case 7:
439 if (ASIC_IS_DCE5(rdev))
440 return 2048 * 2;
441 else
442 return 1920 * 2;
443 }
444 }
445
446 /* controller not enabled, so no lb used */
447 return 0;
448 }
449
450 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
451 {
452 u32 tmp = RREG32(MC_SHARED_CHMAP);
453
454 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
455 case 0:
456 default:
457 return 1;
458 case 1:
459 return 2;
460 case 2:
461 return 4;
462 case 3:
463 return 8;
464 }
465 }
466
467 struct evergreen_wm_params {
468 u32 dram_channels; /* number of dram channels */
469 u32 yclk; /* bandwidth per dram data pin in kHz */
470 u32 sclk; /* engine clock in kHz */
471 u32 disp_clk; /* display clock in kHz */
472 u32 src_width; /* viewport width */
473 u32 active_time; /* active display time in ns */
474 u32 blank_time; /* blank time in ns */
475 bool interlaced; /* mode is interlaced */
476 fixed20_12 vsc; /* vertical scale ratio */
477 u32 num_heads; /* number of active crtcs */
478 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
479 u32 lb_size; /* line buffer allocated to pipe */
480 u32 vtaps; /* vertical scaler taps */
481 };
482
483 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
484 {
485 /* Calculate DRAM Bandwidth and the part allocated to display. */
486 fixed20_12 dram_efficiency; /* 0.7 */
487 fixed20_12 yclk, dram_channels, bandwidth;
488 fixed20_12 a;
489
490 a.full = dfixed_const(1000);
491 yclk.full = dfixed_const(wm->yclk);
492 yclk.full = dfixed_div(yclk, a);
493 dram_channels.full = dfixed_const(wm->dram_channels * 4);
494 a.full = dfixed_const(10);
495 dram_efficiency.full = dfixed_const(7);
496 dram_efficiency.full = dfixed_div(dram_efficiency, a);
497 bandwidth.full = dfixed_mul(dram_channels, yclk);
498 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
499
500 return dfixed_trunc(bandwidth);
501 }
502
503 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
504 {
505 /* Calculate DRAM Bandwidth and the part allocated to display. */
506 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
507 fixed20_12 yclk, dram_channels, bandwidth;
508 fixed20_12 a;
509
510 a.full = dfixed_const(1000);
511 yclk.full = dfixed_const(wm->yclk);
512 yclk.full = dfixed_div(yclk, a);
513 dram_channels.full = dfixed_const(wm->dram_channels * 4);
514 a.full = dfixed_const(10);
515 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
516 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
517 bandwidth.full = dfixed_mul(dram_channels, yclk);
518 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
519
520 return dfixed_trunc(bandwidth);
521 }
522
523 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
524 {
525 /* Calculate the display Data return Bandwidth */
526 fixed20_12 return_efficiency; /* 0.8 */
527 fixed20_12 sclk, bandwidth;
528 fixed20_12 a;
529
530 a.full = dfixed_const(1000);
531 sclk.full = dfixed_const(wm->sclk);
532 sclk.full = dfixed_div(sclk, a);
533 a.full = dfixed_const(10);
534 return_efficiency.full = dfixed_const(8);
535 return_efficiency.full = dfixed_div(return_efficiency, a);
536 a.full = dfixed_const(32);
537 bandwidth.full = dfixed_mul(a, sclk);
538 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
539
540 return dfixed_trunc(bandwidth);
541 }
542
543 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
544 {
545 /* Calculate the DMIF Request Bandwidth */
546 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
547 fixed20_12 disp_clk, bandwidth;
548 fixed20_12 a;
549
550 a.full = dfixed_const(1000);
551 disp_clk.full = dfixed_const(wm->disp_clk);
552 disp_clk.full = dfixed_div(disp_clk, a);
553 a.full = dfixed_const(10);
554 disp_clk_request_efficiency.full = dfixed_const(8);
555 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
556 a.full = dfixed_const(32);
557 bandwidth.full = dfixed_mul(a, disp_clk);
558 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
559
560 return dfixed_trunc(bandwidth);
561 }
562
563 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
564 {
565 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
566 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
567 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
568 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
569
570 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
571 }
572
573 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
574 {
575 /* Calculate the display mode Average Bandwidth
576 * DisplayMode should contain the source and destination dimensions,
577 * timing, etc.
578 */
579 fixed20_12 bpp;
580 fixed20_12 line_time;
581 fixed20_12 src_width;
582 fixed20_12 bandwidth;
583 fixed20_12 a;
584
585 a.full = dfixed_const(1000);
586 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
587 line_time.full = dfixed_div(line_time, a);
588 bpp.full = dfixed_const(wm->bytes_per_pixel);
589 src_width.full = dfixed_const(wm->src_width);
590 bandwidth.full = dfixed_mul(src_width, bpp);
591 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
592 bandwidth.full = dfixed_div(bandwidth, line_time);
593
594 return dfixed_trunc(bandwidth);
595 }
596
597 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
598 {
599 /* First calcualte the latency in ns */
600 u32 mc_latency = 2000; /* 2000 ns. */
601 u32 available_bandwidth = evergreen_available_bandwidth(wm);
602 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
603 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
604 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
605 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
606 (wm->num_heads * cursor_line_pair_return_time);
607 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
608 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
609 fixed20_12 a, b, c;
610
611 if (wm->num_heads == 0)
612 return 0;
613
614 a.full = dfixed_const(2);
615 b.full = dfixed_const(1);
616 if ((wm->vsc.full > a.full) ||
617 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
618 (wm->vtaps >= 5) ||
619 ((wm->vsc.full >= a.full) && wm->interlaced))
620 max_src_lines_per_dst_line = 4;
621 else
622 max_src_lines_per_dst_line = 2;
623
624 a.full = dfixed_const(available_bandwidth);
625 b.full = dfixed_const(wm->num_heads);
626 a.full = dfixed_div(a, b);
627
628 b.full = dfixed_const(1000);
629 c.full = dfixed_const(wm->disp_clk);
630 b.full = dfixed_div(c, b);
631 c.full = dfixed_const(wm->bytes_per_pixel);
632 b.full = dfixed_mul(b, c);
633
634 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
635
636 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
637 b.full = dfixed_const(1000);
638 c.full = dfixed_const(lb_fill_bw);
639 b.full = dfixed_div(c, b);
640 a.full = dfixed_div(a, b);
641 line_fill_time = dfixed_trunc(a);
642
643 if (line_fill_time < wm->active_time)
644 return latency;
645 else
646 return latency + (line_fill_time - wm->active_time);
647
648 }
649
650 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
651 {
652 if (evergreen_average_bandwidth(wm) <=
653 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
654 return true;
655 else
656 return false;
657 };
658
659 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
660 {
661 if (evergreen_average_bandwidth(wm) <=
662 (evergreen_available_bandwidth(wm) / wm->num_heads))
663 return true;
664 else
665 return false;
666 };
667
668 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
669 {
670 u32 lb_partitions = wm->lb_size / wm->src_width;
671 u32 line_time = wm->active_time + wm->blank_time;
672 u32 latency_tolerant_lines;
673 u32 latency_hiding;
674 fixed20_12 a;
675
676 a.full = dfixed_const(1);
677 if (wm->vsc.full > a.full)
678 latency_tolerant_lines = 1;
679 else {
680 if (lb_partitions <= (wm->vtaps + 1))
681 latency_tolerant_lines = 1;
682 else
683 latency_tolerant_lines = 2;
684 }
685
686 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
687
688 if (evergreen_latency_watermark(wm) <= latency_hiding)
689 return true;
690 else
691 return false;
692 }
693
694 static void evergreen_program_watermarks(struct radeon_device *rdev,
695 struct radeon_crtc *radeon_crtc,
696 u32 lb_size, u32 num_heads)
697 {
698 struct drm_display_mode *mode = &radeon_crtc->base.mode;
699 struct evergreen_wm_params wm;
700 u32 pixel_period;
701 u32 line_time = 0;
702 u32 latency_watermark_a = 0, latency_watermark_b = 0;
703 u32 priority_a_mark = 0, priority_b_mark = 0;
704 u32 priority_a_cnt = PRIORITY_OFF;
705 u32 priority_b_cnt = PRIORITY_OFF;
706 u32 pipe_offset = radeon_crtc->crtc_id * 16;
707 u32 tmp, arb_control3;
708 fixed20_12 a, b, c;
709
710 if (radeon_crtc->base.enabled && num_heads && mode) {
711 pixel_period = 1000000 / (u32)mode->clock;
712 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
713 priority_a_cnt = 0;
714 priority_b_cnt = 0;
715
716 wm.yclk = rdev->pm.current_mclk * 10;
717 wm.sclk = rdev->pm.current_sclk * 10;
718 wm.disp_clk = mode->clock;
719 wm.src_width = mode->crtc_hdisplay;
720 wm.active_time = mode->crtc_hdisplay * pixel_period;
721 wm.blank_time = line_time - wm.active_time;
722 wm.interlaced = false;
723 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
724 wm.interlaced = true;
725 wm.vsc = radeon_crtc->vsc;
726 wm.vtaps = 1;
727 if (radeon_crtc->rmx_type != RMX_OFF)
728 wm.vtaps = 2;
729 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
730 wm.lb_size = lb_size;
731 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
732 wm.num_heads = num_heads;
733
734 /* set for high clocks */
735 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
736 /* set for low clocks */
737 /* wm.yclk = low clk; wm.sclk = low clk */
738 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
739
740 /* possibly force display priority to high */
741 /* should really do this at mode validation time... */
742 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
743 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
744 !evergreen_check_latency_hiding(&wm) ||
745 (rdev->disp_priority == 2)) {
746 DRM_INFO("force priority to high\n");
747 priority_a_cnt |= PRIORITY_ALWAYS_ON;
748 priority_b_cnt |= PRIORITY_ALWAYS_ON;
749 }
750
751 a.full = dfixed_const(1000);
752 b.full = dfixed_const(mode->clock);
753 b.full = dfixed_div(b, a);
754 c.full = dfixed_const(latency_watermark_a);
755 c.full = dfixed_mul(c, b);
756 c.full = dfixed_mul(c, radeon_crtc->hsc);
757 c.full = dfixed_div(c, a);
758 a.full = dfixed_const(16);
759 c.full = dfixed_div(c, a);
760 priority_a_mark = dfixed_trunc(c);
761 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
762
763 a.full = dfixed_const(1000);
764 b.full = dfixed_const(mode->clock);
765 b.full = dfixed_div(b, a);
766 c.full = dfixed_const(latency_watermark_b);
767 c.full = dfixed_mul(c, b);
768 c.full = dfixed_mul(c, radeon_crtc->hsc);
769 c.full = dfixed_div(c, a);
770 a.full = dfixed_const(16);
771 c.full = dfixed_div(c, a);
772 priority_b_mark = dfixed_trunc(c);
773 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
774 }
775
776 /* select wm A */
777 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
778 tmp = arb_control3;
779 tmp &= ~LATENCY_WATERMARK_MASK(3);
780 tmp |= LATENCY_WATERMARK_MASK(1);
781 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
782 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
783 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
784 LATENCY_HIGH_WATERMARK(line_time)));
785 /* select wm B */
786 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
787 tmp &= ~LATENCY_WATERMARK_MASK(3);
788 tmp |= LATENCY_WATERMARK_MASK(2);
789 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
790 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
791 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
792 LATENCY_HIGH_WATERMARK(line_time)));
793 /* restore original selection */
794 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
795
796 /* write the priority marks */
797 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
798 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
799
800 }
801
802 void evergreen_bandwidth_update(struct radeon_device *rdev)
803 {
804 struct drm_display_mode *mode0 = NULL;
805 struct drm_display_mode *mode1 = NULL;
806 u32 num_heads = 0, lb_size;
807 int i;
808
809 radeon_update_display_priority(rdev);
810
811 for (i = 0; i < rdev->num_crtc; i++) {
812 if (rdev->mode_info.crtcs[i]->base.enabled)
813 num_heads++;
814 }
815 for (i = 0; i < rdev->num_crtc; i += 2) {
816 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
817 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
818 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
819 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
820 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
821 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
822 }
823 }
824
825 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
826 {
827 unsigned i;
828 u32 tmp;
829
830 for (i = 0; i < rdev->usec_timeout; i++) {
831 /* read MC_STATUS */
832 tmp = RREG32(SRBM_STATUS) & 0x1F00;
833 if (!tmp)
834 return 0;
835 udelay(1);
836 }
837 return -1;
838 }
839
840 /*
841 * GART
842 */
843 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
844 {
845 unsigned i;
846 u32 tmp;
847
848 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
849
850 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
851 for (i = 0; i < rdev->usec_timeout; i++) {
852 /* read MC_STATUS */
853 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
854 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
855 if (tmp == 2) {
856 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
857 return;
858 }
859 if (tmp) {
860 return;
861 }
862 udelay(1);
863 }
864 }
865
866 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
867 {
868 u32 tmp;
869 int r;
870
871 if (rdev->gart.table.vram.robj == NULL) {
872 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
873 return -EINVAL;
874 }
875 r = radeon_gart_table_vram_pin(rdev);
876 if (r)
877 return r;
878 radeon_gart_restore(rdev);
879 /* Setup L2 cache */
880 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
881 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
882 EFFECTIVE_L2_QUEUE_SIZE(7));
883 WREG32(VM_L2_CNTL2, 0);
884 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
885 /* Setup TLB control */
886 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
887 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
888 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
889 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
890 if (rdev->flags & RADEON_IS_IGP) {
891 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
892 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
893 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
894 } else {
895 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
896 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
897 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
898 }
899 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
900 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
901 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
902 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
903 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
904 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
905 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
906 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
907 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
908 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
909 (u32)(rdev->dummy_page.addr >> 12));
910 WREG32(VM_CONTEXT1_CNTL, 0);
911
912 evergreen_pcie_gart_tlb_flush(rdev);
913 rdev->gart.ready = true;
914 return 0;
915 }
916
917 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
918 {
919 u32 tmp;
920 int r;
921
922 /* Disable all tables */
923 WREG32(VM_CONTEXT0_CNTL, 0);
924 WREG32(VM_CONTEXT1_CNTL, 0);
925
926 /* Setup L2 cache */
927 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
928 EFFECTIVE_L2_QUEUE_SIZE(7));
929 WREG32(VM_L2_CNTL2, 0);
930 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
931 /* Setup TLB control */
932 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
933 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
934 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
935 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
936 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
937 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
938 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
939 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
940 if (rdev->gart.table.vram.robj) {
941 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
942 if (likely(r == 0)) {
943 radeon_bo_kunmap(rdev->gart.table.vram.robj);
944 radeon_bo_unpin(rdev->gart.table.vram.robj);
945 radeon_bo_unreserve(rdev->gart.table.vram.robj);
946 }
947 }
948 }
949
950 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
951 {
952 evergreen_pcie_gart_disable(rdev);
953 radeon_gart_table_vram_free(rdev);
954 radeon_gart_fini(rdev);
955 }
956
957
958 void evergreen_agp_enable(struct radeon_device *rdev)
959 {
960 u32 tmp;
961
962 /* Setup L2 cache */
963 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
964 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
965 EFFECTIVE_L2_QUEUE_SIZE(7));
966 WREG32(VM_L2_CNTL2, 0);
967 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
968 /* Setup TLB control */
969 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
970 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
971 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
972 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
973 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
974 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
975 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
976 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
977 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
978 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
979 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
980 WREG32(VM_CONTEXT0_CNTL, 0);
981 WREG32(VM_CONTEXT1_CNTL, 0);
982 }
983
984 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
985 {
986 save->vga_control[0] = RREG32(D1VGA_CONTROL);
987 save->vga_control[1] = RREG32(D2VGA_CONTROL);
988 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
989 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
990 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
991 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
992 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
993 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
994 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
995 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
996 if (!(rdev->flags & RADEON_IS_IGP)) {
997 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
998 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
999 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1000 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1001 }
1002
1003 /* Stop all video */
1004 WREG32(VGA_RENDER_CONTROL, 0);
1005 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1006 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1007 if (!(rdev->flags & RADEON_IS_IGP)) {
1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1009 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1012 }
1013 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1014 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1015 if (!(rdev->flags & RADEON_IS_IGP)) {
1016 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1019 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1020 }
1021 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1022 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1023 if (!(rdev->flags & RADEON_IS_IGP)) {
1024 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1025 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1026 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1028 }
1029
1030 WREG32(D1VGA_CONTROL, 0);
1031 WREG32(D2VGA_CONTROL, 0);
1032 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1033 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1034 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1035 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1036 }
1037
1038 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1039 {
1040 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1041 upper_32_bits(rdev->mc.vram_start));
1042 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1043 upper_32_bits(rdev->mc.vram_start));
1044 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1045 (u32)rdev->mc.vram_start);
1046 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1047 (u32)rdev->mc.vram_start);
1048
1049 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1050 upper_32_bits(rdev->mc.vram_start));
1051 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1052 upper_32_bits(rdev->mc.vram_start));
1053 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1054 (u32)rdev->mc.vram_start);
1055 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1056 (u32)rdev->mc.vram_start);
1057
1058 if (!(rdev->flags & RADEON_IS_IGP)) {
1059 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1060 upper_32_bits(rdev->mc.vram_start));
1061 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1062 upper_32_bits(rdev->mc.vram_start));
1063 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1064 (u32)rdev->mc.vram_start);
1065 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1066 (u32)rdev->mc.vram_start);
1067
1068 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1069 upper_32_bits(rdev->mc.vram_start));
1070 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1071 upper_32_bits(rdev->mc.vram_start));
1072 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1073 (u32)rdev->mc.vram_start);
1074 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1075 (u32)rdev->mc.vram_start);
1076
1077 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1078 upper_32_bits(rdev->mc.vram_start));
1079 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1080 upper_32_bits(rdev->mc.vram_start));
1081 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1082 (u32)rdev->mc.vram_start);
1083 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1084 (u32)rdev->mc.vram_start);
1085
1086 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1087 upper_32_bits(rdev->mc.vram_start));
1088 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1089 upper_32_bits(rdev->mc.vram_start));
1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1091 (u32)rdev->mc.vram_start);
1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1093 (u32)rdev->mc.vram_start);
1094 }
1095
1096 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1097 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1098 /* Unlock host access */
1099 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1100 mdelay(1);
1101 /* Restore video state */
1102 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1103 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1104 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1105 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1106 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1107 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1108 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1109 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1110 if (!(rdev->flags & RADEON_IS_IGP)) {
1111 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1112 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1113 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1114 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1115 }
1116 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1117 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1118 if (!(rdev->flags & RADEON_IS_IGP)) {
1119 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1120 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1121 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1122 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1123 }
1124 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1126 if (!(rdev->flags & RADEON_IS_IGP)) {
1127 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1130 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1131 }
1132 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1133 }
1134
1135 void evergreen_mc_program(struct radeon_device *rdev)
1136 {
1137 struct evergreen_mc_save save;
1138 u32 tmp;
1139 int i, j;
1140
1141 /* Initialize HDP */
1142 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1143 WREG32((0x2c14 + j), 0x00000000);
1144 WREG32((0x2c18 + j), 0x00000000);
1145 WREG32((0x2c1c + j), 0x00000000);
1146 WREG32((0x2c20 + j), 0x00000000);
1147 WREG32((0x2c24 + j), 0x00000000);
1148 }
1149 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1150
1151 evergreen_mc_stop(rdev, &save);
1152 if (evergreen_mc_wait_for_idle(rdev)) {
1153 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1154 }
1155 /* Lockout access through VGA aperture*/
1156 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1157 /* Update configuration */
1158 if (rdev->flags & RADEON_IS_AGP) {
1159 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1160 /* VRAM before AGP */
1161 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1162 rdev->mc.vram_start >> 12);
1163 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1164 rdev->mc.gtt_end >> 12);
1165 } else {
1166 /* VRAM after AGP */
1167 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1168 rdev->mc.gtt_start >> 12);
1169 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1170 rdev->mc.vram_end >> 12);
1171 }
1172 } else {
1173 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1174 rdev->mc.vram_start >> 12);
1175 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1176 rdev->mc.vram_end >> 12);
1177 }
1178 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1179 if (rdev->flags & RADEON_IS_IGP) {
1180 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1181 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1182 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1183 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1184 }
1185 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1186 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1187 WREG32(MC_VM_FB_LOCATION, tmp);
1188 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1189 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1190 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1191 if (rdev->flags & RADEON_IS_AGP) {
1192 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1193 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1194 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1195 } else {
1196 WREG32(MC_VM_AGP_BASE, 0);
1197 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1198 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1199 }
1200 if (evergreen_mc_wait_for_idle(rdev)) {
1201 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1202 }
1203 evergreen_mc_resume(rdev, &save);
1204 /* we need to own VRAM, so turn off the VGA renderer here
1205 * to stop it overwriting our objects */
1206 rv515_vga_render_disable(rdev);
1207 }
1208
1209 /*
1210 * CP.
1211 */
1212 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1213 {
1214 /* set to DX10/11 mode */
1215 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1216 radeon_ring_write(rdev, 1);
1217 /* FIXME: implement */
1218 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1219 radeon_ring_write(rdev,
1220 #ifdef __BIG_ENDIAN
1221 (2 << 0) |
1222 #endif
1223 (ib->gpu_addr & 0xFFFFFFFC));
1224 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1225 radeon_ring_write(rdev, ib->length_dw);
1226 }
1227
1228
1229 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1230 {
1231 const __be32 *fw_data;
1232 int i;
1233
1234 if (!rdev->me_fw || !rdev->pfp_fw)
1235 return -EINVAL;
1236
1237 r700_cp_stop(rdev);
1238 WREG32(CP_RB_CNTL,
1239 #ifdef __BIG_ENDIAN
1240 BUF_SWAP_32BIT |
1241 #endif
1242 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1243
1244 fw_data = (const __be32 *)rdev->pfp_fw->data;
1245 WREG32(CP_PFP_UCODE_ADDR, 0);
1246 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1247 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1248 WREG32(CP_PFP_UCODE_ADDR, 0);
1249
1250 fw_data = (const __be32 *)rdev->me_fw->data;
1251 WREG32(CP_ME_RAM_WADDR, 0);
1252 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1253 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1254
1255 WREG32(CP_PFP_UCODE_ADDR, 0);
1256 WREG32(CP_ME_RAM_WADDR, 0);
1257 WREG32(CP_ME_RAM_RADDR, 0);
1258 return 0;
1259 }
1260
1261 static int evergreen_cp_start(struct radeon_device *rdev)
1262 {
1263 int r, i;
1264 uint32_t cp_me;
1265
1266 r = radeon_ring_lock(rdev, 7);
1267 if (r) {
1268 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1269 return r;
1270 }
1271 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1272 radeon_ring_write(rdev, 0x1);
1273 radeon_ring_write(rdev, 0x0);
1274 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1275 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1276 radeon_ring_write(rdev, 0);
1277 radeon_ring_write(rdev, 0);
1278 radeon_ring_unlock_commit(rdev);
1279
1280 cp_me = 0xff;
1281 WREG32(CP_ME_CNTL, cp_me);
1282
1283 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1284 if (r) {
1285 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1286 return r;
1287 }
1288
1289 /* setup clear context state */
1290 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1291 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1292
1293 for (i = 0; i < evergreen_default_size; i++)
1294 radeon_ring_write(rdev, evergreen_default_state[i]);
1295
1296 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1297 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1298
1299 /* set clear context state */
1300 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1301 radeon_ring_write(rdev, 0);
1302
1303 /* SQ_VTX_BASE_VTX_LOC */
1304 radeon_ring_write(rdev, 0xc0026f00);
1305 radeon_ring_write(rdev, 0x00000000);
1306 radeon_ring_write(rdev, 0x00000000);
1307 radeon_ring_write(rdev, 0x00000000);
1308
1309 /* Clear consts */
1310 radeon_ring_write(rdev, 0xc0036f00);
1311 radeon_ring_write(rdev, 0x00000bc4);
1312 radeon_ring_write(rdev, 0xffffffff);
1313 radeon_ring_write(rdev, 0xffffffff);
1314 radeon_ring_write(rdev, 0xffffffff);
1315
1316 radeon_ring_write(rdev, 0xc0026900);
1317 radeon_ring_write(rdev, 0x00000316);
1318 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1319 radeon_ring_write(rdev, 0x00000010); /* */
1320
1321 radeon_ring_unlock_commit(rdev);
1322
1323 return 0;
1324 }
1325
1326 int evergreen_cp_resume(struct radeon_device *rdev)
1327 {
1328 u32 tmp;
1329 u32 rb_bufsz;
1330 int r;
1331
1332 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1333 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1334 SOFT_RESET_PA |
1335 SOFT_RESET_SH |
1336 SOFT_RESET_VGT |
1337 SOFT_RESET_SX));
1338 RREG32(GRBM_SOFT_RESET);
1339 mdelay(15);
1340 WREG32(GRBM_SOFT_RESET, 0);
1341 RREG32(GRBM_SOFT_RESET);
1342
1343 /* Set ring buffer size */
1344 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1345 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1346 #ifdef __BIG_ENDIAN
1347 tmp |= BUF_SWAP_32BIT;
1348 #endif
1349 WREG32(CP_RB_CNTL, tmp);
1350 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1351
1352 /* Set the write pointer delay */
1353 WREG32(CP_RB_WPTR_DELAY, 0);
1354
1355 /* Initialize the ring buffer's read and write pointers */
1356 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1357 WREG32(CP_RB_RPTR_WR, 0);
1358 WREG32(CP_RB_WPTR, 0);
1359
1360 /* set the wb address wether it's enabled or not */
1361 WREG32(CP_RB_RPTR_ADDR,
1362 #ifdef __BIG_ENDIAN
1363 RB_RPTR_SWAP(2) |
1364 #endif
1365 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1366 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1367 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1368
1369 if (rdev->wb.enabled)
1370 WREG32(SCRATCH_UMSK, 0xff);
1371 else {
1372 tmp |= RB_NO_UPDATE;
1373 WREG32(SCRATCH_UMSK, 0);
1374 }
1375
1376 mdelay(1);
1377 WREG32(CP_RB_CNTL, tmp);
1378
1379 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1380 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1381
1382 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1383 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1384
1385 evergreen_cp_start(rdev);
1386 rdev->cp.ready = true;
1387 r = radeon_ring_test(rdev);
1388 if (r) {
1389 rdev->cp.ready = false;
1390 return r;
1391 }
1392 return 0;
1393 }
1394
1395 /*
1396 * Core functions
1397 */
1398 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1399 u32 num_tile_pipes,
1400 u32 num_backends,
1401 u32 backend_disable_mask)
1402 {
1403 u32 backend_map = 0;
1404 u32 enabled_backends_mask = 0;
1405 u32 enabled_backends_count = 0;
1406 u32 cur_pipe;
1407 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1408 u32 cur_backend = 0;
1409 u32 i;
1410 bool force_no_swizzle;
1411
1412 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1413 num_tile_pipes = EVERGREEN_MAX_PIPES;
1414 if (num_tile_pipes < 1)
1415 num_tile_pipes = 1;
1416 if (num_backends > EVERGREEN_MAX_BACKENDS)
1417 num_backends = EVERGREEN_MAX_BACKENDS;
1418 if (num_backends < 1)
1419 num_backends = 1;
1420
1421 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1422 if (((backend_disable_mask >> i) & 1) == 0) {
1423 enabled_backends_mask |= (1 << i);
1424 ++enabled_backends_count;
1425 }
1426 if (enabled_backends_count == num_backends)
1427 break;
1428 }
1429
1430 if (enabled_backends_count == 0) {
1431 enabled_backends_mask = 1;
1432 enabled_backends_count = 1;
1433 }
1434
1435 if (enabled_backends_count != num_backends)
1436 num_backends = enabled_backends_count;
1437
1438 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1439 switch (rdev->family) {
1440 case CHIP_CEDAR:
1441 case CHIP_REDWOOD:
1442 case CHIP_PALM:
1443 case CHIP_SUMO:
1444 case CHIP_SUMO2:
1445 case CHIP_TURKS:
1446 case CHIP_CAICOS:
1447 force_no_swizzle = false;
1448 break;
1449 case CHIP_CYPRESS:
1450 case CHIP_HEMLOCK:
1451 case CHIP_JUNIPER:
1452 case CHIP_BARTS:
1453 default:
1454 force_no_swizzle = true;
1455 break;
1456 }
1457 if (force_no_swizzle) {
1458 bool last_backend_enabled = false;
1459
1460 force_no_swizzle = false;
1461 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1462 if (((enabled_backends_mask >> i) & 1) == 1) {
1463 if (last_backend_enabled)
1464 force_no_swizzle = true;
1465 last_backend_enabled = true;
1466 } else
1467 last_backend_enabled = false;
1468 }
1469 }
1470
1471 switch (num_tile_pipes) {
1472 case 1:
1473 case 3:
1474 case 5:
1475 case 7:
1476 DRM_ERROR("odd number of pipes!\n");
1477 break;
1478 case 2:
1479 swizzle_pipe[0] = 0;
1480 swizzle_pipe[1] = 1;
1481 break;
1482 case 4:
1483 if (force_no_swizzle) {
1484 swizzle_pipe[0] = 0;
1485 swizzle_pipe[1] = 1;
1486 swizzle_pipe[2] = 2;
1487 swizzle_pipe[3] = 3;
1488 } else {
1489 swizzle_pipe[0] = 0;
1490 swizzle_pipe[1] = 2;
1491 swizzle_pipe[2] = 1;
1492 swizzle_pipe[3] = 3;
1493 }
1494 break;
1495 case 6:
1496 if (force_no_swizzle) {
1497 swizzle_pipe[0] = 0;
1498 swizzle_pipe[1] = 1;
1499 swizzle_pipe[2] = 2;
1500 swizzle_pipe[3] = 3;
1501 swizzle_pipe[4] = 4;
1502 swizzle_pipe[5] = 5;
1503 } else {
1504 swizzle_pipe[0] = 0;
1505 swizzle_pipe[1] = 2;
1506 swizzle_pipe[2] = 4;
1507 swizzle_pipe[3] = 1;
1508 swizzle_pipe[4] = 3;
1509 swizzle_pipe[5] = 5;
1510 }
1511 break;
1512 case 8:
1513 if (force_no_swizzle) {
1514 swizzle_pipe[0] = 0;
1515 swizzle_pipe[1] = 1;
1516 swizzle_pipe[2] = 2;
1517 swizzle_pipe[3] = 3;
1518 swizzle_pipe[4] = 4;
1519 swizzle_pipe[5] = 5;
1520 swizzle_pipe[6] = 6;
1521 swizzle_pipe[7] = 7;
1522 } else {
1523 swizzle_pipe[0] = 0;
1524 swizzle_pipe[1] = 2;
1525 swizzle_pipe[2] = 4;
1526 swizzle_pipe[3] = 6;
1527 swizzle_pipe[4] = 1;
1528 swizzle_pipe[5] = 3;
1529 swizzle_pipe[6] = 5;
1530 swizzle_pipe[7] = 7;
1531 }
1532 break;
1533 }
1534
1535 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1536 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1537 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1538
1539 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1540
1541 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1542 }
1543
1544 return backend_map;
1545 }
1546
1547 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1548 {
1549 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1550
1551 tmp = RREG32(MC_SHARED_CHMAP);
1552 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1553 case 0:
1554 case 1:
1555 case 2:
1556 case 3:
1557 default:
1558 /* default mapping */
1559 mc_shared_chremap = 0x00fac688;
1560 break;
1561 }
1562
1563 switch (rdev->family) {
1564 case CHIP_HEMLOCK:
1565 case CHIP_CYPRESS:
1566 case CHIP_BARTS:
1567 tcp_chan_steer_lo = 0x54763210;
1568 tcp_chan_steer_hi = 0x0000ba98;
1569 break;
1570 case CHIP_JUNIPER:
1571 case CHIP_REDWOOD:
1572 case CHIP_CEDAR:
1573 case CHIP_PALM:
1574 case CHIP_SUMO:
1575 case CHIP_SUMO2:
1576 case CHIP_TURKS:
1577 case CHIP_CAICOS:
1578 default:
1579 tcp_chan_steer_lo = 0x76543210;
1580 tcp_chan_steer_hi = 0x0000ba98;
1581 break;
1582 }
1583
1584 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1585 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1586 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1587 }
1588
1589 static void evergreen_gpu_init(struct radeon_device *rdev)
1590 {
1591 u32 cc_rb_backend_disable = 0;
1592 u32 cc_gc_shader_pipe_config;
1593 u32 gb_addr_config = 0;
1594 u32 mc_shared_chmap, mc_arb_ramcfg;
1595 u32 gb_backend_map;
1596 u32 grbm_gfx_index;
1597 u32 sx_debug_1;
1598 u32 smx_dc_ctl0;
1599 u32 sq_config;
1600 u32 sq_lds_resource_mgmt;
1601 u32 sq_gpr_resource_mgmt_1;
1602 u32 sq_gpr_resource_mgmt_2;
1603 u32 sq_gpr_resource_mgmt_3;
1604 u32 sq_thread_resource_mgmt;
1605 u32 sq_thread_resource_mgmt_2;
1606 u32 sq_stack_resource_mgmt_1;
1607 u32 sq_stack_resource_mgmt_2;
1608 u32 sq_stack_resource_mgmt_3;
1609 u32 vgt_cache_invalidation;
1610 u32 hdp_host_path_cntl, tmp;
1611 int i, j, num_shader_engines, ps_thread_count;
1612
1613 switch (rdev->family) {
1614 case CHIP_CYPRESS:
1615 case CHIP_HEMLOCK:
1616 rdev->config.evergreen.num_ses = 2;
1617 rdev->config.evergreen.max_pipes = 4;
1618 rdev->config.evergreen.max_tile_pipes = 8;
1619 rdev->config.evergreen.max_simds = 10;
1620 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1621 rdev->config.evergreen.max_gprs = 256;
1622 rdev->config.evergreen.max_threads = 248;
1623 rdev->config.evergreen.max_gs_threads = 32;
1624 rdev->config.evergreen.max_stack_entries = 512;
1625 rdev->config.evergreen.sx_num_of_sets = 4;
1626 rdev->config.evergreen.sx_max_export_size = 256;
1627 rdev->config.evergreen.sx_max_export_pos_size = 64;
1628 rdev->config.evergreen.sx_max_export_smx_size = 192;
1629 rdev->config.evergreen.max_hw_contexts = 8;
1630 rdev->config.evergreen.sq_num_cf_insts = 2;
1631
1632 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1633 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1634 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1635 break;
1636 case CHIP_JUNIPER:
1637 rdev->config.evergreen.num_ses = 1;
1638 rdev->config.evergreen.max_pipes = 4;
1639 rdev->config.evergreen.max_tile_pipes = 4;
1640 rdev->config.evergreen.max_simds = 10;
1641 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1642 rdev->config.evergreen.max_gprs = 256;
1643 rdev->config.evergreen.max_threads = 248;
1644 rdev->config.evergreen.max_gs_threads = 32;
1645 rdev->config.evergreen.max_stack_entries = 512;
1646 rdev->config.evergreen.sx_num_of_sets = 4;
1647 rdev->config.evergreen.sx_max_export_size = 256;
1648 rdev->config.evergreen.sx_max_export_pos_size = 64;
1649 rdev->config.evergreen.sx_max_export_smx_size = 192;
1650 rdev->config.evergreen.max_hw_contexts = 8;
1651 rdev->config.evergreen.sq_num_cf_insts = 2;
1652
1653 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1654 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1655 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1656 break;
1657 case CHIP_REDWOOD:
1658 rdev->config.evergreen.num_ses = 1;
1659 rdev->config.evergreen.max_pipes = 4;
1660 rdev->config.evergreen.max_tile_pipes = 4;
1661 rdev->config.evergreen.max_simds = 5;
1662 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1663 rdev->config.evergreen.max_gprs = 256;
1664 rdev->config.evergreen.max_threads = 248;
1665 rdev->config.evergreen.max_gs_threads = 32;
1666 rdev->config.evergreen.max_stack_entries = 256;
1667 rdev->config.evergreen.sx_num_of_sets = 4;
1668 rdev->config.evergreen.sx_max_export_size = 256;
1669 rdev->config.evergreen.sx_max_export_pos_size = 64;
1670 rdev->config.evergreen.sx_max_export_smx_size = 192;
1671 rdev->config.evergreen.max_hw_contexts = 8;
1672 rdev->config.evergreen.sq_num_cf_insts = 2;
1673
1674 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1675 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1676 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1677 break;
1678 case CHIP_CEDAR:
1679 default:
1680 rdev->config.evergreen.num_ses = 1;
1681 rdev->config.evergreen.max_pipes = 2;
1682 rdev->config.evergreen.max_tile_pipes = 2;
1683 rdev->config.evergreen.max_simds = 2;
1684 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1685 rdev->config.evergreen.max_gprs = 256;
1686 rdev->config.evergreen.max_threads = 192;
1687 rdev->config.evergreen.max_gs_threads = 16;
1688 rdev->config.evergreen.max_stack_entries = 256;
1689 rdev->config.evergreen.sx_num_of_sets = 4;
1690 rdev->config.evergreen.sx_max_export_size = 128;
1691 rdev->config.evergreen.sx_max_export_pos_size = 32;
1692 rdev->config.evergreen.sx_max_export_smx_size = 96;
1693 rdev->config.evergreen.max_hw_contexts = 4;
1694 rdev->config.evergreen.sq_num_cf_insts = 1;
1695
1696 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1697 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1698 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1699 break;
1700 case CHIP_PALM:
1701 rdev->config.evergreen.num_ses = 1;
1702 rdev->config.evergreen.max_pipes = 2;
1703 rdev->config.evergreen.max_tile_pipes = 2;
1704 rdev->config.evergreen.max_simds = 2;
1705 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1706 rdev->config.evergreen.max_gprs = 256;
1707 rdev->config.evergreen.max_threads = 192;
1708 rdev->config.evergreen.max_gs_threads = 16;
1709 rdev->config.evergreen.max_stack_entries = 256;
1710 rdev->config.evergreen.sx_num_of_sets = 4;
1711 rdev->config.evergreen.sx_max_export_size = 128;
1712 rdev->config.evergreen.sx_max_export_pos_size = 32;
1713 rdev->config.evergreen.sx_max_export_smx_size = 96;
1714 rdev->config.evergreen.max_hw_contexts = 4;
1715 rdev->config.evergreen.sq_num_cf_insts = 1;
1716
1717 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1718 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1719 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1720 break;
1721 case CHIP_SUMO:
1722 rdev->config.evergreen.num_ses = 1;
1723 rdev->config.evergreen.max_pipes = 4;
1724 rdev->config.evergreen.max_tile_pipes = 2;
1725 if (rdev->pdev->device == 0x9648)
1726 rdev->config.evergreen.max_simds = 3;
1727 else if ((rdev->pdev->device == 0x9647) ||
1728 (rdev->pdev->device == 0x964a))
1729 rdev->config.evergreen.max_simds = 4;
1730 else
1731 rdev->config.evergreen.max_simds = 5;
1732 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1733 rdev->config.evergreen.max_gprs = 256;
1734 rdev->config.evergreen.max_threads = 248;
1735 rdev->config.evergreen.max_gs_threads = 32;
1736 rdev->config.evergreen.max_stack_entries = 256;
1737 rdev->config.evergreen.sx_num_of_sets = 4;
1738 rdev->config.evergreen.sx_max_export_size = 256;
1739 rdev->config.evergreen.sx_max_export_pos_size = 64;
1740 rdev->config.evergreen.sx_max_export_smx_size = 192;
1741 rdev->config.evergreen.max_hw_contexts = 8;
1742 rdev->config.evergreen.sq_num_cf_insts = 2;
1743
1744 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1745 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1746 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1747 break;
1748 case CHIP_SUMO2:
1749 rdev->config.evergreen.num_ses = 1;
1750 rdev->config.evergreen.max_pipes = 4;
1751 rdev->config.evergreen.max_tile_pipes = 4;
1752 rdev->config.evergreen.max_simds = 2;
1753 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1754 rdev->config.evergreen.max_gprs = 256;
1755 rdev->config.evergreen.max_threads = 248;
1756 rdev->config.evergreen.max_gs_threads = 32;
1757 rdev->config.evergreen.max_stack_entries = 512;
1758 rdev->config.evergreen.sx_num_of_sets = 4;
1759 rdev->config.evergreen.sx_max_export_size = 256;
1760 rdev->config.evergreen.sx_max_export_pos_size = 64;
1761 rdev->config.evergreen.sx_max_export_smx_size = 192;
1762 rdev->config.evergreen.max_hw_contexts = 8;
1763 rdev->config.evergreen.sq_num_cf_insts = 2;
1764
1765 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1766 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1767 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1768 break;
1769 case CHIP_BARTS:
1770 rdev->config.evergreen.num_ses = 2;
1771 rdev->config.evergreen.max_pipes = 4;
1772 rdev->config.evergreen.max_tile_pipes = 8;
1773 rdev->config.evergreen.max_simds = 7;
1774 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1775 rdev->config.evergreen.max_gprs = 256;
1776 rdev->config.evergreen.max_threads = 248;
1777 rdev->config.evergreen.max_gs_threads = 32;
1778 rdev->config.evergreen.max_stack_entries = 512;
1779 rdev->config.evergreen.sx_num_of_sets = 4;
1780 rdev->config.evergreen.sx_max_export_size = 256;
1781 rdev->config.evergreen.sx_max_export_pos_size = 64;
1782 rdev->config.evergreen.sx_max_export_smx_size = 192;
1783 rdev->config.evergreen.max_hw_contexts = 8;
1784 rdev->config.evergreen.sq_num_cf_insts = 2;
1785
1786 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1787 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1788 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1789 break;
1790 case CHIP_TURKS:
1791 rdev->config.evergreen.num_ses = 1;
1792 rdev->config.evergreen.max_pipes = 4;
1793 rdev->config.evergreen.max_tile_pipes = 4;
1794 rdev->config.evergreen.max_simds = 6;
1795 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1796 rdev->config.evergreen.max_gprs = 256;
1797 rdev->config.evergreen.max_threads = 248;
1798 rdev->config.evergreen.max_gs_threads = 32;
1799 rdev->config.evergreen.max_stack_entries = 256;
1800 rdev->config.evergreen.sx_num_of_sets = 4;
1801 rdev->config.evergreen.sx_max_export_size = 256;
1802 rdev->config.evergreen.sx_max_export_pos_size = 64;
1803 rdev->config.evergreen.sx_max_export_smx_size = 192;
1804 rdev->config.evergreen.max_hw_contexts = 8;
1805 rdev->config.evergreen.sq_num_cf_insts = 2;
1806
1807 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1808 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1809 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1810 break;
1811 case CHIP_CAICOS:
1812 rdev->config.evergreen.num_ses = 1;
1813 rdev->config.evergreen.max_pipes = 4;
1814 rdev->config.evergreen.max_tile_pipes = 2;
1815 rdev->config.evergreen.max_simds = 2;
1816 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1817 rdev->config.evergreen.max_gprs = 256;
1818 rdev->config.evergreen.max_threads = 192;
1819 rdev->config.evergreen.max_gs_threads = 16;
1820 rdev->config.evergreen.max_stack_entries = 256;
1821 rdev->config.evergreen.sx_num_of_sets = 4;
1822 rdev->config.evergreen.sx_max_export_size = 128;
1823 rdev->config.evergreen.sx_max_export_pos_size = 32;
1824 rdev->config.evergreen.sx_max_export_smx_size = 96;
1825 rdev->config.evergreen.max_hw_contexts = 4;
1826 rdev->config.evergreen.sq_num_cf_insts = 1;
1827
1828 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1829 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1830 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1831 break;
1832 }
1833
1834 /* Initialize HDP */
1835 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1836 WREG32((0x2c14 + j), 0x00000000);
1837 WREG32((0x2c18 + j), 0x00000000);
1838 WREG32((0x2c1c + j), 0x00000000);
1839 WREG32((0x2c20 + j), 0x00000000);
1840 WREG32((0x2c24 + j), 0x00000000);
1841 }
1842
1843 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1844
1845 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1846
1847 cc_gc_shader_pipe_config |=
1848 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1849 & EVERGREEN_MAX_PIPES_MASK);
1850 cc_gc_shader_pipe_config |=
1851 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1852 & EVERGREEN_MAX_SIMDS_MASK);
1853
1854 cc_rb_backend_disable =
1855 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1856 & EVERGREEN_MAX_BACKENDS_MASK);
1857
1858
1859 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1860 if (rdev->flags & RADEON_IS_IGP)
1861 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1862 else
1863 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1864
1865 switch (rdev->config.evergreen.max_tile_pipes) {
1866 case 1:
1867 default:
1868 gb_addr_config |= NUM_PIPES(0);
1869 break;
1870 case 2:
1871 gb_addr_config |= NUM_PIPES(1);
1872 break;
1873 case 4:
1874 gb_addr_config |= NUM_PIPES(2);
1875 break;
1876 case 8:
1877 gb_addr_config |= NUM_PIPES(3);
1878 break;
1879 }
1880
1881 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1882 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1883 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1884 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1885 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1886 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1887
1888 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1889 gb_addr_config |= ROW_SIZE(2);
1890 else
1891 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1892
1893 if (rdev->ddev->pdev->device == 0x689e) {
1894 u32 efuse_straps_4;
1895 u32 efuse_straps_3;
1896 u8 efuse_box_bit_131_124;
1897
1898 WREG32(RCU_IND_INDEX, 0x204);
1899 efuse_straps_4 = RREG32(RCU_IND_DATA);
1900 WREG32(RCU_IND_INDEX, 0x203);
1901 efuse_straps_3 = RREG32(RCU_IND_DATA);
1902 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1903
1904 switch(efuse_box_bit_131_124) {
1905 case 0x00:
1906 gb_backend_map = 0x76543210;
1907 break;
1908 case 0x55:
1909 gb_backend_map = 0x77553311;
1910 break;
1911 case 0x56:
1912 gb_backend_map = 0x77553300;
1913 break;
1914 case 0x59:
1915 gb_backend_map = 0x77552211;
1916 break;
1917 case 0x66:
1918 gb_backend_map = 0x77443300;
1919 break;
1920 case 0x99:
1921 gb_backend_map = 0x66552211;
1922 break;
1923 case 0x5a:
1924 gb_backend_map = 0x77552200;
1925 break;
1926 case 0xaa:
1927 gb_backend_map = 0x66442200;
1928 break;
1929 case 0x95:
1930 gb_backend_map = 0x66553311;
1931 break;
1932 default:
1933 DRM_ERROR("bad backend map, using default\n");
1934 gb_backend_map =
1935 evergreen_get_tile_pipe_to_backend_map(rdev,
1936 rdev->config.evergreen.max_tile_pipes,
1937 rdev->config.evergreen.max_backends,
1938 ((EVERGREEN_MAX_BACKENDS_MASK <<
1939 rdev->config.evergreen.max_backends) &
1940 EVERGREEN_MAX_BACKENDS_MASK));
1941 break;
1942 }
1943 } else if (rdev->ddev->pdev->device == 0x68b9) {
1944 u32 efuse_straps_3;
1945 u8 efuse_box_bit_127_124;
1946
1947 WREG32(RCU_IND_INDEX, 0x203);
1948 efuse_straps_3 = RREG32(RCU_IND_DATA);
1949 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1950
1951 switch(efuse_box_bit_127_124) {
1952 case 0x0:
1953 gb_backend_map = 0x00003210;
1954 break;
1955 case 0x5:
1956 case 0x6:
1957 case 0x9:
1958 case 0xa:
1959 gb_backend_map = 0x00003311;
1960 break;
1961 default:
1962 DRM_ERROR("bad backend map, using default\n");
1963 gb_backend_map =
1964 evergreen_get_tile_pipe_to_backend_map(rdev,
1965 rdev->config.evergreen.max_tile_pipes,
1966 rdev->config.evergreen.max_backends,
1967 ((EVERGREEN_MAX_BACKENDS_MASK <<
1968 rdev->config.evergreen.max_backends) &
1969 EVERGREEN_MAX_BACKENDS_MASK));
1970 break;
1971 }
1972 } else {
1973 switch (rdev->family) {
1974 case CHIP_CYPRESS:
1975 case CHIP_HEMLOCK:
1976 case CHIP_BARTS:
1977 gb_backend_map = 0x66442200;
1978 break;
1979 case CHIP_JUNIPER:
1980 gb_backend_map = 0x00006420;
1981 break;
1982 default:
1983 gb_backend_map =
1984 evergreen_get_tile_pipe_to_backend_map(rdev,
1985 rdev->config.evergreen.max_tile_pipes,
1986 rdev->config.evergreen.max_backends,
1987 ((EVERGREEN_MAX_BACKENDS_MASK <<
1988 rdev->config.evergreen.max_backends) &
1989 EVERGREEN_MAX_BACKENDS_MASK));
1990 }
1991 }
1992
1993 /* setup tiling info dword. gb_addr_config is not adequate since it does
1994 * not have bank info, so create a custom tiling dword.
1995 * bits 3:0 num_pipes
1996 * bits 7:4 num_banks
1997 * bits 11:8 group_size
1998 * bits 15:12 row_size
1999 */
2000 rdev->config.evergreen.tile_config = 0;
2001 switch (rdev->config.evergreen.max_tile_pipes) {
2002 case 1:
2003 default:
2004 rdev->config.evergreen.tile_config |= (0 << 0);
2005 break;
2006 case 2:
2007 rdev->config.evergreen.tile_config |= (1 << 0);
2008 break;
2009 case 4:
2010 rdev->config.evergreen.tile_config |= (2 << 0);
2011 break;
2012 case 8:
2013 rdev->config.evergreen.tile_config |= (3 << 0);
2014 break;
2015 }
2016 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2017 if (rdev->flags & RADEON_IS_IGP)
2018 rdev->config.evergreen.tile_config |= 1 << 4;
2019 else
2020 rdev->config.evergreen.tile_config |=
2021 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2022 rdev->config.evergreen.tile_config |=
2023 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2024 rdev->config.evergreen.tile_config |=
2025 ((gb_addr_config & 0x30000000) >> 28) << 12;
2026
2027 WREG32(GB_BACKEND_MAP, gb_backend_map);
2028 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2029 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2030 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2031
2032 evergreen_program_channel_remap(rdev);
2033
2034 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2035 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2036
2037 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2038 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2039 u32 sp = cc_gc_shader_pipe_config;
2040 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2041
2042 if (i == num_shader_engines) {
2043 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2044 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2045 }
2046
2047 WREG32(GRBM_GFX_INDEX, gfx);
2048 WREG32(RLC_GFX_INDEX, gfx);
2049
2050 WREG32(CC_RB_BACKEND_DISABLE, rb);
2051 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2052 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2053 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2054 }
2055
2056 grbm_gfx_index |= SE_BROADCAST_WRITES;
2057 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2058 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2059
2060 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2061 WREG32(CGTS_TCC_DISABLE, 0);
2062 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2063 WREG32(CGTS_USER_TCC_DISABLE, 0);
2064
2065 /* set HW defaults for 3D engine */
2066 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2067 ROQ_IB2_START(0x2b)));
2068
2069 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2070
2071 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2072 SYNC_GRADIENT |
2073 SYNC_WALKER |
2074 SYNC_ALIGNER));
2075
2076 sx_debug_1 = RREG32(SX_DEBUG_1);
2077 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2078 WREG32(SX_DEBUG_1, sx_debug_1);
2079
2080
2081 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2082 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2083 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2084 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2085
2086 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2087 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2088 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2089
2090 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2091 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2092 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2093
2094 WREG32(VGT_NUM_INSTANCES, 1);
2095 WREG32(SPI_CONFIG_CNTL, 0);
2096 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2097 WREG32(CP_PERFMON_CNTL, 0);
2098
2099 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2100 FETCH_FIFO_HIWATER(0x4) |
2101 DONE_FIFO_HIWATER(0xe0) |
2102 ALU_UPDATE_FIFO_HIWATER(0x8)));
2103
2104 sq_config = RREG32(SQ_CONFIG);
2105 sq_config &= ~(PS_PRIO(3) |
2106 VS_PRIO(3) |
2107 GS_PRIO(3) |
2108 ES_PRIO(3));
2109 sq_config |= (VC_ENABLE |
2110 EXPORT_SRC_C |
2111 PS_PRIO(0) |
2112 VS_PRIO(1) |
2113 GS_PRIO(2) |
2114 ES_PRIO(3));
2115
2116 switch (rdev->family) {
2117 case CHIP_CEDAR:
2118 case CHIP_PALM:
2119 case CHIP_SUMO:
2120 case CHIP_SUMO2:
2121 case CHIP_CAICOS:
2122 /* no vertex cache */
2123 sq_config &= ~VC_ENABLE;
2124 break;
2125 default:
2126 break;
2127 }
2128
2129 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2130
2131 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2132 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2133 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2134 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2135 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2136 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2137 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2138
2139 switch (rdev->family) {
2140 case CHIP_CEDAR:
2141 case CHIP_PALM:
2142 case CHIP_SUMO:
2143 case CHIP_SUMO2:
2144 ps_thread_count = 96;
2145 break;
2146 default:
2147 ps_thread_count = 128;
2148 break;
2149 }
2150
2151 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2152 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2153 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2154 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2155 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2156 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2157
2158 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2159 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2160 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2161 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2162 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2163 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2164
2165 WREG32(SQ_CONFIG, sq_config);
2166 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2167 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2168 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2169 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2170 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2171 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2172 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2173 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2174 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2175 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2176
2177 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2178 FORCE_EOV_MAX_REZ_CNT(255)));
2179
2180 switch (rdev->family) {
2181 case CHIP_CEDAR:
2182 case CHIP_PALM:
2183 case CHIP_SUMO:
2184 case CHIP_SUMO2:
2185 case CHIP_CAICOS:
2186 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2187 break;
2188 default:
2189 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2190 break;
2191 }
2192 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2193 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2194
2195 WREG32(VGT_GS_VERTEX_REUSE, 16);
2196 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2197 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2198
2199 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2200 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2201
2202 WREG32(CB_PERF_CTR0_SEL_0, 0);
2203 WREG32(CB_PERF_CTR0_SEL_1, 0);
2204 WREG32(CB_PERF_CTR1_SEL_0, 0);
2205 WREG32(CB_PERF_CTR1_SEL_1, 0);
2206 WREG32(CB_PERF_CTR2_SEL_0, 0);
2207 WREG32(CB_PERF_CTR2_SEL_1, 0);
2208 WREG32(CB_PERF_CTR3_SEL_0, 0);
2209 WREG32(CB_PERF_CTR3_SEL_1, 0);
2210
2211 /* clear render buffer base addresses */
2212 WREG32(CB_COLOR0_BASE, 0);
2213 WREG32(CB_COLOR1_BASE, 0);
2214 WREG32(CB_COLOR2_BASE, 0);
2215 WREG32(CB_COLOR3_BASE, 0);
2216 WREG32(CB_COLOR4_BASE, 0);
2217 WREG32(CB_COLOR5_BASE, 0);
2218 WREG32(CB_COLOR6_BASE, 0);
2219 WREG32(CB_COLOR7_BASE, 0);
2220 WREG32(CB_COLOR8_BASE, 0);
2221 WREG32(CB_COLOR9_BASE, 0);
2222 WREG32(CB_COLOR10_BASE, 0);
2223 WREG32(CB_COLOR11_BASE, 0);
2224
2225 /* set the shader const cache sizes to 0 */
2226 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2227 WREG32(i, 0);
2228 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2229 WREG32(i, 0);
2230
2231 tmp = RREG32(HDP_MISC_CNTL);
2232 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2233 WREG32(HDP_MISC_CNTL, tmp);
2234
2235 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2236 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2237
2238 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2239
2240 udelay(50);
2241
2242 }
2243
2244 int evergreen_mc_init(struct radeon_device *rdev)
2245 {
2246 u32 tmp;
2247 int chansize, numchan;
2248
2249 /* Get VRAM informations */
2250 rdev->mc.vram_is_ddr = true;
2251 tmp = RREG32(MC_ARB_RAMCFG);
2252 if (tmp & CHANSIZE_OVERRIDE) {
2253 chansize = 16;
2254 } else if (tmp & CHANSIZE_MASK) {
2255 chansize = 64;
2256 } else {
2257 chansize = 32;
2258 }
2259 tmp = RREG32(MC_SHARED_CHMAP);
2260 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2261 case 0:
2262 default:
2263 numchan = 1;
2264 break;
2265 case 1:
2266 numchan = 2;
2267 break;
2268 case 2:
2269 numchan = 4;
2270 break;
2271 case 3:
2272 numchan = 8;
2273 break;
2274 }
2275 rdev->mc.vram_width = numchan * chansize;
2276 /* Could aper size report 0 ? */
2277 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2278 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2279 /* Setup GPU memory space */
2280 if (rdev->flags & RADEON_IS_IGP) {
2281 /* size in bytes on fusion */
2282 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2283 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2284 } else {
2285 /* size in MB on evergreen */
2286 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2287 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2288 }
2289 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2290 r700_vram_gtt_location(rdev, &rdev->mc);
2291 radeon_update_bandwidth_info(rdev);
2292
2293 return 0;
2294 }
2295
2296 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2297 {
2298 u32 srbm_status;
2299 u32 grbm_status;
2300 u32 grbm_status_se0, grbm_status_se1;
2301 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2302 int r;
2303
2304 srbm_status = RREG32(SRBM_STATUS);
2305 grbm_status = RREG32(GRBM_STATUS);
2306 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2307 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2308 if (!(grbm_status & GUI_ACTIVE)) {
2309 r100_gpu_lockup_update(lockup, &rdev->cp);
2310 return false;
2311 }
2312 /* force CP activities */
2313 r = radeon_ring_lock(rdev, 2);
2314 if (!r) {
2315 /* PACKET2 NOP */
2316 radeon_ring_write(rdev, 0x80000000);
2317 radeon_ring_write(rdev, 0x80000000);
2318 radeon_ring_unlock_commit(rdev);
2319 }
2320 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2321 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2322 }
2323
2324 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2325 {
2326 struct evergreen_mc_save save;
2327 u32 grbm_reset = 0;
2328
2329 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2330 return 0;
2331
2332 dev_info(rdev->dev, "GPU softreset \n");
2333 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2334 RREG32(GRBM_STATUS));
2335 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2336 RREG32(GRBM_STATUS_SE0));
2337 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2338 RREG32(GRBM_STATUS_SE1));
2339 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2340 RREG32(SRBM_STATUS));
2341 evergreen_mc_stop(rdev, &save);
2342 if (evergreen_mc_wait_for_idle(rdev)) {
2343 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2344 }
2345 /* Disable CP parsing/prefetching */
2346 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2347
2348 /* reset all the gfx blocks */
2349 grbm_reset = (SOFT_RESET_CP |
2350 SOFT_RESET_CB |
2351 SOFT_RESET_DB |
2352 SOFT_RESET_PA |
2353 SOFT_RESET_SC |
2354 SOFT_RESET_SPI |
2355 SOFT_RESET_SH |
2356 SOFT_RESET_SX |
2357 SOFT_RESET_TC |
2358 SOFT_RESET_TA |
2359 SOFT_RESET_VC |
2360 SOFT_RESET_VGT);
2361
2362 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2363 WREG32(GRBM_SOFT_RESET, grbm_reset);
2364 (void)RREG32(GRBM_SOFT_RESET);
2365 udelay(50);
2366 WREG32(GRBM_SOFT_RESET, 0);
2367 (void)RREG32(GRBM_SOFT_RESET);
2368 /* Wait a little for things to settle down */
2369 udelay(50);
2370 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2371 RREG32(GRBM_STATUS));
2372 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2373 RREG32(GRBM_STATUS_SE0));
2374 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2375 RREG32(GRBM_STATUS_SE1));
2376 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2377 RREG32(SRBM_STATUS));
2378 evergreen_mc_resume(rdev, &save);
2379 return 0;
2380 }
2381
2382 int evergreen_asic_reset(struct radeon_device *rdev)
2383 {
2384 return evergreen_gpu_soft_reset(rdev);
2385 }
2386
2387 /* Interrupts */
2388
2389 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2390 {
2391 switch (crtc) {
2392 case 0:
2393 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2394 case 1:
2395 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2396 case 2:
2397 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2398 case 3:
2399 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2400 case 4:
2401 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2402 case 5:
2403 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2404 default:
2405 return 0;
2406 }
2407 }
2408
2409 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2410 {
2411 u32 tmp;
2412
2413 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2414 WREG32(GRBM_INT_CNTL, 0);
2415 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2416 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2417 if (!(rdev->flags & RADEON_IS_IGP)) {
2418 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2419 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2420 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2421 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2422 }
2423
2424 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2425 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2426 if (!(rdev->flags & RADEON_IS_IGP)) {
2427 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2428 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2429 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2430 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2431 }
2432
2433 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2434 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2435
2436 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2437 WREG32(DC_HPD1_INT_CONTROL, tmp);
2438 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2439 WREG32(DC_HPD2_INT_CONTROL, tmp);
2440 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2441 WREG32(DC_HPD3_INT_CONTROL, tmp);
2442 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2443 WREG32(DC_HPD4_INT_CONTROL, tmp);
2444 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2445 WREG32(DC_HPD5_INT_CONTROL, tmp);
2446 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2447 WREG32(DC_HPD6_INT_CONTROL, tmp);
2448
2449 }
2450
2451 int evergreen_irq_set(struct radeon_device *rdev)
2452 {
2453 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2454 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2455 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2456 u32 grbm_int_cntl = 0;
2457 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2458
2459 if (!rdev->irq.installed) {
2460 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2461 return -EINVAL;
2462 }
2463 /* don't enable anything if the ih is disabled */
2464 if (!rdev->ih.enabled) {
2465 r600_disable_interrupts(rdev);
2466 /* force the active interrupt state to all disabled */
2467 evergreen_disable_interrupt_state(rdev);
2468 return 0;
2469 }
2470
2471 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2472 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2473 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2474 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2475 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2476 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2477
2478 if (rdev->irq.sw_int) {
2479 DRM_DEBUG("evergreen_irq_set: sw int\n");
2480 cp_int_cntl |= RB_INT_ENABLE;
2481 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2482 }
2483 if (rdev->irq.crtc_vblank_int[0] ||
2484 rdev->irq.pflip[0]) {
2485 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2486 crtc1 |= VBLANK_INT_MASK;
2487 }
2488 if (rdev->irq.crtc_vblank_int[1] ||
2489 rdev->irq.pflip[1]) {
2490 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2491 crtc2 |= VBLANK_INT_MASK;
2492 }
2493 if (rdev->irq.crtc_vblank_int[2] ||
2494 rdev->irq.pflip[2]) {
2495 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2496 crtc3 |= VBLANK_INT_MASK;
2497 }
2498 if (rdev->irq.crtc_vblank_int[3] ||
2499 rdev->irq.pflip[3]) {
2500 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2501 crtc4 |= VBLANK_INT_MASK;
2502 }
2503 if (rdev->irq.crtc_vblank_int[4] ||
2504 rdev->irq.pflip[4]) {
2505 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2506 crtc5 |= VBLANK_INT_MASK;
2507 }
2508 if (rdev->irq.crtc_vblank_int[5] ||
2509 rdev->irq.pflip[5]) {
2510 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2511 crtc6 |= VBLANK_INT_MASK;
2512 }
2513 if (rdev->irq.hpd[0]) {
2514 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2515 hpd1 |= DC_HPDx_INT_EN;
2516 }
2517 if (rdev->irq.hpd[1]) {
2518 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2519 hpd2 |= DC_HPDx_INT_EN;
2520 }
2521 if (rdev->irq.hpd[2]) {
2522 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2523 hpd3 |= DC_HPDx_INT_EN;
2524 }
2525 if (rdev->irq.hpd[3]) {
2526 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2527 hpd4 |= DC_HPDx_INT_EN;
2528 }
2529 if (rdev->irq.hpd[4]) {
2530 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2531 hpd5 |= DC_HPDx_INT_EN;
2532 }
2533 if (rdev->irq.hpd[5]) {
2534 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2535 hpd6 |= DC_HPDx_INT_EN;
2536 }
2537 if (rdev->irq.gui_idle) {
2538 DRM_DEBUG("gui idle\n");
2539 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2540 }
2541
2542 WREG32(CP_INT_CNTL, cp_int_cntl);
2543 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2544
2545 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2546 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2547 if (!(rdev->flags & RADEON_IS_IGP)) {
2548 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2549 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2550 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2551 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2552 }
2553
2554 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2555 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2559 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2560
2561 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2562 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2563 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2564 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2565 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2566 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2567
2568 return 0;
2569 }
2570
2571 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2572 {
2573 u32 tmp;
2574
2575 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2576 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2577 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2578 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2579 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2580 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2581 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2582 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2583 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2584 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2585 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2586 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2587
2588 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2589 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2590 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2591 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2592 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2593 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2594 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2595 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2596 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2597 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2598 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2599 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2600
2601 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2602 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2603 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2604 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2605
2606 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2607 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2608 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2609 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2610
2611 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2612 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2613 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2614 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2615
2616 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2617 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2618 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2619 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2620
2621 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2622 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2623 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2624 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2625
2626 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2627 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2628 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2629 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2630
2631 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2632 tmp = RREG32(DC_HPD1_INT_CONTROL);
2633 tmp |= DC_HPDx_INT_ACK;
2634 WREG32(DC_HPD1_INT_CONTROL, tmp);
2635 }
2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2637 tmp = RREG32(DC_HPD2_INT_CONTROL);
2638 tmp |= DC_HPDx_INT_ACK;
2639 WREG32(DC_HPD2_INT_CONTROL, tmp);
2640 }
2641 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2642 tmp = RREG32(DC_HPD3_INT_CONTROL);
2643 tmp |= DC_HPDx_INT_ACK;
2644 WREG32(DC_HPD3_INT_CONTROL, tmp);
2645 }
2646 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2647 tmp = RREG32(DC_HPD4_INT_CONTROL);
2648 tmp |= DC_HPDx_INT_ACK;
2649 WREG32(DC_HPD4_INT_CONTROL, tmp);
2650 }
2651 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2652 tmp = RREG32(DC_HPD5_INT_CONTROL);
2653 tmp |= DC_HPDx_INT_ACK;
2654 WREG32(DC_HPD5_INT_CONTROL, tmp);
2655 }
2656 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2657 tmp = RREG32(DC_HPD5_INT_CONTROL);
2658 tmp |= DC_HPDx_INT_ACK;
2659 WREG32(DC_HPD6_INT_CONTROL, tmp);
2660 }
2661 }
2662
2663 void evergreen_irq_disable(struct radeon_device *rdev)
2664 {
2665 r600_disable_interrupts(rdev);
2666 /* Wait and acknowledge irq */
2667 mdelay(1);
2668 evergreen_irq_ack(rdev);
2669 evergreen_disable_interrupt_state(rdev);
2670 }
2671
2672 void evergreen_irq_suspend(struct radeon_device *rdev)
2673 {
2674 evergreen_irq_disable(rdev);
2675 r600_rlc_stop(rdev);
2676 }
2677
2678 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2679 {
2680 u32 wptr, tmp;
2681
2682 if (rdev->wb.enabled)
2683 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2684 else
2685 wptr = RREG32(IH_RB_WPTR);
2686
2687 if (wptr & RB_OVERFLOW) {
2688 /* When a ring buffer overflow happen start parsing interrupt
2689 * from the last not overwritten vector (wptr + 16). Hopefully
2690 * this should allow us to catchup.
2691 */
2692 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2693 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2694 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2695 tmp = RREG32(IH_RB_CNTL);
2696 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2697 WREG32(IH_RB_CNTL, tmp);
2698 }
2699 return (wptr & rdev->ih.ptr_mask);
2700 }
2701
2702 int evergreen_irq_process(struct radeon_device *rdev)
2703 {
2704 u32 wptr;
2705 u32 rptr;
2706 u32 src_id, src_data;
2707 u32 ring_index;
2708 unsigned long flags;
2709 bool queue_hotplug = false;
2710
2711 if (!rdev->ih.enabled || rdev->shutdown)
2712 return IRQ_NONE;
2713
2714 wptr = evergreen_get_ih_wptr(rdev);
2715 rptr = rdev->ih.rptr;
2716 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2717
2718 spin_lock_irqsave(&rdev->ih.lock, flags);
2719 if (rptr == wptr) {
2720 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2721 return IRQ_NONE;
2722 }
2723 restart_ih:
2724 /* display interrupts */
2725 evergreen_irq_ack(rdev);
2726
2727 rdev->ih.wptr = wptr;
2728 while (rptr != wptr) {
2729 /* wptr/rptr are in bytes! */
2730 ring_index = rptr / 4;
2731 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2732 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2733
2734 switch (src_id) {
2735 case 1: /* D1 vblank/vline */
2736 switch (src_data) {
2737 case 0: /* D1 vblank */
2738 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2739 if (rdev->irq.crtc_vblank_int[0]) {
2740 drm_handle_vblank(rdev->ddev, 0);
2741 rdev->pm.vblank_sync = true;
2742 wake_up(&rdev->irq.vblank_queue);
2743 }
2744 if (rdev->irq.pflip[0])
2745 radeon_crtc_handle_flip(rdev, 0);
2746 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2747 DRM_DEBUG("IH: D1 vblank\n");
2748 }
2749 break;
2750 case 1: /* D1 vline */
2751 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2752 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2753 DRM_DEBUG("IH: D1 vline\n");
2754 }
2755 break;
2756 default:
2757 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2758 break;
2759 }
2760 break;
2761 case 2: /* D2 vblank/vline */
2762 switch (src_data) {
2763 case 0: /* D2 vblank */
2764 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2765 if (rdev->irq.crtc_vblank_int[1]) {
2766 drm_handle_vblank(rdev->ddev, 1);
2767 rdev->pm.vblank_sync = true;
2768 wake_up(&rdev->irq.vblank_queue);
2769 }
2770 if (rdev->irq.pflip[1])
2771 radeon_crtc_handle_flip(rdev, 1);
2772 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2773 DRM_DEBUG("IH: D2 vblank\n");
2774 }
2775 break;
2776 case 1: /* D2 vline */
2777 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2778 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2779 DRM_DEBUG("IH: D2 vline\n");
2780 }
2781 break;
2782 default:
2783 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2784 break;
2785 }
2786 break;
2787 case 3: /* D3 vblank/vline */
2788 switch (src_data) {
2789 case 0: /* D3 vblank */
2790 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2791 if (rdev->irq.crtc_vblank_int[2]) {
2792 drm_handle_vblank(rdev->ddev, 2);
2793 rdev->pm.vblank_sync = true;
2794 wake_up(&rdev->irq.vblank_queue);
2795 }
2796 if (rdev->irq.pflip[2])
2797 radeon_crtc_handle_flip(rdev, 2);
2798 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2799 DRM_DEBUG("IH: D3 vblank\n");
2800 }
2801 break;
2802 case 1: /* D3 vline */
2803 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2804 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2805 DRM_DEBUG("IH: D3 vline\n");
2806 }
2807 break;
2808 default:
2809 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2810 break;
2811 }
2812 break;
2813 case 4: /* D4 vblank/vline */
2814 switch (src_data) {
2815 case 0: /* D4 vblank */
2816 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2817 if (rdev->irq.crtc_vblank_int[3]) {
2818 drm_handle_vblank(rdev->ddev, 3);
2819 rdev->pm.vblank_sync = true;
2820 wake_up(&rdev->irq.vblank_queue);
2821 }
2822 if (rdev->irq.pflip[3])
2823 radeon_crtc_handle_flip(rdev, 3);
2824 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2825 DRM_DEBUG("IH: D4 vblank\n");
2826 }
2827 break;
2828 case 1: /* D4 vline */
2829 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2830 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2831 DRM_DEBUG("IH: D4 vline\n");
2832 }
2833 break;
2834 default:
2835 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2836 break;
2837 }
2838 break;
2839 case 5: /* D5 vblank/vline */
2840 switch (src_data) {
2841 case 0: /* D5 vblank */
2842 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2843 if (rdev->irq.crtc_vblank_int[4]) {
2844 drm_handle_vblank(rdev->ddev, 4);
2845 rdev->pm.vblank_sync = true;
2846 wake_up(&rdev->irq.vblank_queue);
2847 }
2848 if (rdev->irq.pflip[4])
2849 radeon_crtc_handle_flip(rdev, 4);
2850 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2851 DRM_DEBUG("IH: D5 vblank\n");
2852 }
2853 break;
2854 case 1: /* D5 vline */
2855 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2856 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2857 DRM_DEBUG("IH: D5 vline\n");
2858 }
2859 break;
2860 default:
2861 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2862 break;
2863 }
2864 break;
2865 case 6: /* D6 vblank/vline */
2866 switch (src_data) {
2867 case 0: /* D6 vblank */
2868 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2869 if (rdev->irq.crtc_vblank_int[5]) {
2870 drm_handle_vblank(rdev->ddev, 5);
2871 rdev->pm.vblank_sync = true;
2872 wake_up(&rdev->irq.vblank_queue);
2873 }
2874 if (rdev->irq.pflip[5])
2875 radeon_crtc_handle_flip(rdev, 5);
2876 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2877 DRM_DEBUG("IH: D6 vblank\n");
2878 }
2879 break;
2880 case 1: /* D6 vline */
2881 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2882 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2883 DRM_DEBUG("IH: D6 vline\n");
2884 }
2885 break;
2886 default:
2887 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2888 break;
2889 }
2890 break;
2891 case 42: /* HPD hotplug */
2892 switch (src_data) {
2893 case 0:
2894 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2895 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2896 queue_hotplug = true;
2897 DRM_DEBUG("IH: HPD1\n");
2898 }
2899 break;
2900 case 1:
2901 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2902 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2903 queue_hotplug = true;
2904 DRM_DEBUG("IH: HPD2\n");
2905 }
2906 break;
2907 case 2:
2908 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2909 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2910 queue_hotplug = true;
2911 DRM_DEBUG("IH: HPD3\n");
2912 }
2913 break;
2914 case 3:
2915 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2916 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2917 queue_hotplug = true;
2918 DRM_DEBUG("IH: HPD4\n");
2919 }
2920 break;
2921 case 4:
2922 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2923 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2924 queue_hotplug = true;
2925 DRM_DEBUG("IH: HPD5\n");
2926 }
2927 break;
2928 case 5:
2929 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2930 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2931 queue_hotplug = true;
2932 DRM_DEBUG("IH: HPD6\n");
2933 }
2934 break;
2935 default:
2936 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2937 break;
2938 }
2939 break;
2940 case 176: /* CP_INT in ring buffer */
2941 case 177: /* CP_INT in IB1 */
2942 case 178: /* CP_INT in IB2 */
2943 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2944 radeon_fence_process(rdev);
2945 break;
2946 case 181: /* CP EOP event */
2947 DRM_DEBUG("IH: CP EOP\n");
2948 radeon_fence_process(rdev);
2949 break;
2950 case 233: /* GUI IDLE */
2951 DRM_DEBUG("IH: GUI idle\n");
2952 rdev->pm.gui_idle = true;
2953 wake_up(&rdev->irq.idle_queue);
2954 break;
2955 default:
2956 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2957 break;
2958 }
2959
2960 /* wptr/rptr are in bytes! */
2961 rptr += 16;
2962 rptr &= rdev->ih.ptr_mask;
2963 }
2964 /* make sure wptr hasn't changed while processing */
2965 wptr = evergreen_get_ih_wptr(rdev);
2966 if (wptr != rdev->ih.wptr)
2967 goto restart_ih;
2968 if (queue_hotplug)
2969 schedule_work(&rdev->hotplug_work);
2970 rdev->ih.rptr = rptr;
2971 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2972 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2973 return IRQ_HANDLED;
2974 }
2975
2976 static int evergreen_startup(struct radeon_device *rdev)
2977 {
2978 int r;
2979
2980 /* enable pcie gen2 link */
2981 if (!ASIC_IS_DCE5(rdev))
2982 evergreen_pcie_gen2_enable(rdev);
2983
2984 if (ASIC_IS_DCE5(rdev)) {
2985 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2986 r = ni_init_microcode(rdev);
2987 if (r) {
2988 DRM_ERROR("Failed to load firmware!\n");
2989 return r;
2990 }
2991 }
2992 r = ni_mc_load_microcode(rdev);
2993 if (r) {
2994 DRM_ERROR("Failed to load MC firmware!\n");
2995 return r;
2996 }
2997 } else {
2998 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2999 r = r600_init_microcode(rdev);
3000 if (r) {
3001 DRM_ERROR("Failed to load firmware!\n");
3002 return r;
3003 }
3004 }
3005 }
3006
3007 evergreen_mc_program(rdev);
3008 if (rdev->flags & RADEON_IS_AGP) {
3009 evergreen_agp_enable(rdev);
3010 } else {
3011 r = evergreen_pcie_gart_enable(rdev);
3012 if (r)
3013 return r;
3014 }
3015 evergreen_gpu_init(rdev);
3016
3017 r = evergreen_blit_init(rdev);
3018 if (r) {
3019 evergreen_blit_fini(rdev);
3020 rdev->asic->copy = NULL;
3021 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3022 }
3023
3024 /* allocate wb buffer */
3025 r = radeon_wb_init(rdev);
3026 if (r)
3027 return r;
3028
3029 /* Enable IRQ */
3030 r = r600_irq_init(rdev);
3031 if (r) {
3032 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3033 radeon_irq_kms_fini(rdev);
3034 return r;
3035 }
3036 evergreen_irq_set(rdev);
3037
3038 r = radeon_ring_init(rdev, rdev->cp.ring_size);
3039 if (r)
3040 return r;
3041 r = evergreen_cp_load_microcode(rdev);
3042 if (r)
3043 return r;
3044 r = evergreen_cp_resume(rdev);
3045 if (r)
3046 return r;
3047
3048 return 0;
3049 }
3050
3051 int evergreen_resume(struct radeon_device *rdev)
3052 {
3053 int r;
3054
3055 /* reset the asic, the gfx blocks are often in a bad state
3056 * after the driver is unloaded or after a resume
3057 */
3058 if (radeon_asic_reset(rdev))
3059 dev_warn(rdev->dev, "GPU reset failed !\n");
3060 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3061 * posting will perform necessary task to bring back GPU into good
3062 * shape.
3063 */
3064 /* post card */
3065 atom_asic_init(rdev->mode_info.atom_context);
3066
3067 r = evergreen_startup(rdev);
3068 if (r) {
3069 DRM_ERROR("evergreen startup failed on resume\n");
3070 return r;
3071 }
3072
3073 r = r600_ib_test(rdev);
3074 if (r) {
3075 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3076 return r;
3077 }
3078
3079 return r;
3080
3081 }
3082
3083 int evergreen_suspend(struct radeon_device *rdev)
3084 {
3085 int r;
3086
3087 /* FIXME: we should wait for ring to be empty */
3088 r700_cp_stop(rdev);
3089 rdev->cp.ready = false;
3090 evergreen_irq_suspend(rdev);
3091 radeon_wb_disable(rdev);
3092 evergreen_pcie_gart_disable(rdev);
3093
3094 /* unpin shaders bo */
3095 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3096 if (likely(r == 0)) {
3097 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3098 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3099 }
3100
3101 return 0;
3102 }
3103
3104 int evergreen_copy_blit(struct radeon_device *rdev,
3105 uint64_t src_offset, uint64_t dst_offset,
3106 unsigned num_pages, struct radeon_fence *fence)
3107 {
3108 int r;
3109
3110 mutex_lock(&rdev->r600_blit.mutex);
3111 rdev->r600_blit.vb_ib = NULL;
3112 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
3113 if (r) {
3114 if (rdev->r600_blit.vb_ib)
3115 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3116 mutex_unlock(&rdev->r600_blit.mutex);
3117 return r;
3118 }
3119 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3120 evergreen_blit_done_copy(rdev, fence);
3121 mutex_unlock(&rdev->r600_blit.mutex);
3122 return 0;
3123 }
3124
3125 /* Plan is to move initialization in that function and use
3126 * helper function so that radeon_device_init pretty much
3127 * do nothing more than calling asic specific function. This
3128 * should also allow to remove a bunch of callback function
3129 * like vram_info.
3130 */
3131 int evergreen_init(struct radeon_device *rdev)
3132 {
3133 int r;
3134
3135 /* This don't do much */
3136 r = radeon_gem_init(rdev);
3137 if (r)
3138 return r;
3139 /* Read BIOS */
3140 if (!radeon_get_bios(rdev)) {
3141 if (ASIC_IS_AVIVO(rdev))
3142 return -EINVAL;
3143 }
3144 /* Must be an ATOMBIOS */
3145 if (!rdev->is_atom_bios) {
3146 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3147 return -EINVAL;
3148 }
3149 r = radeon_atombios_init(rdev);
3150 if (r)
3151 return r;
3152 /* reset the asic, the gfx blocks are often in a bad state
3153 * after the driver is unloaded or after a resume
3154 */
3155 if (radeon_asic_reset(rdev))
3156 dev_warn(rdev->dev, "GPU reset failed !\n");
3157 /* Post card if necessary */
3158 if (!radeon_card_posted(rdev)) {
3159 if (!rdev->bios) {
3160 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3161 return -EINVAL;
3162 }
3163 DRM_INFO("GPU not posted. posting now...\n");
3164 atom_asic_init(rdev->mode_info.atom_context);
3165 }
3166 /* Initialize scratch registers */
3167 r600_scratch_init(rdev);
3168 /* Initialize surface registers */
3169 radeon_surface_init(rdev);
3170 /* Initialize clocks */
3171 radeon_get_clock_info(rdev->ddev);
3172 /* Fence driver */
3173 r = radeon_fence_driver_init(rdev);
3174 if (r)
3175 return r;
3176 /* initialize AGP */
3177 if (rdev->flags & RADEON_IS_AGP) {
3178 r = radeon_agp_init(rdev);
3179 if (r)
3180 radeon_agp_disable(rdev);
3181 }
3182 /* initialize memory controller */
3183 r = evergreen_mc_init(rdev);
3184 if (r)
3185 return r;
3186 /* Memory manager */
3187 r = radeon_bo_init(rdev);
3188 if (r)
3189 return r;
3190
3191 r = radeon_irq_kms_init(rdev);
3192 if (r)
3193 return r;
3194
3195 rdev->cp.ring_obj = NULL;
3196 r600_ring_init(rdev, 1024 * 1024);
3197
3198 rdev->ih.ring_obj = NULL;
3199 r600_ih_ring_init(rdev, 64 * 1024);
3200
3201 r = r600_pcie_gart_init(rdev);
3202 if (r)
3203 return r;
3204
3205 rdev->accel_working = true;
3206 r = evergreen_startup(rdev);
3207 if (r) {
3208 dev_err(rdev->dev, "disabling GPU acceleration\n");
3209 r700_cp_fini(rdev);
3210 r600_irq_fini(rdev);
3211 radeon_wb_fini(rdev);
3212 radeon_irq_kms_fini(rdev);
3213 evergreen_pcie_gart_fini(rdev);
3214 rdev->accel_working = false;
3215 }
3216 if (rdev->accel_working) {
3217 r = radeon_ib_pool_init(rdev);
3218 if (r) {
3219 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3220 rdev->accel_working = false;
3221 }
3222 r = r600_ib_test(rdev);
3223 if (r) {
3224 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3225 rdev->accel_working = false;
3226 }
3227 }
3228 return 0;
3229 }
3230
3231 void evergreen_fini(struct radeon_device *rdev)
3232 {
3233 evergreen_blit_fini(rdev);
3234 r700_cp_fini(rdev);
3235 r600_irq_fini(rdev);
3236 radeon_wb_fini(rdev);
3237 radeon_irq_kms_fini(rdev);
3238 evergreen_pcie_gart_fini(rdev);
3239 radeon_gem_fini(rdev);
3240 radeon_fence_driver_fini(rdev);
3241 radeon_agp_fini(rdev);
3242 radeon_bo_fini(rdev);
3243 radeon_atombios_fini(rdev);
3244 kfree(rdev->bios);
3245 rdev->bios = NULL;
3246 }
3247
3248 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3249 {
3250 u32 link_width_cntl, speed_cntl;
3251
3252 if (radeon_pcie_gen2 == 0)
3253 return;
3254
3255 if (rdev->flags & RADEON_IS_IGP)
3256 return;
3257
3258 if (!(rdev->flags & RADEON_IS_PCIE))
3259 return;
3260
3261 /* x2 cards have a special sequence */
3262 if (ASIC_IS_X2(rdev))
3263 return;
3264
3265 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3266 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3267 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3268
3269 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3270 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3271 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3272
3273 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3274 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3275 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3276
3277 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3278 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3279 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3280
3281 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3282 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3283 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3284
3285 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3286 speed_cntl |= LC_GEN2_EN_STRAP;
3287 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3288
3289 } else {
3290 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3291 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3292 if (1)
3293 link_width_cntl |= LC_UPCONFIGURE_DIS;
3294 else
3295 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3296 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3297 }
3298 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree