drivers/net/wireless/ath/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci-aspm.h>
  20 #include <linux/ath9k_platform.h>
  21 #include "ath9k.h"
  22
  23 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
  24         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  25         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  26         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  27         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  28         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  29         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  30         { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
  31         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
  32         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
  33         { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
  34         { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
  35         { 0 }
  36 };
  37
  38 /* return bus cachesize in 4B word units */
  39 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
  40 {
  41         struct ath_softc *sc = (struct ath_softc *) common->priv;
  42         u8 u8tmp;
  43
  44         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
  45         *csz = (int)u8tmp;
  46
  47         /*
  48          * This check was put in to avoid "unpleasant" consequences if
  49          * the bootrom has not fully initialized all PCI devices.
  50          * Sometimes the cache line size register is not set
  51          */
  52
  53         if (*csz == 0)
  54                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  55 }
  56
  57 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  58 {
  59         struct ath_softc *sc = (struct ath_softc *) common->priv;
  60         struct ath9k_platform_data *pdata = sc->dev->platform_data;
  61
  62         if (pdata) {
  63                 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
  64                         ath_err(common,
  65                                 "%s: eeprom read failed, offset %08x is out of range\n",
  66                                 __func__, off);
  67                 }
  68
  69                 *data = pdata->eeprom_data[off];
  70         } else {
  71                 struct ath_hw *ah = (struct ath_hw *) common->ah;
  72
  73                 common->ops->read(ah, AR5416_EEPROM_OFFSET +
  74                                       (off << AR5416_EEPROM_S));
  75
  76                 if (!ath9k_hw_wait(ah,
  77                                    AR_EEPROM_STATUS_DATA,
  78                                    AR_EEPROM_STATUS_DATA_BUSY |
  79                                    AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  80                                    AH_WAIT_TIMEOUT)) {
  81                         return false;
  82                 }
  83
  84                 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
  85                            AR_EEPROM_STATUS_DATA_VAL);
  86         }
  87
  88         return true;
  89 }
  90
  91 /*
  92  * Bluetooth coexistance requires disabling ASPM.
  93  */
  94 static void ath_pci_bt_coex_prep(struct ath_common *common)
  95 {
  96         struct ath_softc *sc = (struct ath_softc *) common->priv;
  97         struct pci_dev *pdev = to_pci_dev(sc->dev);
  98         u8 aspm;
  99
 100         if (!pci_is_pcie(pdev))
 101                 return;
 102
 103         pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
 104         aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
 105         pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
 106 }
 107
 108 static void ath_pci_extn_synch_enable(struct ath_common *common)
 109 {
 110         struct ath_softc *sc = (struct ath_softc *) common->priv;
 111         struct pci_dev *pdev = to_pci_dev(sc->dev);
 112         u8 lnkctl;
 113
 114         pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
 115         lnkctl |= PCI_EXP_LNKCTL_ES;
 116         pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
 117 }
 118
 119 static void ath_pci_aspm_init(struct ath_common *common)
 120 {
 121         struct ath_softc *sc = (struct ath_softc *) common->priv;
 122         struct ath_hw *ah = sc->sc_ah;
 123         struct pci_dev *pdev = to_pci_dev(sc->dev);
 124         struct pci_dev *parent;
 125         int pos;
 126         u8 aspm;
 127
 128         if (!pci_is_pcie(pdev))
 129                 return;
 130
 131         parent = pdev->bus->self;
 132         if (WARN_ON(!parent))
 133                 return;
 134
 135         pos = pci_pcie_cap(parent);
 136         pci_read_config_byte(parent, pos +  PCI_EXP_LNKCTL, &aspm);
 137         if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
 138                 ah->aspm_enabled = true;
 139                 /* Initialize PCIe PM and SERDES registers. */
 140                 ath9k_hw_configpcipowersave(ah, 0, 0);
 141         }
 142 }
 143
 144 static const struct ath_bus_ops ath_pci_bus_ops = {
 145         .ath_bus_type = ATH_PCI,
 146         .read_cachesize = ath_pci_read_cachesize,
 147         .eeprom_read = ath_pci_eeprom_read,
 148         .bt_coex_prep = ath_pci_bt_coex_prep,
 149         .extn_synch_en = ath_pci_extn_synch_enable,
 150         .aspm_init = ath_pci_aspm_init,
 151 };
 152
 153 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 154 {
 155         void __iomem *mem;
 156         struct ath_softc *sc;
 157         struct ieee80211_hw *hw;
 158         u8 csz;
 159         u16 subsysid;
 160         u32 val;
 161         int ret = 0;
 162         char hw_name[64];
 163
 164         if (pci_enable_device(pdev))
 165                 return -EIO;
 166
 167         ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 168         if (ret) {
 169                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
 170                 goto err_dma;
 171         }
 172
 173         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 174         if (ret) {
 175                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
 176                         "DMA enable failed\n");
 177                 goto err_dma;
 178         }
 179
 180         /*
 181          * Cache line size is used to size and align various
 182          * structures used to communicate with the hardware.
 183          */
 184         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 185         if (csz == 0) {
 186                 /*
 187                  * Linux 2.4.18 (at least) writes the cache line size
 188                  * register as a 16-bit wide register which is wrong.
 189                  * We must have this setup properly for rx buffer
 190                  * DMA to work so force a reasonable value here if it
 191                  * comes up zero.
 192                  */
 193                 csz = L1_CACHE_BYTES / sizeof(u32);
 194                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 195         }
 196         /*
 197          * The default setting of latency timer yields poor results,
 198          * set it to the value used by other systems. It may be worth
 199          * tweaking this setting more.
 200          */
 201         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 202
 203         pci_set_master(pdev);
 204
 205         /*
 206          * Disable the RETRY_TIMEOUT register (0x41) to keep
 207          * PCI Tx retries from interfering with C3 CPU state.
 208          */
 209         pci_read_config_dword(pdev, 0x40, &val);
 210         if ((val & 0x0000ff00) != 0)
 211                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 212
 213         ret = pci_request_region(pdev, 0, "ath9k");
 214         if (ret) {
 215                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 216                 ret = -ENODEV;
 217                 goto err_region;
 218         }
 219
 220         mem = pci_iomap(pdev, 0, 0);
 221         if (!mem) {
 222                 printk(KERN_ERR "PCI memory map error\n") ;
 223                 ret = -EIO;
 224                 goto err_iomap;
 225         }
 226
 227         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
 228         if (!hw) {
 229                 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
 230                 ret = -ENOMEM;
 231                 goto err_alloc_hw;
 232         }
 233
 234         SET_IEEE80211_DEV(hw, &pdev->dev);
 235         pci_set_drvdata(pdev, hw);
 236
 237         sc = hw->priv;
 238         sc->hw = hw;
 239         sc->dev = &pdev->dev;
 240         sc->mem = mem;
 241
 242         /* Will be cleared in ath9k_start() */
 243         sc->sc_flags |= SC_OP_INVALID;
 244
 245         ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
 246         if (ret) {
 247                 dev_err(&pdev->dev, "request_irq failed\n");
 248                 goto err_irq;
 249         }
 250
 251         sc->irq = pdev->irq;
 252
 253         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
 254         ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
 255         if (ret) {
 256                 dev_err(&pdev->dev, "Failed to initialize device\n");
 257                 goto err_init;
 258         }
 259
 260         ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
 261         wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
 262                    hw_name, (unsigned long)mem, pdev->irq);
 263
 264         return 0;
 265
 266 err_init:
 267         free_irq(sc->irq, sc);
 268 err_irq:
 269         ieee80211_free_hw(hw);
 270 err_alloc_hw:
 271         pci_iounmap(pdev, mem);
 272 err_iomap:
 273         pci_release_region(pdev, 0);
 274 err_region:
 275         /* Nothing */
 276 err_dma:
 277         pci_disable_device(pdev);
 278         return ret;
 279 }
 280
 281 static void ath_pci_remove(struct pci_dev *pdev)
 282 {
 283         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 284         struct ath_softc *sc = hw->priv;
 285         void __iomem *mem = sc->mem;
 286
 287         if (!is_ath9k_unloaded)
 288                 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
 289         ath9k_deinit_device(sc);
 290         free_irq(sc->irq, sc);
 291         ieee80211_free_hw(sc->hw);
 292
 293         pci_iounmap(pdev, mem);
 294         pci_disable_device(pdev);
 295         pci_release_region(pdev, 0);
 296 }
 297
 298 #ifdef CONFIG_PM
 299
 300 static int ath_pci_suspend(struct device *device)
 301 {
 302         struct pci_dev *pdev = to_pci_dev(device);
 303         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 304         struct ath_softc *sc = hw->priv;
 305
 306         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 307
 308         /* The device has to be moved to FULLSLEEP forcibly.
 309          * Otherwise the chip never moved to full sleep,
 310          * when no interface is up.
 311          */
 312         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 313
 314         return 0;
 315 }
 316
 317 static int ath_pci_resume(struct device *device)
 318 {
 319         struct pci_dev *pdev = to_pci_dev(device);
 320         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 321         struct ath_softc *sc = hw->priv;
 322         u32 val;
 323
 324         /*
 325          * Suspend/Resume resets the PCI configuration space, so we have to
 326          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 327          * PCI Tx retries from interfering with C3 CPU state
 328          */
 329         pci_read_config_dword(pdev, 0x40, &val);
 330         if ((val & 0x0000ff00) != 0)
 331                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 332
 333         /* Enable LED */
 334         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
 335                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 336         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 337
 338           /*
 339            * Reset key cache to sane defaults (all entries cleared) instead of
 340            * semi-random values after suspend/resume.
 341            */
 342         ath9k_ps_wakeup(sc);
 343         ath9k_init_crypto(sc);
 344         ath9k_ps_restore(sc);
 345
 346         sc->ps_idle = true;
 347         ath_radio_disable(sc, hw);
 348
 349         return 0;
 350 }
 351
 352 static const struct dev_pm_ops ath9k_pm_ops = {
 353         .suspend = ath_pci_suspend,
 354         .resume = ath_pci_resume,
 355         .freeze = ath_pci_suspend,
 356         .thaw = ath_pci_resume,
 357         .poweroff = ath_pci_suspend,
 358         .restore = ath_pci_resume,
 359 };
 360
 361 #define ATH9K_PM_OPS    (&ath9k_pm_ops)
 362
 363 #else /* !CONFIG_PM */
 364
 365 #define ATH9K_PM_OPS    NULL
 366
 367 #endif /* !CONFIG_PM */
 368
 369
 370 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 371
 372 static struct pci_driver ath_pci_driver = {
 373         .name       = "ath9k",
 374         .id_table   = ath_pci_id_table,
 375         .probe      = ath_pci_probe,
 376         .remove     = ath_pci_remove,
 377         .driver.pm  = ATH9K_PM_OPS,
 378 };
 379
 380 int ath_pci_init(void)
 381 {
 382         return pci_register_driver(&ath_pci_driver);
 383 }
 384
 385 void ath_pci_exit(void)
 386 {
 387         pci_unregister_driver(&ath_pci_driver);
 388 }