include/media/omap3isp.h

   1 /*
   2  * omap3isp.h
   3  *
   4  * TI OMAP3 ISP - Platform data
   5  *
   6  * Copyright (C) 2011 Nokia Corporation
   7  *
   8  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   9  *           Sakari Ailus <sakari.ailus@iki.fi>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23  * 02110-1301 USA
  24  */
  25
  26 #ifndef __MEDIA_OMAP3ISP_H__
  27 #define __MEDIA_OMAP3ISP_H__
  28
  29 struct i2c_board_info;
  30 struct isp_device;
  31
  32 #define ISP_XCLK_NONE                   0
  33 #define ISP_XCLK_A                      1
  34 #define ISP_XCLK_B                      2
  35
  36 enum isp_interface_type {
  37         ISP_INTERFACE_PARALLEL,
  38         ISP_INTERFACE_CSI2A_PHY2,
  39         ISP_INTERFACE_CCP2B_PHY1,
  40         ISP_INTERFACE_CCP2B_PHY2,
  41         ISP_INTERFACE_CSI2C_PHY1,
  42 };
  43
  44 enum {
  45         ISP_LANE_SHIFT_0 = 0,
  46         ISP_LANE_SHIFT_2 = 1,
  47         ISP_LANE_SHIFT_4 = 2,
  48         ISP_LANE_SHIFT_6 = 3,
  49 };
  50
  51 /**
  52  * struct isp_parallel_platform_data - Parallel interface platform data
  53  * @data_lane_shift: Data lane shifter
  54  *              ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
  55  *              ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
  56  *              ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
  57  *              ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
  58  * @clk_pol: Pixel clock polarity
  59  *              0 - Sample on rising edge, 1 - Sample on falling edge
  60  * @hs_pol: Horizontal synchronization polarity
  61  *              0 - Active high, 1 - Active low
  62  * @vs_pol: Vertical synchronization polarity
  63  *              0 - Active high, 1 - Active low
  64  * @data_pol: Data polarity
  65  *              0 - Normal, 1 - One's complement
  66  */
  67 struct isp_parallel_platform_data {
  68         unsigned int data_lane_shift:2;
  69         unsigned int clk_pol:1;
  70         unsigned int hs_pol:1;
  71         unsigned int vs_pol:1;
  72         unsigned int data_pol:1;
  73 };
  74
  75 enum {
  76         ISP_CCP2_PHY_DATA_CLOCK = 0,
  77         ISP_CCP2_PHY_DATA_STROBE = 1,
  78 };
  79
  80 enum {
  81         ISP_CCP2_MODE_MIPI = 0,
  82         ISP_CCP2_MODE_CCP2 = 1,
  83 };
  84
  85 /**
  86  * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
  87  * @pos: position of the lane
  88  * @pol: polarity of the lane
  89  */
  90 struct isp_csiphy_lane {
  91         u8 pos;
  92         u8 pol;
  93 };
  94
  95 #define ISP_CSIPHY1_NUM_DATA_LANES      1
  96 #define ISP_CSIPHY2_NUM_DATA_LANES      2
  97
  98 /**
  99  * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
 100  * @data: Configuration of one or two data lanes
 101  * @clk: Clock lane configuration
 102  */
 103 struct isp_csiphy_lanes_cfg {
 104         struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
 105         struct isp_csiphy_lane clk;
 106 };
 107
 108 /**
 109  * struct isp_ccp2_platform_data - CCP2 interface platform data
 110  * @strobe_clk_pol: Strobe/clock polarity
 111  *              0 - Non Inverted, 1 - Inverted
 112  * @crc: Enable the cyclic redundancy check
 113  * @ccp2_mode: Enable CCP2 compatibility mode
 114  *              ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
 115  *              ISP_CCP2_MODE_CCP2 - CCP2 mode
 116  * @phy_layer: Physical layer selection
 117  *              ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
 118  *              ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
 119  * @vpclk_div: Video port output clock control
 120  */
 121 struct isp_ccp2_platform_data {
 122         unsigned int strobe_clk_pol:1;
 123         unsigned int crc:1;
 124         unsigned int ccp2_mode:1;
 125         unsigned int phy_layer:1;
 126         unsigned int vpclk_div:2;
 127         struct isp_csiphy_lanes_cfg lanecfg;
 128 };
 129
 130 /**
 131  * struct isp_csi2_platform_data - CSI2 interface platform data
 132  * @crc: Enable the cyclic redundancy check
 133  * @vpclk_div: Video port output clock control
 134  */
 135 struct isp_csi2_platform_data {
 136         unsigned crc:1;
 137         unsigned vpclk_div:2;
 138         struct isp_csiphy_lanes_cfg lanecfg;
 139 };
 140
 141 struct isp_subdev_i2c_board_info {
 142         struct i2c_board_info *board_info;
 143         int i2c_adapter_id;
 144 };
 145
 146 struct isp_v4l2_subdevs_group {
 147         struct isp_subdev_i2c_board_info *subdevs;
 148         enum isp_interface_type interface;
 149         union {
 150                 struct isp_parallel_platform_data parallel;
 151                 struct isp_ccp2_platform_data ccp2;
 152                 struct isp_csi2_platform_data csi2;
 153         } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
 154 };
 155
 156 struct isp_platform_data {
 157         struct isp_v4l2_subdevs_group *subdevs;
 158         void (*set_constraints)(struct isp_device *isp, bool enable);
 159 };
 160
 161 #endif  /* __MEDIA_OMAP3ISP_H__ */