?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
iwlagn: implement synchronous firmware load
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
blob12cd5e0352bc333d4938eaa495cce94a1b5b8c5a
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
70 /*
71 * module name, copyright, version, etc.
72 */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88
89 static int iwlagn_ant_coupling;
90 static bool iwlagn_bt_ch_announce = 1;
91
92 void iwl_update_chain_flags(struct iwl_priv *priv)
93 {
94 struct iwl_rxon_context *ctx;
95
96 if (priv->cfg->ops->hcmd->set_rxon_chain) {
97 for_each_context(priv, ctx) {
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
99 if (ctx->active.rx_chain != ctx->staging.rx_chain)
100 iwlcore_commit_rxon(priv, ctx);
101 }
102 }
103 }
104
105 static void iwl_clear_free_frames(struct iwl_priv *priv)
106 {
107 struct list_head *element;
108
109 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
110 priv->frames_count);
111
112 while (!list_empty(&priv->free_frames)) {
113 element = priv->free_frames.next;
114 list_del(element);
115 kfree(list_entry(element, struct iwl_frame, list));
116 priv->frames_count--;
117 }
118
119 if (priv->frames_count) {
120 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
121 priv->frames_count);
122 priv->frames_count = 0;
123 }
124 }
125
126 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
127 {
128 struct iwl_frame *frame;
129 struct list_head *element;
130 if (list_empty(&priv->free_frames)) {
131 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
132 if (!frame) {
133 IWL_ERR(priv, "Could not allocate frame!\n");
134 return NULL;
135 }
136
137 priv->frames_count++;
138 return frame;
139 }
140
141 element = priv->free_frames.next;
142 list_del(element);
143 return list_entry(element, struct iwl_frame, list);
144 }
145
146 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
147 {
148 memset(frame, 0, sizeof(*frame));
149 list_add(&frame->list, &priv->free_frames);
150 }
151
152 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
153 struct ieee80211_hdr *hdr,
154 int left)
155 {
156 lockdep_assert_held(&priv->mutex);
157
158 if (!priv->beacon_skb)
159 return 0;
160
161 if (priv->beacon_skb->len > left)
162 return 0;
163
164 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
165
166 return priv->beacon_skb->len;
167 }
168
169 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
170 static void iwl_set_beacon_tim(struct iwl_priv *priv,
171 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
172 u8 *beacon, u32 frame_size)
173 {
174 u16 tim_idx;
175 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
176
177 /*
178 * The index is relative to frame start but we start looking at the
179 * variable-length part of the beacon.
180 */
181 tim_idx = mgmt->u.beacon.variable - beacon;
182
183 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
184 while ((tim_idx < (frame_size - 2)) &&
185 (beacon[tim_idx] != WLAN_EID_TIM))
186 tim_idx += beacon[tim_idx+1] + 2;
187
188 /* If TIM field was found, set variables */
189 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
190 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
191 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
192 } else
193 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
194 }
195
196 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
197 struct iwl_frame *frame)
198 {
199 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
200 u32 frame_size;
201 u32 rate_flags;
202 u32 rate;
203 /*
204 * We have to set up the TX command, the TX Beacon command, and the
205 * beacon contents.
206 */
207
208 lockdep_assert_held(&priv->mutex);
209
210 if (!priv->beacon_ctx) {
211 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
212 return 0;
213 }
214
215 /* Initialize memory */
216 tx_beacon_cmd = &frame->u.beacon;
217 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
218
219 /* Set up TX beacon contents */
220 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
221 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
222 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
223 return 0;
224 if (!frame_size)
225 return 0;
226
227 /* Set up TX command fields */
228 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
229 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
230 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
231 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
232 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
233
234 /* Set up TX beacon command fields */
235 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
236 frame_size);
237
238 /* Set up packet rate and flags */
239 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
240 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
241 priv->hw_params.valid_tx_ant);
242 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
243 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
244 rate_flags |= RATE_MCS_CCK_MSK;
245 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
246 rate_flags);
247
248 return sizeof(*tx_beacon_cmd) + frame_size;
249 }
250
251 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
252 {
253 struct iwl_frame *frame;
254 unsigned int frame_size;
255 int rc;
256 struct iwl_host_cmd cmd = {
257 .id = REPLY_TX_BEACON,
258 .flags = CMD_SIZE_HUGE,
259 };
260
261 frame = iwl_get_free_frame(priv);
262 if (!frame) {
263 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
264 "command.\n");
265 return -ENOMEM;
266 }
267
268 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
269 if (!frame_size) {
270 IWL_ERR(priv, "Error configuring the beacon command\n");
271 iwl_free_frame(priv, frame);
272 return -EINVAL;
273 }
274
275 cmd.len = frame_size;
276 cmd.data = &frame->u.cmd[0];
277
278 rc = iwl_send_cmd_sync(priv, &cmd);
279
280 iwl_free_frame(priv, frame);
281
282 return rc;
283 }
284
285 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
286 {
287 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
288
289 dma_addr_t addr = get_unaligned_le32(&tb->lo);
290 if (sizeof(dma_addr_t) > sizeof(u32))
291 addr |=
292 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
293
294 return addr;
295 }
296
297 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
298 {
299 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
300
301 return le16_to_cpu(tb->hi_n_len) >> 4;
302 }
303
304 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
305 dma_addr_t addr, u16 len)
306 {
307 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
308 u16 hi_n_len = len << 4;
309
310 put_unaligned_le32(addr, &tb->lo);
311 if (sizeof(dma_addr_t) > sizeof(u32))
312 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
313
314 tb->hi_n_len = cpu_to_le16(hi_n_len);
315
316 tfd->num_tbs = idx + 1;
317 }
318
319 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
320 {
321 return tfd->num_tbs & 0x1f;
322 }
323
324 /**
325 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
326 * @priv - driver private data
327 * @txq - tx queue
328 *
329 * Does NOT advance any TFD circular buffer read/write indexes
330 * Does NOT free the TFD itself (which is within circular buffer)
331 */
332 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
333 {
334 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
335 struct iwl_tfd *tfd;
336 struct pci_dev *dev = priv->pci_dev;
337 int index = txq->q.read_ptr;
338 int i;
339 int num_tbs;
340
341 tfd = &tfd_tmp[index];
342
343 /* Sanity check on number of chunks */
344 num_tbs = iwl_tfd_get_num_tbs(tfd);
345
346 if (num_tbs >= IWL_NUM_OF_TBS) {
347 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
348 /* @todo issue fatal error, it is quite serious situation */
349 return;
350 }
351
352 /* Unmap tx_cmd */
353 if (num_tbs)
354 pci_unmap_single(dev,
355 dma_unmap_addr(&txq->meta[index], mapping),
356 dma_unmap_len(&txq->meta[index], len),
357 PCI_DMA_BIDIRECTIONAL);
358
359 /* Unmap chunks, if any. */
360 for (i = 1; i < num_tbs; i++)
361 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
362 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
363
364 /* free SKB */
365 if (txq->txb) {
366 struct sk_buff *skb;
367
368 skb = txq->txb[txq->q.read_ptr].skb;
369
370 /* can be called from irqs-disabled context */
371 if (skb) {
372 dev_kfree_skb_any(skb);
373 txq->txb[txq->q.read_ptr].skb = NULL;
374 }
375 }
376 }
377
378 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
379 struct iwl_tx_queue *txq,
380 dma_addr_t addr, u16 len,
381 u8 reset, u8 pad)
382 {
383 struct iwl_queue *q;
384 struct iwl_tfd *tfd, *tfd_tmp;
385 u32 num_tbs;
386
387 q = &txq->q;
388 tfd_tmp = (struct iwl_tfd *)txq->tfds;
389 tfd = &tfd_tmp[q->write_ptr];
390
391 if (reset)
392 memset(tfd, 0, sizeof(*tfd));
393
394 num_tbs = iwl_tfd_get_num_tbs(tfd);
395
396 /* Each TFD can point to a maximum 20 Tx buffers */
397 if (num_tbs >= IWL_NUM_OF_TBS) {
398 IWL_ERR(priv, "Error can not send more than %d chunks\n",
399 IWL_NUM_OF_TBS);
400 return -EINVAL;
401 }
402
403 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
404 return -EINVAL;
405
406 if (unlikely(addr & ~IWL_TX_DMA_MASK))
407 IWL_ERR(priv, "Unaligned address = %llx\n",
408 (unsigned long long)addr);
409
410 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
411
412 return 0;
413 }
414
415 /*
416 * Tell nic where to find circular buffer of Tx Frame Descriptors for
417 * given Tx queue, and enable the DMA channel used for that queue.
418 *
419 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
420 * channels supported in hardware.
421 */
422 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
423 struct iwl_tx_queue *txq)
424 {
425 int txq_id = txq->q.id;
426
427 /* Circular buffer (TFD queue in DRAM) physical base address */
428 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
429 txq->q.dma_addr >> 8);
430
431 return 0;
432 }
433
434 static void iwl_bg_beacon_update(struct work_struct *work)
435 {
436 struct iwl_priv *priv =
437 container_of(work, struct iwl_priv, beacon_update);
438 struct sk_buff *beacon;
439
440 mutex_lock(&priv->mutex);
441 if (!priv->beacon_ctx) {
442 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
443 goto out;
444 }
445
446 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
447 /*
448 * The ucode will send beacon notifications even in
449 * IBSS mode, but we don't want to process them. But
450 * we need to defer the type check to here due to
451 * requiring locking around the beacon_ctx access.
452 */
453 goto out;
454 }
455
456 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
457 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
458 if (!beacon) {
459 IWL_ERR(priv, "update beacon failed -- keeping old\n");
460 goto out;
461 }
462
463 /* new beacon skb is allocated every time; dispose previous.*/
464 dev_kfree_skb(priv->beacon_skb);
465
466 priv->beacon_skb = beacon;
467
468 iwlagn_send_beacon_cmd(priv);
469 out:
470 mutex_unlock(&priv->mutex);
471 }
472
473 static void iwl_bg_bt_runtime_config(struct work_struct *work)
474 {
475 struct iwl_priv *priv =
476 container_of(work, struct iwl_priv, bt_runtime_config);
477
478 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
479 return;
480
481 /* dont send host command if rf-kill is on */
482 if (!iwl_is_ready_rf(priv))
483 return;
484 priv->cfg->ops->hcmd->send_bt_config(priv);
485 }
486
487 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
488 {
489 struct iwl_priv *priv =
490 container_of(work, struct iwl_priv, bt_full_concurrency);
491 struct iwl_rxon_context *ctx;
492
493 mutex_lock(&priv->mutex);
494
495 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
496 goto out;
497
498 /* dont send host command if rf-kill is on */
499 if (!iwl_is_ready_rf(priv))
500 goto out;
501
502 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
503 priv->bt_full_concurrent ?
504 "full concurrency" : "3-wire");
505
506 /*
507 * LQ & RXON updated cmds must be sent before BT Config cmd
508 * to avoid 3-wire collisions
509 */
510 for_each_context(priv, ctx) {
511 if (priv->cfg->ops->hcmd->set_rxon_chain)
512 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
513 iwlcore_commit_rxon(priv, ctx);
514 }
515
516 priv->cfg->ops->hcmd->send_bt_config(priv);
517 out:
518 mutex_unlock(&priv->mutex);
519 }
520
521 /**
522 * iwl_bg_statistics_periodic - Timer callback to queue statistics
523 *
524 * This callback is provided in order to send a statistics request.
525 *
526 * This timer function is continually reset to execute within
527 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
528 * was received. We need to ensure we receive the statistics in order
529 * to update the temperature used for calibrating the TXPOWER.
530 */
531 static void iwl_bg_statistics_periodic(unsigned long data)
532 {
533 struct iwl_priv *priv = (struct iwl_priv *)data;
534
535 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
536 return;
537
538 /* dont send host command if rf-kill is on */
539 if (!iwl_is_ready_rf(priv))
540 return;
541
542 iwl_send_statistics_request(priv, CMD_ASYNC, false);
543 }
544
545
546 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
547 u32 start_idx, u32 num_events,
548 u32 mode)
549 {
550 u32 i;
551 u32 ptr; /* SRAM byte address of log data */
552 u32 ev, time, data; /* event log data */
553 unsigned long reg_flags;
554
555 if (mode == 0)
556 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
557 else
558 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
559
560 /* Make sure device is powered up for SRAM reads */
561 spin_lock_irqsave(&priv->reg_lock, reg_flags);
562 if (iwl_grab_nic_access(priv)) {
563 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
564 return;
565 }
566
567 /* Set starting address; reads will auto-increment */
568 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
569 rmb();
570
571 /*
572 * "time" is actually "data" for mode 0 (no timestamp).
573 * place event id # at far right for easier visual parsing.
574 */
575 for (i = 0; i < num_events; i++) {
576 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
577 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
578 if (mode == 0) {
579 trace_iwlwifi_dev_ucode_cont_event(priv,
580 0, time, ev);
581 } else {
582 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
583 trace_iwlwifi_dev_ucode_cont_event(priv,
584 time, data, ev);
585 }
586 }
587 /* Allow device to power down */
588 iwl_release_nic_access(priv);
589 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
590 }
591
592 static void iwl_continuous_event_trace(struct iwl_priv *priv)
593 {
594 u32 capacity; /* event log capacity in # entries */
595 u32 base; /* SRAM byte address of event log header */
596 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
597 u32 num_wraps; /* # times uCode wrapped to top of log */
598 u32 next_entry; /* index of next entry to be written by uCode */
599
600 base = priv->device_pointers.error_event_table;
601 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
602 capacity = iwl_read_targ_mem(priv, base);
603 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
604 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
605 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
606 } else
607 return;
608
609 if (num_wraps == priv->event_log.num_wraps) {
610 iwl_print_cont_event_trace(priv,
611 base, priv->event_log.next_entry,
612 next_entry - priv->event_log.next_entry,
613 mode);
614 priv->event_log.non_wraps_count++;
615 } else {
616 if ((num_wraps - priv->event_log.num_wraps) > 1)
617 priv->event_log.wraps_more_count++;
618 else
619 priv->event_log.wraps_once_count++;
620 trace_iwlwifi_dev_ucode_wrap_event(priv,
621 num_wraps - priv->event_log.num_wraps,
622 next_entry, priv->event_log.next_entry);
623 if (next_entry < priv->event_log.next_entry) {
624 iwl_print_cont_event_trace(priv, base,
625 priv->event_log.next_entry,
626 capacity - priv->event_log.next_entry,
627 mode);
628
629 iwl_print_cont_event_trace(priv, base, 0,
630 next_entry, mode);
631 } else {
632 iwl_print_cont_event_trace(priv, base,
633 next_entry, capacity - next_entry,
634 mode);
635
636 iwl_print_cont_event_trace(priv, base, 0,
637 next_entry, mode);
638 }
639 }
640 priv->event_log.num_wraps = num_wraps;
641 priv->event_log.next_entry = next_entry;
642 }
643
644 /**
645 * iwl_bg_ucode_trace - Timer callback to log ucode event
646 *
647 * The timer is continually set to execute every
648 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
649 * this function is to perform continuous uCode event logging operation
650 * if enabled
651 */
652 static void iwl_bg_ucode_trace(unsigned long data)
653 {
654 struct iwl_priv *priv = (struct iwl_priv *)data;
655
656 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
657 return;
658
659 if (priv->event_log.ucode_trace) {
660 iwl_continuous_event_trace(priv);
661 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
662 mod_timer(&priv->ucode_trace,
663 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
664 }
665 }
666
667 static void iwl_bg_tx_flush(struct work_struct *work)
668 {
669 struct iwl_priv *priv =
670 container_of(work, struct iwl_priv, tx_flush);
671
672 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
673 return;
674
675 /* do nothing if rf-kill is on */
676 if (!iwl_is_ready_rf(priv))
677 return;
678
679 if (priv->cfg->ops->lib->txfifo_flush) {
680 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
681 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
682 }
683 }
684
685 /**
686 * iwl_rx_handle - Main entry function for receiving responses from uCode
687 *
688 * Uses the priv->rx_handlers callback function array to invoke
689 * the appropriate handlers, including command responses,
690 * frame-received notifications, and other notifications.
691 */
692 static void iwl_rx_handle(struct iwl_priv *priv)
693 {
694 struct iwl_rx_mem_buffer *rxb;
695 struct iwl_rx_packet *pkt;
696 struct iwl_rx_queue *rxq = &priv->rxq;
697 u32 r, i;
698 int reclaim;
699 unsigned long flags;
700 u8 fill_rx = 0;
701 u32 count = 8;
702 int total_empty;
703
704 /* uCode's read index (stored in shared DRAM) indicates the last Rx
705 * buffer that the driver may process (last buffer filled by ucode). */
706 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
707 i = rxq->read;
708
709 /* Rx interrupt, but nothing sent from uCode */
710 if (i == r)
711 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
712
713 /* calculate total frames need to be restock after handling RX */
714 total_empty = r - rxq->write_actual;
715 if (total_empty < 0)
716 total_empty += RX_QUEUE_SIZE;
717
718 if (total_empty > (RX_QUEUE_SIZE / 2))
719 fill_rx = 1;
720
721 while (i != r) {
722 int len;
723
724 rxb = rxq->queue[i];
725
726 /* If an RXB doesn't have a Rx queue slot associated with it,
727 * then a bug has been introduced in the queue refilling
728 * routines -- catch it here */
729 if (WARN_ON(rxb == NULL)) {
730 i = (i + 1) & RX_QUEUE_MASK;
731 continue;
732 }
733
734 rxq->queue[i] = NULL;
735
736 pci_unmap_page(priv->pci_dev, rxb->page_dma,
737 PAGE_SIZE << priv->hw_params.rx_page_order,
738 PCI_DMA_FROMDEVICE);
739 pkt = rxb_addr(rxb);
740
741 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
742 len += sizeof(u32); /* account for status word */
743 trace_iwlwifi_dev_rx(priv, pkt, len);
744
745 /* Reclaim a command buffer only if this packet is a response
746 * to a (driver-originated) command.
747 * If the packet (e.g. Rx frame) originated from uCode,
748 * there is no command buffer to reclaim.
749 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
750 * but apparently a few don't get set; catch them here. */
751 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
752 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
753 (pkt->hdr.cmd != REPLY_RX) &&
754 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
755 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
756 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
757 (pkt->hdr.cmd != REPLY_TX);
758
759 /*
760 * Do the notification wait before RX handlers so
761 * even if the RX handler consumes the RXB we have
762 * access to it in the notification wait entry.
763 */
764 if (!list_empty(&priv->_agn.notif_waits)) {
765 struct iwl_notification_wait *w;
766
767 spin_lock(&priv->_agn.notif_wait_lock);
768 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
769 if (w->cmd == pkt->hdr.cmd) {
770 w->triggered = true;
771 if (w->fn)
772 w->fn(priv, pkt, w->fn_data);
773 }
774 }
775 spin_unlock(&priv->_agn.notif_wait_lock);
776
777 wake_up_all(&priv->_agn.notif_waitq);
778 }
779
780 /* Based on type of command response or notification,
781 * handle those that need handling via function in
782 * rx_handlers table. See iwl_setup_rx_handlers() */
783 if (priv->rx_handlers[pkt->hdr.cmd]) {
784 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
785 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
786 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
787 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
788 } else {
789 /* No handling needed */
790 IWL_DEBUG_RX(priv,
791 "r %d i %d No handler needed for %s, 0x%02x\n",
792 r, i, get_cmd_string(pkt->hdr.cmd),
793 pkt->hdr.cmd);
794 }
795
796 /*
797 * XXX: After here, we should always check rxb->page
798 * against NULL before touching it or its virtual
799 * memory (pkt). Because some rx_handler might have
800 * already taken or freed the pages.
801 */
802
803 if (reclaim) {
804 /* Invoke any callbacks, transfer the buffer to caller,
805 * and fire off the (possibly) blocking iwl_send_cmd()
806 * as we reclaim the driver command queue */
807 if (rxb->page)
808 iwl_tx_cmd_complete(priv, rxb);
809 else
810 IWL_WARN(priv, "Claim null rxb?\n");
811 }
812
813 /* Reuse the page if possible. For notification packets and
814 * SKBs that fail to Rx correctly, add them back into the
815 * rx_free list for reuse later. */
816 spin_lock_irqsave(&rxq->lock, flags);
817 if (rxb->page != NULL) {
818 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
819 0, PAGE_SIZE << priv->hw_params.rx_page_order,
820 PCI_DMA_FROMDEVICE);
821 list_add_tail(&rxb->list, &rxq->rx_free);
822 rxq->free_count++;
823 } else
824 list_add_tail(&rxb->list, &rxq->rx_used);
825
826 spin_unlock_irqrestore(&rxq->lock, flags);
827
828 i = (i + 1) & RX_QUEUE_MASK;
829 /* If there are a lot of unused frames,
830 * restock the Rx queue so ucode wont assert. */
831 if (fill_rx) {
832 count++;
833 if (count >= 8) {
834 rxq->read = i;
835 iwlagn_rx_replenish_now(priv);
836 count = 0;
837 }
838 }
839 }
840
841 /* Backtrack one entry */
842 rxq->read = i;
843 if (fill_rx)
844 iwlagn_rx_replenish_now(priv);
845 else
846 iwlagn_rx_queue_restock(priv);
847 }
848
849 /* tasklet for iwlagn interrupt */
850 static void iwl_irq_tasklet(struct iwl_priv *priv)
851 {
852 u32 inta = 0;
853 u32 handled = 0;
854 unsigned long flags;
855 u32 i;
856 #ifdef CONFIG_IWLWIFI_DEBUG
857 u32 inta_mask;
858 #endif
859
860 spin_lock_irqsave(&priv->lock, flags);
861
862 /* Ack/clear/reset pending uCode interrupts.
863 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
864 */
865 /* There is a hardware bug in the interrupt mask function that some
866 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
867 * they are disabled in the CSR_INT_MASK register. Furthermore the
868 * ICT interrupt handling mechanism has another bug that might cause
869 * these unmasked interrupts fail to be detected. We workaround the
870 * hardware bugs here by ACKing all the possible interrupts so that
871 * interrupt coalescing can still be achieved.
872 */
873 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
874
875 inta = priv->_agn.inta;
876
877 #ifdef CONFIG_IWLWIFI_DEBUG
878 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
879 /* just for debug */
880 inta_mask = iwl_read32(priv, CSR_INT_MASK);
881 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
882 inta, inta_mask);
883 }
884 #endif
885
886 spin_unlock_irqrestore(&priv->lock, flags);
887
888 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
889 priv->_agn.inta = 0;
890
891 /* Now service all interrupt bits discovered above. */
892 if (inta & CSR_INT_BIT_HW_ERR) {
893 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
894
895 /* Tell the device to stop sending interrupts */
896 iwl_disable_interrupts(priv);
897
898 priv->isr_stats.hw++;
899 iwl_irq_handle_error(priv);
900
901 handled |= CSR_INT_BIT_HW_ERR;
902
903 return;
904 }
905
906 #ifdef CONFIG_IWLWIFI_DEBUG
907 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
908 /* NIC fires this, but we don't use it, redundant with WAKEUP */
909 if (inta & CSR_INT_BIT_SCD) {
910 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
911 "the frame/frames.\n");
912 priv->isr_stats.sch++;
913 }
914
915 /* Alive notification via Rx interrupt will do the real work */
916 if (inta & CSR_INT_BIT_ALIVE) {
917 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
918 priv->isr_stats.alive++;
919 }
920 }
921 #endif
922 /* Safely ignore these bits for debug checks below */
923 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
924
925 /* HW RF KILL switch toggled */
926 if (inta & CSR_INT_BIT_RF_KILL) {
927 int hw_rf_kill = 0;
928 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
929 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
930 hw_rf_kill = 1;
931
932 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
933 hw_rf_kill ? "disable radio" : "enable radio");
934
935 priv->isr_stats.rfkill++;
936
937 /* driver only loads ucode once setting the interface up.
938 * the driver allows loading the ucode even if the radio
939 * is killed. Hence update the killswitch state here. The
940 * rfkill handler will care about restarting if needed.
941 */
942 if (!test_bit(STATUS_ALIVE, &priv->status)) {
943 if (hw_rf_kill)
944 set_bit(STATUS_RF_KILL_HW, &priv->status);
945 else
946 clear_bit(STATUS_RF_KILL_HW, &priv->status);
947 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
948 }
949
950 handled |= CSR_INT_BIT_RF_KILL;
951 }
952
953 /* Chip got too hot and stopped itself */
954 if (inta & CSR_INT_BIT_CT_KILL) {
955 IWL_ERR(priv, "Microcode CT kill error detected.\n");
956 priv->isr_stats.ctkill++;
957 handled |= CSR_INT_BIT_CT_KILL;
958 }
959
960 /* Error detected by uCode */
961 if (inta & CSR_INT_BIT_SW_ERR) {
962 IWL_ERR(priv, "Microcode SW error detected. "
963 " Restarting 0x%X.\n", inta);
964 priv->isr_stats.sw++;
965 iwl_irq_handle_error(priv);
966 handled |= CSR_INT_BIT_SW_ERR;
967 }
968
969 /* uCode wakes up after power-down sleep */
970 if (inta & CSR_INT_BIT_WAKEUP) {
971 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
972 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
973 for (i = 0; i < priv->hw_params.max_txq_num; i++)
974 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
975
976 priv->isr_stats.wakeup++;
977
978 handled |= CSR_INT_BIT_WAKEUP;
979 }
980
981 /* All uCode command responses, including Tx command responses,
982 * Rx "responses" (frame-received notification), and other
983 * notifications from uCode come through here*/
984 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
985 CSR_INT_BIT_RX_PERIODIC)) {
986 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
987 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
988 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
989 iwl_write32(priv, CSR_FH_INT_STATUS,
990 CSR_FH_INT_RX_MASK);
991 }
992 if (inta & CSR_INT_BIT_RX_PERIODIC) {
993 handled |= CSR_INT_BIT_RX_PERIODIC;
994 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
995 }
996 /* Sending RX interrupt require many steps to be done in the
997 * the device:
998 * 1- write interrupt to current index in ICT table.
999 * 2- dma RX frame.
1000 * 3- update RX shared data to indicate last write index.
1001 * 4- send interrupt.
1002 * This could lead to RX race, driver could receive RX interrupt
1003 * but the shared data changes does not reflect this;
1004 * periodic interrupt will detect any dangling Rx activity.
1005 */
1006
1007 /* Disable periodic interrupt; we use it as just a one-shot. */
1008 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1009 CSR_INT_PERIODIC_DIS);
1010 iwl_rx_handle(priv);
1011
1012 /*
1013 * Enable periodic interrupt in 8 msec only if we received
1014 * real RX interrupt (instead of just periodic int), to catch
1015 * any dangling Rx interrupt. If it was just the periodic
1016 * interrupt, there was no dangling Rx activity, and no need
1017 * to extend the periodic interrupt; one-shot is enough.
1018 */
1019 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1020 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1021 CSR_INT_PERIODIC_ENA);
1022
1023 priv->isr_stats.rx++;
1024 }
1025
1026 /* This "Tx" DMA channel is used only for loading uCode */
1027 if (inta & CSR_INT_BIT_FH_TX) {
1028 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1029 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1030 priv->isr_stats.tx++;
1031 handled |= CSR_INT_BIT_FH_TX;
1032 /* Wake up uCode load routine, now that load is complete */
1033 priv->ucode_write_complete = 1;
1034 wake_up_interruptible(&priv->wait_command_queue);
1035 }
1036
1037 if (inta & ~handled) {
1038 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1039 priv->isr_stats.unhandled++;
1040 }
1041
1042 if (inta & ~(priv->inta_mask)) {
1043 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1044 inta & ~priv->inta_mask);
1045 }
1046
1047 /* Re-enable all interrupts */
1048 /* only Re-enable if disabled by irq */
1049 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1050 iwl_enable_interrupts(priv);
1051 /* Re-enable RF_KILL if it occurred */
1052 else if (handled & CSR_INT_BIT_RF_KILL)
1053 iwl_enable_rfkill_int(priv);
1054 }
1055
1056 /*****************************************************************************
1057 *
1058 * sysfs attributes
1059 *
1060 *****************************************************************************/
1061
1062 #ifdef CONFIG_IWLWIFI_DEBUG
1063
1064 /*
1065 * The following adds a new attribute to the sysfs representation
1066 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1067 * used for controlling the debug level.
1068 *
1069 * See the level definitions in iwl for details.
1070 *
1071 * The debug_level being managed using sysfs below is a per device debug
1072 * level that is used instead of the global debug level if it (the per
1073 * device debug level) is set.
1074 */
1075 static ssize_t show_debug_level(struct device *d,
1076 struct device_attribute *attr, char *buf)
1077 {
1078 struct iwl_priv *priv = dev_get_drvdata(d);
1079 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1080 }
1081 static ssize_t store_debug_level(struct device *d,
1082 struct device_attribute *attr,
1083 const char *buf, size_t count)
1084 {
1085 struct iwl_priv *priv = dev_get_drvdata(d);
1086 unsigned long val;
1087 int ret;
1088
1089 ret = strict_strtoul(buf, 0, &val);
1090 if (ret)
1091 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1092 else {
1093 priv->debug_level = val;
1094 if (iwl_alloc_traffic_mem(priv))
1095 IWL_ERR(priv,
1096 "Not enough memory to generate traffic log\n");
1097 }
1098 return strnlen(buf, count);
1099 }
1100
1101 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1102 show_debug_level, store_debug_level);
1103
1104
1105 #endif /* CONFIG_IWLWIFI_DEBUG */
1106
1107
1108 static ssize_t show_temperature(struct device *d,
1109 struct device_attribute *attr, char *buf)
1110 {
1111 struct iwl_priv *priv = dev_get_drvdata(d);
1112
1113 if (!iwl_is_alive(priv))
1114 return -EAGAIN;
1115
1116 return sprintf(buf, "%d\n", priv->temperature);
1117 }
1118
1119 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1120
1121 static ssize_t show_tx_power(struct device *d,
1122 struct device_attribute *attr, char *buf)
1123 {
1124 struct iwl_priv *priv = dev_get_drvdata(d);
1125
1126 if (!iwl_is_ready_rf(priv))
1127 return sprintf(buf, "off\n");
1128 else
1129 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1130 }
1131
1132 static ssize_t store_tx_power(struct device *d,
1133 struct device_attribute *attr,
1134 const char *buf, size_t count)
1135 {
1136 struct iwl_priv *priv = dev_get_drvdata(d);
1137 unsigned long val;
1138 int ret;
1139
1140 ret = strict_strtoul(buf, 10, &val);
1141 if (ret)
1142 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1143 else {
1144 ret = iwl_set_tx_power(priv, val, false);
1145 if (ret)
1146 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1147 ret);
1148 else
1149 ret = count;
1150 }
1151 return ret;
1152 }
1153
1154 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1155
1156 static struct attribute *iwl_sysfs_entries[] = {
1157 &dev_attr_temperature.attr,
1158 &dev_attr_tx_power.attr,
1159 #ifdef CONFIG_IWLWIFI_DEBUG
1160 &dev_attr_debug_level.attr,
1161 #endif
1162 NULL
1163 };
1164
1165 static struct attribute_group iwl_attribute_group = {
1166 .name = NULL, /* put in device directory */
1167 .attrs = iwl_sysfs_entries,
1168 };
1169
1170 /******************************************************************************
1171 *
1172 * uCode download functions
1173 *
1174 ******************************************************************************/
1175
1176 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1177 {
1178 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1179 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1180 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1181 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1182 }
1183
1184 struct iwlagn_ucode_capabilities {
1185 u32 max_probe_length;
1186 u32 standard_phy_calibration_size;
1187 u32 flags;
1188 };
1189
1190 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1191 static int iwl_mac_setup_register(struct iwl_priv *priv,
1192 struct iwlagn_ucode_capabilities *capa);
1193
1194 #define UCODE_EXPERIMENTAL_INDEX 100
1195 #define UCODE_EXPERIMENTAL_TAG "exp"
1196
1197 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1198 {
1199 const char *name_pre = priv->cfg->fw_name_pre;
1200 char tag[8];
1201
1202 if (first) {
1203 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1204 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1205 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1206 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1207 #endif
1208 priv->fw_index = priv->cfg->ucode_api_max;
1209 sprintf(tag, "%d", priv->fw_index);
1210 } else {
1211 priv->fw_index--;
1212 sprintf(tag, "%d", priv->fw_index);
1213 }
1214
1215 if (priv->fw_index < priv->cfg->ucode_api_min) {
1216 IWL_ERR(priv, "no suitable firmware found!\n");
1217 return -ENOENT;
1218 }
1219
1220 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1221
1222 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1223 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1224 ? "EXPERIMENTAL " : "",
1225 priv->firmware_name);
1226
1227 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1228 &priv->pci_dev->dev, GFP_KERNEL, priv,
1229 iwl_ucode_callback);
1230 }
1231
1232 struct iwlagn_firmware_pieces {
1233 const void *inst, *data, *init, *init_data;
1234 size_t inst_size, data_size, init_size, init_data_size;
1235
1236 u32 build;
1237
1238 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1239 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1240 };
1241
1242 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1243 const struct firmware *ucode_raw,
1244 struct iwlagn_firmware_pieces *pieces)
1245 {
1246 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1247 u32 api_ver, hdr_size;
1248 const u8 *src;
1249
1250 priv->ucode_ver = le32_to_cpu(ucode->ver);
1251 api_ver = IWL_UCODE_API(priv->ucode_ver);
1252
1253 switch (api_ver) {
1254 default:
1255 hdr_size = 28;
1256 if (ucode_raw->size < hdr_size) {
1257 IWL_ERR(priv, "File size too small!\n");
1258 return -EINVAL;
1259 }
1260 pieces->build = le32_to_cpu(ucode->u.v2.build);
1261 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1262 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1263 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1264 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1265 src = ucode->u.v2.data;
1266 break;
1267 case 0:
1268 case 1:
1269 case 2:
1270 hdr_size = 24;
1271 if (ucode_raw->size < hdr_size) {
1272 IWL_ERR(priv, "File size too small!\n");
1273 return -EINVAL;
1274 }
1275 pieces->build = 0;
1276 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1277 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1278 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1279 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1280 src = ucode->u.v1.data;
1281 break;
1282 }
1283
1284 /* Verify size of file vs. image size info in file's header */
1285 if (ucode_raw->size != hdr_size + pieces->inst_size +
1286 pieces->data_size + pieces->init_size +
1287 pieces->init_data_size) {
1288
1289 IWL_ERR(priv,
1290 "uCode file size %d does not match expected size\n",
1291 (int)ucode_raw->size);
1292 return -EINVAL;
1293 }
1294
1295 pieces->inst = src;
1296 src += pieces->inst_size;
1297 pieces->data = src;
1298 src += pieces->data_size;
1299 pieces->init = src;
1300 src += pieces->init_size;
1301 pieces->init_data = src;
1302 src += pieces->init_data_size;
1303
1304 return 0;
1305 }
1306
1307 static int iwlagn_wanted_ucode_alternative = 1;
1308
1309 static int iwlagn_load_firmware(struct iwl_priv *priv,
1310 const struct firmware *ucode_raw,
1311 struct iwlagn_firmware_pieces *pieces,
1312 struct iwlagn_ucode_capabilities *capa)
1313 {
1314 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1315 struct iwl_ucode_tlv *tlv;
1316 size_t len = ucode_raw->size;
1317 const u8 *data;
1318 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1319 u64 alternatives;
1320 u32 tlv_len;
1321 enum iwl_ucode_tlv_type tlv_type;
1322 const u8 *tlv_data;
1323
1324 if (len < sizeof(*ucode)) {
1325 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1326 return -EINVAL;
1327 }
1328
1329 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1330 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1331 le32_to_cpu(ucode->magic));
1332 return -EINVAL;
1333 }
1334
1335 /*
1336 * Check which alternatives are present, and "downgrade"
1337 * when the chosen alternative is not present, warning
1338 * the user when that happens. Some files may not have
1339 * any alternatives, so don't warn in that case.
1340 */
1341 alternatives = le64_to_cpu(ucode->alternatives);
1342 tmp = wanted_alternative;
1343 if (wanted_alternative > 63)
1344 wanted_alternative = 63;
1345 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1346 wanted_alternative--;
1347 if (wanted_alternative && wanted_alternative != tmp)
1348 IWL_WARN(priv,
1349 "uCode alternative %d not available, choosing %d\n",
1350 tmp, wanted_alternative);
1351
1352 priv->ucode_ver = le32_to_cpu(ucode->ver);
1353 pieces->build = le32_to_cpu(ucode->build);
1354 data = ucode->data;
1355
1356 len -= sizeof(*ucode);
1357
1358 while (len >= sizeof(*tlv)) {
1359 u16 tlv_alt;
1360
1361 len -= sizeof(*tlv);
1362 tlv = (void *)data;
1363
1364 tlv_len = le32_to_cpu(tlv->length);
1365 tlv_type = le16_to_cpu(tlv->type);
1366 tlv_alt = le16_to_cpu(tlv->alternative);
1367 tlv_data = tlv->data;
1368
1369 if (len < tlv_len) {
1370 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1371 len, tlv_len);
1372 return -EINVAL;
1373 }
1374 len -= ALIGN(tlv_len, 4);
1375 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1376
1377 /*
1378 * Alternative 0 is always valid.
1379 *
1380 * Skip alternative TLVs that are not selected.
1381 */
1382 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1383 continue;
1384
1385 switch (tlv_type) {
1386 case IWL_UCODE_TLV_INST:
1387 pieces->inst = tlv_data;
1388 pieces->inst_size = tlv_len;
1389 break;
1390 case IWL_UCODE_TLV_DATA:
1391 pieces->data = tlv_data;
1392 pieces->data_size = tlv_len;
1393 break;
1394 case IWL_UCODE_TLV_INIT:
1395 pieces->init = tlv_data;
1396 pieces->init_size = tlv_len;
1397 break;
1398 case IWL_UCODE_TLV_INIT_DATA:
1399 pieces->init_data = tlv_data;
1400 pieces->init_data_size = tlv_len;
1401 break;
1402 case IWL_UCODE_TLV_BOOT:
1403 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1404 break;
1405 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1406 if (tlv_len != sizeof(u32))
1407 goto invalid_tlv_len;
1408 capa->max_probe_length =
1409 le32_to_cpup((__le32 *)tlv_data);
1410 break;
1411 case IWL_UCODE_TLV_PAN:
1412 if (tlv_len)
1413 goto invalid_tlv_len;
1414 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1415 break;
1416 case IWL_UCODE_TLV_FLAGS:
1417 /* must be at least one u32 */
1418 if (tlv_len < sizeof(u32))
1419 goto invalid_tlv_len;
1420 /* and a proper number of u32s */
1421 if (tlv_len % sizeof(u32))
1422 goto invalid_tlv_len;
1423 /*
1424 * This driver only reads the first u32 as
1425 * right now no more features are defined,
1426 * if that changes then either the driver
1427 * will not work with the new firmware, or
1428 * it'll not take advantage of new features.
1429 */
1430 capa->flags = le32_to_cpup((__le32 *)tlv_data);
1431 break;
1432 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1433 if (tlv_len != sizeof(u32))
1434 goto invalid_tlv_len;
1435 pieces->init_evtlog_ptr =
1436 le32_to_cpup((__le32 *)tlv_data);
1437 break;
1438 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1439 if (tlv_len != sizeof(u32))
1440 goto invalid_tlv_len;
1441 pieces->init_evtlog_size =
1442 le32_to_cpup((__le32 *)tlv_data);
1443 break;
1444 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1445 if (tlv_len != sizeof(u32))
1446 goto invalid_tlv_len;
1447 pieces->init_errlog_ptr =
1448 le32_to_cpup((__le32 *)tlv_data);
1449 break;
1450 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1451 if (tlv_len != sizeof(u32))
1452 goto invalid_tlv_len;
1453 pieces->inst_evtlog_ptr =
1454 le32_to_cpup((__le32 *)tlv_data);
1455 break;
1456 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1457 if (tlv_len != sizeof(u32))
1458 goto invalid_tlv_len;
1459 pieces->inst_evtlog_size =
1460 le32_to_cpup((__le32 *)tlv_data);
1461 break;
1462 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1463 if (tlv_len != sizeof(u32))
1464 goto invalid_tlv_len;
1465 pieces->inst_errlog_ptr =
1466 le32_to_cpup((__le32 *)tlv_data);
1467 break;
1468 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1469 if (tlv_len)
1470 goto invalid_tlv_len;
1471 priv->enhance_sensitivity_table = true;
1472 break;
1473 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1474 if (tlv_len != sizeof(u32))
1475 goto invalid_tlv_len;
1476 capa->standard_phy_calibration_size =
1477 le32_to_cpup((__le32 *)tlv_data);
1478 break;
1479 default:
1480 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1481 break;
1482 }
1483 }
1484
1485 if (len) {
1486 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1487 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1488 return -EINVAL;
1489 }
1490
1491 return 0;
1492
1493 invalid_tlv_len:
1494 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1495 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1496
1497 return -EINVAL;
1498 }
1499
1500 /**
1501 * iwl_ucode_callback - callback when firmware was loaded
1502 *
1503 * If loaded successfully, copies the firmware into buffers
1504 * for the card to fetch (via DMA).
1505 */
1506 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1507 {
1508 struct iwl_priv *priv = context;
1509 struct iwl_ucode_header *ucode;
1510 int err;
1511 struct iwlagn_firmware_pieces pieces;
1512 const unsigned int api_max = priv->cfg->ucode_api_max;
1513 const unsigned int api_min = priv->cfg->ucode_api_min;
1514 u32 api_ver;
1515 char buildstr[25];
1516 u32 build;
1517 struct iwlagn_ucode_capabilities ucode_capa = {
1518 .max_probe_length = 200,
1519 .standard_phy_calibration_size =
1520 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1521 };
1522
1523 memset(&pieces, 0, sizeof(pieces));
1524
1525 if (!ucode_raw) {
1526 if (priv->fw_index <= priv->cfg->ucode_api_max)
1527 IWL_ERR(priv,
1528 "request for firmware file '%s' failed.\n",
1529 priv->firmware_name);
1530 goto try_again;
1531 }
1532
1533 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1534 priv->firmware_name, ucode_raw->size);
1535
1536 /* Make sure that we got at least the API version number */
1537 if (ucode_raw->size < 4) {
1538 IWL_ERR(priv, "File size way too small!\n");
1539 goto try_again;
1540 }
1541
1542 /* Data from ucode file: header followed by uCode images */
1543 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1544
1545 if (ucode->ver)
1546 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1547 else
1548 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1549 &ucode_capa);
1550
1551 if (err)
1552 goto try_again;
1553
1554 api_ver = IWL_UCODE_API(priv->ucode_ver);
1555 build = pieces.build;
1556
1557 /*
1558 * api_ver should match the api version forming part of the
1559 * firmware filename ... but we don't check for that and only rely
1560 * on the API version read from firmware header from here on forward
1561 */
1562 /* no api version check required for experimental uCode */
1563 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1564 if (api_ver < api_min || api_ver > api_max) {
1565 IWL_ERR(priv,
1566 "Driver unable to support your firmware API. "
1567 "Driver supports v%u, firmware is v%u.\n",
1568 api_max, api_ver);
1569 goto try_again;
1570 }
1571
1572 if (api_ver != api_max)
1573 IWL_ERR(priv,
1574 "Firmware has old API version. Expected v%u, "
1575 "got v%u. New firmware can be obtained "
1576 "from http://www.intellinuxwireless.org.\n",
1577 api_max, api_ver);
1578 }
1579
1580 if (build)
1581 sprintf(buildstr, " build %u%s", build,
1582 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1583 ? " (EXP)" : "");
1584 else
1585 buildstr[0] = '\0';
1586
1587 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1588 IWL_UCODE_MAJOR(priv->ucode_ver),
1589 IWL_UCODE_MINOR(priv->ucode_ver),
1590 IWL_UCODE_API(priv->ucode_ver),
1591 IWL_UCODE_SERIAL(priv->ucode_ver),
1592 buildstr);
1593
1594 snprintf(priv->hw->wiphy->fw_version,
1595 sizeof(priv->hw->wiphy->fw_version),
1596 "%u.%u.%u.%u%s",
1597 IWL_UCODE_MAJOR(priv->ucode_ver),
1598 IWL_UCODE_MINOR(priv->ucode_ver),
1599 IWL_UCODE_API(priv->ucode_ver),
1600 IWL_UCODE_SERIAL(priv->ucode_ver),
1601 buildstr);
1602
1603 /*
1604 * For any of the failures below (before allocating pci memory)
1605 * we will try to load a version with a smaller API -- maybe the
1606 * user just got a corrupted version of the latest API.
1607 */
1608
1609 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1610 priv->ucode_ver);
1611 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1612 pieces.inst_size);
1613 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1614 pieces.data_size);
1615 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1616 pieces.init_size);
1617 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1618 pieces.init_data_size);
1619
1620 /* Verify that uCode images will fit in card's SRAM */
1621 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1622 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1623 pieces.inst_size);
1624 goto try_again;
1625 }
1626
1627 if (pieces.data_size > priv->hw_params.max_data_size) {
1628 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1629 pieces.data_size);
1630 goto try_again;
1631 }
1632
1633 if (pieces.init_size > priv->hw_params.max_inst_size) {
1634 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1635 pieces.init_size);
1636 goto try_again;
1637 }
1638
1639 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1640 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1641 pieces.init_data_size);
1642 goto try_again;
1643 }
1644
1645 /* Allocate ucode buffers for card's bus-master loading ... */
1646
1647 /* Runtime instructions and 2 copies of data:
1648 * 1) unmodified from disk
1649 * 2) backup cache for save/restore during power-downs */
1650 priv->ucode_code.len = pieces.inst_size;
1651 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1652
1653 priv->ucode_data.len = pieces.data_size;
1654 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1655
1656 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
1657 goto err_pci_alloc;
1658
1659 /* Initialization instructions and data */
1660 if (pieces.init_size && pieces.init_data_size) {
1661 priv->ucode_init.len = pieces.init_size;
1662 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1663
1664 priv->ucode_init_data.len = pieces.init_data_size;
1665 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1666
1667 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1668 goto err_pci_alloc;
1669 }
1670
1671 /* Now that we can no longer fail, copy information */
1672
1673 /*
1674 * The (size - 16) / 12 formula is based on the information recorded
1675 * for each event, which is of mode 1 (including timestamp) for all
1676 * new microcodes that include this information.
1677 */
1678 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1679 if (pieces.init_evtlog_size)
1680 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1681 else
1682 priv->_agn.init_evtlog_size =
1683 priv->cfg->base_params->max_event_log_size;
1684 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1685 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1686 if (pieces.inst_evtlog_size)
1687 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1688 else
1689 priv->_agn.inst_evtlog_size =
1690 priv->cfg->base_params->max_event_log_size;
1691 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1692
1693 if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1694 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1695 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1696 } else
1697 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1698
1699 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1700 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1701 else
1702 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1703
1704 /* Copy images into buffers for card's bus-master reads ... */
1705
1706 /* Runtime instructions (first block of data in file) */
1707 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1708 pieces.inst_size);
1709 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1710
1711 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1712 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1713
1714 /*
1715 * Runtime data
1716 * NOTE: Copy into backup buffer will be done in iwl_up()
1717 */
1718 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1719 pieces.data_size);
1720 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1721
1722 /* Initialization instructions */
1723 if (pieces.init_size) {
1724 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1725 pieces.init_size);
1726 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1727 }
1728
1729 /* Initialization data */
1730 if (pieces.init_data_size) {
1731 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1732 pieces.init_data_size);
1733 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1734 pieces.init_data_size);
1735 }
1736
1737 /*
1738 * figure out the offset of chain noise reset and gain commands
1739 * base on the size of standard phy calibration commands table size
1740 */
1741 if (ucode_capa.standard_phy_calibration_size >
1742 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1743 ucode_capa.standard_phy_calibration_size =
1744 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1745
1746 priv->_agn.phy_calib_chain_noise_reset_cmd =
1747 ucode_capa.standard_phy_calibration_size;
1748 priv->_agn.phy_calib_chain_noise_gain_cmd =
1749 ucode_capa.standard_phy_calibration_size + 1;
1750
1751 /**************************************************
1752 * This is still part of probe() in a sense...
1753 *
1754 * 9. Setup and register with mac80211 and debugfs
1755 **************************************************/
1756 err = iwl_mac_setup_register(priv, &ucode_capa);
1757 if (err)
1758 goto out_unbind;
1759
1760 err = iwl_dbgfs_register(priv, DRV_NAME);
1761 if (err)
1762 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1763
1764 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1765 &iwl_attribute_group);
1766 if (err) {
1767 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1768 goto out_unbind;
1769 }
1770
1771 /* We have our copies now, allow OS release its copies */
1772 release_firmware(ucode_raw);
1773 complete(&priv->_agn.firmware_loading_complete);
1774 return;
1775
1776 try_again:
1777 /* try next, if any */
1778 if (iwl_request_firmware(priv, false))
1779 goto out_unbind;
1780 release_firmware(ucode_raw);
1781 return;
1782
1783 err_pci_alloc:
1784 IWL_ERR(priv, "failed to allocate pci memory\n");
1785 iwl_dealloc_ucode_pci(priv);
1786 out_unbind:
1787 complete(&priv->_agn.firmware_loading_complete);
1788 device_release_driver(&priv->pci_dev->dev);
1789 release_firmware(ucode_raw);
1790 }
1791
1792 static const char *desc_lookup_text[] = {
1793 "OK",
1794 "FAIL",
1795 "BAD_PARAM",
1796 "BAD_CHECKSUM",
1797 "NMI_INTERRUPT_WDG",
1798 "SYSASSERT",
1799 "FATAL_ERROR",
1800 "BAD_COMMAND",
1801 "HW_ERROR_TUNE_LOCK",
1802 "HW_ERROR_TEMPERATURE",
1803 "ILLEGAL_CHAN_FREQ",
1804 "VCC_NOT_STABLE",
1805 "FH_ERROR",
1806 "NMI_INTERRUPT_HOST",
1807 "NMI_INTERRUPT_ACTION_PT",
1808 "NMI_INTERRUPT_UNKNOWN",
1809 "UCODE_VERSION_MISMATCH",
1810 "HW_ERROR_ABS_LOCK",
1811 "HW_ERROR_CAL_LOCK_FAIL",
1812 "NMI_INTERRUPT_INST_ACTION_PT",
1813 "NMI_INTERRUPT_DATA_ACTION_PT",
1814 "NMI_TRM_HW_ER",
1815 "NMI_INTERRUPT_TRM",
1816 "NMI_INTERRUPT_BREAK_POINT"
1817 "DEBUG_0",
1818 "DEBUG_1",
1819 "DEBUG_2",
1820 "DEBUG_3",
1821 };
1822
1823 static struct { char *name; u8 num; } advanced_lookup[] = {
1824 { "NMI_INTERRUPT_WDG", 0x34 },
1825 { "SYSASSERT", 0x35 },
1826 { "UCODE_VERSION_MISMATCH", 0x37 },
1827 { "BAD_COMMAND", 0x38 },
1828 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1829 { "FATAL_ERROR", 0x3D },
1830 { "NMI_TRM_HW_ERR", 0x46 },
1831 { "NMI_INTERRUPT_TRM", 0x4C },
1832 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1833 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1834 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1835 { "NMI_INTERRUPT_HOST", 0x66 },
1836 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1837 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1838 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1839 { "ADVANCED_SYSASSERT", 0 },
1840 };
1841
1842 static const char *desc_lookup(u32 num)
1843 {
1844 int i;
1845 int max = ARRAY_SIZE(desc_lookup_text);
1846
1847 if (num < max)
1848 return desc_lookup_text[num];
1849
1850 max = ARRAY_SIZE(advanced_lookup) - 1;
1851 for (i = 0; i < max; i++) {
1852 if (advanced_lookup[i].num == num)
1853 break;;
1854 }
1855 return advanced_lookup[i].name;
1856 }
1857
1858 #define ERROR_START_OFFSET (1 * sizeof(u32))
1859 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1860
1861 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1862 {
1863 u32 data2, line;
1864 u32 desc, time, count, base, data1;
1865 u32 blink1, blink2, ilink1, ilink2;
1866 u32 pc, hcmd;
1867 struct iwl_error_event_table table;
1868
1869 base = priv->device_pointers.error_event_table;
1870 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
1871 if (!base)
1872 base = priv->_agn.init_errlog_ptr;
1873 } else {
1874 if (!base)
1875 base = priv->_agn.inst_errlog_ptr;
1876 }
1877
1878 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1879 IWL_ERR(priv,
1880 "Not valid error log pointer 0x%08X for %s uCode\n",
1881 base,
1882 (priv->ucode_type == UCODE_SUBTYPE_INIT)
1883 ? "Init" : "RT");
1884 return;
1885 }
1886
1887 iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
1888
1889 count = table.valid;
1890
1891 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1892 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1893 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1894 priv->status, count);
1895 }
1896
1897 desc = table.error_id;
1898 priv->isr_stats.err_code = desc;
1899 pc = table.pc;
1900 blink1 = table.blink1;
1901 blink2 = table.blink2;
1902 ilink1 = table.ilink1;
1903 ilink2 = table.ilink2;
1904 data1 = table.data1;
1905 data2 = table.data2;
1906 line = table.line;
1907 time = table.tsf_low;
1908 hcmd = table.hcmd;
1909
1910 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1911 blink1, blink2, ilink1, ilink2);
1912
1913 IWL_ERR(priv, "Desc Time "
1914 "data1 data2 line\n");
1915 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1916 desc_lookup(desc), desc, time, data1, data2, line);
1917 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1918 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1919 pc, blink1, blink2, ilink1, ilink2, hcmd);
1920 }
1921
1922 #define EVENT_START_OFFSET (4 * sizeof(u32))
1923
1924 /**
1925 * iwl_print_event_log - Dump error event log to syslog
1926 *
1927 */
1928 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1929 u32 num_events, u32 mode,
1930 int pos, char **buf, size_t bufsz)
1931 {
1932 u32 i;
1933 u32 base; /* SRAM byte address of event log header */
1934 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1935 u32 ptr; /* SRAM byte address of log data */
1936 u32 ev, time, data; /* event log data */
1937 unsigned long reg_flags;
1938
1939 if (num_events == 0)
1940 return pos;
1941
1942 base = priv->device_pointers.log_event_table;
1943 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
1944 if (!base)
1945 base = priv->_agn.init_evtlog_ptr;
1946 } else {
1947 if (!base)
1948 base = priv->_agn.inst_evtlog_ptr;
1949 }
1950
1951 if (mode == 0)
1952 event_size = 2 * sizeof(u32);
1953 else
1954 event_size = 3 * sizeof(u32);
1955
1956 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1957
1958 /* Make sure device is powered up for SRAM reads */
1959 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1960 iwl_grab_nic_access(priv);
1961
1962 /* Set starting address; reads will auto-increment */
1963 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1964 rmb();
1965
1966 /* "time" is actually "data" for mode 0 (no timestamp).
1967 * place event id # at far right for easier visual parsing. */
1968 for (i = 0; i < num_events; i++) {
1969 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1970 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1971 if (mode == 0) {
1972 /* data, ev */
1973 if (bufsz) {
1974 pos += scnprintf(*buf + pos, bufsz - pos,
1975 "EVT_LOG:0x%08x:%04u\n",
1976 time, ev);
1977 } else {
1978 trace_iwlwifi_dev_ucode_event(priv, 0,
1979 time, ev);
1980 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1981 time, ev);
1982 }
1983 } else {
1984 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1985 if (bufsz) {
1986 pos += scnprintf(*buf + pos, bufsz - pos,
1987 "EVT_LOGT:%010u:0x%08x:%04u\n",
1988 time, data, ev);
1989 } else {
1990 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1991 time, data, ev);
1992 trace_iwlwifi_dev_ucode_event(priv, time,
1993 data, ev);
1994 }
1995 }
1996 }
1997
1998 /* Allow device to power down */
1999 iwl_release_nic_access(priv);
2000 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2001 return pos;
2002 }
2003
2004 /**
2005 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2006 */
2007 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2008 u32 num_wraps, u32 next_entry,
2009 u32 size, u32 mode,
2010 int pos, char **buf, size_t bufsz)
2011 {
2012 /*
2013 * display the newest DEFAULT_LOG_ENTRIES entries
2014 * i.e the entries just before the next ont that uCode would fill.
2015 */
2016 if (num_wraps) {
2017 if (next_entry < size) {
2018 pos = iwl_print_event_log(priv,
2019 capacity - (size - next_entry),
2020 size - next_entry, mode,
2021 pos, buf, bufsz);
2022 pos = iwl_print_event_log(priv, 0,
2023 next_entry, mode,
2024 pos, buf, bufsz);
2025 } else
2026 pos = iwl_print_event_log(priv, next_entry - size,
2027 size, mode, pos, buf, bufsz);
2028 } else {
2029 if (next_entry < size) {
2030 pos = iwl_print_event_log(priv, 0, next_entry,
2031 mode, pos, buf, bufsz);
2032 } else {
2033 pos = iwl_print_event_log(priv, next_entry - size,
2034 size, mode, pos, buf, bufsz);
2035 }
2036 }
2037 return pos;
2038 }
2039
2040 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2041
2042 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2043 char **buf, bool display)
2044 {
2045 u32 base; /* SRAM byte address of event log header */
2046 u32 capacity; /* event log capacity in # entries */
2047 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2048 u32 num_wraps; /* # times uCode wrapped to top of log */
2049 u32 next_entry; /* index of next entry to be written by uCode */
2050 u32 size; /* # entries that we'll print */
2051 u32 logsize;
2052 int pos = 0;
2053 size_t bufsz = 0;
2054
2055 base = priv->device_pointers.log_event_table;
2056 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
2057 logsize = priv->_agn.init_evtlog_size;
2058 if (!base)
2059 base = priv->_agn.init_evtlog_ptr;
2060 } else {
2061 logsize = priv->_agn.inst_evtlog_size;
2062 if (!base)
2063 base = priv->_agn.inst_evtlog_ptr;
2064 }
2065
2066 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2067 IWL_ERR(priv,
2068 "Invalid event log pointer 0x%08X for %s uCode\n",
2069 base,
2070 (priv->ucode_type == UCODE_SUBTYPE_INIT)
2071 ? "Init" : "RT");
2072 return -EINVAL;
2073 }
2074
2075 /* event log header */
2076 capacity = iwl_read_targ_mem(priv, base);
2077 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2078 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2079 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2080
2081 if (capacity > logsize) {
2082 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2083 capacity, logsize);
2084 capacity = logsize;
2085 }
2086
2087 if (next_entry > logsize) {
2088 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2089 next_entry, logsize);
2090 next_entry = logsize;
2091 }
2092
2093 size = num_wraps ? capacity : next_entry;
2094
2095 /* bail out if nothing in log */
2096 if (size == 0) {
2097 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2098 return pos;
2099 }
2100
2101 /* enable/disable bt channel inhibition */
2102 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2103
2104 #ifdef CONFIG_IWLWIFI_DEBUG
2105 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2106 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2107 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2108 #else
2109 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2110 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2111 #endif
2112 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2113 size);
2114
2115 #ifdef CONFIG_IWLWIFI_DEBUG
2116 if (display) {
2117 if (full_log)
2118 bufsz = capacity * 48;
2119 else
2120 bufsz = size * 48;
2121 *buf = kmalloc(bufsz, GFP_KERNEL);
2122 if (!*buf)
2123 return -ENOMEM;
2124 }
2125 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2126 /*
2127 * if uCode has wrapped back to top of log,
2128 * start at the oldest entry,
2129 * i.e the next one that uCode would fill.
2130 */
2131 if (num_wraps)
2132 pos = iwl_print_event_log(priv, next_entry,
2133 capacity - next_entry, mode,
2134 pos, buf, bufsz);
2135 /* (then/else) start at top of log */
2136 pos = iwl_print_event_log(priv, 0,
2137 next_entry, mode, pos, buf, bufsz);
2138 } else
2139 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2140 next_entry, size, mode,
2141 pos, buf, bufsz);
2142 #else
2143 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2144 next_entry, size, mode,
2145 pos, buf, bufsz);
2146 #endif
2147 return pos;
2148 }
2149
2150 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2151 {
2152 struct iwl_ct_kill_config cmd;
2153 struct iwl_ct_kill_throttling_config adv_cmd;
2154 unsigned long flags;
2155 int ret = 0;
2156
2157 spin_lock_irqsave(&priv->lock, flags);
2158 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2159 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2160 spin_unlock_irqrestore(&priv->lock, flags);
2161 priv->thermal_throttle.ct_kill_toggle = false;
2162
2163 if (priv->cfg->base_params->support_ct_kill_exit) {
2164 adv_cmd.critical_temperature_enter =
2165 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2166 adv_cmd.critical_temperature_exit =
2167 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2168
2169 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2170 sizeof(adv_cmd), &adv_cmd);
2171 if (ret)
2172 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2173 else
2174 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2175 "succeeded, "
2176 "critical temperature enter is %d,"
2177 "exit is %d\n",
2178 priv->hw_params.ct_kill_threshold,
2179 priv->hw_params.ct_kill_exit_threshold);
2180 } else {
2181 cmd.critical_temperature_R =
2182 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2183
2184 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2185 sizeof(cmd), &cmd);
2186 if (ret)
2187 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2188 else
2189 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2190 "succeeded, "
2191 "critical temperature is %d\n",
2192 priv->hw_params.ct_kill_threshold);
2193 }
2194 }
2195
2196 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2197 {
2198 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2199 struct iwl_host_cmd cmd = {
2200 .id = CALIBRATION_CFG_CMD,
2201 .len = sizeof(struct iwl_calib_cfg_cmd),
2202 .data = &calib_cfg_cmd,
2203 };
2204
2205 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2206 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2207 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2208
2209 return iwl_send_cmd(priv, &cmd);
2210 }
2211
2212
2213 /**
2214 * iwl_alive_start - called after REPLY_ALIVE notification received
2215 * from protocol/runtime uCode (initialization uCode's
2216 * Alive gets handled by iwl_init_alive_start()).
2217 */
2218 static int iwl_alive_start(struct iwl_priv *priv)
2219 {
2220 int ret = 0;
2221 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2222
2223 iwl_reset_ict(priv);
2224
2225 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2226
2227 /* After the ALIVE response, we can send host commands to the uCode */
2228 set_bit(STATUS_ALIVE, &priv->status);
2229
2230 /* Enable watchdog to monitor the driver tx queues */
2231 iwl_setup_watchdog(priv);
2232
2233 if (iwl_is_rfkill(priv))
2234 return -ERFKILL;
2235
2236 /* download priority table before any calibration request */
2237 if (priv->cfg->bt_params &&
2238 priv->cfg->bt_params->advanced_bt_coexist) {
2239 /* Configure Bluetooth device coexistence support */
2240 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2241 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2242 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2243 priv->cfg->ops->hcmd->send_bt_config(priv);
2244 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2245 iwlagn_send_prio_tbl(priv);
2246
2247 /* FIXME: w/a to force change uCode BT state machine */
2248 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2249 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2250 if (ret)
2251 return ret;
2252 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2253 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2254 if (ret)
2255 return ret;
2256 }
2257 if (priv->hw_params.calib_rt_cfg)
2258 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2259
2260 ieee80211_wake_queues(priv->hw);
2261
2262 priv->active_rate = IWL_RATES_MASK;
2263
2264 /* Configure Tx antenna selection based on H/W config */
2265 if (priv->cfg->ops->hcmd->set_tx_ant)
2266 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2267
2268 if (iwl_is_associated_ctx(ctx)) {
2269 struct iwl_rxon_cmd *active_rxon =
2270 (struct iwl_rxon_cmd *)&ctx->active;
2271 /* apply any changes in staging */
2272 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2273 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2274 } else {
2275 struct iwl_rxon_context *tmp;
2276 /* Initialize our rx_config data */
2277 for_each_context(priv, tmp)
2278 iwl_connection_init_rx_config(priv, tmp);
2279
2280 if (priv->cfg->ops->hcmd->set_rxon_chain)
2281 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2282 }
2283
2284 if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2285 !priv->cfg->bt_params->advanced_bt_coexist)) {
2286 /*
2287 * default is 2-wire BT coexexistence support
2288 */
2289 priv->cfg->ops->hcmd->send_bt_config(priv);
2290 }
2291
2292 iwl_reset_run_time_calib(priv);
2293
2294 set_bit(STATUS_READY, &priv->status);
2295
2296 /* Configure the adapter for unassociated operation */
2297 ret = iwlcore_commit_rxon(priv, ctx);
2298 if (ret)
2299 return ret;
2300
2301 /* At this point, the NIC is initialized and operational */
2302 iwl_rf_kill_ct_config(priv);
2303
2304 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2305
2306 return iwl_power_update_mode(priv, true);
2307 }
2308
2309 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2310
2311 static void __iwl_down(struct iwl_priv *priv)
2312 {
2313 int exit_pending;
2314
2315 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2316
2317 iwl_scan_cancel_timeout(priv, 200);
2318
2319 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2320
2321 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2322 * to prevent rearm timer */
2323 del_timer_sync(&priv->watchdog);
2324
2325 iwl_clear_ucode_stations(priv, NULL);
2326 iwl_dealloc_bcast_stations(priv);
2327 iwl_clear_driver_stations(priv);
2328
2329 /* reset BT coex data */
2330 priv->bt_status = 0;
2331 if (priv->cfg->bt_params)
2332 priv->bt_traffic_load =
2333 priv->cfg->bt_params->bt_init_traffic_load;
2334 else
2335 priv->bt_traffic_load = 0;
2336 priv->bt_full_concurrent = false;
2337 priv->bt_ci_compliance = 0;
2338
2339 /* Wipe out the EXIT_PENDING status bit if we are not actually
2340 * exiting the module */
2341 if (!exit_pending)
2342 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2343
2344 if (priv->mac80211_registered)
2345 ieee80211_stop_queues(priv->hw);
2346
2347 /* Clear out all status bits but a few that are stable across reset */
2348 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2349 STATUS_RF_KILL_HW |
2350 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2351 STATUS_GEO_CONFIGURED |
2352 test_bit(STATUS_FW_ERROR, &priv->status) <<
2353 STATUS_FW_ERROR |
2354 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2355 STATUS_EXIT_PENDING;
2356
2357 iwlagn_stop_device(priv);
2358
2359 dev_kfree_skb(priv->beacon_skb);
2360 priv->beacon_skb = NULL;
2361
2362 /* clear out any free frames */
2363 iwl_clear_free_frames(priv);
2364 }
2365
2366 static void iwl_down(struct iwl_priv *priv)
2367 {
2368 mutex_lock(&priv->mutex);
2369 __iwl_down(priv);
2370 mutex_unlock(&priv->mutex);
2371
2372 iwl_cancel_deferred_work(priv);
2373 }
2374
2375 #define HW_READY_TIMEOUT (50)
2376
2377 static int iwl_set_hw_ready(struct iwl_priv *priv)
2378 {
2379 int ret = 0;
2380
2381 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2382 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2383
2384 /* See if we got it */
2385 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2386 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2387 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2388 HW_READY_TIMEOUT);
2389 if (ret != -ETIMEDOUT)
2390 priv->hw_ready = true;
2391 else
2392 priv->hw_ready = false;
2393
2394 IWL_DEBUG_INFO(priv, "hardware %s\n",
2395 (priv->hw_ready == 1) ? "ready" : "not ready");
2396 return ret;
2397 }
2398
2399 int iwl_prepare_card_hw(struct iwl_priv *priv)
2400 {
2401 int ret = 0;
2402
2403 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2404
2405 ret = iwl_set_hw_ready(priv);
2406 if (priv->hw_ready)
2407 return ret;
2408
2409 /* If HW is not ready, prepare the conditions to check again */
2410 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2411 CSR_HW_IF_CONFIG_REG_PREPARE);
2412
2413 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2414 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2415 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2416
2417 /* HW should be ready by now, check again. */
2418 if (ret != -ETIMEDOUT)
2419 iwl_set_hw_ready(priv);
2420
2421 return ret;
2422 }
2423
2424 #define MAX_HW_RESTARTS 5
2425
2426 static int __iwl_up(struct iwl_priv *priv)
2427 {
2428 struct iwl_rxon_context *ctx;
2429 int ret;
2430
2431 lockdep_assert_held(&priv->mutex);
2432
2433 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2434 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2435 return -EIO;
2436 }
2437
2438 for_each_context(priv, ctx) {
2439 ret = iwlagn_alloc_bcast_station(priv, ctx);
2440 if (ret) {
2441 iwl_dealloc_bcast_stations(priv);
2442 return ret;
2443 }
2444 }
2445
2446 ret = iwlagn_run_init_ucode(priv);
2447 if (ret) {
2448 IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
2449 goto error;
2450 }
2451
2452 ret = iwlagn_load_ucode_wait_alive(priv,
2453 &priv->ucode_code,
2454 &priv->ucode_data,
2455 UCODE_SUBTYPE_REGULAR,
2456 UCODE_SUBTYPE_REGULAR_NEW);
2457 if (ret) {
2458 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
2459 goto error;
2460 }
2461
2462 ret = iwl_alive_start(priv);
2463 if (ret)
2464 goto error;
2465 return 0;
2466
2467 error:
2468 set_bit(STATUS_EXIT_PENDING, &priv->status);
2469 __iwl_down(priv);
2470 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2471
2472 IWL_ERR(priv, "Unable to initialize device.\n");
2473 return ret;
2474 }
2475
2476
2477 /*****************************************************************************
2478 *
2479 * Workqueue callbacks
2480 *
2481 *****************************************************************************/
2482
2483 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2484 {
2485 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2486 run_time_calib_work);
2487
2488 mutex_lock(&priv->mutex);
2489
2490 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2491 test_bit(STATUS_SCANNING, &priv->status)) {
2492 mutex_unlock(&priv->mutex);
2493 return;
2494 }
2495
2496 if (priv->start_calib) {
2497 iwl_chain_noise_calibration(priv);
2498 iwl_sensitivity_calibration(priv);
2499 }
2500
2501 mutex_unlock(&priv->mutex);
2502 }
2503
2504 static void iwl_bg_restart(struct work_struct *data)
2505 {
2506 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2507
2508 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2509 return;
2510
2511 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2512 struct iwl_rxon_context *ctx;
2513 bool bt_full_concurrent;
2514 u8 bt_ci_compliance;
2515 u8 bt_load;
2516 u8 bt_status;
2517
2518 mutex_lock(&priv->mutex);
2519 for_each_context(priv, ctx)
2520 ctx->vif = NULL;
2521 priv->is_open = 0;
2522
2523 /*
2524 * __iwl_down() will clear the BT status variables,
2525 * which is correct, but when we restart we really
2526 * want to keep them so restore them afterwards.
2527 *
2528 * The restart process will later pick them up and
2529 * re-configure the hw when we reconfigure the BT
2530 * command.
2531 */
2532 bt_full_concurrent = priv->bt_full_concurrent;
2533 bt_ci_compliance = priv->bt_ci_compliance;
2534 bt_load = priv->bt_traffic_load;
2535 bt_status = priv->bt_status;
2536
2537 __iwl_down(priv);
2538
2539 priv->bt_full_concurrent = bt_full_concurrent;
2540 priv->bt_ci_compliance = bt_ci_compliance;
2541 priv->bt_traffic_load = bt_load;
2542 priv->bt_status = bt_status;
2543
2544 mutex_unlock(&priv->mutex);
2545 iwl_cancel_deferred_work(priv);
2546 ieee80211_restart_hw(priv->hw);
2547 } else {
2548 WARN_ON(1);
2549 }
2550 }
2551
2552 static void iwl_bg_rx_replenish(struct work_struct *data)
2553 {
2554 struct iwl_priv *priv =
2555 container_of(data, struct iwl_priv, rx_replenish);
2556
2557 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2558 return;
2559
2560 mutex_lock(&priv->mutex);
2561 iwlagn_rx_replenish(priv);
2562 mutex_unlock(&priv->mutex);
2563 }
2564
2565 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2566 struct ieee80211_channel *chan,
2567 enum nl80211_channel_type channel_type,
2568 unsigned int wait)
2569 {
2570 struct iwl_priv *priv = hw->priv;
2571 int ret;
2572
2573 /* Not supported if we don't have PAN */
2574 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2575 ret = -EOPNOTSUPP;
2576 goto free;
2577 }
2578
2579 /* Not supported on pre-P2P firmware */
2580 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2581 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2582 ret = -EOPNOTSUPP;
2583 goto free;
2584 }
2585
2586 mutex_lock(&priv->mutex);
2587
2588 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2589 /*
2590 * If the PAN context is free, use the normal
2591 * way of doing remain-on-channel offload + TX.
2592 */
2593 ret = 1;
2594 goto out;
2595 }
2596
2597 /* TODO: queue up if scanning? */
2598 if (test_bit(STATUS_SCANNING, &priv->status) ||
2599 priv->_agn.offchan_tx_skb) {
2600 ret = -EBUSY;
2601 goto out;
2602 }
2603
2604 /*
2605 * max_scan_ie_len doesn't include the blank SSID or the header,
2606 * so need to add that again here.
2607 */
2608 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2609 ret = -ENOBUFS;
2610 goto out;
2611 }
2612
2613 priv->_agn.offchan_tx_skb = skb;
2614 priv->_agn.offchan_tx_timeout = wait;
2615 priv->_agn.offchan_tx_chan = chan;
2616
2617 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2618 IWL_SCAN_OFFCH_TX, chan->band);
2619 if (ret)
2620 priv->_agn.offchan_tx_skb = NULL;
2621 out:
2622 mutex_unlock(&priv->mutex);
2623 free:
2624 if (ret < 0)
2625 kfree_skb(skb);
2626
2627 return ret;
2628 }
2629
2630 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2631 {
2632 struct iwl_priv *priv = hw->priv;
2633 int ret;
2634
2635 mutex_lock(&priv->mutex);
2636
2637 if (!priv->_agn.offchan_tx_skb) {
2638 ret = -EINVAL;
2639 goto unlock;
2640 }
2641
2642 priv->_agn.offchan_tx_skb = NULL;
2643
2644 ret = iwl_scan_cancel_timeout(priv, 200);
2645 if (ret)
2646 ret = -EIO;
2647 unlock:
2648 mutex_unlock(&priv->mutex);
2649
2650 return ret;
2651 }
2652
2653 /*****************************************************************************
2654 *
2655 * mac80211 entry point functions
2656 *
2657 *****************************************************************************/
2658
2659 /*
2660 * Not a mac80211 entry point function, but it fits in with all the
2661 * other mac80211 functions grouped here.
2662 */
2663 static int iwl_mac_setup_register(struct iwl_priv *priv,
2664 struct iwlagn_ucode_capabilities *capa)
2665 {
2666 int ret;
2667 struct ieee80211_hw *hw = priv->hw;
2668 struct iwl_rxon_context *ctx;
2669
2670 hw->rate_control_algorithm = "iwl-agn-rs";
2671
2672 /* Tell mac80211 our characteristics */
2673 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2674 IEEE80211_HW_AMPDU_AGGREGATION |
2675 IEEE80211_HW_NEED_DTIM_PERIOD |
2676 IEEE80211_HW_SPECTRUM_MGMT |
2677 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2678
2679 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2680
2681 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2682 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2683
2684 if (priv->cfg->sku & IWL_SKU_N)
2685 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2686 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2687
2688 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2689 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2690
2691 hw->sta_data_size = sizeof(struct iwl_station_priv);
2692 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2693
2694 for_each_context(priv, ctx) {
2695 hw->wiphy->interface_modes |= ctx->interface_modes;
2696 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2697 }
2698
2699 hw->wiphy->max_remain_on_channel_duration = 1000;
2700
2701 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2702 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2703 WIPHY_FLAG_IBSS_RSN;
2704
2705 /*
2706 * For now, disable PS by default because it affects
2707 * RX performance significantly.
2708 */
2709 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2710
2711 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2712 /* we create the 802.11 header and a zero-length SSID element */
2713 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2714
2715 /* Default value; 4 EDCA QOS priorities */
2716 hw->queues = 4;
2717
2718 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2719
2720 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2721 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2722 &priv->bands[IEEE80211_BAND_2GHZ];
2723 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2724 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2725 &priv->bands[IEEE80211_BAND_5GHZ];
2726
2727 iwl_leds_init(priv);
2728
2729 ret = ieee80211_register_hw(priv->hw);
2730 if (ret) {
2731 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2732 return ret;
2733 }
2734 priv->mac80211_registered = 1;
2735
2736 return 0;
2737 }
2738
2739
2740 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2741 {
2742 struct iwl_priv *priv = hw->priv;
2743 int ret;
2744
2745 IWL_DEBUG_MAC80211(priv, "enter\n");
2746
2747 /* we should be verifying the device is ready to be opened */
2748 mutex_lock(&priv->mutex);
2749 ret = __iwl_up(priv);
2750 mutex_unlock(&priv->mutex);
2751 if (ret)
2752 return ret;
2753
2754 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2755
2756 /* Now we should be done, and the READY bit should be set. */
2757 if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
2758 ret = -EIO;
2759
2760 iwlagn_led_enable(priv);
2761
2762 priv->is_open = 1;
2763 IWL_DEBUG_MAC80211(priv, "leave\n");
2764 return 0;
2765 }
2766
2767 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2768 {
2769 struct iwl_priv *priv = hw->priv;
2770
2771 IWL_DEBUG_MAC80211(priv, "enter\n");
2772
2773 if (!priv->is_open)
2774 return;
2775
2776 priv->is_open = 0;
2777
2778 iwl_down(priv);
2779
2780 flush_workqueue(priv->workqueue);
2781
2782 /* User space software may expect getting rfkill changes
2783 * even if interface is down */
2784 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2785 iwl_enable_rfkill_int(priv);
2786
2787 IWL_DEBUG_MAC80211(priv, "leave\n");
2788 }
2789
2790 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2791 {
2792 struct iwl_priv *priv = hw->priv;
2793
2794 IWL_DEBUG_MACDUMP(priv, "enter\n");
2795
2796 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2797 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2798
2799 if (iwlagn_tx_skb(priv, skb))
2800 dev_kfree_skb_any(skb);
2801
2802 IWL_DEBUG_MACDUMP(priv, "leave\n");
2803 }
2804
2805 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2806 struct ieee80211_vif *vif,
2807 struct ieee80211_key_conf *keyconf,
2808 struct ieee80211_sta *sta,
2809 u32 iv32, u16 *phase1key)
2810 {
2811 struct iwl_priv *priv = hw->priv;
2812 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2813
2814 IWL_DEBUG_MAC80211(priv, "enter\n");
2815
2816 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2817 iv32, phase1key);
2818
2819 IWL_DEBUG_MAC80211(priv, "leave\n");
2820 }
2821
2822 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2823 struct ieee80211_vif *vif,
2824 struct ieee80211_sta *sta,
2825 struct ieee80211_key_conf *key)
2826 {
2827 struct iwl_priv *priv = hw->priv;
2828 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2829 struct iwl_rxon_context *ctx = vif_priv->ctx;
2830 int ret;
2831 u8 sta_id;
2832 bool is_default_wep_key = false;
2833
2834 IWL_DEBUG_MAC80211(priv, "enter\n");
2835
2836 if (priv->cfg->mod_params->sw_crypto) {
2837 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2838 return -EOPNOTSUPP;
2839 }
2840
2841 /*
2842 * To support IBSS RSN, don't program group keys in IBSS, the
2843 * hardware will then not attempt to decrypt the frames.
2844 */
2845 if (vif->type == NL80211_IFTYPE_ADHOC &&
2846 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2847 return -EOPNOTSUPP;
2848
2849 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
2850 if (sta_id == IWL_INVALID_STATION)
2851 return -EINVAL;
2852
2853 mutex_lock(&priv->mutex);
2854 iwl_scan_cancel_timeout(priv, 100);
2855
2856 /*
2857 * If we are getting WEP group key and we didn't receive any key mapping
2858 * so far, we are in legacy wep mode (group key only), otherwise we are
2859 * in 1X mode.
2860 * In legacy wep mode, we use another host command to the uCode.
2861 */
2862 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2863 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2864 !sta) {
2865 if (cmd == SET_KEY)
2866 is_default_wep_key = !ctx->key_mapping_keys;
2867 else
2868 is_default_wep_key =
2869 (key->hw_key_idx == HW_KEY_DEFAULT);
2870 }
2871
2872 switch (cmd) {
2873 case SET_KEY:
2874 if (is_default_wep_key)
2875 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
2876 else
2877 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
2878 key, sta_id);
2879
2880 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2881 break;
2882 case DISABLE_KEY:
2883 if (is_default_wep_key)
2884 ret = iwl_remove_default_wep_key(priv, ctx, key);
2885 else
2886 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
2887
2888 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2889 break;
2890 default:
2891 ret = -EINVAL;
2892 }
2893
2894 mutex_unlock(&priv->mutex);
2895 IWL_DEBUG_MAC80211(priv, "leave\n");
2896
2897 return ret;
2898 }
2899
2900 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2901 struct ieee80211_vif *vif,
2902 enum ieee80211_ampdu_mlme_action action,
2903 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2904 u8 buf_size)
2905 {
2906 struct iwl_priv *priv = hw->priv;
2907 int ret = -EINVAL;
2908 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
2909
2910 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2911 sta->addr, tid);
2912
2913 if (!(priv->cfg->sku & IWL_SKU_N))
2914 return -EACCES;
2915
2916 mutex_lock(&priv->mutex);
2917
2918 switch (action) {
2919 case IEEE80211_AMPDU_RX_START:
2920 IWL_DEBUG_HT(priv, "start Rx\n");
2921 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
2922 break;
2923 case IEEE80211_AMPDU_RX_STOP:
2924 IWL_DEBUG_HT(priv, "stop Rx\n");
2925 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
2926 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2927 ret = 0;
2928 break;
2929 case IEEE80211_AMPDU_TX_START:
2930 IWL_DEBUG_HT(priv, "start Tx\n");
2931 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
2932 if (ret == 0) {
2933 priv->_agn.agg_tids_count++;
2934 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2935 priv->_agn.agg_tids_count);
2936 }
2937 break;
2938 case IEEE80211_AMPDU_TX_STOP:
2939 IWL_DEBUG_HT(priv, "stop Tx\n");
2940 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
2941 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2942 priv->_agn.agg_tids_count--;
2943 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2944 priv->_agn.agg_tids_count);
2945 }
2946 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2947 ret = 0;
2948 if (priv->cfg->ht_params &&
2949 priv->cfg->ht_params->use_rts_for_aggregation) {
2950 struct iwl_station_priv *sta_priv =
2951 (void *) sta->drv_priv;
2952 /*
2953 * switch off RTS/CTS if it was previously enabled
2954 */
2955
2956 sta_priv->lq_sta.lq.general_params.flags &=
2957 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2958 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2959 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
2960 }
2961 break;
2962 case IEEE80211_AMPDU_TX_OPERATIONAL:
2963 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
2964
2965 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
2966
2967 /*
2968 * If the limit is 0, then it wasn't initialised yet,
2969 * use the default. We can do that since we take the
2970 * minimum below, and we don't want to go above our
2971 * default due to hardware restrictions.
2972 */
2973 if (sta_priv->max_agg_bufsize == 0)
2974 sta_priv->max_agg_bufsize =
2975 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2976
2977 /*
2978 * Even though in theory the peer could have different
2979 * aggregation reorder buffer sizes for different sessions,
2980 * our ucode doesn't allow for that and has a global limit
2981 * for each station. Therefore, use the minimum of all the
2982 * aggregation sessions and our default value.
2983 */
2984 sta_priv->max_agg_bufsize =
2985 min(sta_priv->max_agg_bufsize, buf_size);
2986
2987 if (priv->cfg->ht_params &&
2988 priv->cfg->ht_params->use_rts_for_aggregation) {
2989 /*
2990 * switch to RTS/CTS if it is the prefer protection
2991 * method for HT traffic
2992 */
2993
2994 sta_priv->lq_sta.lq.general_params.flags |=
2995 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2996 }
2997
2998 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
2999 sta_priv->max_agg_bufsize;
3000
3001 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3002 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3003 ret = 0;
3004 break;
3005 }
3006 mutex_unlock(&priv->mutex);
3007
3008 return ret;
3009 }
3010
3011 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3012 struct ieee80211_vif *vif,
3013 struct ieee80211_sta *sta)
3014 {
3015 struct iwl_priv *priv = hw->priv;
3016 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3017 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3018 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3019 int ret;
3020 u8 sta_id;
3021
3022 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3023 sta->addr);
3024 mutex_lock(&priv->mutex);
3025 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3026 sta->addr);
3027 sta_priv->common.sta_id = IWL_INVALID_STATION;
3028
3029 atomic_set(&sta_priv->pending_frames, 0);
3030 if (vif->type == NL80211_IFTYPE_AP)
3031 sta_priv->client = true;
3032
3033 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3034 is_ap, sta, &sta_id);
3035 if (ret) {
3036 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3037 sta->addr, ret);
3038 /* Should we return success if return code is EEXIST ? */
3039 mutex_unlock(&priv->mutex);
3040 return ret;
3041 }
3042
3043 sta_priv->common.sta_id = sta_id;
3044
3045 /* Initialize rate scaling */
3046 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3047 sta->addr);
3048 iwl_rs_rate_init(priv, sta, sta_id);
3049 mutex_unlock(&priv->mutex);
3050
3051 return 0;
3052 }
3053
3054 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3055 struct ieee80211_channel_switch *ch_switch)
3056 {
3057 struct iwl_priv *priv = hw->priv;
3058 const struct iwl_channel_info *ch_info;
3059 struct ieee80211_conf *conf = &hw->conf;
3060 struct ieee80211_channel *channel = ch_switch->channel;
3061 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3062 /*
3063 * MULTI-FIXME
3064 * When we add support for multiple interfaces, we need to
3065 * revisit this. The channel switch command in the device
3066 * only affects the BSS context, but what does that really
3067 * mean? And what if we get a CSA on the second interface?
3068 * This needs a lot of work.
3069 */
3070 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3071 u16 ch;
3072 unsigned long flags = 0;
3073
3074 IWL_DEBUG_MAC80211(priv, "enter\n");
3075
3076 mutex_lock(&priv->mutex);
3077
3078 if (iwl_is_rfkill(priv))
3079 goto out;
3080
3081 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3082 test_bit(STATUS_SCANNING, &priv->status))
3083 goto out;
3084
3085 if (!iwl_is_associated_ctx(ctx))
3086 goto out;
3087
3088 /* channel switch in progress */
3089 if (priv->switch_rxon.switch_in_progress == true)
3090 goto out;
3091
3092 if (priv->cfg->ops->lib->set_channel_switch) {
3093
3094 ch = channel->hw_value;
3095 if (le16_to_cpu(ctx->active.channel) != ch) {
3096 ch_info = iwl_get_channel_info(priv,
3097 channel->band,
3098 ch);
3099 if (!is_channel_valid(ch_info)) {
3100 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3101 goto out;
3102 }
3103 spin_lock_irqsave(&priv->lock, flags);
3104
3105 priv->current_ht_config.smps = conf->smps_mode;
3106
3107 /* Configure HT40 channels */
3108 ctx->ht.enabled = conf_is_ht(conf);
3109 if (ctx->ht.enabled) {
3110 if (conf_is_ht40_minus(conf)) {
3111 ctx->ht.extension_chan_offset =
3112 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3113 ctx->ht.is_40mhz = true;
3114 } else if (conf_is_ht40_plus(conf)) {
3115 ctx->ht.extension_chan_offset =
3116 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3117 ctx->ht.is_40mhz = true;
3118 } else {
3119 ctx->ht.extension_chan_offset =
3120 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3121 ctx->ht.is_40mhz = false;
3122 }
3123 } else
3124 ctx->ht.is_40mhz = false;
3125
3126 if ((le16_to_cpu(ctx->staging.channel) != ch))
3127 ctx->staging.flags = 0;
3128
3129 iwl_set_rxon_channel(priv, channel, ctx);
3130 iwl_set_rxon_ht(priv, ht_conf);
3131 iwl_set_flags_for_band(priv, ctx, channel->band,
3132 ctx->vif);
3133 spin_unlock_irqrestore(&priv->lock, flags);
3134
3135 iwl_set_rate(priv);
3136 /*
3137 * at this point, staging_rxon has the
3138 * configuration for channel switch
3139 */
3140 if (priv->cfg->ops->lib->set_channel_switch(priv,
3141 ch_switch))
3142 priv->switch_rxon.switch_in_progress = false;
3143 }
3144 }
3145 out:
3146 mutex_unlock(&priv->mutex);
3147 if (!priv->switch_rxon.switch_in_progress)
3148 ieee80211_chswitch_done(ctx->vif, false);
3149 IWL_DEBUG_MAC80211(priv, "leave\n");
3150 }
3151
3152 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3153 unsigned int changed_flags,
3154 unsigned int *total_flags,
3155 u64 multicast)
3156 {
3157 struct iwl_priv *priv = hw->priv;
3158 __le32 filter_or = 0, filter_nand = 0;
3159 struct iwl_rxon_context *ctx;
3160
3161 #define CHK(test, flag) do { \
3162 if (*total_flags & (test)) \
3163 filter_or |= (flag); \
3164 else \
3165 filter_nand |= (flag); \
3166 } while (0)
3167
3168 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3169 changed_flags, *total_flags);
3170
3171 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3172 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3173 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3174 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3175
3176 #undef CHK
3177
3178 mutex_lock(&priv->mutex);
3179
3180 for_each_context(priv, ctx) {
3181 ctx->staging.filter_flags &= ~filter_nand;
3182 ctx->staging.filter_flags |= filter_or;
3183
3184 /*
3185 * Not committing directly because hardware can perform a scan,
3186 * but we'll eventually commit the filter flags change anyway.
3187 */
3188 }
3189
3190 mutex_unlock(&priv->mutex);
3191
3192 /*
3193 * Receiving all multicast frames is always enabled by the
3194 * default flags setup in iwl_connection_init_rx_config()
3195 * since we currently do not support programming multicast
3196 * filters into the device.
3197 */
3198 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3199 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3200 }
3201
3202 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3203 {
3204 struct iwl_priv *priv = hw->priv;
3205
3206 mutex_lock(&priv->mutex);
3207 IWL_DEBUG_MAC80211(priv, "enter\n");
3208
3209 /* do not support "flush" */
3210 if (!priv->cfg->ops->lib->txfifo_flush)
3211 goto done;
3212
3213 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3214 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3215 goto done;
3216 }
3217 if (iwl_is_rfkill(priv)) {
3218 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3219 goto done;
3220 }
3221
3222 /*
3223 * mac80211 will not push any more frames for transmit
3224 * until the flush is completed
3225 */
3226 if (drop) {
3227 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3228 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3229 IWL_ERR(priv, "flush request fail\n");
3230 goto done;
3231 }
3232 }
3233 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3234 iwlagn_wait_tx_queue_empty(priv);
3235 done:
3236 mutex_unlock(&priv->mutex);
3237 IWL_DEBUG_MAC80211(priv, "leave\n");
3238 }
3239
3240 static void iwlagn_disable_roc(struct iwl_priv *priv)
3241 {
3242 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3243 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3244
3245 lockdep_assert_held(&priv->mutex);
3246
3247 if (!ctx->is_active)
3248 return;
3249
3250 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3251 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3252 iwl_set_rxon_channel(priv, chan, ctx);
3253 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3254
3255 priv->_agn.hw_roc_channel = NULL;
3256
3257 iwlcore_commit_rxon(priv, ctx);
3258
3259 ctx->is_active = false;
3260 }
3261
3262 static void iwlagn_bg_roc_done(struct work_struct *work)
3263 {
3264 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3265 _agn.hw_roc_work.work);
3266
3267 mutex_lock(&priv->mutex);
3268 ieee80211_remain_on_channel_expired(priv->hw);
3269 iwlagn_disable_roc(priv);
3270 mutex_unlock(&priv->mutex);
3271 }
3272
3273 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3274 struct ieee80211_channel *channel,
3275 enum nl80211_channel_type channel_type,
3276 int duration)
3277 {
3278 struct iwl_priv *priv = hw->priv;
3279 int err = 0;
3280
3281 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3282 return -EOPNOTSUPP;
3283
3284 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3285 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3286 return -EOPNOTSUPP;
3287
3288 mutex_lock(&priv->mutex);
3289
3290 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3291 test_bit(STATUS_SCAN_HW, &priv->status)) {
3292 err = -EBUSY;
3293 goto out;
3294 }
3295
3296 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3297 priv->_agn.hw_roc_channel = channel;
3298 priv->_agn.hw_roc_chantype = channel_type;
3299 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3300 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3301 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3302 msecs_to_jiffies(duration + 20));
3303
3304 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3305 ieee80211_ready_on_channel(priv->hw);
3306
3307 out:
3308 mutex_unlock(&priv->mutex);
3309
3310 return err;
3311 }
3312
3313 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3314 {
3315 struct iwl_priv *priv = hw->priv;
3316
3317 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3318 return -EOPNOTSUPP;
3319
3320 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3321
3322 mutex_lock(&priv->mutex);
3323 iwlagn_disable_roc(priv);
3324 mutex_unlock(&priv->mutex);
3325
3326 return 0;
3327 }
3328
3329 /*****************************************************************************
3330 *
3331 * driver setup and teardown
3332 *
3333 *****************************************************************************/
3334
3335 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3336 {
3337 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3338
3339 init_waitqueue_head(&priv->wait_command_queue);
3340
3341 INIT_WORK(&priv->restart, iwl_bg_restart);
3342 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3343 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3344 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3345 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3346 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3347 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3348 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3349
3350 iwl_setup_scan_deferred_work(priv);
3351
3352 if (priv->cfg->ops->lib->setup_deferred_work)
3353 priv->cfg->ops->lib->setup_deferred_work(priv);
3354
3355 init_timer(&priv->statistics_periodic);
3356 priv->statistics_periodic.data = (unsigned long)priv;
3357 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3358
3359 init_timer(&priv->ucode_trace);
3360 priv->ucode_trace.data = (unsigned long)priv;
3361 priv->ucode_trace.function = iwl_bg_ucode_trace;
3362
3363 init_timer(&priv->watchdog);
3364 priv->watchdog.data = (unsigned long)priv;
3365 priv->watchdog.function = iwl_bg_watchdog;
3366
3367 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3368 iwl_irq_tasklet, (unsigned long)priv);
3369 }
3370
3371 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3372 {
3373 if (priv->cfg->ops->lib->cancel_deferred_work)
3374 priv->cfg->ops->lib->cancel_deferred_work(priv);
3375
3376 cancel_work_sync(&priv->run_time_calib_work);
3377 cancel_work_sync(&priv->beacon_update);
3378
3379 iwl_cancel_scan_deferred_work(priv);
3380
3381 cancel_work_sync(&priv->bt_full_concurrency);
3382 cancel_work_sync(&priv->bt_runtime_config);
3383
3384 del_timer_sync(&priv->statistics_periodic);
3385 del_timer_sync(&priv->ucode_trace);
3386 }
3387
3388 static void iwl_init_hw_rates(struct iwl_priv *priv,
3389 struct ieee80211_rate *rates)
3390 {
3391 int i;
3392
3393 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3394 rates[i].bitrate = iwl_rates[i].ieee * 5;
3395 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3396 rates[i].hw_value_short = i;
3397 rates[i].flags = 0;
3398 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3399 /*
3400 * If CCK != 1M then set short preamble rate flag.
3401 */
3402 rates[i].flags |=
3403 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3404 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3405 }
3406 }
3407 }
3408
3409 static int iwl_init_drv(struct iwl_priv *priv)
3410 {
3411 int ret;
3412
3413 spin_lock_init(&priv->sta_lock);
3414 spin_lock_init(&priv->hcmd_lock);
3415
3416 INIT_LIST_HEAD(&priv->free_frames);
3417
3418 mutex_init(&priv->mutex);
3419
3420 priv->ieee_channels = NULL;
3421 priv->ieee_rates = NULL;
3422 priv->band = IEEE80211_BAND_2GHZ;
3423
3424 priv->iw_mode = NL80211_IFTYPE_STATION;
3425 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3426 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3427 priv->_agn.agg_tids_count = 0;
3428
3429 /* initialize force reset */
3430 priv->force_reset[IWL_RF_RESET].reset_duration =
3431 IWL_DELAY_NEXT_FORCE_RF_RESET;
3432 priv->force_reset[IWL_FW_RESET].reset_duration =
3433 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3434
3435 priv->rx_statistics_jiffies = jiffies;
3436
3437 /* Choose which receivers/antennas to use */
3438 if (priv->cfg->ops->hcmd->set_rxon_chain)
3439 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3440 &priv->contexts[IWL_RXON_CTX_BSS]);
3441
3442 iwl_init_scan_params(priv);
3443
3444 /* init bt coex */
3445 if (priv->cfg->bt_params &&
3446 priv->cfg->bt_params->advanced_bt_coexist) {
3447 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3448 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3449 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3450 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3451 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3452 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3453 }
3454
3455 /* Set the tx_power_user_lmt to the lowest power level
3456 * this value will get overwritten by channel max power avg
3457 * from eeprom */
3458 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3459 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3460
3461 ret = iwl_init_channel_map(priv);
3462 if (ret) {
3463 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3464 goto err;
3465 }
3466
3467 ret = iwlcore_init_geos(priv);
3468 if (ret) {
3469 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3470 goto err_free_channel_map;
3471 }
3472 iwl_init_hw_rates(priv, priv->ieee_rates);
3473
3474 return 0;
3475
3476 err_free_channel_map:
3477 iwl_free_channel_map(priv);
3478 err:
3479 return ret;
3480 }
3481
3482 static void iwl_uninit_drv(struct iwl_priv *priv)
3483 {
3484 iwl_calib_free_results(priv);
3485 iwlcore_free_geos(priv);
3486 iwl_free_channel_map(priv);
3487 kfree(priv->scan_cmd);
3488 }
3489
3490 struct ieee80211_ops iwlagn_hw_ops = {
3491 .tx = iwlagn_mac_tx,
3492 .start = iwlagn_mac_start,
3493 .stop = iwlagn_mac_stop,
3494 .add_interface = iwl_mac_add_interface,
3495 .remove_interface = iwl_mac_remove_interface,
3496 .change_interface = iwl_mac_change_interface,
3497 .config = iwlagn_mac_config,
3498 .configure_filter = iwlagn_configure_filter,
3499 .set_key = iwlagn_mac_set_key,
3500 .update_tkip_key = iwlagn_mac_update_tkip_key,
3501 .conf_tx = iwl_mac_conf_tx,
3502 .bss_info_changed = iwlagn_bss_info_changed,
3503 .ampdu_action = iwlagn_mac_ampdu_action,
3504 .hw_scan = iwl_mac_hw_scan,
3505 .sta_notify = iwlagn_mac_sta_notify,
3506 .sta_add = iwlagn_mac_sta_add,
3507 .sta_remove = iwl_mac_sta_remove,
3508 .channel_switch = iwlagn_mac_channel_switch,
3509 .flush = iwlagn_mac_flush,
3510 .tx_last_beacon = iwl_mac_tx_last_beacon,
3511 .remain_on_channel = iwl_mac_remain_on_channel,
3512 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3513 .offchannel_tx = iwl_mac_offchannel_tx,
3514 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3515 };
3516
3517 static u32 iwl_hw_detect(struct iwl_priv *priv)
3518 {
3519 u8 rev_id;
3520
3521 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3522 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3523 return iwl_read32(priv, CSR_HW_REV);
3524 }
3525
3526 static int iwl_set_hw_params(struct iwl_priv *priv)
3527 {
3528 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3529 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3530 if (priv->cfg->mod_params->amsdu_size_8K)
3531 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3532 else
3533 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3534
3535 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3536
3537 if (priv->cfg->mod_params->disable_11n)
3538 priv->cfg->sku &= ~IWL_SKU_N;
3539
3540 /* Device-specific setup */
3541 return priv->cfg->ops->lib->set_hw_params(priv);
3542 }
3543
3544 static const u8 iwlagn_bss_ac_to_fifo[] = {
3545 IWL_TX_FIFO_VO,
3546 IWL_TX_FIFO_VI,
3547 IWL_TX_FIFO_BE,
3548 IWL_TX_FIFO_BK,
3549 };
3550
3551 static const u8 iwlagn_bss_ac_to_queue[] = {
3552 0, 1, 2, 3,
3553 };
3554
3555 static const u8 iwlagn_pan_ac_to_fifo[] = {
3556 IWL_TX_FIFO_VO_IPAN,
3557 IWL_TX_FIFO_VI_IPAN,
3558 IWL_TX_FIFO_BE_IPAN,
3559 IWL_TX_FIFO_BK_IPAN,
3560 };
3561
3562 static const u8 iwlagn_pan_ac_to_queue[] = {
3563 7, 6, 5, 4,
3564 };
3565
3566 /* This function both allocates and initializes hw and priv. */
3567 static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
3568 {
3569 struct iwl_priv *priv;
3570 /* mac80211 allocates memory for this device instance, including
3571 * space for this driver's private structure */
3572 struct ieee80211_hw *hw;
3573
3574 hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
3575 if (hw == NULL) {
3576 pr_err("%s: Can not allocate network device\n",
3577 cfg->name);
3578 goto out;
3579 }
3580
3581 priv = hw->priv;
3582 priv->hw = hw;
3583
3584 out:
3585 return hw;
3586 }
3587
3588 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3589 {
3590 int err = 0, i;
3591 struct iwl_priv *priv;
3592 struct ieee80211_hw *hw;
3593 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3594 unsigned long flags;
3595 u16 pci_cmd, num_mac;
3596 u32 hw_rev;
3597
3598 /************************
3599 * 1. Allocating HW data
3600 ************************/
3601
3602 hw = iwl_alloc_all(cfg);
3603 if (!hw) {
3604 err = -ENOMEM;
3605 goto out;
3606 }
3607 priv = hw->priv;
3608 /* At this point both hw and priv are allocated. */
3609
3610 priv->ucode_type = UCODE_SUBTYPE_NONE_LOADED;
3611
3612 /*
3613 * The default context is always valid,
3614 * more may be discovered when firmware
3615 * is loaded.
3616 */
3617 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3618
3619 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3620 priv->contexts[i].ctxid = i;
3621
3622 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3623 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3624 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3625 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3626 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3627 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3628 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3629 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3630 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3631 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3632 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3633 BIT(NL80211_IFTYPE_ADHOC);
3634 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3635 BIT(NL80211_IFTYPE_STATION);
3636 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3637 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3638 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3639 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3640
3641 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3642 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3643 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3644 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3645 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3646 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3647 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3648 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3649 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3650 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3651 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3652 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3653 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3654 #ifdef CONFIG_IWL_P2P
3655 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3656 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3657 #endif
3658 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3659 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3660 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3661
3662 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3663
3664 SET_IEEE80211_DEV(hw, &pdev->dev);
3665
3666 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3667 priv->cfg = cfg;
3668 priv->pci_dev = pdev;
3669 priv->inta_mask = CSR_INI_SET_MASK;
3670
3671 /* is antenna coupling more than 35dB ? */
3672 priv->bt_ant_couple_ok =
3673 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3674 true : false;
3675
3676 /* enable/disable bt channel inhibition */
3677 priv->bt_ch_announce = iwlagn_bt_ch_announce;
3678 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3679 (priv->bt_ch_announce) ? "On" : "Off");
3680
3681 if (iwl_alloc_traffic_mem(priv))
3682 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3683
3684 /**************************
3685 * 2. Initializing PCI bus
3686 **************************/
3687 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3688 PCIE_LINK_STATE_CLKPM);
3689
3690 if (pci_enable_device(pdev)) {
3691 err = -ENODEV;
3692 goto out_ieee80211_free_hw;
3693 }
3694
3695 pci_set_master(pdev);
3696
3697 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3698 if (!err)
3699 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3700 if (err) {
3701 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3702 if (!err)
3703 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3704 /* both attempts failed: */
3705 if (err) {
3706 IWL_WARN(priv, "No suitable DMA available.\n");
3707 goto out_pci_disable_device;
3708 }
3709 }
3710
3711 err = pci_request_regions(pdev, DRV_NAME);
3712 if (err)
3713 goto out_pci_disable_device;
3714
3715 pci_set_drvdata(pdev, priv);
3716
3717
3718 /***********************
3719 * 3. Read REV register
3720 ***********************/
3721 priv->hw_base = pci_iomap(pdev, 0, 0);
3722 if (!priv->hw_base) {
3723 err = -ENODEV;
3724 goto out_pci_release_regions;
3725 }
3726
3727 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3728 (unsigned long long) pci_resource_len(pdev, 0));
3729 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3730
3731 /* these spin locks will be used in apm_ops.init and EEPROM access
3732 * we should init now
3733 */
3734 spin_lock_init(&priv->reg_lock);
3735 spin_lock_init(&priv->lock);
3736
3737 /*
3738 * stop and reset the on-board processor just in case it is in a
3739 * strange state ... like being left stranded by a primary kernel
3740 * and this is now the kdump kernel trying to start up
3741 */
3742 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3743
3744 hw_rev = iwl_hw_detect(priv);
3745 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3746 priv->cfg->name, hw_rev);
3747
3748 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3749 * PCI Tx retries from interfering with C3 CPU state */
3750 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3751
3752 iwl_prepare_card_hw(priv);
3753 if (!priv->hw_ready) {
3754 IWL_WARN(priv, "Failed, HW not ready\n");
3755 goto out_iounmap;
3756 }
3757
3758 /*****************
3759 * 4. Read EEPROM
3760 *****************/
3761 /* Read the EEPROM */
3762 err = iwl_eeprom_init(priv, hw_rev);
3763 if (err) {
3764 IWL_ERR(priv, "Unable to init EEPROM\n");
3765 goto out_iounmap;
3766 }
3767 err = iwl_eeprom_check_version(priv);
3768 if (err)
3769 goto out_free_eeprom;
3770
3771 err = iwl_eeprom_check_sku(priv);
3772 if (err)
3773 goto out_free_eeprom;
3774
3775 /* extract MAC Address */
3776 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3777 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3778 priv->hw->wiphy->addresses = priv->addresses;
3779 priv->hw->wiphy->n_addresses = 1;
3780 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3781 if (num_mac > 1) {
3782 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3783 ETH_ALEN);
3784 priv->addresses[1].addr[5]++;
3785 priv->hw->wiphy->n_addresses++;
3786 }
3787
3788 /************************
3789 * 5. Setup HW constants
3790 ************************/
3791 if (iwl_set_hw_params(priv)) {
3792 IWL_ERR(priv, "failed to set hw parameters\n");
3793 goto out_free_eeprom;
3794 }
3795
3796 /*******************
3797 * 6. Setup priv
3798 *******************/
3799
3800 err = iwl_init_drv(priv);
3801 if (err)
3802 goto out_free_eeprom;
3803 /* At this point both hw and priv are initialized. */
3804
3805 /********************
3806 * 7. Setup services
3807 ********************/
3808 spin_lock_irqsave(&priv->lock, flags);
3809 iwl_disable_interrupts(priv);
3810 spin_unlock_irqrestore(&priv->lock, flags);
3811
3812 pci_enable_msi(priv->pci_dev);
3813
3814 iwl_alloc_isr_ict(priv);
3815
3816 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3817 IRQF_SHARED, DRV_NAME, priv);
3818 if (err) {
3819 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3820 goto out_disable_msi;
3821 }
3822
3823 iwl_setup_deferred_work(priv);
3824 iwl_setup_rx_handlers(priv);
3825
3826 /*********************************************
3827 * 8. Enable interrupts and read RFKILL state
3828 *********************************************/
3829
3830 /* enable rfkill interrupt: hw bug w/a */
3831 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3832 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3833 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3834 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3835 }
3836
3837 iwl_enable_rfkill_int(priv);
3838
3839 /* If platform's RF_KILL switch is NOT set to KILL */
3840 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3841 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3842 else
3843 set_bit(STATUS_RF_KILL_HW, &priv->status);
3844
3845 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3846 test_bit(STATUS_RF_KILL_HW, &priv->status));
3847
3848 iwl_power_initialize(priv);
3849 iwl_tt_initialize(priv);
3850
3851 init_completion(&priv->_agn.firmware_loading_complete);
3852
3853 err = iwl_request_firmware(priv, true);
3854 if (err)
3855 goto out_destroy_workqueue;
3856
3857 return 0;
3858
3859 out_destroy_workqueue:
3860 destroy_workqueue(priv->workqueue);
3861 priv->workqueue = NULL;
3862 free_irq(priv->pci_dev->irq, priv);
3863 iwl_free_isr_ict(priv);
3864 out_disable_msi:
3865 pci_disable_msi(priv->pci_dev);
3866 iwl_uninit_drv(priv);
3867 out_free_eeprom:
3868 iwl_eeprom_free(priv);
3869 out_iounmap:
3870 pci_iounmap(pdev, priv->hw_base);
3871 out_pci_release_regions:
3872 pci_set_drvdata(pdev, NULL);
3873 pci_release_regions(pdev);
3874 out_pci_disable_device:
3875 pci_disable_device(pdev);
3876 out_ieee80211_free_hw:
3877 iwl_free_traffic_mem(priv);
3878 ieee80211_free_hw(priv->hw);
3879 out:
3880 return err;
3881 }
3882
3883 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3884 {
3885 struct iwl_priv *priv = pci_get_drvdata(pdev);
3886 unsigned long flags;
3887
3888 if (!priv)
3889 return;
3890
3891 wait_for_completion(&priv->_agn.firmware_loading_complete);
3892
3893 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3894
3895 iwl_dbgfs_unregister(priv);
3896 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3897
3898 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3899 * to be called and iwl_down since we are removing the device
3900 * we need to set STATUS_EXIT_PENDING bit.
3901 */
3902 set_bit(STATUS_EXIT_PENDING, &priv->status);
3903
3904 iwl_leds_exit(priv);
3905
3906 if (priv->mac80211_registered) {
3907 ieee80211_unregister_hw(priv->hw);
3908 priv->mac80211_registered = 0;
3909 }
3910
3911 /* Reset to low power before unloading driver. */
3912 iwl_apm_stop(priv);
3913
3914 iwl_tt_exit(priv);
3915
3916 /* make sure we flush any pending irq or
3917 * tasklet for the driver
3918 */
3919 spin_lock_irqsave(&priv->lock, flags);
3920 iwl_disable_interrupts(priv);
3921 spin_unlock_irqrestore(&priv->lock, flags);
3922
3923 iwl_synchronize_irq(priv);
3924
3925 iwl_dealloc_ucode_pci(priv);
3926
3927 if (priv->rxq.bd)
3928 iwlagn_rx_queue_free(priv, &priv->rxq);
3929 iwlagn_hw_txq_ctx_free(priv);
3930
3931 iwl_eeprom_free(priv);
3932
3933
3934 /*netif_stop_queue(dev); */
3935 flush_workqueue(priv->workqueue);
3936
3937 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3938 * priv->workqueue... so we can't take down the workqueue
3939 * until now... */
3940 destroy_workqueue(priv->workqueue);
3941 priv->workqueue = NULL;
3942 iwl_free_traffic_mem(priv);
3943
3944 free_irq(priv->pci_dev->irq, priv);
3945 pci_disable_msi(priv->pci_dev);
3946 pci_iounmap(pdev, priv->hw_base);
3947 pci_release_regions(pdev);
3948 pci_disable_device(pdev);
3949 pci_set_drvdata(pdev, NULL);
3950
3951 iwl_uninit_drv(priv);
3952
3953 iwl_free_isr_ict(priv);
3954
3955 dev_kfree_skb(priv->beacon_skb);
3956
3957 ieee80211_free_hw(priv->hw);
3958 }
3959
3960
3961 /*****************************************************************************
3962 *
3963 * driver and module entry point
3964 *
3965 *****************************************************************************/
3966
3967 /* Hardware specific file defines the PCI IDs table for that hardware module */
3968 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3969 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3970 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3971 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3972 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3973 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3974 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3975 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3976 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3977 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3978 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3979 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3980 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3981 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3982 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3983 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3984 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3985 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3986 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3987 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3988 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3989 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3990 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3991 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3992 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3993
3994 /* 5300 Series WiFi */
3995 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3996 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3997 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3998 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3999 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4000 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4001 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4002 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4003 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4004 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4005 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4006 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4007
4008 /* 5350 Series WiFi/WiMax */
4009 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4010 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4011 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4012
4013 /* 5150 Series Wifi/WiMax */
4014 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4015 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4016 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4017 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4018 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4019 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4020
4021 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4022 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4023 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4024 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4025
4026 /* 6x00 Series */
4027 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4028 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4029 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4030 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4031 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4032 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4033 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4034 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4035 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4036 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4037
4038 /* 6x05 Series */
4039 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4040 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4041 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4042 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4043 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4044 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4045 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4046
4047 /* 6x30 Series */
4048 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4049 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4050 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4051 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4052 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4053 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4054 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4055 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4056 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4057 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4058 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4059 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4060 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4061 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4062 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4063 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4064
4065 /* 6x50 WiFi/WiMax Series */
4066 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4067 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4068 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4069 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4070 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4071 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4072
4073 /* 6150 WiFi/WiMax Series */
4074 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4075 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4076 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4077 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4078 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4079 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4080
4081 /* 1000 Series WiFi */
4082 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4083 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4084 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4085 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4086 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4087 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4088 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4089 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4090 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4091 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4092 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4093 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4094
4095 /* 100 Series WiFi */
4096 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4097 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4098 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4099 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4100 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4101 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4102
4103 /* 130 Series WiFi */
4104 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4105 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4106 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4107 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4108 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4109 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4110
4111 /* 2x00 Series */
4112 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4113 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4114 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4115 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4116 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4117 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4118
4119 /* 2x30 Series */
4120 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4121 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4122 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4123 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4124 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4125 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4126
4127 /* 6x35 Series */
4128 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4129 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4130 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4131 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4132 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4133 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4134 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4135 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4136 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4137
4138 /* 200 Series */
4139 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4140 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4141 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4142 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4143 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4144 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4145
4146 /* 230 Series */
4147 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4148 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4149 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4150 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4151 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4152 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4153
4154 {0}
4155 };
4156 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4157
4158 static struct pci_driver iwl_driver = {
4159 .name = DRV_NAME,
4160 .id_table = iwl_hw_card_ids,
4161 .probe = iwl_pci_probe,
4162 .remove = __devexit_p(iwl_pci_remove),
4163 .driver.pm = IWL_PM_OPS,
4164 };
4165
4166 static int __init iwl_init(void)
4167 {
4168
4169 int ret;
4170 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4171 pr_info(DRV_COPYRIGHT "\n");
4172
4173 ret = iwlagn_rate_control_register();
4174 if (ret) {
4175 pr_err("Unable to register rate control algorithm: %d\n", ret);
4176 return ret;
4177 }
4178
4179 ret = pci_register_driver(&iwl_driver);
4180 if (ret) {
4181 pr_err("Unable to initialize PCI module\n");
4182 goto error_register;
4183 }
4184
4185 return ret;
4186
4187 error_register:
4188 iwlagn_rate_control_unregister();
4189 return ret;
4190 }
4191
4192 static void __exit iwl_exit(void)
4193 {
4194 pci_unregister_driver(&iwl_driver);
4195 iwlagn_rate_control_unregister();
4196 }
4197
4198 module_exit(iwl_exit);
4199 module_init(iwl_init);
4200
4201 #ifdef CONFIG_IWLWIFI_DEBUG
4202 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4203 MODULE_PARM_DESC(debug, "debug output mask");
4204 #endif
4205
4206 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4207 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4208 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4209 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4210 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4211 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4212 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4213 int, S_IRUGO);
4214 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4215 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4216 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4217
4218 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4219 S_IRUGO);
4220 MODULE_PARM_DESC(ucode_alternative,
4221 "specify ucode alternative to use from ucode file");
4222
4223 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4224 MODULE_PARM_DESC(antenna_coupling,
4225 "specify antenna coupling in dB (defualt: 0 dB)");
4226
4227 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4228 MODULE_PARM_DESC(bt_ch_inhibition,
4229 "Disable BT channel inhibition (default: enable)");
4230
4231 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4232 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4233
4234 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4235 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree