2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #define RADEON_IDLE_LOOP_MS 100
28 #define RADEON_RECLOCK_DELAY_MS 200
29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
30 #define RADEON_WAIT_IDLE_TIMEOUT 200
32 static void radeon_pm_idle_work_handler(struct work_struct
*work
);
33 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
35 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
37 struct radeon_bo
*bo
, *n
;
39 if (list_empty(&rdev
->gem
.objects
))
42 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
43 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
44 ttm_bo_unmap_virtual(&bo
->tbo
);
47 if (rdev
->gart
.table
.vram
.robj
)
48 ttm_bo_unmap_virtual(&rdev
->gart
.table
.vram
.robj
->tbo
);
50 if (rdev
->stollen_vga_memory
)
51 ttm_bo_unmap_virtual(&rdev
->stollen_vga_memory
->tbo
);
53 if (rdev
->r600_blit
.shader_obj
)
54 ttm_bo_unmap_virtual(&rdev
->r600_blit
.shader_obj
->tbo
);
57 static void radeon_pm_set_clocks(struct radeon_device
*rdev
, int static_switch
)
62 radeon_get_power_state(rdev
, rdev
->pm
.planned_action
);
64 mutex_lock(&rdev
->cp
.mutex
);
66 /* wait for GPU idle */
67 rdev
->pm
.gui_idle
= false;
68 rdev
->irq
.gui_idle
= true;
70 wait_event_interruptible_timeout(
71 rdev
->irq
.idle_queue
, rdev
->pm
.gui_idle
,
72 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT
));
73 rdev
->irq
.gui_idle
= false;
76 mutex_lock(&rdev
->vram_mutex
);
78 radeon_unmap_vram_bos(rdev
);
81 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
82 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
83 rdev
->pm
.req_vblank
|= (1 << i
);
84 drm_vblank_get(rdev
->ddev
, i
);
89 radeon_set_power_state(rdev
, static_switch
);
92 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
93 if (rdev
->pm
.req_vblank
& (1 << i
)) {
94 rdev
->pm
.req_vblank
&= ~(1 << i
);
95 drm_vblank_put(rdev
->ddev
, i
);
100 mutex_unlock(&rdev
->vram_mutex
);
102 /* update display watermarks based on new power state */
103 radeon_update_bandwidth_info(rdev
);
104 if (rdev
->pm
.active_crtc_count
)
105 radeon_bandwidth_update(rdev
);
107 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
109 mutex_unlock(&rdev
->cp
.mutex
);
112 static ssize_t
radeon_get_power_state_static(struct device
*dev
,
113 struct device_attribute
*attr
,
116 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
117 struct radeon_device
*rdev
= ddev
->dev_private
;
119 return snprintf(buf
, PAGE_SIZE
, "%d.%d\n", rdev
->pm
.current_power_state_index
,
120 rdev
->pm
.current_clock_mode_index
);
123 static ssize_t
radeon_set_power_state_static(struct device
*dev
,
124 struct device_attribute
*attr
,
128 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
129 struct radeon_device
*rdev
= ddev
->dev_private
;
132 if (sscanf(buf
, "%u.%u", &ps
, &cm
) != 2) {
133 DRM_ERROR("Invalid power state!\n");
137 mutex_lock(&rdev
->ddev
->struct_mutex
);
138 mutex_lock(&rdev
->pm
.mutex
);
139 if ((ps
>= 0) && (ps
< rdev
->pm
.num_power_states
) &&
140 (cm
>= 0) && (cm
< rdev
->pm
.power_state
[ps
].num_clock_modes
)) {
141 if ((rdev
->pm
.active_crtc_count
> 1) &&
142 (rdev
->pm
.power_state
[ps
].flags
& RADEON_PM_SINGLE_DISPLAY_ONLY
)) {
143 DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps
, cm
);
146 rdev
->pm
.state
= PM_STATE_DISABLED
;
147 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
148 rdev
->pm
.requested_power_state_index
= ps
;
149 rdev
->pm
.requested_clock_mode_index
= cm
;
150 radeon_pm_set_clocks(rdev
, true);
153 DRM_ERROR("Invalid power state: %d.%d\n\n", ps
, cm
);
154 mutex_unlock(&rdev
->pm
.mutex
);
155 mutex_unlock(&rdev
->ddev
->struct_mutex
);
160 static ssize_t
radeon_get_dynpm(struct device
*dev
,
161 struct device_attribute
*attr
,
164 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
165 struct radeon_device
*rdev
= ddev
->dev_private
;
167 return snprintf(buf
, PAGE_SIZE
, "%s\n",
168 (rdev
->pm
.state
== PM_STATE_DISABLED
) ? "disabled" : "enabled");
171 static ssize_t
radeon_set_dynpm(struct device
*dev
,
172 struct device_attribute
*attr
,
176 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
177 struct radeon_device
*rdev
= ddev
->dev_private
;
178 int tmp
= simple_strtoul(buf
, NULL
, 10);
181 /* update power mode info */
182 radeon_pm_compute_clocks(rdev
);
184 mutex_lock(&rdev
->pm
.mutex
);
185 rdev
->pm
.state
= PM_STATE_DISABLED
;
186 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
187 mutex_unlock(&rdev
->pm
.mutex
);
188 DRM_INFO("radeon: dynamic power management disabled\n");
189 } else if (tmp
== 1) {
190 if (rdev
->pm
.num_power_states
> 1) {
192 mutex_lock(&rdev
->ddev
->struct_mutex
);
193 mutex_lock(&rdev
->pm
.mutex
);
194 rdev
->pm
.state
= PM_STATE_PAUSED
;
195 rdev
->pm
.planned_action
= PM_ACTION_DEFAULT
;
196 radeon_get_power_state(rdev
, rdev
->pm
.planned_action
);
197 mutex_unlock(&rdev
->pm
.mutex
);
198 mutex_unlock(&rdev
->ddev
->struct_mutex
);
199 /* update power mode info */
200 radeon_pm_compute_clocks(rdev
);
201 DRM_INFO("radeon: dynamic power management enabled\n");
203 DRM_ERROR("dynpm not valid on this system\n");
205 DRM_ERROR("Invalid setting: %d\n", tmp
);
210 static DEVICE_ATTR(power_state
, S_IRUGO
| S_IWUSR
, radeon_get_power_state_static
, radeon_set_power_state_static
);
211 static DEVICE_ATTR(dynpm
, S_IRUGO
| S_IWUSR
, radeon_get_dynpm
, radeon_set_dynpm
);
214 static const char *pm_state_names
[4] = {
221 static const char *pm_state_types
[5] = {
229 static void radeon_print_power_mode_info(struct radeon_device
*rdev
)
234 DRM_INFO("%d Power State(s)\n", rdev
->pm
.num_power_states
);
235 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
236 if (rdev
->pm
.default_power_state_index
== i
)
240 DRM_INFO("State %d %s %s\n", i
,
241 pm_state_types
[rdev
->pm
.power_state
[i
].type
],
242 is_default
? "(default)" : "");
243 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
244 DRM_INFO("\t%d PCIE Lanes\n", rdev
->pm
.power_state
[i
].pcie_lanes
);
245 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_SINGLE_DISPLAY_ONLY
)
246 DRM_INFO("\tSingle display only\n");
247 DRM_INFO("\t%d Clock Mode(s)\n", rdev
->pm
.power_state
[i
].num_clock_modes
);
248 for (j
= 0; j
< rdev
->pm
.power_state
[i
].num_clock_modes
; j
++) {
249 if (rdev
->flags
& RADEON_IS_IGP
)
250 DRM_INFO("\t\t%d engine: %d\n",
252 rdev
->pm
.power_state
[i
].clock_info
[j
].sclk
* 10);
254 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
256 rdev
->pm
.power_state
[i
].clock_info
[j
].sclk
* 10,
257 rdev
->pm
.power_state
[i
].clock_info
[j
].mclk
* 10);
262 void radeon_sync_with_vblank(struct radeon_device
*rdev
)
264 if (rdev
->pm
.active_crtcs
) {
265 rdev
->pm
.vblank_sync
= false;
267 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
268 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
272 int radeon_pm_init(struct radeon_device
*rdev
)
274 rdev
->pm
.state
= PM_STATE_DISABLED
;
275 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
276 rdev
->pm
.can_upclock
= true;
277 rdev
->pm
.can_downclock
= true;
280 if (rdev
->is_atom_bios
)
281 radeon_atombios_get_power_modes(rdev
);
283 radeon_combios_get_power_modes(rdev
);
284 radeon_print_power_mode_info(rdev
);
287 if (radeon_debugfs_pm_init(rdev
)) {
288 DRM_ERROR("Failed to register debugfs file for PM!\n");
291 /* where's the best place to put this? */
292 device_create_file(rdev
->dev
, &dev_attr_power_state
);
293 device_create_file(rdev
->dev
, &dev_attr_dynpm
);
295 INIT_DELAYED_WORK(&rdev
->pm
.idle_work
, radeon_pm_idle_work_handler
);
297 if ((radeon_dynpm
!= -1 && radeon_dynpm
) && (rdev
->pm
.num_power_states
> 1)) {
298 rdev
->pm
.state
= PM_STATE_PAUSED
;
299 DRM_INFO("radeon: dynamic power management enabled\n");
302 DRM_INFO("radeon: power management initialized\n");
307 void radeon_pm_fini(struct radeon_device
*rdev
)
309 if (rdev
->pm
.state
!= PM_STATE_DISABLED
) {
311 cancel_delayed_work_sync(&rdev
->pm
.idle_work
);
312 /* reset default clocks */
313 rdev
->pm
.state
= PM_STATE_DISABLED
;
314 rdev
->pm
.planned_action
= PM_ACTION_DEFAULT
;
315 radeon_pm_set_clocks(rdev
, false);
316 } else if ((rdev
->pm
.current_power_state_index
!=
317 rdev
->pm
.default_power_state_index
) ||
318 (rdev
->pm
.current_clock_mode_index
!= 0)) {
319 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
320 rdev
->pm
.requested_clock_mode_index
= 0;
321 mutex_lock(&rdev
->ddev
->struct_mutex
);
322 mutex_lock(&rdev
->pm
.mutex
);
323 radeon_pm_set_clocks(rdev
, true);
324 mutex_unlock(&rdev
->pm
.mutex
);
325 mutex_unlock(&rdev
->ddev
->struct_mutex
);
328 device_remove_file(rdev
->dev
, &dev_attr_power_state
);
329 device_remove_file(rdev
->dev
, &dev_attr_dynpm
);
331 if (rdev
->pm
.i2c_bus
)
332 radeon_i2c_destroy(rdev
->pm
.i2c_bus
);
335 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
337 struct drm_device
*ddev
= rdev
->ddev
;
338 struct drm_crtc
*crtc
;
339 struct radeon_crtc
*radeon_crtc
;
341 if (rdev
->pm
.state
== PM_STATE_DISABLED
)
344 mutex_lock(&rdev
->ddev
->struct_mutex
);
345 mutex_lock(&rdev
->pm
.mutex
);
347 rdev
->pm
.active_crtcs
= 0;
348 rdev
->pm
.active_crtc_count
= 0;
349 list_for_each_entry(crtc
,
350 &ddev
->mode_config
.crtc_list
, head
) {
351 radeon_crtc
= to_radeon_crtc(crtc
);
352 if (radeon_crtc
->enabled
) {
353 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
354 rdev
->pm
.active_crtc_count
++;
358 if (rdev
->pm
.active_crtc_count
> 1) {
359 if (rdev
->pm
.state
== PM_STATE_ACTIVE
) {
360 cancel_delayed_work(&rdev
->pm
.idle_work
);
362 rdev
->pm
.state
= PM_STATE_PAUSED
;
363 rdev
->pm
.planned_action
= PM_ACTION_UPCLOCK
;
364 radeon_pm_set_clocks(rdev
, false);
366 DRM_DEBUG("radeon: dynamic power management deactivated\n");
368 } else if (rdev
->pm
.active_crtc_count
== 1) {
369 /* TODO: Increase clocks if needed for current mode */
371 if (rdev
->pm
.state
== PM_STATE_MINIMUM
) {
372 rdev
->pm
.state
= PM_STATE_ACTIVE
;
373 rdev
->pm
.planned_action
= PM_ACTION_UPCLOCK
;
374 radeon_pm_set_clocks(rdev
, false);
376 queue_delayed_work(rdev
->wq
, &rdev
->pm
.idle_work
,
377 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
378 } else if (rdev
->pm
.state
== PM_STATE_PAUSED
) {
379 rdev
->pm
.state
= PM_STATE_ACTIVE
;
380 queue_delayed_work(rdev
->wq
, &rdev
->pm
.idle_work
,
381 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
382 DRM_DEBUG("radeon: dynamic power management activated\n");
384 } else { /* count == 0 */
385 if (rdev
->pm
.state
!= PM_STATE_MINIMUM
) {
386 cancel_delayed_work(&rdev
->pm
.idle_work
);
388 rdev
->pm
.state
= PM_STATE_MINIMUM
;
389 rdev
->pm
.planned_action
= PM_ACTION_MINIMUM
;
390 radeon_pm_set_clocks(rdev
, false);
394 mutex_unlock(&rdev
->pm
.mutex
);
395 mutex_unlock(&rdev
->ddev
->struct_mutex
);
398 bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
403 if (ASIC_IS_DCE4(rdev
)) {
404 if (rdev
->pm
.active_crtcs
& (1 << 0)) {
405 stat_crtc
= RREG32(EVERGREEN_CRTC_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
406 if (!(stat_crtc
& 1))
409 if (rdev
->pm
.active_crtcs
& (1 << 1)) {
410 stat_crtc
= RREG32(EVERGREEN_CRTC_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
411 if (!(stat_crtc
& 1))
414 if (rdev
->pm
.active_crtcs
& (1 << 2)) {
415 stat_crtc
= RREG32(EVERGREEN_CRTC_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
416 if (!(stat_crtc
& 1))
419 if (rdev
->pm
.active_crtcs
& (1 << 3)) {
420 stat_crtc
= RREG32(EVERGREEN_CRTC_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
421 if (!(stat_crtc
& 1))
424 if (rdev
->pm
.active_crtcs
& (1 << 4)) {
425 stat_crtc
= RREG32(EVERGREEN_CRTC_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
426 if (!(stat_crtc
& 1))
429 if (rdev
->pm
.active_crtcs
& (1 << 5)) {
430 stat_crtc
= RREG32(EVERGREEN_CRTC_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
431 if (!(stat_crtc
& 1))
434 } else if (ASIC_IS_AVIVO(rdev
)) {
435 if (rdev
->pm
.active_crtcs
& (1 << 0)) {
436 stat_crtc
= RREG32(D1CRTC_STATUS
);
437 if (!(stat_crtc
& 1))
440 if (rdev
->pm
.active_crtcs
& (1 << 1)) {
441 stat_crtc
= RREG32(D2CRTC_STATUS
);
442 if (!(stat_crtc
& 1))
446 if (rdev
->pm
.active_crtcs
& (1 << 0)) {
447 stat_crtc
= RREG32(RADEON_CRTC_STATUS
);
448 if (!(stat_crtc
& 1))
451 if (rdev
->pm
.active_crtcs
& (1 << 1)) {
452 stat_crtc
= RREG32(RADEON_CRTC2_STATUS
);
453 if (!(stat_crtc
& 1))
458 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc
,
459 finish
? "exit" : "entry");
463 static void radeon_pm_idle_work_handler(struct work_struct
*work
)
465 struct radeon_device
*rdev
;
467 rdev
= container_of(work
, struct radeon_device
,
470 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
471 mutex_lock(&rdev
->ddev
->struct_mutex
);
472 mutex_lock(&rdev
->pm
.mutex
);
473 if (rdev
->pm
.state
== PM_STATE_ACTIVE
) {
474 unsigned long irq_flags
;
475 int not_processed
= 0;
477 read_lock_irqsave(&rdev
->fence_drv
.lock
, irq_flags
);
478 if (!list_empty(&rdev
->fence_drv
.emited
)) {
479 struct list_head
*ptr
;
480 list_for_each(ptr
, &rdev
->fence_drv
.emited
) {
481 /* count up to 3, that's enought info */
482 if (++not_processed
>= 3)
486 read_unlock_irqrestore(&rdev
->fence_drv
.lock
, irq_flags
);
488 if (not_processed
>= 3) { /* should upclock */
489 if (rdev
->pm
.planned_action
== PM_ACTION_DOWNCLOCK
) {
490 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
491 } else if (rdev
->pm
.planned_action
== PM_ACTION_NONE
&&
492 rdev
->pm
.can_upclock
) {
493 rdev
->pm
.planned_action
=
495 rdev
->pm
.action_timeout
= jiffies
+
496 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
498 } else if (not_processed
== 0) { /* should downclock */
499 if (rdev
->pm
.planned_action
== PM_ACTION_UPCLOCK
) {
500 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
501 } else if (rdev
->pm
.planned_action
== PM_ACTION_NONE
&&
502 rdev
->pm
.can_downclock
) {
503 rdev
->pm
.planned_action
=
505 rdev
->pm
.action_timeout
= jiffies
+
506 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
510 if (rdev
->pm
.planned_action
!= PM_ACTION_NONE
&&
511 jiffies
> rdev
->pm
.action_timeout
) {
512 radeon_pm_set_clocks(rdev
, false);
515 mutex_unlock(&rdev
->pm
.mutex
);
516 mutex_unlock(&rdev
->ddev
->struct_mutex
);
517 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
519 queue_delayed_work(rdev
->wq
, &rdev
->pm
.idle_work
,
520 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
526 #if defined(CONFIG_DEBUG_FS)
528 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
530 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
531 struct drm_device
*dev
= node
->minor
->dev
;
532 struct radeon_device
*rdev
= dev
->dev_private
;
534 seq_printf(m
, "state: %s\n", pm_state_names
[rdev
->pm
.state
]);
535 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->clock
.default_sclk
);
536 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
537 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->clock
.default_mclk
);
538 if (rdev
->asic
->get_memory_clock
)
539 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
540 if (rdev
->asic
->get_pcie_lanes
)
541 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
546 static struct drm_info_list radeon_pm_info_list
[] = {
547 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
551 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
553 #if defined(CONFIG_DEBUG_FS)
554 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));