2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/mlx4/qp.h>
37 #include <linux/skbuff.h>
38 #include <linux/if_vlan.h>
39 #include <linux/vmalloc.h>
44 MAX_INLINE
= 104, /* 128 - 16 - 4 - 4 */
47 static int inline_thold __read_mostly
= MAX_INLINE
;
49 module_param_named(inline_thold
, inline_thold
, int, 0444);
50 MODULE_PARM_DESC(inline_thold
, "treshold for using inline data");
52 int mlx4_en_create_tx_ring(struct mlx4_en_priv
*priv
,
53 struct mlx4_en_tx_ring
*ring
, u32 size
,
56 struct mlx4_en_dev
*mdev
= priv
->mdev
;
61 ring
->size_mask
= size
- 1;
62 ring
->stride
= stride
;
64 inline_thold
= min(inline_thold
, MAX_INLINE
);
66 spin_lock_init(&ring
->comp_lock
);
68 tmp
= size
* sizeof(struct mlx4_en_tx_info
);
69 ring
->tx_info
= vmalloc(tmp
);
71 mlx4_err(mdev
, "Failed allocating tx_info ring\n");
74 mlx4_dbg(DRV
, priv
, "Allocated tx_info ring at addr:%p size:%d\n",
77 ring
->bounce_buf
= kmalloc(MAX_DESC_SIZE
, GFP_KERNEL
);
78 if (!ring
->bounce_buf
) {
79 mlx4_err(mdev
, "Failed allocating bounce buffer\n");
83 ring
->buf_size
= ALIGN(size
* ring
->stride
, MLX4_EN_PAGE_SIZE
);
85 err
= mlx4_alloc_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
,
88 mlx4_err(mdev
, "Failed allocating hwq resources\n");
92 err
= mlx4_en_map_buffer(&ring
->wqres
.buf
);
94 mlx4_err(mdev
, "Failed to map TX buffer\n");
98 ring
->buf
= ring
->wqres
.buf
.direct
.buf
;
100 mlx4_dbg(DRV
, priv
, "Allocated TX ring (addr:%p) - buf:%p size:%d "
101 "buf_size:%d dma:%llx\n", ring
, ring
->buf
, ring
->size
,
102 ring
->buf_size
, (unsigned long long) ring
->wqres
.buf
.direct
.map
);
104 err
= mlx4_qp_reserve_range(mdev
->dev
, 1, 1, &ring
->qpn
);
106 mlx4_err(mdev
, "Failed reserving qp for tx ring.\n");
110 err
= mlx4_qp_alloc(mdev
->dev
, ring
->qpn
, &ring
->qp
);
112 mlx4_err(mdev
, "Failed allocating qp %d\n", ring
->qpn
);
119 mlx4_qp_release_range(mdev
->dev
, ring
->qpn
, 1);
121 mlx4_en_unmap_buffer(&ring
->wqres
.buf
);
123 mlx4_free_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
125 kfree(ring
->bounce_buf
);
126 ring
->bounce_buf
= NULL
;
128 vfree(ring
->tx_info
);
129 ring
->tx_info
= NULL
;
133 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv
*priv
,
134 struct mlx4_en_tx_ring
*ring
)
136 struct mlx4_en_dev
*mdev
= priv
->mdev
;
137 mlx4_dbg(DRV
, priv
, "Destroying tx ring, qpn: %d\n", ring
->qpn
);
139 mlx4_qp_remove(mdev
->dev
, &ring
->qp
);
140 mlx4_qp_free(mdev
->dev
, &ring
->qp
);
141 mlx4_qp_release_range(mdev
->dev
, ring
->qpn
, 1);
142 mlx4_en_unmap_buffer(&ring
->wqres
.buf
);
143 mlx4_free_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
144 kfree(ring
->bounce_buf
);
145 ring
->bounce_buf
= NULL
;
146 vfree(ring
->tx_info
);
147 ring
->tx_info
= NULL
;
150 int mlx4_en_activate_tx_ring(struct mlx4_en_priv
*priv
,
151 struct mlx4_en_tx_ring
*ring
,
154 struct mlx4_en_dev
*mdev
= priv
->mdev
;
159 ring
->cons
= 0xffffffff;
160 ring
->last_nr_txbb
= 1;
163 memset(ring
->tx_info
, 0, ring
->size
* sizeof(struct mlx4_en_tx_info
));
164 memset(ring
->buf
, 0, ring
->buf_size
);
166 ring
->qp_state
= MLX4_QP_STATE_RST
;
167 ring
->doorbell_qpn
= swab32(ring
->qp
.qpn
<< 8);
169 mlx4_en_fill_qp_context(priv
, ring
->size
, ring
->stride
, 1, 0, ring
->qpn
,
170 ring
->cqn
, srqn
, &ring
->context
);
172 err
= mlx4_qp_to_ready(mdev
->dev
, &ring
->wqres
.mtt
, &ring
->context
,
173 &ring
->qp
, &ring
->qp_state
);
178 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv
*priv
,
179 struct mlx4_en_tx_ring
*ring
)
181 struct mlx4_en_dev
*mdev
= priv
->mdev
;
183 mlx4_qp_modify(mdev
->dev
, NULL
, ring
->qp_state
,
184 MLX4_QP_STATE_RST
, NULL
, 0, 0, &ring
->qp
);
188 static u32
mlx4_en_free_tx_desc(struct mlx4_en_priv
*priv
,
189 struct mlx4_en_tx_ring
*ring
,
192 struct mlx4_en_dev
*mdev
= priv
->mdev
;
193 struct mlx4_en_tx_info
*tx_info
= &ring
->tx_info
[index
];
194 struct mlx4_en_tx_desc
*tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
195 struct mlx4_wqe_data_seg
*data
= (void *) tx_desc
+ tx_info
->data_offset
;
196 struct sk_buff
*skb
= tx_info
->skb
;
197 struct skb_frag_struct
*frag
;
198 void *end
= ring
->buf
+ ring
->buf_size
;
199 int frags
= skb_shinfo(skb
)->nr_frags
;
201 __be32
*ptr
= (__be32
*)tx_desc
;
202 __be32 stamp
= cpu_to_be32(STAMP_VAL
| (!!owner
<< STAMP_SHIFT
));
204 /* Optimize the common case when there are no wraparounds */
205 if (likely((void *) tx_desc
+ tx_info
->nr_txbb
* TXBB_SIZE
<= end
)) {
206 if (tx_info
->linear
) {
207 pci_unmap_single(mdev
->pdev
,
208 (dma_addr_t
) be64_to_cpu(data
->addr
),
209 be32_to_cpu(data
->byte_count
),
214 for (i
= 0; i
< frags
; i
++) {
215 frag
= &skb_shinfo(skb
)->frags
[i
];
216 pci_unmap_page(mdev
->pdev
,
217 (dma_addr_t
) be64_to_cpu(data
[i
].addr
),
218 frag
->size
, PCI_DMA_TODEVICE
);
220 /* Stamp the freed descriptor */
221 for (i
= 0; i
< tx_info
->nr_txbb
* TXBB_SIZE
; i
+= STAMP_STRIDE
) {
227 if ((void *) data
>= end
) {
228 data
= (struct mlx4_wqe_data_seg
*)
229 (ring
->buf
+ ((void *) data
- end
));
232 if (tx_info
->linear
) {
233 pci_unmap_single(mdev
->pdev
,
234 (dma_addr_t
) be64_to_cpu(data
->addr
),
235 be32_to_cpu(data
->byte_count
),
240 for (i
= 0; i
< frags
; i
++) {
241 /* Check for wraparound before unmapping */
242 if ((void *) data
>= end
)
243 data
= (struct mlx4_wqe_data_seg
*) ring
->buf
;
244 frag
= &skb_shinfo(skb
)->frags
[i
];
245 pci_unmap_page(mdev
->pdev
,
246 (dma_addr_t
) be64_to_cpu(data
->addr
),
247 frag
->size
, PCI_DMA_TODEVICE
);
249 /* Stamp the freed descriptor */
250 for (i
= 0; i
< tx_info
->nr_txbb
* TXBB_SIZE
; i
+= STAMP_STRIDE
) {
253 if ((void *) ptr
>= end
) {
255 stamp
^= cpu_to_be32(0x80000000);
260 dev_kfree_skb_any(skb
);
261 return tx_info
->nr_txbb
;
265 int mlx4_en_free_tx_buf(struct net_device
*dev
, struct mlx4_en_tx_ring
*ring
)
267 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
270 /* Skip last polled descriptor */
271 ring
->cons
+= ring
->last_nr_txbb
;
272 mlx4_dbg(DRV
, priv
, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
273 ring
->cons
, ring
->prod
);
275 if ((u32
) (ring
->prod
- ring
->cons
) > ring
->size
) {
276 if (netif_msg_tx_err(priv
))
277 mlx4_warn(priv
->mdev
, "Tx consumer passed producer!\n");
281 while (ring
->cons
!= ring
->prod
) {
282 ring
->last_nr_txbb
= mlx4_en_free_tx_desc(priv
, ring
,
283 ring
->cons
& ring
->size_mask
,
284 !!(ring
->cons
& ring
->size
));
285 ring
->cons
+= ring
->last_nr_txbb
;
290 mlx4_dbg(DRV
, priv
, "Freed %d uncompleted tx descriptors\n", cnt
);
295 void mlx4_en_set_prio_map(struct mlx4_en_priv
*priv
, u16
*prio_map
, u32 ring_num
)
297 int block
= 8 / ring_num
;
298 int extra
= 8 - (block
* ring_num
);
304 for (prio
= 0; prio
< 8; prio
++)
309 for (prio
= 0; prio
< 8; prio
++) {
310 if (extra
&& (num
== block
+ 1)) {
314 } else if (!extra
&& (num
== block
)) {
318 prio_map
[prio
] = ring
;
319 mlx4_dbg(DRV
, priv
, " prio:%d --> ring:%d\n", prio
, ring
);
324 static void mlx4_en_process_tx_cq(struct net_device
*dev
, struct mlx4_en_cq
*cq
)
326 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
327 struct mlx4_cq
*mcq
= &cq
->mcq
;
328 struct mlx4_en_tx_ring
*ring
= &priv
->tx_ring
[cq
->ring
];
329 struct mlx4_cqe
*cqe
= cq
->buf
;
332 u32 txbbs_skipped
= 0;
335 /* index always points to the first TXBB of the last polled descriptor */
336 index
= ring
->cons
& ring
->size_mask
;
337 new_index
= be16_to_cpu(cqe
->wqe_index
) & ring
->size_mask
;
338 if (index
== new_index
)
345 * We use a two-stage loop:
346 * - the first samples the HW-updated CQE
347 * - the second frees TXBBs until the last sample
348 * This lets us amortize CQE cache misses, while still polling the CQ
349 * until is quiescent.
351 cq_last_sav
= mcq
->cons_index
;
354 /* Skip over last polled CQE */
355 index
= (index
+ ring
->last_nr_txbb
) & ring
->size_mask
;
356 txbbs_skipped
+= ring
->last_nr_txbb
;
359 ring
->last_nr_txbb
= mlx4_en_free_tx_desc(
361 !!((ring
->cons
+ txbbs_skipped
) &
365 } while (index
!= new_index
);
367 new_index
= be16_to_cpu(cqe
->wqe_index
) & ring
->size_mask
;
368 } while (index
!= new_index
);
369 AVG_PERF_COUNTER(priv
->pstats
.tx_coal_avg
,
370 (u32
) (mcq
->cons_index
- cq_last_sav
));
373 * To prevent CQ overflow we first update CQ consumer and only then
378 ring
->cons
+= txbbs_skipped
;
380 /* Wakeup Tx queue if this ring stopped it */
381 if (unlikely(ring
->blocked
)) {
382 if ((u32
) (ring
->prod
- ring
->cons
) <=
383 ring
->size
- HEADROOM
- MAX_DESC_TXBBS
) {
385 /* TODO: support multiqueue netdevs. Currently, we block
386 * when *any* ring is full. Note that:
387 * - 2 Tx rings can unblock at the same time and call
388 * netif_wake_queue(), which is OK since this
389 * operation is idempotent.
390 * - We might wake the queue just after another ring
391 * stopped it. This is no big deal because the next
392 * transmission on that ring would stop the queue.
395 netif_wake_queue(dev
);
396 priv
->port_stats
.wake_queue
++;
401 void mlx4_en_tx_irq(struct mlx4_cq
*mcq
)
403 struct mlx4_en_cq
*cq
= container_of(mcq
, struct mlx4_en_cq
, mcq
);
404 struct mlx4_en_priv
*priv
= netdev_priv(cq
->dev
);
405 struct mlx4_en_tx_ring
*ring
= &priv
->tx_ring
[cq
->ring
];
407 if (!spin_trylock(&ring
->comp_lock
))
409 mlx4_en_process_tx_cq(cq
->dev
, cq
);
410 mod_timer(&cq
->timer
, jiffies
+ 1);
411 spin_unlock(&ring
->comp_lock
);
415 void mlx4_en_poll_tx_cq(unsigned long data
)
417 struct mlx4_en_cq
*cq
= (struct mlx4_en_cq
*) data
;
418 struct mlx4_en_priv
*priv
= netdev_priv(cq
->dev
);
419 struct mlx4_en_tx_ring
*ring
= &priv
->tx_ring
[cq
->ring
];
422 INC_PERF_COUNTER(priv
->pstats
.tx_poll
);
424 if (!spin_trylock(&ring
->comp_lock
)) {
425 mod_timer(&cq
->timer
, jiffies
+ MLX4_EN_TX_POLL_TIMEOUT
);
428 mlx4_en_process_tx_cq(cq
->dev
, cq
);
429 inflight
= (u32
) (ring
->prod
- ring
->cons
- ring
->last_nr_txbb
);
431 /* If there are still packets in flight and the timer has not already
432 * been scheduled by the Tx routine then schedule it here to guarantee
433 * completion processing of these packets */
434 if (inflight
&& priv
->port_up
)
435 mod_timer(&cq
->timer
, jiffies
+ MLX4_EN_TX_POLL_TIMEOUT
);
437 spin_unlock(&ring
->comp_lock
);
440 static struct mlx4_en_tx_desc
*mlx4_en_bounce_to_desc(struct mlx4_en_priv
*priv
,
441 struct mlx4_en_tx_ring
*ring
,
443 unsigned int desc_size
)
445 u32 copy
= (ring
->size
- index
) * TXBB_SIZE
;
448 for (i
= desc_size
- copy
- 4; i
>= 0; i
-= 4) {
449 if ((i
& (TXBB_SIZE
- 1)) == 0)
452 *((u32
*) (ring
->buf
+ i
)) =
453 *((u32
*) (ring
->bounce_buf
+ copy
+ i
));
456 for (i
= copy
- 4; i
>= 4 ; i
-= 4) {
457 if ((i
& (TXBB_SIZE
- 1)) == 0)
460 *((u32
*) (ring
->buf
+ index
* TXBB_SIZE
+ i
)) =
461 *((u32
*) (ring
->bounce_buf
+ i
));
464 /* Return real descriptor location */
465 return ring
->buf
+ index
* TXBB_SIZE
;
468 static inline void mlx4_en_xmit_poll(struct mlx4_en_priv
*priv
, int tx_ind
)
470 struct mlx4_en_cq
*cq
= &priv
->tx_cq
[tx_ind
];
471 struct mlx4_en_tx_ring
*ring
= &priv
->tx_ring
[tx_ind
];
473 /* If we don't have a pending timer, set one up to catch our recent
474 post in case the interface becomes idle */
475 if (!timer_pending(&cq
->timer
))
476 mod_timer(&cq
->timer
, jiffies
+ MLX4_EN_TX_POLL_TIMEOUT
);
478 /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
479 if ((++ring
->poll_cnt
& (MLX4_EN_TX_POLL_MODER
- 1)) == 0)
480 if (spin_trylock(&ring
->comp_lock
)) {
481 mlx4_en_process_tx_cq(priv
->dev
, cq
);
482 spin_unlock(&ring
->comp_lock
);
486 static void *get_frag_ptr(struct sk_buff
*skb
)
488 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[0];
489 struct page
*page
= frag
->page
;
492 ptr
= page_address(page
);
496 return ptr
+ frag
->page_offset
;
499 static int is_inline(struct sk_buff
*skb
, void **pfrag
)
503 if (inline_thold
&& !skb_is_gso(skb
) && skb
->len
<= inline_thold
) {
504 if (skb_shinfo(skb
)->nr_frags
== 1) {
505 ptr
= get_frag_ptr(skb
);
513 } else if (unlikely(skb_shinfo(skb
)->nr_frags
))
522 static int inline_size(struct sk_buff
*skb
)
524 if (skb
->len
+ CTRL_SIZE
+ sizeof(struct mlx4_wqe_inline_seg
)
525 <= MLX4_INLINE_ALIGN
)
526 return ALIGN(skb
->len
+ CTRL_SIZE
+
527 sizeof(struct mlx4_wqe_inline_seg
), 16);
529 return ALIGN(skb
->len
+ CTRL_SIZE
+ 2 *
530 sizeof(struct mlx4_wqe_inline_seg
), 16);
533 static int get_real_size(struct sk_buff
*skb
, struct net_device
*dev
,
534 int *lso_header_size
)
536 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
537 struct mlx4_en_dev
*mdev
= priv
->mdev
;
540 if (skb_is_gso(skb
)) {
541 *lso_header_size
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
542 real_size
= CTRL_SIZE
+ skb_shinfo(skb
)->nr_frags
* DS_SIZE
+
543 ALIGN(*lso_header_size
+ 4, DS_SIZE
);
544 if (unlikely(*lso_header_size
!= skb_headlen(skb
))) {
545 /* We add a segment for the skb linear buffer only if
546 * it contains data */
547 if (*lso_header_size
< skb_headlen(skb
))
548 real_size
+= DS_SIZE
;
550 if (netif_msg_tx_err(priv
))
551 mlx4_warn(mdev
, "Non-linear headers\n");
552 dev_kfree_skb_any(skb
);
556 if (unlikely(*lso_header_size
> MAX_LSO_HDR_SIZE
)) {
557 if (netif_msg_tx_err(priv
))
558 mlx4_warn(mdev
, "LSO header size too big\n");
559 dev_kfree_skb_any(skb
);
563 *lso_header_size
= 0;
564 if (!is_inline(skb
, NULL
))
565 real_size
= CTRL_SIZE
+ (skb_shinfo(skb
)->nr_frags
+ 1) * DS_SIZE
;
567 real_size
= inline_size(skb
);
573 static void build_inline_wqe(struct mlx4_en_tx_desc
*tx_desc
, struct sk_buff
*skb
,
574 int real_size
, u16
*vlan_tag
, int tx_ind
, void *fragptr
)
576 struct mlx4_wqe_inline_seg
*inl
= &tx_desc
->inl
;
577 int spc
= MLX4_INLINE_ALIGN
- CTRL_SIZE
- sizeof *inl
;
579 if (skb
->len
<= spc
) {
580 inl
->byte_count
= cpu_to_be32(1 << 31 | skb
->len
);
581 skb_copy_from_linear_data(skb
, inl
+ 1, skb_headlen(skb
));
582 if (skb_shinfo(skb
)->nr_frags
)
583 memcpy(((void *)(inl
+ 1)) + skb_headlen(skb
), fragptr
,
584 skb_shinfo(skb
)->frags
[0].size
);
587 inl
->byte_count
= cpu_to_be32(1 << 31 | spc
);
588 if (skb_headlen(skb
) <= spc
) {
589 skb_copy_from_linear_data(skb
, inl
+ 1, skb_headlen(skb
));
590 if (skb_headlen(skb
) < spc
) {
591 memcpy(((void *)(inl
+ 1)) + skb_headlen(skb
),
592 fragptr
, spc
- skb_headlen(skb
));
593 fragptr
+= spc
- skb_headlen(skb
);
595 inl
= (void *) (inl
+ 1) + spc
;
596 memcpy(((void *)(inl
+ 1)), fragptr
, skb
->len
- spc
);
598 skb_copy_from_linear_data(skb
, inl
+ 1, spc
);
599 inl
= (void *) (inl
+ 1) + spc
;
600 skb_copy_from_linear_data_offset(skb
, spc
, inl
+ 1,
601 skb_headlen(skb
) - spc
);
602 if (skb_shinfo(skb
)->nr_frags
)
603 memcpy(((void *)(inl
+ 1)) + skb_headlen(skb
) - spc
,
604 fragptr
, skb_shinfo(skb
)->frags
[0].size
);
608 inl
->byte_count
= cpu_to_be32(1 << 31 | (skb
->len
- spc
));
610 tx_desc
->ctrl
.vlan_tag
= cpu_to_be16(*vlan_tag
);
611 tx_desc
->ctrl
.ins_vlan
= MLX4_WQE_CTRL_INS_VLAN
* !!(*vlan_tag
);
612 tx_desc
->ctrl
.fence_size
= (real_size
/ 16) & 0x3f;
615 static int get_vlan_info(struct mlx4_en_priv
*priv
, struct sk_buff
*skb
,
620 /* Obtain VLAN information if present */
621 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
622 *vlan_tag
= vlan_tx_tag_get(skb
);
623 /* Set the Tx ring to use according to vlan priority */
624 tx_ind
= priv
->tx_prio_map
[*vlan_tag
>> 13];
632 int mlx4_en_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
634 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
635 struct mlx4_en_dev
*mdev
= priv
->mdev
;
636 struct mlx4_en_tx_ring
*ring
;
637 struct mlx4_en_cq
*cq
;
638 struct mlx4_en_tx_desc
*tx_desc
;
639 struct mlx4_wqe_data_seg
*data
;
640 struct skb_frag_struct
*frag
;
641 struct mlx4_en_tx_info
*tx_info
;
654 if (unlikely(!skb
->len
)) {
655 dev_kfree_skb_any(skb
);
658 real_size
= get_real_size(skb
, dev
, &lso_header_size
);
659 if (unlikely(!real_size
))
662 /* Allign descriptor to TXBB size */
663 desc_size
= ALIGN(real_size
, TXBB_SIZE
);
664 nr_txbb
= desc_size
/ TXBB_SIZE
;
665 if (unlikely(nr_txbb
> MAX_DESC_TXBBS
)) {
666 if (netif_msg_tx_err(priv
))
667 mlx4_warn(mdev
, "Oversized header or SG list\n");
668 dev_kfree_skb_any(skb
);
672 tx_ind
= get_vlan_info(priv
, skb
, &vlan_tag
);
673 ring
= &priv
->tx_ring
[tx_ind
];
675 /* Check available TXBBs And 2K spare for prefetch */
676 if (unlikely(((int)(ring
->prod
- ring
->cons
)) >
677 ring
->size
- HEADROOM
- MAX_DESC_TXBBS
)) {
678 /* every full Tx ring stops queue.
679 * TODO: implement multi-queue support (per-queue stop) */
680 netif_stop_queue(dev
);
682 priv
->port_stats
.queue_stopped
++;
684 /* Use interrupts to find out when queue opened */
685 cq
= &priv
->tx_cq
[tx_ind
];
686 mlx4_en_arm_cq(priv
, cq
);
687 return NETDEV_TX_BUSY
;
690 /* Now that we know what Tx ring to use */
691 if (unlikely(!priv
->port_up
)) {
692 if (netif_msg_tx_err(priv
))
693 mlx4_warn(mdev
, "xmit: port down!\n");
694 dev_kfree_skb_any(skb
);
698 /* Track current inflight packets for performance analysis */
699 AVG_PERF_COUNTER(priv
->pstats
.inflight_avg
,
700 (u32
) (ring
->prod
- ring
->cons
- 1));
702 /* Packet is good - grab an index and transmit it */
703 index
= ring
->prod
& ring
->size_mask
;
705 /* See if we have enough space for whole descriptor TXBB for setting
706 * SW ownership on next descriptor; if not, use a bounce buffer. */
707 if (likely(index
+ nr_txbb
<= ring
->size
))
708 tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
710 tx_desc
= (struct mlx4_en_tx_desc
*) ring
->bounce_buf
;
712 /* Save skb in tx_info ring */
713 tx_info
= &ring
->tx_info
[index
];
715 tx_info
->nr_txbb
= nr_txbb
;
717 /* Prepare ctrl segement apart opcode+ownership, which depends on
718 * whether LSO is used */
719 tx_desc
->ctrl
.vlan_tag
= cpu_to_be16(vlan_tag
);
720 tx_desc
->ctrl
.ins_vlan
= MLX4_WQE_CTRL_INS_VLAN
* !!vlan_tag
;
721 tx_desc
->ctrl
.fence_size
= (real_size
/ 16) & 0x3f;
722 tx_desc
->ctrl
.srcrb_flags
= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
|
723 MLX4_WQE_CTRL_SOLICITED
);
724 if (likely(skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
725 tx_desc
->ctrl
.srcrb_flags
|= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM
|
726 MLX4_WQE_CTRL_TCP_UDP_CSUM
);
727 priv
->port_stats
.tx_chksum_offload
++;
730 /* Handle LSO (TSO) packets */
731 if (lso_header_size
) {
732 /* Mark opcode as LSO */
733 op_own
= cpu_to_be32(MLX4_OPCODE_LSO
| (1 << 6)) |
734 ((ring
->prod
& ring
->size
) ?
735 cpu_to_be32(MLX4_EN_BIT_DESC_OWN
) : 0);
737 /* Fill in the LSO prefix */
738 tx_desc
->lso
.mss_hdr_size
= cpu_to_be32(
739 skb_shinfo(skb
)->gso_size
<< 16 | lso_header_size
);
742 * note that we already verified that it is linear */
743 memcpy(tx_desc
->lso
.header
, skb
->data
, lso_header_size
);
744 data
= ((void *) &tx_desc
->lso
+
745 ALIGN(lso_header_size
+ 4, DS_SIZE
));
747 priv
->port_stats
.tso_packets
++;
748 i
= ((skb
->len
- lso_header_size
) / skb_shinfo(skb
)->gso_size
) +
749 !!((skb
->len
- lso_header_size
) % skb_shinfo(skb
)->gso_size
);
750 ring
->bytes
+= skb
->len
+ (i
- 1) * lso_header_size
;
753 /* Normal (Non LSO) packet */
754 op_own
= cpu_to_be32(MLX4_OPCODE_SEND
) |
755 ((ring
->prod
& ring
->size
) ?
756 cpu_to_be32(MLX4_EN_BIT_DESC_OWN
) : 0);
757 data
= &tx_desc
->data
;
758 ring
->bytes
+= max(skb
->len
, (unsigned int) ETH_ZLEN
);
762 AVG_PERF_COUNTER(priv
->pstats
.tx_pktsz_avg
, skb
->len
);
765 /* valid only for none inline segments */
766 tx_info
->data_offset
= (void *) data
- (void *) tx_desc
;
768 tx_info
->linear
= (lso_header_size
< skb_headlen(skb
) && !is_inline(skb
, NULL
)) ? 1 : 0;
769 data
+= skb_shinfo(skb
)->nr_frags
+ tx_info
->linear
- 1;
771 if (!is_inline(skb
, &fragptr
)) {
773 for (i
= skb_shinfo(skb
)->nr_frags
- 1; i
>= 0; i
--) {
774 frag
= &skb_shinfo(skb
)->frags
[i
];
775 dma
= pci_map_page(mdev
->dev
->pdev
, frag
->page
, frag
->page_offset
,
776 frag
->size
, PCI_DMA_TODEVICE
);
777 data
->addr
= cpu_to_be64(dma
);
778 data
->lkey
= cpu_to_be32(mdev
->mr
.key
);
780 data
->byte_count
= cpu_to_be32(frag
->size
);
784 /* Map linear part */
785 if (tx_info
->linear
) {
786 dma
= pci_map_single(mdev
->dev
->pdev
, skb
->data
+ lso_header_size
,
787 skb_headlen(skb
) - lso_header_size
, PCI_DMA_TODEVICE
);
788 data
->addr
= cpu_to_be64(dma
);
789 data
->lkey
= cpu_to_be32(mdev
->mr
.key
);
791 data
->byte_count
= cpu_to_be32(skb_headlen(skb
) - lso_header_size
);
794 build_inline_wqe(tx_desc
, skb
, real_size
, &vlan_tag
, tx_ind
, fragptr
);
796 ring
->prod
+= nr_txbb
;
798 /* If we used a bounce buffer then copy descriptor back into place */
799 if (tx_desc
== (struct mlx4_en_tx_desc
*) ring
->bounce_buf
)
800 tx_desc
= mlx4_en_bounce_to_desc(priv
, ring
, index
, desc_size
);
802 /* Run destructor before passing skb to HW */
803 if (likely(!skb_shared(skb
)))
806 /* Ensure new descirptor hits memory
807 * before setting ownership of this descriptor to HW */
809 tx_desc
->ctrl
.owner_opcode
= op_own
;
813 writel(ring
->doorbell_qpn
, mdev
->uar_map
+ MLX4_SEND_DOORBELL
);
814 dev
->trans_start
= jiffies
;
817 mlx4_en_xmit_poll(priv
, tx_ind
);