drivers/net/wireless/ipw2200.h

   1 /******************************************************************************
   2
   3   Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
   4
   5   This program is free software; you can redistribute it and/or modify it
   6   under the terms of version 2 of the GNU General Public License as
   7   published by the Free Software Foundation.
   8
   9   This program is distributed in the hope that it will be useful, but WITHOUT
  10   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12   more details.
  13
  14   You should have received a copy of the GNU General Public License along with
  15   this program; if not, write to the Free Software Foundation, Inc., 59
  16   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17
  18   The full GNU General Public License is included in this distribution in the
  19   file called LICENSE.
  20
  21   Contact Information:
  22   James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24
  25 ******************************************************************************/
  26
  27 #ifndef __ipw2200_h__
  28 #define __ipw2200_h__
  29
  30 #define WEXT_USECHANNELS 1
  31
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/init.h>
  35 #include <linux/mutex.h>
  36
  37 #include <linux/pci.h>
  38 #include <linux/netdevice.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/etherdevice.h>
  42 #include <linux/delay.h>
  43 #include <linux/random.h>
  44 #include <linux/dma-mapping.h>
  45
  46 #include <linux/firmware.h>
  47 #include <linux/wireless.h>
  48 #include <linux/jiffies.h>
  49 #include <asm/io.h>
  50
  51 #include <net/ieee80211.h>
  52 #include <net/ieee80211_radiotap.h>
  53
  54 #define DRV_NAME        "ipw2200"
  55
  56 #include <linux/workqueue.h>
  57
  58 /* Authentication  and Association States */
  59 enum connection_manager_assoc_states {
  60         CMAS_INIT = 0,
  61         CMAS_TX_AUTH_SEQ_1,
  62         CMAS_RX_AUTH_SEQ_2,
  63         CMAS_AUTH_SEQ_1_PASS,
  64         CMAS_AUTH_SEQ_1_FAIL,
  65         CMAS_TX_AUTH_SEQ_3,
  66         CMAS_RX_AUTH_SEQ_4,
  67         CMAS_AUTH_SEQ_2_PASS,
  68         CMAS_AUTH_SEQ_2_FAIL,
  69         CMAS_AUTHENTICATED,
  70         CMAS_TX_ASSOC,
  71         CMAS_RX_ASSOC_RESP,
  72         CMAS_ASSOCIATED,
  73         CMAS_LAST
  74 };
  75
  76 #define IPW_WAIT                     (1<<0)
  77 #define IPW_QUIET                    (1<<1)
  78 #define IPW_ROAMING                  (1<<2)
  79
  80 #define IPW_POWER_MODE_CAM           0x00       //(always on)
  81 #define IPW_POWER_INDEX_1            0x01
  82 #define IPW_POWER_INDEX_2            0x02
  83 #define IPW_POWER_INDEX_3            0x03
  84 #define IPW_POWER_INDEX_4            0x04
  85 #define IPW_POWER_INDEX_5            0x05
  86 #define IPW_POWER_AC                 0x06
  87 #define IPW_POWER_BATTERY            0x07
  88 #define IPW_POWER_LIMIT              0x07
  89 #define IPW_POWER_MASK               0x0F
  90 #define IPW_POWER_ENABLED            0x10
  91 #define IPW_POWER_LEVEL(x)           ((x) & IPW_POWER_MASK)
  92
  93 #define IPW_CMD_HOST_COMPLETE                 2
  94 #define IPW_CMD_POWER_DOWN                    4
  95 #define IPW_CMD_SYSTEM_CONFIG                 6
  96 #define IPW_CMD_MULTICAST_ADDRESS             7
  97 #define IPW_CMD_SSID                          8
  98 #define IPW_CMD_ADAPTER_ADDRESS              11
  99 #define IPW_CMD_PORT_TYPE                    12
 100 #define IPW_CMD_RTS_THRESHOLD                15
 101 #define IPW_CMD_FRAG_THRESHOLD               16
 102 #define IPW_CMD_POWER_MODE                   17
 103 #define IPW_CMD_WEP_KEY                      18
 104 #define IPW_CMD_TGI_TX_KEY                   19
 105 #define IPW_CMD_SCAN_REQUEST                 20
 106 #define IPW_CMD_ASSOCIATE                    21
 107 #define IPW_CMD_SUPPORTED_RATES              22
 108 #define IPW_CMD_SCAN_ABORT                   23
 109 #define IPW_CMD_TX_FLUSH                     24
 110 #define IPW_CMD_QOS_PARAMETERS               25
 111 #define IPW_CMD_SCAN_REQUEST_EXT             26
 112 #define IPW_CMD_DINO_CONFIG                  30
 113 #define IPW_CMD_RSN_CAPABILITIES             31
 114 #define IPW_CMD_RX_KEY                       32
 115 #define IPW_CMD_CARD_DISABLE                 33
 116 #define IPW_CMD_SEED_NUMBER                  34
 117 #define IPW_CMD_TX_POWER                     35
 118 #define IPW_CMD_COUNTRY_INFO                 36
 119 #define IPW_CMD_AIRONET_INFO                 37
 120 #define IPW_CMD_AP_TX_POWER                  38
 121 #define IPW_CMD_CCKM_INFO                    39
 122 #define IPW_CMD_CCX_VER_INFO                 40
 123 #define IPW_CMD_SET_CALIBRATION              41
 124 #define IPW_CMD_SENSITIVITY_CALIB            42
 125 #define IPW_CMD_RETRY_LIMIT                  51
 126 #define IPW_CMD_IPW_PRE_POWER_DOWN           58
 127 #define IPW_CMD_VAP_BEACON_TEMPLATE          60
 128 #define IPW_CMD_VAP_DTIM_PERIOD              61
 129 #define IPW_CMD_EXT_SUPPORTED_RATES          62
 130 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT  63
 131 #define IPW_CMD_VAP_QUIET_INTERVALS          64
 132 #define IPW_CMD_VAP_CHANNEL_SWITCH           65
 133 #define IPW_CMD_VAP_MANDATORY_CHANNELS       66
 134 #define IPW_CMD_VAP_CELL_PWR_LIMIT           67
 135 #define IPW_CMD_VAP_CF_PARAM_SET             68
 136 #define IPW_CMD_VAP_SET_BEACONING_STATE      69
 137 #define IPW_CMD_MEASUREMENT                  80
 138 #define IPW_CMD_POWER_CAPABILITY             81
 139 #define IPW_CMD_SUPPORTED_CHANNELS           82
 140 #define IPW_CMD_TPC_REPORT                   83
 141 #define IPW_CMD_WME_INFO                     84
 142 #define IPW_CMD_PRODUCTION_COMMAND           85
 143 #define IPW_CMD_LINKSYS_EOU_INFO             90
 144
 145 #define RFD_SIZE                              4
 146 #define NUM_TFD_CHUNKS                        6
 147
 148 #define TX_QUEUE_SIZE                        32
 149 #define RX_QUEUE_SIZE                        32
 150
 151 #define DINO_CMD_WEP_KEY                   0x08
 152 #define DINO_CMD_TX                        0x0B
 153 #define DCT_ANTENNA_A                      0x01
 154 #define DCT_ANTENNA_B                      0x02
 155
 156 #define IPW_A_MODE                         0
 157 #define IPW_B_MODE                         1
 158 #define IPW_G_MODE                         2
 159
 160 /*
 161  * TX Queue Flag Definitions
 162  */
 163
 164 /* tx wep key definition */
 165 #define DCT_WEP_KEY_NOT_IMMIDIATE       0x00
 166 #define DCT_WEP_KEY_64Bit               0x40
 167 #define DCT_WEP_KEY_128Bit              0x80
 168 #define DCT_WEP_KEY_128bitIV            0xC0
 169 #define DCT_WEP_KEY_SIZE_MASK           0xC0
 170
 171 #define DCT_WEP_KEY_INDEX_MASK          0x0F
 172 #define DCT_WEP_INDEX_USE_IMMEDIATE     0x20
 173
 174 /* abort attempt if mgmt frame is rx'd */
 175 #define DCT_FLAG_ABORT_MGMT                0x01
 176
 177 /* require CTS */
 178 #define DCT_FLAG_CTS_REQUIRED              0x02
 179
 180 /* use short preamble */
 181 #define DCT_FLAG_LONG_PREAMBLE             0x00
 182 #define DCT_FLAG_SHORT_PREAMBLE            0x04
 183
 184 /* RTS/CTS first */
 185 #define DCT_FLAG_RTS_REQD                  0x08
 186
 187 /* dont calculate duration field */
 188 #define DCT_FLAG_DUR_SET                   0x10
 189
 190 /* even if MAC WEP set (allows pre-encrypt) */
 191 #define DCT_FLAG_NO_WEP              0x20
 192
 193 /* overwrite TSF field */
 194 #define DCT_FLAG_TSF_REQD                  0x40
 195
 196 /* ACK rx is expected to follow */
 197 #define DCT_FLAG_ACK_REQD                  0x80
 198
 199 /* TX flags extension */
 200 #define DCT_FLAG_EXT_MODE_CCK  0x01
 201 #define DCT_FLAG_EXT_MODE_OFDM 0x00
 202
 203 #define DCT_FLAG_EXT_SECURITY_WEP     0x00
 204 #define DCT_FLAG_EXT_SECURITY_NO      DCT_FLAG_EXT_SECURITY_WEP
 205 #define DCT_FLAG_EXT_SECURITY_CKIP    0x04
 206 #define DCT_FLAG_EXT_SECURITY_CCM     0x08
 207 #define DCT_FLAG_EXT_SECURITY_TKIP    0x0C
 208 #define DCT_FLAG_EXT_SECURITY_MASK    0x0C
 209
 210 #define DCT_FLAG_EXT_QOS_ENABLED      0x10
 211
 212 #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS  0x00
 213 #define DCT_FLAG_EXT_HC_SIFS          0x20
 214 #define DCT_FLAG_EXT_HC_PIFS          0x40
 215
 216 #define TX_RX_TYPE_MASK                    0xFF
 217 #define TX_FRAME_TYPE                      0x00
 218 #define TX_HOST_COMMAND_TYPE               0x01
 219 #define RX_FRAME_TYPE                      0x09
 220 #define RX_HOST_NOTIFICATION_TYPE          0x03
 221 #define RX_HOST_CMD_RESPONSE_TYPE          0x04
 222 #define RX_TX_FRAME_RESPONSE_TYPE          0x05
 223 #define TFD_NEED_IRQ_MASK                  0x04
 224
 225 #define HOST_CMD_DINO_CONFIG               30
 226
 227 #define HOST_NOTIFICATION_STATUS_ASSOCIATED             10
 228 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE           11
 229 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT    12
 230 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED         13
 231 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH            14
 232 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION     15
 233 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE          16
 234 #define HOST_NOTIFICATION_STATUS_BEACON_STATE           17
 235 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY             18
 236 #define HOST_NOTIFICATION_TX_STATUS                     19
 237 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS            20
 238 #define HOST_NOTIFICATION_MEASUREMENT_STARTED           21
 239 #define HOST_NOTIFICATION_MEASUREMENT_ENDED             22
 240 #define HOST_NOTIFICATION_CHANNEL_SWITCHED              23
 241 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD        24
 242 #define HOST_NOTIFICATION_NOISE_STATS                   25
 243 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED      30
 244 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED       31
 245
 246 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING         1
 247 #define IPW_MB_ROAMING_THRESHOLD_MIN                    1
 248 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT                8
 249 #define IPW_MB_ROAMING_THRESHOLD_MAX                    30
 250 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT           3*IPW_MB_ROAMING_THRESHOLD_DEFAULT
 251 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD               300
 252
 253 #define MACADRR_BYTE_LEN                     6
 254
 255 #define DCR_TYPE_AP                       0x01
 256 #define DCR_TYPE_WLAP                     0x02
 257 #define DCR_TYPE_MU_ESS                   0x03
 258 #define DCR_TYPE_MU_IBSS                  0x04
 259 #define DCR_TYPE_MU_PIBSS                 0x05
 260 #define DCR_TYPE_SNIFFER                  0x06
 261 #define DCR_TYPE_MU_BSS        DCR_TYPE_MU_ESS
 262
 263 /* QoS  definitions */
 264
 265 #define CW_MIN_OFDM          15
 266 #define CW_MAX_OFDM          1023
 267 #define CW_MIN_CCK           31
 268 #define CW_MAX_CCK           1023
 269
 270 #define QOS_TX0_CW_MIN_OFDM      CW_MIN_OFDM
 271 #define QOS_TX1_CW_MIN_OFDM      CW_MIN_OFDM
 272 #define QOS_TX2_CW_MIN_OFDM      ( (CW_MIN_OFDM + 1) / 2 - 1 )
 273 #define QOS_TX3_CW_MIN_OFDM      ( (CW_MIN_OFDM + 1) / 4 - 1 )
 274
 275 #define QOS_TX0_CW_MIN_CCK       CW_MIN_CCK
 276 #define QOS_TX1_CW_MIN_CCK       CW_MIN_CCK
 277 #define QOS_TX2_CW_MIN_CCK       ( (CW_MIN_CCK + 1) / 2 - 1 )
 278 #define QOS_TX3_CW_MIN_CCK       ( (CW_MIN_CCK + 1) / 4 - 1 )
 279
 280 #define QOS_TX0_CW_MAX_OFDM      CW_MAX_OFDM
 281 #define QOS_TX1_CW_MAX_OFDM      CW_MAX_OFDM
 282 #define QOS_TX2_CW_MAX_OFDM      CW_MIN_OFDM
 283 #define QOS_TX3_CW_MAX_OFDM      ( (CW_MIN_OFDM + 1) / 2 - 1 )
 284
 285 #define QOS_TX0_CW_MAX_CCK       CW_MAX_CCK
 286 #define QOS_TX1_CW_MAX_CCK       CW_MAX_CCK
 287 #define QOS_TX2_CW_MAX_CCK       CW_MIN_CCK
 288 #define QOS_TX3_CW_MAX_CCK       ( (CW_MIN_CCK + 1) / 2 - 1 )
 289
 290 #define QOS_TX0_AIFS            (3 - QOS_AIFSN_MIN_VALUE)
 291 #define QOS_TX1_AIFS            (7 - QOS_AIFSN_MIN_VALUE)
 292 #define QOS_TX2_AIFS            (2 - QOS_AIFSN_MIN_VALUE)
 293 #define QOS_TX3_AIFS            (2 - QOS_AIFSN_MIN_VALUE)
 294
 295 #define QOS_TX0_ACM             0
 296 #define QOS_TX1_ACM             0
 297 #define QOS_TX2_ACM             0
 298 #define QOS_TX3_ACM             0
 299
 300 #define QOS_TX0_TXOP_LIMIT_CCK          0
 301 #define QOS_TX1_TXOP_LIMIT_CCK          0
 302 #define QOS_TX2_TXOP_LIMIT_CCK          6016
 303 #define QOS_TX3_TXOP_LIMIT_CCK          3264
 304
 305 #define QOS_TX0_TXOP_LIMIT_OFDM      0
 306 #define QOS_TX1_TXOP_LIMIT_OFDM      0
 307 #define QOS_TX2_TXOP_LIMIT_OFDM      3008
 308 #define QOS_TX3_TXOP_LIMIT_OFDM      1504
 309
 310 #define DEF_TX0_CW_MIN_OFDM      CW_MIN_OFDM
 311 #define DEF_TX1_CW_MIN_OFDM      CW_MIN_OFDM
 312 #define DEF_TX2_CW_MIN_OFDM      CW_MIN_OFDM
 313 #define DEF_TX3_CW_MIN_OFDM      CW_MIN_OFDM
 314
 315 #define DEF_TX0_CW_MIN_CCK       CW_MIN_CCK
 316 #define DEF_TX1_CW_MIN_CCK       CW_MIN_CCK
 317 #define DEF_TX2_CW_MIN_CCK       CW_MIN_CCK
 318 #define DEF_TX3_CW_MIN_CCK       CW_MIN_CCK
 319
 320 #define DEF_TX0_CW_MAX_OFDM      CW_MAX_OFDM
 321 #define DEF_TX1_CW_MAX_OFDM      CW_MAX_OFDM
 322 #define DEF_TX2_CW_MAX_OFDM      CW_MAX_OFDM
 323 #define DEF_TX3_CW_MAX_OFDM      CW_MAX_OFDM
 324
 325 #define DEF_TX0_CW_MAX_CCK       CW_MAX_CCK
 326 #define DEF_TX1_CW_MAX_CCK       CW_MAX_CCK
 327 #define DEF_TX2_CW_MAX_CCK       CW_MAX_CCK
 328 #define DEF_TX3_CW_MAX_CCK       CW_MAX_CCK
 329
 330 #define DEF_TX0_AIFS            0
 331 #define DEF_TX1_AIFS            0
 332 #define DEF_TX2_AIFS            0
 333 #define DEF_TX3_AIFS            0
 334
 335 #define DEF_TX0_ACM             0
 336 #define DEF_TX1_ACM             0
 337 #define DEF_TX2_ACM             0
 338 #define DEF_TX3_ACM             0
 339
 340 #define DEF_TX0_TXOP_LIMIT_CCK        0
 341 #define DEF_TX1_TXOP_LIMIT_CCK        0
 342 #define DEF_TX2_TXOP_LIMIT_CCK        0
 343 #define DEF_TX3_TXOP_LIMIT_CCK        0
 344
 345 #define DEF_TX0_TXOP_LIMIT_OFDM       0
 346 #define DEF_TX1_TXOP_LIMIT_OFDM       0
 347 #define DEF_TX2_TXOP_LIMIT_OFDM       0
 348 #define DEF_TX3_TXOP_LIMIT_OFDM       0
 349
 350 #define QOS_QOS_SETS                  3
 351 #define QOS_PARAM_SET_ACTIVE          0
 352 #define QOS_PARAM_SET_DEF_CCK         1
 353 #define QOS_PARAM_SET_DEF_OFDM        2
 354
 355 #define CTRL_QOS_NO_ACK               (0x0020)
 356
 357 #define IPW_TX_QUEUE_1        1
 358 #define IPW_TX_QUEUE_2        2
 359 #define IPW_TX_QUEUE_3        3
 360 #define IPW_TX_QUEUE_4        4
 361
 362 /* QoS sturctures */
 363 struct ipw_qos_info {
 364         int qos_enable;
 365         struct ieee80211_qos_parameters *def_qos_parm_OFDM;
 366         struct ieee80211_qos_parameters *def_qos_parm_CCK;
 367         u32 burst_duration_CCK;
 368         u32 burst_duration_OFDM;
 369         u16 qos_no_ack_mask;
 370         int burst_enable;
 371 };
 372
 373 /**************************************************************/
 374 /**
 375  * Generic queue structure
 376  *
 377  * Contains common data for Rx and Tx queues
 378  */
 379 struct clx2_queue {
 380         int n_bd;                      /**< number of BDs in this queue */
 381         int first_empty;               /**< 1-st empty entry (index) */
 382         int last_used;                 /**< last used entry (index) */
 383         u32 reg_w;                   /**< 'write' reg (queue head), addr in domain 1 */
 384         u32 reg_r;                   /**< 'read' reg (queue tail), addr in domain 1 */
 385         dma_addr_t dma_addr;            /**< physical addr for BD's */
 386         int low_mark;                  /**< low watermark, resume queue if free space more than this */
 387         int high_mark;                 /**< high watermark, stop queue if free space less than this */
 388 } __attribute__ ((packed));
 389
 390 struct machdr32 {
 391         u16 frame_ctl;
 392         u16 duration;           // watch out for endians!
 393         u8 addr1[MACADRR_BYTE_LEN];
 394         u8 addr2[MACADRR_BYTE_LEN];
 395         u8 addr3[MACADRR_BYTE_LEN];
 396         u16 seq_ctrl;           // more endians!
 397         u8 addr4[MACADRR_BYTE_LEN];
 398         u16 qos_ctrl;
 399 } __attribute__ ((packed));
 400
 401 struct machdr30 {
 402         u16 frame_ctl;
 403         u16 duration;           // watch out for endians!
 404         u8 addr1[MACADRR_BYTE_LEN];
 405         u8 addr2[MACADRR_BYTE_LEN];
 406         u8 addr3[MACADRR_BYTE_LEN];
 407         u16 seq_ctrl;           // more endians!
 408         u8 addr4[MACADRR_BYTE_LEN];
 409 } __attribute__ ((packed));
 410
 411 struct machdr26 {
 412         u16 frame_ctl;
 413         u16 duration;           // watch out for endians!
 414         u8 addr1[MACADRR_BYTE_LEN];
 415         u8 addr2[MACADRR_BYTE_LEN];
 416         u8 addr3[MACADRR_BYTE_LEN];
 417         u16 seq_ctrl;           // more endians!
 418         u16 qos_ctrl;
 419 } __attribute__ ((packed));
 420
 421 struct machdr24 {
 422         u16 frame_ctl;
 423         u16 duration;           // watch out for endians!
 424         u8 addr1[MACADRR_BYTE_LEN];
 425         u8 addr2[MACADRR_BYTE_LEN];
 426         u8 addr3[MACADRR_BYTE_LEN];
 427         u16 seq_ctrl;           // more endians!
 428 } __attribute__ ((packed));
 429
 430 // TX TFD with 32 byte MAC Header
 431 struct tx_tfd_32 {
 432         struct machdr32 mchdr;  // 32
 433         u32 uivplaceholder[2];  // 8
 434 } __attribute__ ((packed));
 435
 436 // TX TFD with 30 byte MAC Header
 437 struct tx_tfd_30 {
 438         struct machdr30 mchdr;  // 30
 439         u8 reserved[2];         // 2
 440         u32 uivplaceholder[2];  // 8
 441 } __attribute__ ((packed));
 442
 443 // tx tfd with 26 byte mac header
 444 struct tx_tfd_26 {
 445         struct machdr26 mchdr;  // 26
 446         u8 reserved1[2];        // 2
 447         u32 uivplaceholder[2];  // 8
 448         u8 reserved2[4];        // 4
 449 } __attribute__ ((packed));
 450
 451 // tx tfd with 24 byte mac header
 452 struct tx_tfd_24 {
 453         struct machdr24 mchdr;  // 24
 454         u32 uivplaceholder[2];  // 8
 455         u8 reserved[8];         // 8
 456 } __attribute__ ((packed));
 457
 458 #define DCT_WEP_KEY_FIELD_LENGTH 16
 459
 460 struct tfd_command {
 461         u8 index;
 462         u8 length;
 463         u16 reserved;
 464         u8 payload[0];
 465 } __attribute__ ((packed));
 466
 467 struct tfd_data {
 468         /* Header */
 469         u32 work_area_ptr;
 470         u8 station_number;      /* 0 for BSS */
 471         u8 reserved1;
 472         u16 reserved2;
 473
 474         /* Tx Parameters */
 475         u8 cmd_id;
 476         u8 seq_num;
 477         u16 len;
 478         u8 priority;
 479         u8 tx_flags;
 480         u8 tx_flags_ext;
 481         u8 key_index;
 482         u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
 483         u8 rate;
 484         u8 antenna;
 485         u16 next_packet_duration;
 486         u16 next_frag_len;
 487         u16 back_off_counter;   //////txop;
 488         u8 retrylimit;
 489         u16 cwcurrent;
 490         u8 reserved3;
 491
 492         /* 802.11 MAC Header */
 493         union {
 494                 struct tx_tfd_24 tfd_24;
 495                 struct tx_tfd_26 tfd_26;
 496                 struct tx_tfd_30 tfd_30;
 497                 struct tx_tfd_32 tfd_32;
 498         } tfd;
 499
 500         /* Payload DMA info */
 501         u32 num_chunks;
 502         u32 chunk_ptr[NUM_TFD_CHUNKS];
 503         u16 chunk_len[NUM_TFD_CHUNKS];
 504 } __attribute__ ((packed));
 505
 506 struct txrx_control_flags {
 507         u8 message_type;
 508         u8 rx_seq_num;
 509         u8 control_bits;
 510         u8 reserved;
 511 } __attribute__ ((packed));
 512
 513 #define  TFD_SIZE                           128
 514 #define  TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH   (TFD_SIZE - sizeof(struct txrx_control_flags))
 515
 516 struct tfd_frame {
 517         struct txrx_control_flags control_flags;
 518         union {
 519                 struct tfd_data data;
 520                 struct tfd_command cmd;
 521                 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
 522         } u;
 523 } __attribute__ ((packed));
 524
 525 typedef void destructor_func(const void *);
 526
 527 /**
 528  * Tx Queue for DMA. Queue consists of circular buffer of
 529  * BD's and required locking structures.
 530  */
 531 struct clx2_tx_queue {
 532         struct clx2_queue q;
 533         struct tfd_frame *bd;
 534         struct ieee80211_txb **txb;
 535 };
 536
 537 /*
 538  * RX related structures and functions
 539  */
 540 #define RX_FREE_BUFFERS 32
 541 #define RX_LOW_WATERMARK 8
 542
 543 #define SUP_RATE_11A_MAX_NUM_CHANNELS  8
 544 #define SUP_RATE_11B_MAX_NUM_CHANNELS  4
 545 #define SUP_RATE_11G_MAX_NUM_CHANNELS  12
 546
 547 // Used for passing to driver number of successes and failures per rate
 548 struct rate_histogram {
 549         union {
 550                 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
 551                 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
 552                 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
 553         } success;
 554         union {
 555                 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
 556                 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
 557                 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
 558         } failed;
 559 } __attribute__ ((packed));
 560
 561 /* statistics command response */
 562 struct ipw_cmd_stats {
 563         u8 cmd_id;
 564         u8 seq_num;
 565         u16 good_sfd;
 566         u16 bad_plcp;
 567         u16 wrong_bssid;
 568         u16 valid_mpdu;
 569         u16 bad_mac_header;
 570         u16 reserved_frame_types;
 571         u16 rx_ina;
 572         u16 bad_crc32;
 573         u16 invalid_cts;
 574         u16 invalid_acks;
 575         u16 long_distance_ina_fina;
 576         u16 dsp_silence_unreachable;
 577         u16 accumulated_rssi;
 578         u16 rx_ovfl_frame_tossed;
 579         u16 rssi_silence_threshold;
 580         u16 rx_ovfl_frame_supplied;
 581         u16 last_rx_frame_signal;
 582         u16 last_rx_frame_noise;
 583         u16 rx_autodetec_no_ofdm;
 584         u16 rx_autodetec_no_barker;
 585         u16 reserved;
 586 } __attribute__ ((packed));
 587
 588 struct notif_channel_result {
 589         u8 channel_num;
 590         struct ipw_cmd_stats stats;
 591         u8 uReserved;
 592 } __attribute__ ((packed));
 593
 594 #define SCAN_COMPLETED_STATUS_COMPLETE  1
 595 #define SCAN_COMPLETED_STATUS_ABORTED   2
 596
 597 struct notif_scan_complete {
 598         u8 scan_type;
 599         u8 num_channels;
 600         u8 status;
 601         u8 reserved;
 602 } __attribute__ ((packed));
 603
 604 struct notif_frag_length {
 605         u16 frag_length;
 606         u16 reserved;
 607 } __attribute__ ((packed));
 608
 609 struct notif_beacon_state {
 610         u32 state;
 611         u32 number;
 612 } __attribute__ ((packed));
 613
 614 struct notif_tgi_tx_key {
 615         u8 key_state;
 616         u8 security_type;
 617         u8 station_index;
 618         u8 reserved;
 619 } __attribute__ ((packed));
 620
 621 #define SILENCE_OVER_THRESH (1)
 622 #define SILENCE_UNDER_THRESH (2)
 623
 624 struct notif_link_deterioration {
 625         struct ipw_cmd_stats stats;
 626         u8 rate;
 627         u8 modulation;
 628         struct rate_histogram histogram;
 629         u8 silence_notification_type;   /* SILENCE_OVER/UNDER_THRESH */
 630         u16 silence_count;
 631 } __attribute__ ((packed));
 632
 633 struct notif_association {
 634         u8 state;
 635 } __attribute__ ((packed));
 636
 637 struct notif_authenticate {
 638         u8 state;
 639         struct machdr24 addr;
 640         u16 status;
 641 } __attribute__ ((packed));
 642
 643 struct notif_calibration {
 644         u8 data[104];
 645 } __attribute__ ((packed));
 646
 647 struct notif_noise {
 648         u32 value;
 649 } __attribute__ ((packed));
 650
 651 struct ipw_rx_notification {
 652         u8 reserved[8];
 653         u8 subtype;
 654         u8 flags;
 655         u16 size;
 656         union {
 657                 struct notif_association assoc;
 658                 struct notif_authenticate auth;
 659                 struct notif_channel_result channel_result;
 660                 struct notif_scan_complete scan_complete;
 661                 struct notif_frag_length frag_len;
 662                 struct notif_beacon_state beacon_state;
 663                 struct notif_tgi_tx_key tgi_tx_key;
 664                 struct notif_link_deterioration link_deterioration;
 665                 struct notif_calibration calibration;
 666                 struct notif_noise noise;
 667                 u8 raw[0];
 668         } u;
 669 } __attribute__ ((packed));
 670
 671 struct ipw_rx_frame {
 672         u32 reserved1;
 673         u8 parent_tsf[4];       // fw_use[0] is boolean for OUR_TSF_IS_GREATER
 674         u8 received_channel;    // The channel that this frame was received on.
 675         // Note that for .11b this does not have to be
 676         // the same as the channel that it was sent.
 677         // Filled by LMAC
 678         u8 frameStatus;
 679         u8 rate;
 680         u8 rssi;
 681         u8 agc;
 682         u8 rssi_dbm;
 683         u16 signal;
 684         u16 noise;
 685         u8 antennaAndPhy;
 686         u8 control;             // control bit should be on in bg
 687         u8 rtscts_rate;         // rate of rts or cts (in rts cts sequence rate
 688         // is identical)
 689         u8 rtscts_seen;         // 0x1 RTS seen ; 0x2 CTS seen
 690         u16 length;
 691         u8 data[0];
 692 } __attribute__ ((packed));
 693
 694 struct ipw_rx_header {
 695         u8 message_type;
 696         u8 rx_seq_num;
 697         u8 control_bits;
 698         u8 reserved;
 699 } __attribute__ ((packed));
 700
 701 struct ipw_rx_packet {
 702         struct ipw_rx_header header;
 703         union {
 704                 struct ipw_rx_frame frame;
 705                 struct ipw_rx_notification notification;
 706         } u;
 707 } __attribute__ ((packed));
 708
 709 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
 710 #define IPW_RX_FRAME_SIZE        (unsigned int)(sizeof(struct ipw_rx_header) + \
 711                                  sizeof(struct ipw_rx_frame))
 712
 713 struct ipw_rx_mem_buffer {
 714         dma_addr_t dma_addr;
 715         struct sk_buff *skb;
 716         struct list_head list;
 717 };                              /* Not transferred over network, so not  __attribute__ ((packed)) */
 718
 719 struct ipw_rx_queue {
 720         struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
 721         struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
 722         u32 processed;          /* Internal index to last handled Rx packet */
 723         u32 read;               /* Shared index to newest available Rx buffer */
 724         u32 write;              /* Shared index to oldest written Rx packet */
 725         u32 free_count;         /* Number of pre-allocated buffers in rx_free */
 726         /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
 727         struct list_head rx_free;       /* Own an SKBs */
 728         struct list_head rx_used;       /* No SKB allocated */
 729         spinlock_t lock;
 730 };                              /* Not transferred over network, so not  __attribute__ ((packed)) */
 731
 732 struct alive_command_responce {
 733         u8 alive_command;
 734         u8 sequence_number;
 735         u16 software_revision;
 736         u8 device_identifier;
 737         u8 reserved1[5];
 738         u16 reserved2;
 739         u16 reserved3;
 740         u16 clock_settle_time;
 741         u16 powerup_settle_time;
 742         u16 reserved4;
 743         u8 time_stamp[5];       /* month, day, year, hours, minutes */
 744         u8 ucode_valid;
 745 } __attribute__ ((packed));
 746
 747 #define IPW_MAX_RATES 12
 748
 749 struct ipw_rates {
 750         u8 num_rates;
 751         u8 rates[IPW_MAX_RATES];
 752 } __attribute__ ((packed));
 753
 754 struct command_block {
 755         unsigned int control;
 756         u32 source_addr;
 757         u32 dest_addr;
 758         unsigned int status;
 759 } __attribute__ ((packed));
 760
 761 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
 762 struct fw_image_desc {
 763         unsigned long last_cb_index;
 764         unsigned long current_cb_index;
 765         struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
 766         void *v_addr;
 767         unsigned long p_addr;
 768         unsigned long len;
 769 };
 770
 771 struct ipw_sys_config {
 772         u8 bt_coexistence;
 773         u8 reserved1;
 774         u8 answer_broadcast_ssid_probe;
 775         u8 accept_all_data_frames;
 776         u8 accept_non_directed_frames;
 777         u8 exclude_unicast_unencrypted;
 778         u8 disable_unicast_decryption;
 779         u8 exclude_multicast_unencrypted;
 780         u8 disable_multicast_decryption;
 781         u8 antenna_diversity;
 782         u8 pass_crc_to_host;
 783         u8 dot11g_auto_detection;
 784         u8 enable_cts_to_self;
 785         u8 enable_multicast_filtering;
 786         u8 bt_coexist_collision_thr;
 787         u8 silence_threshold;
 788         u8 accept_all_mgmt_bcpr;
 789         u8 accept_all_mgmt_frames;
 790         u8 pass_noise_stats_to_host;
 791         u8 reserved3;
 792 } __attribute__ ((packed));
 793
 794 struct ipw_multicast_addr {
 795         u8 num_of_multicast_addresses;
 796         u8 reserved[3];
 797         u8 mac1[6];
 798         u8 mac2[6];
 799         u8 mac3[6];
 800         u8 mac4[6];
 801 } __attribute__ ((packed));
 802
 803 #define DCW_WEP_KEY_INDEX_MASK          0x03    /* bits [0:1] */
 804 #define DCW_WEP_KEY_SEC_TYPE_MASK       0x30    /* bits [4:5] */
 805
 806 #define DCW_WEP_KEY_SEC_TYPE_WEP        0x00
 807 #define DCW_WEP_KEY_SEC_TYPE_CCM        0x20
 808 #define DCW_WEP_KEY_SEC_TYPE_TKIP       0x30
 809
 810 #define DCW_WEP_KEY_INVALID_SIZE        0x00    /* 0 = Invalid key */
 811 #define DCW_WEP_KEY64Bit_SIZE           0x05    /* 64-bit encryption */
 812 #define DCW_WEP_KEY128Bit_SIZE          0x0D    /* 128-bit encryption */
 813 #define DCW_CCM_KEY128Bit_SIZE          0x10    /* 128-bit key */
 814 //#define DCW_WEP_KEY128BitIV_SIZE      0x10    /* 128-bit key and 128-bit IV */
 815
 816 struct ipw_wep_key {
 817         u8 cmd_id;
 818         u8 seq_num;
 819         u8 key_index;
 820         u8 key_size;
 821         u8 key[16];
 822 } __attribute__ ((packed));
 823
 824 struct ipw_tgi_tx_key {
 825         u8 key_id;
 826         u8 security_type;
 827         u8 station_index;
 828         u8 flags;
 829         u8 key[16];
 830         u32 tx_counter[2];
 831 } __attribute__ ((packed));
 832
 833 #define IPW_SCAN_CHANNELS 54
 834
 835 struct ipw_scan_request {
 836         u8 scan_type;
 837         u16 dwell_time;
 838         u8 channels_list[IPW_SCAN_CHANNELS];
 839         u8 channels_reserved[3];
 840 } __attribute__ ((packed));
 841
 842 enum {
 843         IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
 844         IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
 845         IPW_SCAN_ACTIVE_DIRECT_SCAN,
 846         IPW_SCAN_ACTIVE_BROADCAST_SCAN,
 847         IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
 848         IPW_SCAN_TYPES
 849 };
 850
 851 struct ipw_scan_request_ext {
 852         u32 full_scan_index;
 853         u8 channels_list[IPW_SCAN_CHANNELS];
 854         u8 scan_type[IPW_SCAN_CHANNELS / 2];
 855         u8 reserved;
 856         u16 dwell_time[IPW_SCAN_TYPES];
 857 } __attribute__ ((packed));
 858
 859 static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
 860 {
 861         if (index % 2)
 862                 return scan->scan_type[index / 2] & 0x0F;
 863         else
 864                 return (scan->scan_type[index / 2] & 0xF0) >> 4;
 865 }
 866
 867 static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
 868                                      u8 index, u8 scan_type)
 869 {
 870         if (index % 2)
 871                 scan->scan_type[index / 2] =
 872                     (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
 873         else
 874                 scan->scan_type[index / 2] =
 875                     (scan->scan_type[index / 2] & 0x0F) |
 876                     ((scan_type & 0x0F) << 4);
 877 }
 878
 879 struct ipw_associate {
 880         u8 channel;
 881         u8 auth_type:4, auth_key:4;
 882         u8 assoc_type;
 883         u8 reserved;
 884         u16 policy_support;
 885         u8 preamble_length;
 886         u8 ieee_mode;
 887         u8 bssid[ETH_ALEN];
 888         u32 assoc_tsf_msw;
 889         u32 assoc_tsf_lsw;
 890         u16 capability;
 891         u16 listen_interval;
 892         u16 beacon_interval;
 893         u8 dest[ETH_ALEN];
 894         u16 atim_window;
 895         u8 smr;
 896         u8 reserved1;
 897         u16 reserved2;
 898 } __attribute__ ((packed));
 899
 900 struct ipw_supported_rates {
 901         u8 ieee_mode;
 902         u8 num_rates;
 903         u8 purpose;
 904         u8 reserved;
 905         u8 supported_rates[IPW_MAX_RATES];
 906 } __attribute__ ((packed));
 907
 908 struct ipw_rts_threshold {
 909         u16 rts_threshold;
 910         u16 reserved;
 911 } __attribute__ ((packed));
 912
 913 struct ipw_frag_threshold {
 914         u16 frag_threshold;
 915         u16 reserved;
 916 } __attribute__ ((packed));
 917
 918 struct ipw_retry_limit {
 919         u8 short_retry_limit;
 920         u8 long_retry_limit;
 921         u16 reserved;
 922 } __attribute__ ((packed));
 923
 924 struct ipw_dino_config {
 925         u32 dino_config_addr;
 926         u16 dino_config_size;
 927         u8 dino_response;
 928         u8 reserved;
 929 } __attribute__ ((packed));
 930
 931 struct ipw_aironet_info {
 932         u8 id;
 933         u8 length;
 934         u16 reserved;
 935 } __attribute__ ((packed));
 936
 937 struct ipw_rx_key {
 938         u8 station_index;
 939         u8 key_type;
 940         u8 key_id;
 941         u8 key_flag;
 942         u8 key[16];
 943         u8 station_address[6];
 944         u8 key_index;
 945         u8 reserved;
 946 } __attribute__ ((packed));
 947
 948 struct ipw_country_channel_info {
 949         u8 first_channel;
 950         u8 no_channels;
 951         s8 max_tx_power;
 952 } __attribute__ ((packed));
 953
 954 struct ipw_country_info {
 955         u8 id;
 956         u8 length;
 957         u8 country_str[3];
 958         struct ipw_country_channel_info groups[7];
 959 } __attribute__ ((packed));
 960
 961 struct ipw_channel_tx_power {
 962         u8 channel_number;
 963         s8 tx_power;
 964 } __attribute__ ((packed));
 965
 966 #define SCAN_ASSOCIATED_INTERVAL (HZ)
 967 #define SCAN_INTERVAL (HZ / 10)
 968 #define MAX_A_CHANNELS  37
 969 #define MAX_B_CHANNELS  14
 970
 971 struct ipw_tx_power {
 972         u8 num_channels;
 973         u8 ieee_mode;
 974         struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
 975 } __attribute__ ((packed));
 976
 977 struct ipw_rsn_capabilities {
 978         u8 id;
 979         u8 length;
 980         u16 version;
 981 } __attribute__ ((packed));
 982
 983 struct ipw_sensitivity_calib {
 984         u16 beacon_rssi_raw;
 985         u16 reserved;
 986 } __attribute__ ((packed));
 987
 988 /**
 989  * Host command structure.
 990  *
 991  * On input, the following fields should be filled:
 992  * - cmd
 993  * - len
 994  * - status_len
 995  * - param (if needed)
 996  *
 997  * On output,
 998  * - \a status contains status;
 999  * - \a param filled with status parameters.
1000  */
1001 struct ipw_cmd {
1002         u32 cmd;   /**< Host command */
1003         u32 status;/**< Status */
1004         u32 status_len;
1005                    /**< How many 32 bit parameters in the status */
1006         u32 len;   /**< incoming parameters length, bytes */
1007   /**
1008    * command parameters.
1009    * There should be enough space for incoming and
1010    * outcoming parameters.
1011    * Incoming parameters listed 1-st, followed by outcoming params.
1012    * nParams=(len+3)/4+status_len
1013    */
1014         u32 param[0];
1015 } __attribute__ ((packed));
1016
1017 #define STATUS_HCMD_ACTIVE      (1<<0)  /**< host command in progress */
1018
1019 #define STATUS_INT_ENABLED      (1<<1)
1020 #define STATUS_RF_KILL_HW       (1<<2)
1021 #define STATUS_RF_KILL_SW       (1<<3)
1022 #define STATUS_RF_KILL_MASK     (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
1023
1024 #define STATUS_INIT             (1<<5)
1025 #define STATUS_AUTH             (1<<6)
1026 #define STATUS_ASSOCIATED       (1<<7)
1027 #define STATUS_STATE_MASK       (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
1028
1029 #define STATUS_ASSOCIATING      (1<<8)
1030 #define STATUS_DISASSOCIATING   (1<<9)
1031 #define STATUS_ROAMING          (1<<10)
1032 #define STATUS_EXIT_PENDING     (1<<11)
1033 #define STATUS_DISASSOC_PENDING (1<<12)
1034 #define STATUS_STATE_PENDING    (1<<13)
1035
1036 #define STATUS_SCAN_PENDING     (1<<20)
1037 #define STATUS_SCANNING         (1<<21)
1038 #define STATUS_SCAN_ABORTING    (1<<22)
1039 #define STATUS_SCAN_FORCED      (1<<23)
1040
1041 #define STATUS_LED_LINK_ON      (1<<24)
1042 #define STATUS_LED_ACT_ON       (1<<25)
1043
1044 #define STATUS_INDIRECT_BYTE    (1<<28) /* sysfs entry configured for access */
1045 #define STATUS_INDIRECT_DWORD   (1<<29) /* sysfs entry configured for access */
1046 #define STATUS_DIRECT_DWORD     (1<<30) /* sysfs entry configured for access */
1047
1048 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
1049
1050 #define CFG_STATIC_CHANNEL      (1<<0)  /* Restrict assoc. to single channel */
1051 #define CFG_STATIC_ESSID        (1<<1)  /* Restrict assoc. to single SSID */
1052 #define CFG_STATIC_BSSID        (1<<2)  /* Restrict assoc. to single BSSID */
1053 #define CFG_CUSTOM_MAC          (1<<3)
1054 #define CFG_PREAMBLE_LONG       (1<<4)
1055 #define CFG_ADHOC_PERSIST       (1<<5)
1056 #define CFG_ASSOCIATE           (1<<6)
1057 #define CFG_FIXED_RATE          (1<<7)
1058 #define CFG_ADHOC_CREATE        (1<<8)
1059 #define CFG_NO_LED              (1<<9)
1060 #define CFG_BACKGROUND_SCAN     (1<<10)
1061 #define CFG_SPEED_SCAN          (1<<11)
1062 #define CFG_NET_STATS           (1<<12)
1063
1064 #define CAP_SHARED_KEY          (1<<0)  /* Off = OPEN */
1065 #define CAP_PRIVACY_ON          (1<<1)  /* Off = No privacy */
1066
1067 #define MAX_STATIONS            32
1068 #define IPW_INVALID_STATION     (0xff)
1069
1070 struct ipw_station_entry {
1071         u8 mac_addr[ETH_ALEN];
1072         u8 reserved;
1073         u8 support_mode;
1074 };
1075
1076 #define AVG_ENTRIES 8
1077 struct average {
1078         s16 entries[AVG_ENTRIES];
1079         u8 pos;
1080         u8 init;
1081         s32 sum;
1082 };
1083
1084 #define MAX_SPEED_SCAN 100
1085 #define IPW_IBSS_MAC_HASH_SIZE 31
1086
1087 struct ipw_ibss_seq {
1088         u8 mac[ETH_ALEN];
1089         u16 seq_num;
1090         u16 frag_num;
1091         unsigned long packet_time;
1092         struct list_head list;
1093 };
1094
1095 struct ipw_error_elem {
1096         u32 desc;
1097         u32 time;
1098         u32 blink1;
1099         u32 blink2;
1100         u32 link1;
1101         u32 link2;
1102         u32 data;
1103 };
1104
1105 struct ipw_event {
1106         u32 event;
1107         u32 time;
1108         u32 data;
1109 } __attribute__ ((packed));
1110
1111 struct ipw_fw_error {
1112         unsigned long jiffies;
1113         u32 status;
1114         u32 config;
1115         u32 elem_len;
1116         u32 log_len;
1117         struct ipw_error_elem *elem;
1118         struct ipw_event *log;
1119         u8 payload[0];
1120 } __attribute__ ((packed));
1121
1122 #ifdef CONFIG_IPW2200_PROMISCUOUS
1123
1124 enum ipw_prom_filter {
1125         IPW_PROM_CTL_HEADER_ONLY = (1 << 0),
1126         IPW_PROM_MGMT_HEADER_ONLY = (1 << 1),
1127         IPW_PROM_DATA_HEADER_ONLY = (1 << 2),
1128         IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */
1129         IPW_PROM_NO_TX = (1 << 4),
1130         IPW_PROM_NO_RX = (1 << 5),
1131         IPW_PROM_NO_CTL = (1 << 6),
1132         IPW_PROM_NO_MGMT = (1 << 7),
1133         IPW_PROM_NO_DATA = (1 << 8),
1134 };
1135
1136 struct ipw_priv;
1137 struct ipw_prom_priv {
1138         struct ipw_priv *priv;
1139         struct ieee80211_device *ieee;
1140         enum ipw_prom_filter filter;
1141         int tx_packets;
1142         int rx_packets;
1143 };
1144 #endif
1145
1146 #if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS)
1147 /* Magic struct that slots into the radiotap header -- no reason
1148  * to build this manually element by element, we can write it much
1149  * more efficiently than we can parse it. ORDER MATTERS HERE
1150  *
1151  * When sent to us via the simulated Rx interface in sysfs, the entire
1152  * structure is provided regardless of any bits unset.
1153  */
1154 struct ipw_rt_hdr {
1155         struct ieee80211_radiotap_header rt_hdr;
1156         u64 rt_tsf;      /* TSF */
1157         u8 rt_flags;    /* radiotap packet flags */
1158         u8 rt_rate;     /* rate in 500kb/s */
1159         u16 rt_channel; /* channel in mhz */
1160         u16 rt_chbitmask;       /* channel bitfield */
1161         s8 rt_dbmsignal;        /* signal in dbM, kluged to signed */
1162         s8 rt_dbmnoise;
1163         u8 rt_antenna;  /* antenna number */
1164         u8 payload[0];  /* payload... */
1165 } __attribute__ ((packed));
1166 #endif
1167
1168 struct ipw_priv {
1169         /* ieee device used by generic ieee processing code */
1170         struct ieee80211_device *ieee;
1171
1172         spinlock_t lock;
1173         spinlock_t irq_lock;
1174         struct mutex mutex;
1175
1176         /* basic pci-network driver stuff */
1177         struct pci_dev *pci_dev;
1178         struct net_device *net_dev;
1179
1180 #ifdef CONFIG_IPW2200_PROMISCUOUS
1181         /* Promiscuous mode */
1182         struct ipw_prom_priv *prom_priv;
1183         struct net_device *prom_net_dev;
1184 #endif
1185
1186         /* pci hardware address support */
1187         void __iomem *hw_base;
1188         unsigned long hw_len;
1189
1190         struct fw_image_desc sram_desc;
1191
1192         /* result of ucode download */
1193         struct alive_command_responce dino_alive;
1194
1195         wait_queue_head_t wait_command_queue;
1196         wait_queue_head_t wait_state;
1197
1198         /* Rx and Tx DMA processing queues */
1199         struct ipw_rx_queue *rxq;
1200         struct clx2_tx_queue txq_cmd;
1201         struct clx2_tx_queue txq[4];
1202         u32 status;
1203         u32 config;
1204         u32 capability;
1205
1206         struct average average_missed_beacons;
1207         s16 exp_avg_rssi;
1208         s16 exp_avg_noise;
1209         u32 port_type;
1210         int rx_bufs_min;          /**< minimum number of bufs in Rx queue */
1211         int rx_pend_max;          /**< maximum pending buffers for one IRQ */
1212         u32 hcmd_seq;             /**< sequence number for hcmd */
1213         u32 disassociate_threshold;
1214         u32 roaming_threshold;
1215
1216         struct ipw_associate assoc_request;
1217         struct ieee80211_network *assoc_network;
1218
1219         unsigned long ts_scan_abort;
1220         struct ipw_supported_rates rates;
1221         struct ipw_rates phy[3];           /**< PHY restrictions, per band */
1222         struct ipw_rates supp;             /**< software defined */
1223         struct ipw_rates extended;         /**< use for corresp. IE, AP only */
1224
1225         struct notif_link_deterioration last_link_deterioration; /** for statistics */
1226         struct ipw_cmd *hcmd; /**< host command currently executed */
1227
1228         wait_queue_head_t hcmd_wq;     /**< host command waits for execution */
1229         u32 tsf_bcn[2];              /**< TSF from latest beacon */
1230
1231         struct notif_calibration calib; /**< last calibration */
1232
1233         /* ordinal interface with firmware */
1234         u32 table0_addr;
1235         u32 table0_len;
1236         u32 table1_addr;
1237         u32 table1_len;
1238         u32 table2_addr;
1239         u32 table2_len;
1240
1241         /* context information */
1242         u8 essid[IW_ESSID_MAX_SIZE];
1243         u8 essid_len;
1244         u8 nick[IW_ESSID_MAX_SIZE];
1245         u16 rates_mask;
1246         u8 channel;
1247         struct ipw_sys_config sys_config;
1248         u32 power_mode;
1249         u8 bssid[ETH_ALEN];
1250         u16 rts_threshold;
1251         u8 mac_addr[ETH_ALEN];
1252         u8 num_stations;
1253         u8 stations[MAX_STATIONS][ETH_ALEN];
1254         u8 short_retry_limit;
1255         u8 long_retry_limit;
1256
1257         u32 notif_missed_beacons;
1258
1259         /* Statistics and counters normalized with each association */
1260         u32 last_missed_beacons;
1261         u32 last_tx_packets;
1262         u32 last_rx_packets;
1263         u32 last_tx_failures;
1264         u32 last_rx_err;
1265         u32 last_rate;
1266
1267         u32 missed_adhoc_beacons;
1268         u32 missed_beacons;
1269         u32 rx_packets;
1270         u32 tx_packets;
1271         u32 quality;
1272
1273         u8 speed_scan[MAX_SPEED_SCAN];
1274         u8 speed_scan_pos;
1275
1276         u16 last_seq_num;
1277         u16 last_frag_num;
1278         unsigned long last_packet_time;
1279         struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];
1280
1281         /* eeprom */
1282         u8 eeprom[0x100];       /* 256 bytes of eeprom */
1283         u8 country[4];
1284         int eeprom_delay;
1285
1286         struct iw_statistics wstats;
1287
1288         struct iw_public_data wireless_data;
1289
1290         struct workqueue_struct *workqueue;
1291
1292         struct delayed_work adhoc_check;
1293         struct work_struct associate;
1294         struct work_struct disassociate;
1295         struct work_struct system_config;
1296         struct work_struct rx_replenish;
1297         struct delayed_work request_scan;
1298         struct work_struct request_passive_scan;
1299         struct work_struct adapter_restart;
1300         struct delayed_work rf_kill;
1301         struct work_struct up;
1302         struct work_struct down;
1303         struct delayed_work gather_stats;
1304         struct work_struct abort_scan;
1305         struct work_struct roam;
1306         struct delayed_work scan_check;
1307         struct work_struct link_up;
1308         struct work_struct link_down;
1309
1310         struct tasklet_struct irq_tasklet;
1311
1312         /* LED related variables and work_struct */
1313         u8 nic_type;
1314         u32 led_activity_on;
1315         u32 led_activity_off;
1316         u32 led_association_on;
1317         u32 led_association_off;
1318         u32 led_ofdm_on;
1319         u32 led_ofdm_off;
1320
1321         struct delayed_work led_link_on;
1322         struct delayed_work led_link_off;
1323         struct delayed_work led_act_off;
1324         struct work_struct merge_networks;
1325
1326         struct ipw_cmd_log *cmdlog;
1327         int cmdlog_len;
1328         int cmdlog_pos;
1329
1330 #define IPW_2200BG  1
1331 #define IPW_2915ABG 2
1332         u8 adapter;
1333
1334         s8 tx_power;
1335
1336 #ifdef CONFIG_PM
1337         u32 pm_state[16];
1338 #endif
1339
1340         struct ipw_fw_error *error;
1341
1342         /* network state */
1343
1344         /* Used to pass the current INTA value from ISR to Tasklet */
1345         u32 isr_inta;
1346
1347         /* QoS */
1348         struct ipw_qos_info qos_data;
1349         struct work_struct qos_activate;
1350         /*********************************/
1351
1352         /* debugging info */
1353         u32 indirect_dword;
1354         u32 direct_dword;
1355         u32 indirect_byte;
1356 };                              /*ipw_priv */
1357
1358 /* debug macros */
1359
1360 /* Debug and printf string expansion helpers for printing bitfields */
1361 #define BIT_FMT8 "%c%c%c%c-%c%c%c%c"
1362 #define BIT_FMT16 BIT_FMT8 ":" BIT_FMT8
1363 #define BIT_FMT32 BIT_FMT16 " " BIT_FMT16
1364
1365 #define BITC(x,y) (((x>>y)&1)?'1':'0')
1366 #define BIT_ARG8(x) \
1367 BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\
1368 BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)
1369
1370 #define BIT_ARG16(x) \
1371 BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\
1372 BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\
1373 BIT_ARG8(x)
1374
1375 #define BIT_ARG32(x) \
1376 BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\
1377 BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\
1378 BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\
1379 BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\
1380 BIT_ARG16(x)
1381
1382
1383 #define IPW_DEBUG(level, fmt, args...) \
1384 do { if (ipw_debug_level & (level)) \
1385   printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1386          in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1387
1388 #ifdef CONFIG_IPW2200_DEBUG
1389 #define IPW_LL_DEBUG(level, fmt, args...) \
1390 do { if (ipw_debug_level & (level)) \
1391   printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1392          in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1393 #else
1394 #define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)
1395 #endif                          /* CONFIG_IPW2200_DEBUG */
1396
1397 /*
1398  * To use the debug system;
1399  *
1400  * If you are defining a new debug classification, simply add it to the #define
1401  * list here in the form of:
1402  *
1403  * #define IPW_DL_xxxx VALUE
1404  *
1405  * shifting value to the left one bit from the previous entry.  xxxx should be
1406  * the name of the classification (for example, WEP)
1407  *
1408  * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1409  * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1410  * to send output to that classification.
1411  *
1412  * To add your debug level to the list of levels seen when you perform
1413  *
1414  * % cat /proc/net/ipw/debug_level
1415  *
1416  * you simply need to add your entry to the ipw_debug_levels array.
1417  *
1418  * If you do not see debug_level in /proc/net/ipw then you do not have
1419  * CONFIG_IPW2200_DEBUG defined in your kernel configuration
1420  *
1421  */
1422
1423 #define IPW_DL_ERROR         (1<<0)
1424 #define IPW_DL_WARNING       (1<<1)
1425 #define IPW_DL_INFO          (1<<2)
1426 #define IPW_DL_WX            (1<<3)
1427 #define IPW_DL_HOST_COMMAND  (1<<5)
1428 #define IPW_DL_STATE         (1<<6)
1429
1430 #define IPW_DL_NOTIF         (1<<10)
1431 #define IPW_DL_SCAN          (1<<11)
1432 #define IPW_DL_ASSOC         (1<<12)
1433 #define IPW_DL_DROP          (1<<13)
1434 #define IPW_DL_IOCTL         (1<<14)
1435
1436 #define IPW_DL_MANAGE        (1<<15)
1437 #define IPW_DL_FW            (1<<16)
1438 #define IPW_DL_RF_KILL       (1<<17)
1439 #define IPW_DL_FW_ERRORS     (1<<18)
1440
1441 #define IPW_DL_LED           (1<<19)
1442
1443 #define IPW_DL_ORD           (1<<20)
1444
1445 #define IPW_DL_FRAG          (1<<21)
1446 #define IPW_DL_WEP           (1<<22)
1447 #define IPW_DL_TX            (1<<23)
1448 #define IPW_DL_RX            (1<<24)
1449 #define IPW_DL_ISR           (1<<25)
1450 #define IPW_DL_FW_INFO       (1<<26)
1451 #define IPW_DL_IO            (1<<27)
1452 #define IPW_DL_TRACE         (1<<28)
1453
1454 #define IPW_DL_STATS         (1<<29)
1455 #define IPW_DL_MERGE         (1<<30)
1456 #define IPW_DL_QOS           (1<<31)
1457
1458 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1459 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1460 #define IPW_DEBUG_INFO(f, a...)    IPW_DEBUG(IPW_DL_INFO, f, ## a)
1461
1462 #define IPW_DEBUG_WX(f, a...)     IPW_DEBUG(IPW_DL_WX, f, ## a)
1463 #define IPW_DEBUG_SCAN(f, a...)   IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1464 #define IPW_DEBUG_TRACE(f, a...)  IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a)
1465 #define IPW_DEBUG_RX(f, a...)     IPW_LL_DEBUG(IPW_DL_RX, f, ## a)
1466 #define IPW_DEBUG_TX(f, a...)     IPW_LL_DEBUG(IPW_DL_TX, f, ## a)
1467 #define IPW_DEBUG_ISR(f, a...)    IPW_LL_DEBUG(IPW_DL_ISR, f, ## a)
1468 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1469 #define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a)
1470 #define IPW_DEBUG_WEP(f, a...)    IPW_LL_DEBUG(IPW_DL_WEP, f, ## a)
1471 #define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1472 #define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a)
1473 #define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a)
1474 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1475 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1476 #define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a)
1477 #define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a)
1478 #define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a)
1479 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1480 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1481 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1482 #define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a)
1483 #define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a)
1484 #define IPW_DEBUG_QOS(f, a...)   IPW_LL_DEBUG(IPW_DL_QOS, f, ## a)
1485
1486 #include <linux/ctype.h>
1487
1488 /*
1489 * Register bit definitions
1490 */
1491
1492 #define IPW_INTA_RW       0x00000008
1493 #define IPW_INTA_MASK_R   0x0000000C
1494 #define IPW_INDIRECT_ADDR 0x00000010
1495 #define IPW_INDIRECT_DATA 0x00000014
1496 #define IPW_AUTOINC_ADDR  0x00000018
1497 #define IPW_AUTOINC_DATA  0x0000001C
1498 #define IPW_RESET_REG     0x00000020
1499 #define IPW_GP_CNTRL_RW   0x00000024
1500
1501 #define IPW_READ_INT_REGISTER 0xFF4
1502
1503 #define IPW_GP_CNTRL_BIT_INIT_DONE      0x00000004
1504
1505 #define IPW_REGISTER_DOMAIN1_END        0x00001000
1506 #define IPW_SRAM_READ_INT_REGISTER      0x00000ff4
1507
1508 #define IPW_SHARED_LOWER_BOUND          0x00000200
1509 #define IPW_INTERRUPT_AREA_LOWER_BOUND  0x00000f80
1510
1511 #define IPW_NIC_SRAM_LOWER_BOUND        0x00000000
1512 #define IPW_NIC_SRAM_UPPER_BOUND        0x00030000
1513
1514 #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1515 #define IPW_GP_CNTRL_BIT_CLOCK_READY    0x00000001
1516 #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1517
1518 /*
1519  * RESET Register Bit Indexes
1520  */
1521 #define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1522 #define IPW_START_STANDBY             (1<<2)
1523 #define IPW_ACTIVITY_LED              (1<<4)
1524 #define IPW_ASSOCIATED_LED            (1<<5)
1525 #define IPW_OFDM_LED                  (1<<6)
1526 #define IPW_RESET_REG_SW_RESET        (1<<7)
1527 #define IPW_RESET_REG_MASTER_DISABLED (1<<8)
1528 #define IPW_RESET_REG_STOP_MASTER     (1<<9)
1529 #define IPW_GATE_ODMA                 (1<<25)
1530 #define IPW_GATE_IDMA                 (1<<26)
1531 #define IPW_ARC_KESHET_CONFIG         (1<<27)
1532 #define IPW_GATE_ADMA                 (1<<29)
1533
1534 #define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1535 #define IPW_DOMAIN_0_END 0x1000
1536 #define CLX_MEM_BAR_SIZE 0x1000
1537
1538 /* Dino/baseband control registers bits */
1539
1540 #define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
1541 #define DINO_ENABLE_CS     0x40 /* 1 = enable ucode load */
1542 #define DINO_RXFIFO_DATA   0x01 /* 1 = data available */
1543 #define IPW_BASEBAND_CONTROL_STATUS     0X00200000
1544 #define IPW_BASEBAND_TX_FIFO_WRITE      0X00200004
1545 #define IPW_BASEBAND_RX_FIFO_READ       0X00200004
1546 #define IPW_BASEBAND_CONTROL_STORE      0X00200010
1547
1548 #define IPW_INTERNAL_CMD_EVENT  0X00300004
1549 #define IPW_BASEBAND_POWER_DOWN 0x00000001
1550
1551 #define IPW_MEM_HALT_AND_RESET  0x003000e0
1552
1553 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1554 #define IPW_BIT_HALT_RESET_ON   0x80000000
1555 #define IPW_BIT_HALT_RESET_OFF  0x00000000
1556
1557 #define CB_LAST_VALID     0x20000000
1558 #define CB_INT_ENABLED    0x40000000
1559 #define CB_VALID          0x80000000
1560 #define CB_SRC_LE         0x08000000
1561 #define CB_DEST_LE        0x04000000
1562 #define CB_SRC_AUTOINC    0x00800000
1563 #define CB_SRC_IO_GATED   0x00400000
1564 #define CB_DEST_AUTOINC   0x00080000
1565 #define CB_SRC_SIZE_LONG  0x00200000
1566 #define CB_DEST_SIZE_LONG 0x00020000
1567
1568 /* DMA DEFINES */
1569
1570 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1571 #define DMA_CB_STOP_AND_ABORT            0x00000C00
1572 #define DMA_CB_START                     0x00000100
1573
1574 #define IPW_SHARED_SRAM_SIZE               0x00030000
1575 #define IPW_SHARED_SRAM_DMA_CONTROL        0x00027000
1576 #define CB_MAX_LENGTH                      0x1FFF
1577
1578 #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1579 #define IPW_EEPROM_IMAGE_SIZE          0x100
1580
1581 /* DMA defs */
1582 #define IPW_DMA_I_CURRENT_CB  0x003000D0
1583 #define IPW_DMA_O_CURRENT_CB  0x003000D4
1584 #define IPW_DMA_I_DMA_CONTROL 0x003000A4
1585 #define IPW_DMA_I_CB_BASE     0x003000A0
1586
1587 #define IPW_TX_CMD_QUEUE_BD_BASE        0x00000200
1588 #define IPW_TX_CMD_QUEUE_BD_SIZE        0x00000204
1589 #define IPW_TX_QUEUE_0_BD_BASE          0x00000208
1590 #define IPW_TX_QUEUE_0_BD_SIZE          (0x0000020C)
1591 #define IPW_TX_QUEUE_1_BD_BASE          0x00000210
1592 #define IPW_TX_QUEUE_1_BD_SIZE          0x00000214
1593 #define IPW_TX_QUEUE_2_BD_BASE          0x00000218
1594 #define IPW_TX_QUEUE_2_BD_SIZE          (0x0000021C)
1595 #define IPW_TX_QUEUE_3_BD_BASE          0x00000220
1596 #define IPW_TX_QUEUE_3_BD_SIZE          0x00000224
1597 #define IPW_RX_BD_BASE                  0x00000240
1598 #define IPW_RX_BD_SIZE                  0x00000244
1599 #define IPW_RFDS_TABLE_LOWER            0x00000500
1600
1601 #define IPW_TX_CMD_QUEUE_READ_INDEX     0x00000280
1602 #define IPW_TX_QUEUE_0_READ_INDEX       0x00000284
1603 #define IPW_TX_QUEUE_1_READ_INDEX       0x00000288
1604 #define IPW_TX_QUEUE_2_READ_INDEX       (0x0000028C)
1605 #define IPW_TX_QUEUE_3_READ_INDEX       0x00000290
1606 #define IPW_RX_READ_INDEX               (0x000002A0)
1607
1608 #define IPW_TX_CMD_QUEUE_WRITE_INDEX    (0x00000F80)
1609 #define IPW_TX_QUEUE_0_WRITE_INDEX      (0x00000F84)
1610 #define IPW_TX_QUEUE_1_WRITE_INDEX      (0x00000F88)
1611 #define IPW_TX_QUEUE_2_WRITE_INDEX      (0x00000F8C)
1612 #define IPW_TX_QUEUE_3_WRITE_INDEX      (0x00000F90)
1613 #define IPW_RX_WRITE_INDEX              (0x00000FA0)
1614
1615 /*
1616  * EEPROM Related Definitions
1617  */
1618
1619 #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1620 #define IPW_EEPROM_DATA_SRAM_SIZE    (IPW_SHARED_LOWER_BOUND + 0x818)
1621 #define IPW_EEPROM_LOAD_DISABLE      (IPW_SHARED_LOWER_BOUND + 0x81C)
1622 #define IPW_EEPROM_DATA              (IPW_SHARED_LOWER_BOUND + 0x820)
1623 #define IPW_EEPROM_UPPER_ADDRESS     (IPW_SHARED_LOWER_BOUND + 0x9E0)
1624
1625 #define IPW_STATION_TABLE_LOWER      (IPW_SHARED_LOWER_BOUND + 0xA0C)
1626 #define IPW_STATION_TABLE_UPPER      (IPW_SHARED_LOWER_BOUND + 0xB0C)
1627 #define IPW_REQUEST_ATIM             (IPW_SHARED_LOWER_BOUND + 0xB0C)
1628 #define IPW_ATIM_SENT                (IPW_SHARED_LOWER_BOUND + 0xB10)
1629 #define IPW_WHO_IS_AWAKE             (IPW_SHARED_LOWER_BOUND + 0xB14)
1630 #define IPW_DURING_ATIM_WINDOW       (IPW_SHARED_LOWER_BOUND + 0xB18)
1631
1632 #define MSB                             1
1633 #define LSB                             0
1634 #define WORD_TO_BYTE(_word)             ((_word) * sizeof(u16))
1635
1636 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1637     ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1638
1639 /* EEPROM access by BYTE */
1640 #define EEPROM_PME_CAPABILITY   (GET_EEPROM_ADDR(0x09,MSB))     /* 1 byte   */
1641 #define EEPROM_MAC_ADDRESS      (GET_EEPROM_ADDR(0x21,LSB))     /* 6 byte   */
1642 #define EEPROM_VERSION          (GET_EEPROM_ADDR(0x24,MSB))     /* 1 byte   */
1643 #define EEPROM_NIC_TYPE         (GET_EEPROM_ADDR(0x25,LSB))     /* 1 byte   */
1644 #define EEPROM_SKU_CAPABILITY   (GET_EEPROM_ADDR(0x25,MSB))     /* 1 byte   */
1645 #define EEPROM_COUNTRY_CODE     (GET_EEPROM_ADDR(0x26,LSB))     /* 3 bytes  */
1646 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB))     /* 2 bytes  */
1647 #define EEPROM_IBSS_CHANNELS_A  (GET_EEPROM_ADDR(0x29,MSB))     /* 5 bytes  */
1648 #define EEPROM_BSS_CHANNELS_BG  (GET_EEPROM_ADDR(0x2c,LSB))     /* 2 bytes  */
1649 #define EEPROM_HW_VERSION       (GET_EEPROM_ADDR(0x72,LSB))     /* 2 bytes  */
1650
1651 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset */
1652 #define EEPROM_NIC_TYPE_0 0
1653 #define EEPROM_NIC_TYPE_1 1
1654 #define EEPROM_NIC_TYPE_2 2
1655 #define EEPROM_NIC_TYPE_3 3
1656 #define EEPROM_NIC_TYPE_4 4
1657
1658 /* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */
1659 #define EEPROM_SKU_CAP_BT_CHANNEL_SIG  0x01     /* we can tell BT our channel # */
1660 #define EEPROM_SKU_CAP_BT_PRIORITY     0x02     /* BT can take priority over us */
1661 #define EEPROM_SKU_CAP_BT_OOB          0x04     /* we can signal BT out-of-band */
1662
1663 #define FW_MEM_REG_LOWER_BOUND          0x00300000
1664 #define FW_MEM_REG_EEPROM_ACCESS        (FW_MEM_REG_LOWER_BOUND + 0x40)
1665 #define IPW_EVENT_REG                   (FW_MEM_REG_LOWER_BOUND + 0x04)
1666 #define EEPROM_BIT_SK                   (1<<0)
1667 #define EEPROM_BIT_CS                   (1<<1)
1668 #define EEPROM_BIT_DI                   (1<<2)
1669 #define EEPROM_BIT_DO                   (1<<4)
1670
1671 #define EEPROM_CMD_READ                 0x2
1672
1673 /* Interrupts masks */
1674 #define IPW_INTA_NONE   0x00000000
1675
1676 #define IPW_INTA_BIT_RX_TRANSFER                   0x00000002
1677 #define IPW_INTA_BIT_STATUS_CHANGE                 0x00000010
1678 #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED         0x00000020
1679
1680 //Inta Bits for CF
1681 #define IPW_INTA_BIT_TX_CMD_QUEUE                  0x00000800
1682 #define IPW_INTA_BIT_TX_QUEUE_1                    0x00001000
1683 #define IPW_INTA_BIT_TX_QUEUE_2                    0x00002000
1684 #define IPW_INTA_BIT_TX_QUEUE_3                    0x00004000
1685 #define IPW_INTA_BIT_TX_QUEUE_4                    0x00008000
1686
1687 #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE      0x00010000
1688
1689 #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN        0x00100000
1690 #define IPW_INTA_BIT_POWER_DOWN                    0x00200000
1691
1692 #define IPW_INTA_BIT_FW_INITIALIZATION_DONE        0x01000000
1693 #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE  0x02000000
1694 #define IPW_INTA_BIT_RF_KILL_DONE                  0x04000000
1695 #define IPW_INTA_BIT_FATAL_ERROR             0x40000000
1696 #define IPW_INTA_BIT_PARITY_ERROR            0x80000000
1697
1698 /* Interrupts enabled at init time. */
1699 #define IPW_INTA_MASK_ALL                        \
1700         (IPW_INTA_BIT_TX_QUEUE_1               | \
1701          IPW_INTA_BIT_TX_QUEUE_2               | \
1702          IPW_INTA_BIT_TX_QUEUE_3               | \
1703          IPW_INTA_BIT_TX_QUEUE_4               | \
1704          IPW_INTA_BIT_TX_CMD_QUEUE             | \
1705          IPW_INTA_BIT_RX_TRANSFER              | \
1706          IPW_INTA_BIT_FATAL_ERROR              | \
1707          IPW_INTA_BIT_PARITY_ERROR             | \
1708          IPW_INTA_BIT_STATUS_CHANGE            | \
1709          IPW_INTA_BIT_FW_INITIALIZATION_DONE   | \
1710          IPW_INTA_BIT_BEACON_PERIOD_EXPIRED    | \
1711          IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1712          IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN   | \
1713          IPW_INTA_BIT_POWER_DOWN               | \
1714          IPW_INTA_BIT_RF_KILL_DONE )
1715
1716 /* FW event log definitions */
1717 #define EVENT_ELEM_SIZE     (3 * sizeof(u32))
1718 #define EVENT_START_OFFSET  (1 * sizeof(u32) + 2 * sizeof(u16))
1719
1720 /* FW error log definitions */
1721 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1722 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1723
1724 /* TX power level (dbm) */
1725 #define IPW_TX_POWER_MIN        -12
1726 #define IPW_TX_POWER_MAX        20
1727 #define IPW_TX_POWER_DEFAULT    IPW_TX_POWER_MAX
1728
1729 enum {
1730         IPW_FW_ERROR_OK = 0,
1731         IPW_FW_ERROR_FAIL,
1732         IPW_FW_ERROR_MEMORY_UNDERFLOW,
1733         IPW_FW_ERROR_MEMORY_OVERFLOW,
1734         IPW_FW_ERROR_BAD_PARAM,
1735         IPW_FW_ERROR_BAD_CHECKSUM,
1736         IPW_FW_ERROR_NMI_INTERRUPT,
1737         IPW_FW_ERROR_BAD_DATABASE,
1738         IPW_FW_ERROR_ALLOC_FAIL,
1739         IPW_FW_ERROR_DMA_UNDERRUN,
1740         IPW_FW_ERROR_DMA_STATUS,
1741         IPW_FW_ERROR_DINO_ERROR,
1742         IPW_FW_ERROR_EEPROM_ERROR,
1743         IPW_FW_ERROR_SYSASSERT,
1744         IPW_FW_ERROR_FATAL_ERROR
1745 };
1746
1747 #define AUTH_OPEN       0
1748 #define AUTH_SHARED_KEY 1
1749 #define AUTH_LEAP       2
1750 #define AUTH_IGNORE     3
1751
1752 #define HC_ASSOCIATE      0
1753 #define HC_REASSOCIATE    1
1754 #define HC_DISASSOCIATE   2
1755 #define HC_IBSS_START     3
1756 #define HC_IBSS_RECONF    4
1757 #define HC_DISASSOC_QUIET 5
1758
1759 #define HC_QOS_SUPPORT_ASSOC  0x01
1760
1761 #define IPW_RATE_CAPABILITIES 1
1762 #define IPW_RATE_CONNECT      0
1763
1764 /*
1765  * Rate values and masks
1766  */
1767 #define IPW_TX_RATE_1MB  0x0A
1768 #define IPW_TX_RATE_2MB  0x14
1769 #define IPW_TX_RATE_5MB  0x37
1770 #define IPW_TX_RATE_6MB  0x0D
1771 #define IPW_TX_RATE_9MB  0x0F
1772 #define IPW_TX_RATE_11MB 0x6E
1773 #define IPW_TX_RATE_12MB 0x05
1774 #define IPW_TX_RATE_18MB 0x07
1775 #define IPW_TX_RATE_24MB 0x09
1776 #define IPW_TX_RATE_36MB 0x0B
1777 #define IPW_TX_RATE_48MB 0x01
1778 #define IPW_TX_RATE_54MB 0x03
1779
1780 #define IPW_ORD_TABLE_ID_MASK             0x0000FF00
1781 #define IPW_ORD_TABLE_VALUE_MASK          0x000000FF
1782
1783 #define IPW_ORD_TABLE_0_MASK              0x0000F000
1784 #define IPW_ORD_TABLE_1_MASK              0x0000F100
1785 #define IPW_ORD_TABLE_2_MASK              0x0000F200
1786 #define IPW_ORD_TABLE_3_MASK              0x0000F300
1787 #define IPW_ORD_TABLE_4_MASK              0x0000F400
1788 #define IPW_ORD_TABLE_5_MASK              0x0000F500
1789 #define IPW_ORD_TABLE_6_MASK              0x0000F600
1790 #define IPW_ORD_TABLE_7_MASK              0x0000F700
1791
1792 /*
1793  * Table 0 Entries (all entries are 32 bits)
1794  */
1795 enum {
1796         IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1797         IPW_ORD_STAT_FRAG_TRESHOLD,
1798         IPW_ORD_STAT_RTS_THRESHOLD,
1799         IPW_ORD_STAT_TX_HOST_REQUESTS,
1800         IPW_ORD_STAT_TX_HOST_COMPLETE,
1801         IPW_ORD_STAT_TX_DIR_DATA,
1802         IPW_ORD_STAT_TX_DIR_DATA_B_1,
1803         IPW_ORD_STAT_TX_DIR_DATA_B_2,
1804         IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1805         IPW_ORD_STAT_TX_DIR_DATA_B_11,
1806         /* Hole */
1807
1808         IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1809         IPW_ORD_STAT_TX_DIR_DATA_G_2,
1810         IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1811         IPW_ORD_STAT_TX_DIR_DATA_G_6,
1812         IPW_ORD_STAT_TX_DIR_DATA_G_9,
1813         IPW_ORD_STAT_TX_DIR_DATA_G_11,
1814         IPW_ORD_STAT_TX_DIR_DATA_G_12,
1815         IPW_ORD_STAT_TX_DIR_DATA_G_18,
1816         IPW_ORD_STAT_TX_DIR_DATA_G_24,
1817         IPW_ORD_STAT_TX_DIR_DATA_G_36,
1818         IPW_ORD_STAT_TX_DIR_DATA_G_48,
1819         IPW_ORD_STAT_TX_DIR_DATA_G_54,
1820         IPW_ORD_STAT_TX_NON_DIR_DATA,
1821         IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1822         IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1823         IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1824         IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1825         /* Hole */
1826
1827         IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1828         IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1829         IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1830         IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1831         IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1832         IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1833         IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1834         IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1835         IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1836         IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1837         IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1838         IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1839         IPW_ORD_STAT_TX_RETRY,
1840         IPW_ORD_STAT_TX_FAILURE,
1841         IPW_ORD_STAT_RX_ERR_CRC,
1842         IPW_ORD_STAT_RX_ERR_ICV,
1843         IPW_ORD_STAT_RX_NO_BUFFER,
1844         IPW_ORD_STAT_FULL_SCANS,
1845         IPW_ORD_STAT_PARTIAL_SCANS,
1846         IPW_ORD_STAT_TGH_ABORTED_SCANS,
1847         IPW_ORD_STAT_TX_TOTAL_BYTES,
1848         IPW_ORD_STAT_CURR_RSSI_RAW,
1849         IPW_ORD_STAT_RX_BEACON,
1850         IPW_ORD_STAT_MISSED_BEACONS,
1851         IPW_ORD_TABLE_0_LAST
1852 };
1853
1854 #define IPW_RSSI_TO_DBM 112
1855
1856 /* Table 1 Entries
1857  */
1858 enum {
1859         IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1860 };
1861
1862 /*
1863  * Table 2 Entries
1864  *
1865  * FW_VERSION:    16 byte string
1866  * FW_DATE:       16 byte string (only 14 bytes used)
1867  * UCODE_VERSION: 4 byte version code
1868  * UCODE_DATE:    5 bytes code code
1869  * ADDAPTER_MAC:  6 byte MAC address
1870  * RTC:           4 byte clock
1871  */
1872 enum {
1873         IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1874         IPW_ORD_STAT_FW_DATE,
1875         IPW_ORD_STAT_UCODE_VERSION,
1876         IPW_ORD_STAT_UCODE_DATE,
1877         IPW_ORD_STAT_ADAPTER_MAC,
1878         IPW_ORD_STAT_RTC,
1879         IPW_ORD_TABLE_2_LAST
1880 };
1881
1882 /* Table 3 */
1883 enum {
1884         IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1885         IPW_ORD_STAT_TX_PACKET_FAILURE,
1886         IPW_ORD_STAT_TX_PACKET_SUCCESS,
1887         IPW_ORD_STAT_TX_PACKET_ABORTED,
1888         IPW_ORD_TABLE_3_LAST
1889 };
1890
1891 /* Table 4 */
1892 enum {
1893         IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1894 };
1895
1896 /* Table 5 */
1897 enum {
1898         IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1899         IPW_ORD_STAT_AP_ASSNS,
1900         IPW_ORD_STAT_ROAM,
1901         IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1902         IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1903         IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1904         IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1905         IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1906         IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1907         IPW_ORD_STAT_LINK_UP,
1908         IPW_ORD_STAT_LINK_DOWN,
1909         IPW_ORD_ANTENNA_DIVERSITY,
1910         IPW_ORD_CURR_FREQ,
1911         IPW_ORD_TABLE_5_LAST
1912 };
1913
1914 /* Table 6 */
1915 enum {
1916         IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1917         IPW_ORD_CURR_BSSID,
1918         IPW_ORD_CURR_SSID,
1919         IPW_ORD_TABLE_6_LAST
1920 };
1921
1922 /* Table 7 */
1923 enum {
1924         IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1925         IPW_ORD_STAT_PERCENT_TX_RETRIES,
1926         IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1927         IPW_ORD_STAT_CURR_RSSI_DBM,
1928         IPW_ORD_TABLE_7_LAST
1929 };
1930
1931 #define IPW_ERROR_LOG     (IPW_SHARED_LOWER_BOUND + 0x410)
1932 #define IPW_EVENT_LOG     (IPW_SHARED_LOWER_BOUND + 0x414)
1933 #define IPW_ORDINALS_TABLE_LOWER        (IPW_SHARED_LOWER_BOUND + 0x500)
1934 #define IPW_ORDINALS_TABLE_0            (IPW_SHARED_LOWER_BOUND + 0x180)
1935 #define IPW_ORDINALS_TABLE_1            (IPW_SHARED_LOWER_BOUND + 0x184)
1936 #define IPW_ORDINALS_TABLE_2            (IPW_SHARED_LOWER_BOUND + 0x188)
1937 #define IPW_MEM_FIXED_OVERRIDE          (IPW_SHARED_LOWER_BOUND + 0x41C)
1938
1939 struct ipw_fixed_rate {
1940         u16 tx_rates;
1941         u16 reserved;
1942 } __attribute__ ((packed));
1943
1944 #define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1945
1946 struct host_cmd {
1947         u8 cmd;
1948         u8 len;
1949         u16 reserved;
1950         u32 *param;
1951 } __attribute__ ((packed));
1952
1953 struct cmdlog_host_cmd {
1954         u8 cmd;
1955         u8 len;
1956         u16 reserved;
1957         char param[124];
1958 } __attribute__ ((packed));
1959
1960 struct ipw_cmd_log {
1961         unsigned long jiffies;
1962         int retcode;
1963         struct cmdlog_host_cmd cmd;
1964 };
1965
1966 /* SysConfig command parameters ... */
1967 /* bt_coexistence param */
1968 #define CFG_BT_COEXISTENCE_SIGNAL_CHNL  0x01    /* tell BT our chnl # */
1969 #define CFG_BT_COEXISTENCE_DEFER        0x02    /* defer our Tx if BT traffic */
1970 #define CFG_BT_COEXISTENCE_KILL         0x04    /* kill our Tx if BT traffic */
1971 #define CFG_BT_COEXISTENCE_WME_OVER_BT  0x08    /* multimedia extensions */
1972 #define CFG_BT_COEXISTENCE_OOB          0x10    /* signal BT via out-of-band */
1973
1974 /* clear-to-send to self param */
1975 #define CFG_CTS_TO_ITSELF_ENABLED_MIN   0x00
1976 #define CFG_CTS_TO_ITSELF_ENABLED_MAX   0x01
1977 #define CFG_CTS_TO_ITSELF_ENABLED_DEF   CFG_CTS_TO_ITSELF_ENABLED_MIN
1978
1979 /* Antenna diversity param (h/w can select best antenna, based on signal) */
1980 #define CFG_SYS_ANTENNA_BOTH            0x00    /* NIC selects best antenna */
1981 #define CFG_SYS_ANTENNA_A               0x01    /* force antenna A */
1982 #define CFG_SYS_ANTENNA_B               0x03    /* force antenna B */
1983 #define CFG_SYS_ANTENNA_SLOW_DIV        0x02    /* consider background noise */
1984
1985 /*
1986  * The definitions below were lifted off the ipw2100 driver, which only
1987  * supports 'b' mode, so I'm sure these are not exactly correct.
1988  *
1989  * Somebody fix these!!
1990  */
1991 #define REG_MIN_CHANNEL             0
1992 #define REG_MAX_CHANNEL             14
1993
1994 #define REG_CHANNEL_MASK            0x00003FFF
1995 #define IPW_IBSS_11B_DEFAULT_MASK   0x87ff
1996
1997 #define IPW_MAX_CONFIG_RETRIES 10
1998
1999 #endif                          /* __ipw2200_h__ */