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tuntap: switch to use rtnl_dereference()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / pci / quirks.c
blob0369fb6fc1da412d2f55d8346d2dca0a9424b158
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/acpi.h>
25 #include <linux/kallsyms.h>
26 #include <linux/dmi.h>
27 #include <linux/pci-aspm.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/ktime.h>
31 #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 #include "pci.h"
33
34 /*
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit.
39 */
40 static void quirk_mmio_always_on(struct pci_dev *dev)
41 {
42 dev->mmio_always_on = 1;
43 }
44 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
46
47 /* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device.
50 */
51 static void quirk_mellanox_tavor(struct pci_dev *dev)
52 {
53 dev->broken_parity_status = 1; /* This device gives false positives */
54 }
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
57
58 /* Deal with broken BIOS'es that neglect to enable passive release,
59 which can cause problems in combination with the 82441FX/PPro MTRRs */
60 static void quirk_passive_release(struct pci_dev *dev)
61 {
62 struct pci_dev *d = NULL;
63 unsigned char dlc;
64
65 /* We have to make sure a particular bit is set in the PIIX3
66 ISA bridge, so we have to go out and find it. */
67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
68 pci_read_config_byte(d, 0x82, &dlc);
69 if (!(dlc & 1<<1)) {
70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
71 dlc |= 1<<1;
72 pci_write_config_byte(d, 0x82, dlc);
73 }
74 }
75 }
76 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
78
79 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
80 but VIA don't answer queries. If you happen to have good contacts at VIA
81 ask them for me please -- Alan
82
83 This appears to be BIOS not version dependent. So presumably there is a
84 chipset level fix */
85
86 static void quirk_isa_dma_hangs(struct pci_dev *dev)
87 {
88 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy=1;
90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
91 }
92 }
93 /*
94 * Its not totally clear which chipsets are the problematic ones
95 * We know 82C586 and 82C596 variants are affected.
96 */
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
104
105 /*
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging.
108 */
109 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
110 {
111 u32 pmbase;
112 u16 pm1a;
113
114 pci_read_config_dword(dev, 0x40, &pmbase);
115 pmbase = pmbase & 0xff80;
116 pm1a = inw(pmbase);
117
118 if (pm1a & 0x10) {
119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 outw(0x10, pmbase);
121 }
122 }
123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
124
125 /*
126 * Chipsets where PCI->PCI transfers vanish or hang
127 */
128 static void quirk_nopcipci(struct pci_dev *dev)
129 {
130 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
132 pci_pci_problems |= PCIPCI_FAIL;
133 }
134 }
135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
137
138 static void quirk_nopciamd(struct pci_dev *dev)
139 {
140 u8 rev;
141 pci_read_config_byte(dev, 0x08, &rev);
142 if (rev == 0x13) {
143 /* Erratum 24 */
144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
145 pci_pci_problems |= PCIAGP_FAIL;
146 }
147 }
148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
149
150 /*
151 * Triton requires workarounds to be used by the drivers
152 */
153 static void quirk_triton(struct pci_dev *dev)
154 {
155 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
157 pci_pci_problems |= PCIPCI_TRITON;
158 }
159 }
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
164
165 /*
166 * VIA Apollo KT133 needs PCI latency patch
167 * Made according to a windows driver based patch by George E. Breese
168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
169 * and http://www.georgebreese.com/net/software/#PCI
170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
171 * the info on which Mr Breese based his work.
172 *
173 * Updated based on further information from the site and also on
174 * information provided by VIA
175 */
176 static void quirk_vialatency(struct pci_dev *dev)
177 {
178 struct pci_dev *p;
179 u8 busarb;
180 /* Ok we have a potential problem chipset here. Now see if we have
181 a buggy southbridge */
182
183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
184 if (p!=NULL) {
185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
186 /* Check for buggy part revisions */
187 if (p->revision < 0x40 || p->revision > 0x42)
188 goto exit;
189 } else {
190 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
191 if (p==NULL) /* No problem parts */
192 goto exit;
193 /* Check for buggy part revisions */
194 if (p->revision < 0x10 || p->revision > 0x12)
195 goto exit;
196 }
197
198 /*
199 * Ok we have the problem. Now set the PCI master grant to
200 * occur every master grant. The apparent bug is that under high
201 * PCI load (quite common in Linux of course) you can get data
202 * loss when the CPU is held off the bus for 3 bus master requests
203 * This happens to include the IDE controllers....
204 *
205 * VIA only apply this fix when an SB Live! is present but under
206 * both Linux and Windows this isn't enough, and we have seen
207 * corruption without SB Live! but with things like 3 UDMA IDE
208 * controllers. So we ignore that bit of the VIA recommendation..
209 */
210
211 pci_read_config_byte(dev, 0x76, &busarb);
212 /* Set bit 4 and bi 5 of byte 76 to 0x01
213 "Master priority rotation on every PCI master grant */
214 busarb &= ~(1<<5);
215 busarb |= (1<<4);
216 pci_write_config_byte(dev, 0x76, busarb);
217 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
218 exit:
219 pci_dev_put(p);
220 }
221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224 /* Must restore this on a resume from RAM */
225 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
226 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
227 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
228
229 /*
230 * VIA Apollo VP3 needs ETBF on BT848/878
231 */
232 static void quirk_viaetbf(struct pci_dev *dev)
233 {
234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
236 pci_pci_problems |= PCIPCI_VIAETBF;
237 }
238 }
239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
240
241 static void quirk_vsfx(struct pci_dev *dev)
242 {
243 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
245 pci_pci_problems |= PCIPCI_VSFX;
246 }
247 }
248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
249
250 /*
251 * Ali Magik requires workarounds to be used by the drivers
252 * that DMA to AGP space. Latency must be set to 0xA and triton
253 * workaround applied too
254 * [Info kindly provided by ALi]
255 */
256 static void quirk_alimagik(struct pci_dev *dev)
257 {
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
261 }
262 }
263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
265
266 /*
267 * Natoma has some interesting boundary conditions with Zoran stuff
268 * at least
269 */
270 static void quirk_natoma(struct pci_dev *dev)
271 {
272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
274 pci_pci_problems |= PCIPCI_NATOMA;
275 }
276 }
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
283
284 /*
285 * This chip can cause PCI parity errors if config register 0xA0 is read
286 * while DMAs are occurring.
287 */
288 static void quirk_citrine(struct pci_dev *dev)
289 {
290 dev->cfg_size = 0xA0;
291 }
292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
293
294 /*
295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
296 * If it's needed, re-allocate the region.
297 */
298 static void quirk_s3_64M(struct pci_dev *dev)
299 {
300 struct resource *r = &dev->resource[0];
301
302 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
303 r->start = 0;
304 r->end = 0x3ffffff;
305 }
306 }
307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
309
310 /*
311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
312 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
314 * (which conflicts w/ BAR1's memory range).
315 */
316 static void quirk_cs5536_vsa(struct pci_dev *dev)
317 {
318 if (pci_resource_len(dev, 0) != 8) {
319 struct resource *res = &dev->resource[0];
320 res->end = res->start + 8 - 1;
321 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
322 "(incorrect header); workaround applied.\n");
323 }
324 }
325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
326
327 static void quirk_io_region(struct pci_dev *dev, unsigned region,
328 unsigned size, int nr, const char *name)
329 {
330 region &= ~(size-1);
331 if (region) {
332 struct pci_bus_region bus_region;
333 struct resource *res = dev->resource + nr;
334
335 res->name = pci_name(dev);
336 res->start = region;
337 res->end = region + size - 1;
338 res->flags = IORESOURCE_IO;
339
340 /* Convert from PCI bus to resource space. */
341 bus_region.start = res->start;
342 bus_region.end = res->end;
343 pcibios_bus_to_resource(dev, res, &bus_region);
344
345 if (pci_claim_resource(dev, nr) == 0)
346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
347 res, name);
348 }
349 }
350
351 /*
352 * ATI Northbridge setups MCE the processor if you even
353 * read somewhere between 0x3b0->0x3bb or read 0x3d3
354 */
355 static void quirk_ati_exploding_mce(struct pci_dev *dev)
356 {
357 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
358 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
359 request_region(0x3b0, 0x0C, "RadeonIGP");
360 request_region(0x3d3, 0x01, "RadeonIGP");
361 }
362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
363
364 /*
365 * Let's make the southbridge information explicit instead
366 * of having to worry about people probing the ACPI areas,
367 * for example.. (Yes, it happens, and if you read the wrong
368 * ACPI register it will put the machine to sleep with no
369 * way of waking it up again. Bummer).
370 *
371 * ALI M7101: Two IO regions pointed to by words at
372 * 0xE0 (64 bytes of ACPI registers)
373 * 0xE2 (32 bytes of SMB registers)
374 */
375 static void quirk_ali7101_acpi(struct pci_dev *dev)
376 {
377 u16 region;
378
379 pci_read_config_word(dev, 0xE0, &region);
380 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
381 pci_read_config_word(dev, 0xE2, &region);
382 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
383 }
384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
385
386 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
387 {
388 u32 devres;
389 u32 mask, size, base;
390
391 pci_read_config_dword(dev, port, &devres);
392 if ((devres & enable) != enable)
393 return;
394 mask = (devres >> 16) & 15;
395 base = devres & 0xffff;
396 size = 16;
397 for (;;) {
398 unsigned bit = size >> 1;
399 if ((bit & mask) == bit)
400 break;
401 size = bit;
402 }
403 /*
404 * For now we only print it out. Eventually we'll want to
405 * reserve it (at least if it's in the 0x1000+ range), but
406 * let's get enough confirmation reports first.
407 */
408 base &= -size;
409 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
410 }
411
412 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
413 {
414 u32 devres;
415 u32 mask, size, base;
416
417 pci_read_config_dword(dev, port, &devres);
418 if ((devres & enable) != enable)
419 return;
420 base = devres & 0xffff0000;
421 mask = (devres & 0x3f) << 16;
422 size = 128 << 16;
423 for (;;) {
424 unsigned bit = size >> 1;
425 if ((bit & mask) == bit)
426 break;
427 size = bit;
428 }
429 /*
430 * For now we only print it out. Eventually we'll want to
431 * reserve it, but let's get enough confirmation reports first.
432 */
433 base &= -size;
434 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
435 }
436
437 /*
438 * PIIX4 ACPI: Two IO regions pointed to by longwords at
439 * 0x40 (64 bytes of ACPI registers)
440 * 0x90 (16 bytes of SMB registers)
441 * and a few strange programmable PIIX4 device resources.
442 */
443 static void quirk_piix4_acpi(struct pci_dev *dev)
444 {
445 u32 region, res_a;
446
447 pci_read_config_dword(dev, 0x40, &region);
448 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
449 pci_read_config_dword(dev, 0x90, &region);
450 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
451
452 /* Device resource A has enables for some of the other ones */
453 pci_read_config_dword(dev, 0x5c, &res_a);
454
455 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
456 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
457
458 /* Device resource D is just bitfields for static resources */
459
460 /* Device 12 enabled? */
461 if (res_a & (1 << 29)) {
462 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
463 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
464 }
465 /* Device 13 enabled? */
466 if (res_a & (1 << 30)) {
467 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
468 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
469 }
470 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
471 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
472 }
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
475
476 #define ICH_PMBASE 0x40
477 #define ICH_ACPI_CNTL 0x44
478 #define ICH4_ACPI_EN 0x10
479 #define ICH6_ACPI_EN 0x80
480 #define ICH4_GPIOBASE 0x58
481 #define ICH4_GPIO_CNTL 0x5c
482 #define ICH4_GPIO_EN 0x10
483 #define ICH6_GPIOBASE 0x48
484 #define ICH6_GPIO_CNTL 0x4c
485 #define ICH6_GPIO_EN 0x10
486
487 /*
488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
490 * 0x58 (64 bytes of GPIO I/O space)
491 */
492 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
493 {
494 u32 region;
495 u8 enable;
496
497 /*
498 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
499 * with low legacy (and fixed) ports. We don't know the decoding
500 * priority and can't tell whether the legacy device or the one created
501 * here is really at that address. This happens on boards with broken
502 * BIOSes.
503 */
504
505 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
506 if (enable & ICH4_ACPI_EN) {
507 pci_read_config_dword(dev, ICH_PMBASE, &region);
508 region &= PCI_BASE_ADDRESS_IO_MASK;
509 if (region >= PCIBIOS_MIN_IO)
510 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
511 "ICH4 ACPI/GPIO/TCO");
512 }
513
514 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
515 if (enable & ICH4_GPIO_EN) {
516 pci_read_config_dword(dev, ICH4_GPIOBASE, &region);
517 region &= PCI_BASE_ADDRESS_IO_MASK;
518 if (region >= PCIBIOS_MIN_IO)
519 quirk_io_region(dev, region, 64,
520 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
521 }
522 }
523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
533
534 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
535 {
536 u32 region;
537 u8 enable;
538
539 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
540 if (enable & ICH6_ACPI_EN) {
541 pci_read_config_dword(dev, ICH_PMBASE, &region);
542 region &= PCI_BASE_ADDRESS_IO_MASK;
543 if (region >= PCIBIOS_MIN_IO)
544 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
545 "ICH6 ACPI/GPIO/TCO");
546 }
547
548 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
549 if (enable & ICH6_GPIO_EN) {
550 pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
551 region &= PCI_BASE_ADDRESS_IO_MASK;
552 if (region >= PCIBIOS_MIN_IO)
553 quirk_io_region(dev, region, 64,
554 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
555 }
556 }
557
558 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
559 {
560 u32 val;
561 u32 size, base;
562
563 pci_read_config_dword(dev, reg, &val);
564
565 /* Enabled? */
566 if (!(val & 1))
567 return;
568 base = val & 0xfffc;
569 if (dynsize) {
570 /*
571 * This is not correct. It is 16, 32 or 64 bytes depending on
572 * register D31:F0:ADh bits 5:4.
573 *
574 * But this gets us at least _part_ of it.
575 */
576 size = 16;
577 } else {
578 size = 128;
579 }
580 base &= ~(size-1);
581
582 /* Just print it out for now. We should reserve it after more debugging */
583 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
584 }
585
586 static void quirk_ich6_lpc(struct pci_dev *dev)
587 {
588 /* Shared ACPI/GPIO decode with all ICH6+ */
589 ich6_lpc_acpi_gpio(dev);
590
591 /* ICH6-specific generic IO decode */
592 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
593 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
594 }
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
597
598 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
599 {
600 u32 val;
601 u32 mask, base;
602
603 pci_read_config_dword(dev, reg, &val);
604
605 /* Enabled? */
606 if (!(val & 1))
607 return;
608
609 /*
610 * IO base in bits 15:2, mask in bits 23:18, both
611 * are dword-based
612 */
613 base = val & 0xfffc;
614 mask = (val >> 16) & 0xfc;
615 mask |= 3;
616
617 /* Just print it out for now. We should reserve it after more debugging */
618 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
619 }
620
621 /* ICH7-10 has the same common LPC generic IO decode registers */
622 static void quirk_ich7_lpc(struct pci_dev *dev)
623 {
624 /* We share the common ACPI/GPIO decode with ICH6 */
625 ich6_lpc_acpi_gpio(dev);
626
627 /* And have 4 ICH7+ generic decodes */
628 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
629 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
630 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
631 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
632 }
633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
646
647 /*
648 * VIA ACPI: One IO region pointed to by longword at
649 * 0x48 or 0x20 (256 bytes of ACPI registers)
650 */
651 static void quirk_vt82c586_acpi(struct pci_dev *dev)
652 {
653 u32 region;
654
655 if (dev->revision & 0x10) {
656 pci_read_config_dword(dev, 0x48, &region);
657 region &= PCI_BASE_ADDRESS_IO_MASK;
658 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
659 }
660 }
661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
662
663 /*
664 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
665 * 0x48 (256 bytes of ACPI registers)
666 * 0x70 (128 bytes of hardware monitoring register)
667 * 0x90 (16 bytes of SMB registers)
668 */
669 static void quirk_vt82c686_acpi(struct pci_dev *dev)
670 {
671 u16 hm;
672 u32 smb;
673
674 quirk_vt82c586_acpi(dev);
675
676 pci_read_config_word(dev, 0x70, &hm);
677 hm &= PCI_BASE_ADDRESS_IO_MASK;
678 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
679
680 pci_read_config_dword(dev, 0x90, &smb);
681 smb &= PCI_BASE_ADDRESS_IO_MASK;
682 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
683 }
684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
685
686 /*
687 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
688 * 0x88 (128 bytes of power management registers)
689 * 0xd0 (16 bytes of SMB registers)
690 */
691 static void quirk_vt8235_acpi(struct pci_dev *dev)
692 {
693 u16 pm, smb;
694
695 pci_read_config_word(dev, 0x88, &pm);
696 pm &= PCI_BASE_ADDRESS_IO_MASK;
697 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
698
699 pci_read_config_word(dev, 0xd0, &smb);
700 smb &= PCI_BASE_ADDRESS_IO_MASK;
701 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
702 }
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
704
705 /*
706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
707 * Disable fast back-to-back on the secondary bus segment
708 */
709 static void quirk_xio2000a(struct pci_dev *dev)
710 {
711 struct pci_dev *pdev;
712 u16 command;
713
714 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
715 "secondary bus fast back-to-back transfers disabled\n");
716 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
717 pci_read_config_word(pdev, PCI_COMMAND, &command);
718 if (command & PCI_COMMAND_FAST_BACK)
719 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
720 }
721 }
722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
723 quirk_xio2000a);
724
725 #ifdef CONFIG_X86_IO_APIC
726
727 #include <asm/io_apic.h>
728
729 /*
730 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
731 * devices to the external APIC.
732 *
733 * TODO: When we have device-specific interrupt routers,
734 * this code will go away from quirks.
735 */
736 static void quirk_via_ioapic(struct pci_dev *dev)
737 {
738 u8 tmp;
739
740 if (nr_ioapics < 1)
741 tmp = 0; /* nothing routed to external APIC */
742 else
743 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
744
745 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
746 tmp == 0 ? "Disa" : "Ena");
747
748 /* Offset 0x58: External APIC IRQ output control */
749 pci_write_config_byte (dev, 0x58, tmp);
750 }
751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
752 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
753
754 /*
755 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
756 * This leads to doubled level interrupt rates.
757 * Set this bit to get rid of cycle wastage.
758 * Otherwise uncritical.
759 */
760 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
761 {
762 u8 misc_control2;
763 #define BYPASS_APIC_DEASSERT 8
764
765 pci_read_config_byte(dev, 0x5B, &misc_control2);
766 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
767 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
768 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
769 }
770 }
771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
773
774 /*
775 * The AMD io apic can hang the box when an apic irq is masked.
776 * We check all revs >= B0 (yet not in the pre production!) as the bug
777 * is currently marked NoFix
778 *
779 * We have multiple reports of hangs with this chipset that went away with
780 * noapic specified. For the moment we assume it's the erratum. We may be wrong
781 * of course. However the advice is demonstrably good even if so..
782 */
783 static void quirk_amd_ioapic(struct pci_dev *dev)
784 {
785 if (dev->revision >= 0x02) {
786 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
787 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
788 }
789 }
790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791
792 static void quirk_ioapic_rmw(struct pci_dev *dev)
793 {
794 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1;
796 }
797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
798 #endif /* CONFIG_X86_IO_APIC */
799
800 /*
801 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */
804 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
805 {
806 if (dev->subordinate && dev->revision <= 0x12) {
807 dev_info(&dev->dev, "AMD8131 rev %x detected; "
808 "disabling PCI-X MMRBC\n", dev->revision);
809 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
810 }
811 }
812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
813
814 /*
815 * FIXME: it is questionable that quirk_via_acpi
816 * is needed. It shows up as an ISA bridge, and does not
817 * support the PCI_INTERRUPT_LINE register at all. Therefore
818 * it seems like setting the pci_dev's 'irq' to the
819 * value of the ACPI SCI interrupt is only done for convenience.
820 * -jgarzik
821 */
822 static void quirk_via_acpi(struct pci_dev *d)
823 {
824 /*
825 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
826 */
827 u8 irq;
828 pci_read_config_byte(d, 0x42, &irq);
829 irq &= 0xf;
830 if (irq && (irq != 2))
831 d->irq = irq;
832 }
833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
834 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
835
836
837 /*
838 * VIA bridges which have VLink
839 */
840
841 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
842
843 static void quirk_via_bridge(struct pci_dev *dev)
844 {
845 /* See what bridge we have and find the device ranges */
846 switch (dev->device) {
847 case PCI_DEVICE_ID_VIA_82C686:
848 /* The VT82C686 is special, it attaches to PCI and can have
849 any device number. All its subdevices are functions of
850 that single device. */
851 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
852 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
853 break;
854 case PCI_DEVICE_ID_VIA_8237:
855 case PCI_DEVICE_ID_VIA_8237A:
856 via_vlink_dev_lo = 15;
857 break;
858 case PCI_DEVICE_ID_VIA_8235:
859 via_vlink_dev_lo = 16;
860 break;
861 case PCI_DEVICE_ID_VIA_8231:
862 case PCI_DEVICE_ID_VIA_8233_0:
863 case PCI_DEVICE_ID_VIA_8233A:
864 case PCI_DEVICE_ID_VIA_8233C_0:
865 via_vlink_dev_lo = 17;
866 break;
867 }
868 }
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
877
878 /**
879 * quirk_via_vlink - VIA VLink IRQ number update
880 * @dev: PCI device
881 *
882 * If the device we are dealing with is on a PIC IRQ we need to
883 * ensure that the IRQ line register which usually is not relevant
884 * for PCI cards, is actually written so that interrupts get sent
885 * to the right place.
886 * We only do this on systems where a VIA south bridge was detected,
887 * and only for VIA devices on the motherboard (see quirk_via_bridge
888 * above).
889 */
890
891 static void quirk_via_vlink(struct pci_dev *dev)
892 {
893 u8 irq, new_irq;
894
895 /* Check if we have VLink at all */
896 if (via_vlink_dev_lo == -1)
897 return;
898
899 new_irq = dev->irq;
900
901 /* Don't quirk interrupts outside the legacy IRQ range */
902 if (!new_irq || new_irq > 15)
903 return;
904
905 /* Internal device ? */
906 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
907 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
908 return;
909
910 /* This is an internal VLink device on a PIC interrupt. The BIOS
911 ought to have set this but may not have, so we redo it */
912
913 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
914 if (new_irq != irq) {
915 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
916 irq, new_irq);
917 udelay(15); /* unknown if delay really needed */
918 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
919 }
920 }
921 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
922
923 /*
924 * VIA VT82C598 has its device ID settable and many BIOSes
925 * set it to the ID of VT82C597 for backward compatibility.
926 * We need to switch it off to be able to recognize the real
927 * type of the chip.
928 */
929 static void quirk_vt82c598_id(struct pci_dev *dev)
930 {
931 pci_write_config_byte(dev, 0xfc, 0);
932 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
933 }
934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
935
936 /*
937 * CardBus controllers have a legacy base address that enables them
938 * to respond as i82365 pcmcia controllers. We don't want them to
939 * do this even if the Linux CardBus driver is not loaded, because
940 * the Linux i82365 driver does not (and should not) handle CardBus.
941 */
942 static void quirk_cardbus_legacy(struct pci_dev *dev)
943 {
944 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
945 }
946 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
947 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
948 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
949 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
950
951 /*
952 * Following the PCI ordering rules is optional on the AMD762. I'm not
953 * sure what the designers were smoking but let's not inhale...
954 *
955 * To be fair to AMD, it follows the spec by default, its BIOS people
956 * who turn it off!
957 */
958 static void quirk_amd_ordering(struct pci_dev *dev)
959 {
960 u32 pcic;
961 pci_read_config_dword(dev, 0x4C, &pcic);
962 if ((pcic&6)!=6) {
963 pcic |= 6;
964 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
965 pci_write_config_dword(dev, 0x4C, pcic);
966 pci_read_config_dword(dev, 0x84, &pcic);
967 pcic |= (1<<23); /* Required in this mode */
968 pci_write_config_dword(dev, 0x84, pcic);
969 }
970 }
971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
972 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
973
974 /*
975 * DreamWorks provided workaround for Dunord I-3000 problem
976 *
977 * This card decodes and responds to addresses not apparently
978 * assigned to it. We force a larger allocation to ensure that
979 * nothing gets put too close to it.
980 */
981 static void quirk_dunord(struct pci_dev *dev)
982 {
983 struct resource *r = &dev->resource [1];
984 r->start = 0;
985 r->end = 0xffffff;
986 }
987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
988
989 /*
990 * i82380FB mobile docking controller: its PCI-to-PCI bridge
991 * is subtractive decoding (transparent), and does indicate this
992 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
993 * instead of 0x01.
994 */
995 static void quirk_transparent_bridge(struct pci_dev *dev)
996 {
997 dev->transparent = 1;
998 }
999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1001
1002 /*
1003 * Common misconfiguration of the MediaGX/Geode PCI master that will
1004 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1005 * datasheets found at http://www.national.com/analog for info on what
1006 * these bits do. <christer@weinigel.se>
1007 */
1008 static void quirk_mediagx_master(struct pci_dev *dev)
1009 {
1010 u8 reg;
1011 pci_read_config_byte(dev, 0x41, &reg);
1012 if (reg & 2) {
1013 reg &= ~2;
1014 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1015 pci_write_config_byte(dev, 0x41, reg);
1016 }
1017 }
1018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1019 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1020
1021 /*
1022 * Ensure C0 rev restreaming is off. This is normally done by
1023 * the BIOS but in the odd case it is not the results are corruption
1024 * hence the presence of a Linux check
1025 */
1026 static void quirk_disable_pxb(struct pci_dev *pdev)
1027 {
1028 u16 config;
1029
1030 if (pdev->revision != 0x04) /* Only C0 requires this */
1031 return;
1032 pci_read_config_word(pdev, 0x40, &config);
1033 if (config & (1<<6)) {
1034 config &= ~(1<<6);
1035 pci_write_config_word(pdev, 0x40, config);
1036 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1037 }
1038 }
1039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1040 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1041
1042 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1043 {
1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1045 u8 tmp;
1046
1047 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1048 if (tmp == 0x01) {
1049 pci_read_config_byte(pdev, 0x40, &tmp);
1050 pci_write_config_byte(pdev, 0x40, tmp|1);
1051 pci_write_config_byte(pdev, 0x9, 1);
1052 pci_write_config_byte(pdev, 0xa, 6);
1053 pci_write_config_byte(pdev, 0x40, tmp);
1054
1055 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1056 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1057 }
1058 }
1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1060 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1062 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1064 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1065
1066 /*
1067 * Serverworks CSB5 IDE does not fully support native mode
1068 */
1069 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1070 {
1071 u8 prog;
1072 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1073 if (prog & 5) {
1074 prog &= ~5;
1075 pdev->class &= ~5;
1076 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1077 /* PCI layer will sort out resources */
1078 }
1079 }
1080 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1081
1082 /*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */
1085 static void quirk_ide_samemode(struct pci_dev *pdev)
1086 {
1087 u8 prog;
1088
1089 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1090
1091 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1092 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1093 prog &= ~5;
1094 pdev->class &= ~5;
1095 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1096 }
1097 }
1098 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1099
1100 /*
1101 * Some ATA devices break if put into D3
1102 */
1103
1104 static void quirk_no_ata_d3(struct pci_dev *pdev)
1105 {
1106 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1107 }
1108 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1109 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1110 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1111 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1112 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1113 /* ALi loses some register settings that we cannot then restore */
1114 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1115 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1116 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1117 occur when mode detecting */
1118 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1119 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1120
1121 /* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */
1124 static void quirk_eisa_bridge(struct pci_dev *dev)
1125 {
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127 }
1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1129
1130
1131 /*
1132 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1133 * is not activated. The myth is that Asus said that they do not want the
1134 * users to be irritated by just another PCI Device in the Win98 device
1135 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1136 * package 2.7.0 for details)
1137 *
1138 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1139 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1140 * becomes necessary to do this tweak in two steps -- the chosen trigger
1141 * is either the Host bridge (preferred) or on-board VGA controller.
1142 *
1143 * Note that we used to unhide the SMBus that way on Toshiba laptops
1144 * (Satellite A40 and Tecra M2) but then found that the thermal management
1145 * was done by SMM code, which could cause unsynchronized concurrent
1146 * accesses to the SMBus registers, with potentially bad effects. Thus you
1147 * should be very careful when adding new entries: if SMM is accessing the
1148 * Intel SMBus, this is a very good reason to leave it hidden.
1149 *
1150 * Likewise, many recent laptops use ACPI for thermal management. If the
1151 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1152 * natively, and keeping the SMBus hidden is the right thing to do. If you
1153 * are about to add an entry in the table below, please first disassemble
1154 * the DSDT and double-check that there is no code accessing the SMBus.
1155 */
1156 static int asus_hides_smbus;
1157
1158 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159 {
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1162 switch(dev->subsystem_device) {
1163 case 0x8025: /* P4B-LX */
1164 case 0x8070: /* P4B */
1165 case 0x8088: /* P4B533 */
1166 case 0x1626: /* L3C notebook */
1167 asus_hides_smbus = 1;
1168 }
1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1170 switch(dev->subsystem_device) {
1171 case 0x80b1: /* P4GE-V */
1172 case 0x80b2: /* P4PE */
1173 case 0x8093: /* P4B533-V */
1174 asus_hides_smbus = 1;
1175 }
1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1177 switch(dev->subsystem_device) {
1178 case 0x8030: /* P4T533 */
1179 asus_hides_smbus = 1;
1180 }
1181 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1182 switch (dev->subsystem_device) {
1183 case 0x8070: /* P4G8X Deluxe */
1184 asus_hides_smbus = 1;
1185 }
1186 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1187 switch (dev->subsystem_device) {
1188 case 0x80c9: /* PU-DLS */
1189 asus_hides_smbus = 1;
1190 }
1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1192 switch (dev->subsystem_device) {
1193 case 0x1751: /* M2N notebook */
1194 case 0x1821: /* M5N notebook */
1195 case 0x1897: /* A6L notebook */
1196 asus_hides_smbus = 1;
1197 }
1198 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1199 switch (dev->subsystem_device) {
1200 case 0x184b: /* W1N notebook */
1201 case 0x186a: /* M6Ne notebook */
1202 asus_hides_smbus = 1;
1203 }
1204 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1205 switch (dev->subsystem_device) {
1206 case 0x80f2: /* P4P800-X */
1207 asus_hides_smbus = 1;
1208 }
1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1210 switch (dev->subsystem_device) {
1211 case 0x1882: /* M6V notebook */
1212 case 0x1977: /* A6VA notebook */
1213 asus_hides_smbus = 1;
1214 }
1215 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1216 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1217 switch(dev->subsystem_device) {
1218 case 0x088C: /* HP Compaq nc8000 */
1219 case 0x0890: /* HP Compaq nc6000 */
1220 asus_hides_smbus = 1;
1221 }
1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1223 switch (dev->subsystem_device) {
1224 case 0x12bc: /* HP D330L */
1225 case 0x12bd: /* HP D530 */
1226 case 0x006a: /* HP Compaq nx9500 */
1227 asus_hides_smbus = 1;
1228 }
1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1230 switch (dev->subsystem_device) {
1231 case 0x12bf: /* HP xw4100 */
1232 asus_hides_smbus = 1;
1233 }
1234 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1235 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1236 switch(dev->subsystem_device) {
1237 case 0xC00C: /* Samsung P35 notebook */
1238 asus_hides_smbus = 1;
1239 }
1240 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1241 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1242 switch(dev->subsystem_device) {
1243 case 0x0058: /* Compaq Evo N620c */
1244 asus_hides_smbus = 1;
1245 }
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1247 switch(dev->subsystem_device) {
1248 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1249 /* Motherboard doesn't have Host bridge
1250 * subvendor/subdevice IDs, therefore checking
1251 * its on-board VGA controller */
1252 asus_hides_smbus = 1;
1253 }
1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1255 switch(dev->subsystem_device) {
1256 case 0x00b8: /* Compaq Evo D510 CMT */
1257 case 0x00b9: /* Compaq Evo D510 SFF */
1258 case 0x00ba: /* Compaq Evo D510 USDT */
1259 /* Motherboard doesn't have Host bridge
1260 * subvendor/subdevice IDs and on-board VGA
1261 * controller is disabled if an AGP card is
1262 * inserted, therefore checking USB UHCI
1263 * Controller #1 */
1264 asus_hides_smbus = 1;
1265 }
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1267 switch (dev->subsystem_device) {
1268 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1269 /* Motherboard doesn't have host bridge
1270 * subvendor/subdevice IDs, therefore checking
1271 * its on-board VGA controller */
1272 asus_hides_smbus = 1;
1273 }
1274 }
1275 }
1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1286
1287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1290
1291 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1292 {
1293 u16 val;
1294
1295 if (likely(!asus_hides_smbus))
1296 return;
1297
1298 pci_read_config_word(dev, 0xF2, &val);
1299 if (val & 0x8) {
1300 pci_write_config_word(dev, 0xF2, val & (~0x8));
1301 pci_read_config_word(dev, 0xF2, &val);
1302 if (val & 0x8)
1303 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1304 else
1305 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1306 }
1307 }
1308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1315 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1316 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1317 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1318 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1319 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1320 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1321 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1322
1323 /* It appears we just have one such device. If not, we have a warning */
1324 static void __iomem *asus_rcba_base;
1325 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1326 {
1327 u32 rcba;
1328
1329 if (likely(!asus_hides_smbus))
1330 return;
1331 WARN_ON(asus_rcba_base);
1332
1333 pci_read_config_dword(dev, 0xF0, &rcba);
1334 /* use bits 31:14, 16 kB aligned */
1335 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1336 if (asus_rcba_base == NULL)
1337 return;
1338 }
1339
1340 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1341 {
1342 u32 val;
1343
1344 if (likely(!asus_hides_smbus || !asus_rcba_base))
1345 return;
1346 /* read the Function Disable register, dword mode only */
1347 val = readl(asus_rcba_base + 0x3418);
1348 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1349 }
1350
1351 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1352 {
1353 if (likely(!asus_hides_smbus || !asus_rcba_base))
1354 return;
1355 iounmap(asus_rcba_base);
1356 asus_rcba_base = NULL;
1357 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1358 }
1359
1360 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1361 {
1362 asus_hides_smbus_lpc_ich6_suspend(dev);
1363 asus_hides_smbus_lpc_ich6_resume_early(dev);
1364 asus_hides_smbus_lpc_ich6_resume(dev);
1365 }
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1367 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1368 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1369 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1370
1371 /*
1372 * SiS 96x south bridge: BIOS typically hides SMBus device...
1373 */
1374 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1375 {
1376 u8 val = 0;
1377 pci_read_config_byte(dev, 0x77, &val);
1378 if (val & 0x10) {
1379 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1380 pci_write_config_byte(dev, 0x77, val & ~0x10);
1381 }
1382 }
1383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1387 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1388 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1389 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1390 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1391
1392 /*
1393 * ... This is further complicated by the fact that some SiS96x south
1394 * bridges pretend to be 85C503/5513 instead. In that case see if we
1395 * spotted a compatible north bridge to make sure.
1396 * (pci_find_device doesn't work yet)
1397 *
1398 * We can also enable the sis96x bit in the discovery register..
1399 */
1400 #define SIS_DETECT_REGISTER 0x40
1401
1402 static void quirk_sis_503(struct pci_dev *dev)
1403 {
1404 u8 reg;
1405 u16 devid;
1406
1407 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1408 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1409 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1410 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1411 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1412 return;
1413 }
1414
1415 /*
1416 * Ok, it now shows up as a 96x.. run the 96x quirk by
1417 * hand in case it has already been processed.
1418 * (depends on link order, which is apparently not guaranteed)
1419 */
1420 dev->device = devid;
1421 quirk_sis_96x_smbus(dev);
1422 }
1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1425
1426
1427 /*
1428 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1429 * and MC97 modem controller are disabled when a second PCI soundcard is
1430 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1431 * -- bjd
1432 */
1433 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1434 {
1435 u8 val;
1436 int asus_hides_ac97 = 0;
1437
1438 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1439 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1440 asus_hides_ac97 = 1;
1441 }
1442
1443 if (!asus_hides_ac97)
1444 return;
1445
1446 pci_read_config_byte(dev, 0x50, &val);
1447 if (val & 0xc0) {
1448 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1449 pci_read_config_byte(dev, 0x50, &val);
1450 if (val & 0xc0)
1451 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1452 else
1453 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1454 }
1455 }
1456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1457 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1458
1459 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1460
1461 /*
1462 * If we are using libata we can drive this chip properly but must
1463 * do this early on to make the additional device appear during
1464 * the PCI scanning.
1465 */
1466 static void quirk_jmicron_ata(struct pci_dev *pdev)
1467 {
1468 u32 conf1, conf5, class;
1469 u8 hdr;
1470
1471 /* Only poke fn 0 */
1472 if (PCI_FUNC(pdev->devfn))
1473 return;
1474
1475 pci_read_config_dword(pdev, 0x40, &conf1);
1476 pci_read_config_dword(pdev, 0x80, &conf5);
1477
1478 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1479 conf5 &= ~(1 << 24); /* Clear bit 24 */
1480
1481 switch (pdev->device) {
1482 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1483 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1484 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1485 /* The controller should be in single function ahci mode */
1486 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1487 break;
1488
1489 case PCI_DEVICE_ID_JMICRON_JMB365:
1490 case PCI_DEVICE_ID_JMICRON_JMB366:
1491 /* Redirect IDE second PATA port to the right spot */
1492 conf5 |= (1 << 24);
1493 /* Fall through */
1494 case PCI_DEVICE_ID_JMICRON_JMB361:
1495 case PCI_DEVICE_ID_JMICRON_JMB363:
1496 case PCI_DEVICE_ID_JMICRON_JMB369:
1497 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1498 /* Set the class codes correctly and then direct IDE 0 */
1499 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1500 break;
1501
1502 case PCI_DEVICE_ID_JMICRON_JMB368:
1503 /* The controller should be in single function IDE mode */
1504 conf1 |= 0x00C00000; /* Set 22, 23 */
1505 break;
1506 }
1507
1508 pci_write_config_dword(pdev, 0x40, conf1);
1509 pci_write_config_dword(pdev, 0x80, conf5);
1510
1511 /* Update pdev accordingly */
1512 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1513 pdev->hdr_type = hdr & 0x7f;
1514 pdev->multifunction = !!(hdr & 0x80);
1515
1516 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1517 pdev->class = class >> 8;
1518 }
1519 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1520 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1521 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1522 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1525 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1526 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1527 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1529 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1530 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1532 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1534 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1535 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1536 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1537
1538 #endif
1539
1540 #ifdef CONFIG_X86_IO_APIC
1541 static void quirk_alder_ioapic(struct pci_dev *pdev)
1542 {
1543 int i;
1544
1545 if ((pdev->class >> 8) != 0xff00)
1546 return;
1547
1548 /* the first BAR is the location of the IO APIC...we must
1549 * not touch this (and it's already covered by the fixmap), so
1550 * forcibly insert it into the resource tree */
1551 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1552 insert_resource(&iomem_resource, &pdev->resource[0]);
1553
1554 /* The next five BARs all seem to be rubbish, so just clean
1555 * them out */
1556 for (i=1; i < 6; i++) {
1557 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1558 }
1559
1560 }
1561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1562 #endif
1563
1564 static void quirk_pcie_mch(struct pci_dev *pdev)
1565 {
1566 pci_msi_off(pdev);
1567 pdev->no_msi = 1;
1568 }
1569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1572
1573
1574 /*
1575 * It's possible for the MSI to get corrupted if shpc and acpi
1576 * are used together on certain PXH-based systems.
1577 */
1578 static void quirk_pcie_pxh(struct pci_dev *dev)
1579 {
1580 pci_msi_off(dev);
1581 dev->no_msi = 1;
1582 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1583 }
1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1587 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1588 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1589
1590 /*
1591 * Some Intel PCI Express chipsets have trouble with downstream
1592 * device power management.
1593 */
1594 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1595 {
1596 pci_pm_d3_delay = 120;
1597 dev->no_d1d2 = 1;
1598 }
1599
1600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1621
1622 #ifdef CONFIG_X86_IO_APIC
1623 /*
1624 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1625 * remap the original interrupt in the linux kernel to the boot interrupt, so
1626 * that a PCI device's interrupt handler is installed on the boot interrupt
1627 * line instead.
1628 */
1629 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1630 {
1631 if (noioapicquirk || noioapicreroute)
1632 return;
1633
1634 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1635 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1636 dev->vendor, dev->device);
1637 }
1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1646 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1647 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1648 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1649 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1650 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1651 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1652 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1653 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1654
1655 /*
1656 * On some chipsets we can disable the generation of legacy INTx boot
1657 * interrupts.
1658 */
1659
1660 /*
1661 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1662 * 300641-004US, section 5.7.3.
1663 */
1664 #define INTEL_6300_IOAPIC_ABAR 0x40
1665 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1666
1667 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1668 {
1669 u16 pci_config_word;
1670
1671 if (noioapicquirk)
1672 return;
1673
1674 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1675 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1676 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1677
1678 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1679 dev->vendor, dev->device);
1680 }
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1682 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1683
1684 /*
1685 * disable boot interrupts on HT-1000
1686 */
1687 #define BC_HT1000_FEATURE_REG 0x64
1688 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1689 #define BC_HT1000_MAP_IDX 0xC00
1690 #define BC_HT1000_MAP_DATA 0xC01
1691
1692 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1693 {
1694 u32 pci_config_dword;
1695 u8 irq;
1696
1697 if (noioapicquirk)
1698 return;
1699
1700 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1701 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1702 BC_HT1000_PIC_REGS_ENABLE);
1703
1704 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1705 outb(irq, BC_HT1000_MAP_IDX);
1706 outb(0x00, BC_HT1000_MAP_DATA);
1707 }
1708
1709 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1710
1711 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1712 dev->vendor, dev->device);
1713 }
1714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1715 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1716
1717 /*
1718 * disable boot interrupts on AMD and ATI chipsets
1719 */
1720 /*
1721 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1722 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1723 * (due to an erratum).
1724 */
1725 #define AMD_813X_MISC 0x40
1726 #define AMD_813X_NOIOAMODE (1<<0)
1727 #define AMD_813X_REV_B1 0x12
1728 #define AMD_813X_REV_B2 0x13
1729
1730 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1731 {
1732 u32 pci_config_dword;
1733
1734 if (noioapicquirk)
1735 return;
1736 if ((dev->revision == AMD_813X_REV_B1) ||
1737 (dev->revision == AMD_813X_REV_B2))
1738 return;
1739
1740 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1741 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1742 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1743
1744 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1745 dev->vendor, dev->device);
1746 }
1747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1748 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1751
1752 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1753
1754 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1755 {
1756 u16 pci_config_word;
1757
1758 if (noioapicquirk)
1759 return;
1760
1761 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1762 if (!pci_config_word) {
1763 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1764 "already disabled\n", dev->vendor, dev->device);
1765 return;
1766 }
1767 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1769 dev->vendor, dev->device);
1770 }
1771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1772 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1773 #endif /* CONFIG_X86_IO_APIC */
1774
1775 /*
1776 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed...
1779 */
1780 static void quirk_tc86c001_ide(struct pci_dev *dev)
1781 {
1782 struct resource *r = &dev->resource[0];
1783
1784 if (r->start & 0x8) {
1785 r->start = 0;
1786 r->end = 0xf;
1787 }
1788 }
1789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1790 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1791 quirk_tc86c001_ide);
1792
1793 /*
1794 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1795 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1796 * being read correctly if bit 7 of the base address is set.
1797 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1798 * Re-allocate the regions to a 256-byte boundary if necessary.
1799 */
1800 static void quirk_plx_pci9050(struct pci_dev *dev)
1801 {
1802 unsigned int bar;
1803
1804 /* Fixed in revision 2 (PCI 9052). */
1805 if (dev->revision >= 2)
1806 return;
1807 for (bar = 0; bar <= 1; bar++)
1808 if (pci_resource_len(dev, bar) == 0x80 &&
1809 (pci_resource_start(dev, bar) & 0x80)) {
1810 struct resource *r = &dev->resource[bar];
1811 dev_info(&dev->dev,
1812 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1813 bar);
1814 r->start = 0;
1815 r->end = 0xff;
1816 }
1817 }
1818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1819 quirk_plx_pci9050);
1820 /*
1821 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1822 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1823 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1824 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1825 *
1826 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1827 * driver.
1828 */
1829 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1830 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1831
1832 static void quirk_netmos(struct pci_dev *dev)
1833 {
1834 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1835 unsigned int num_serial = dev->subsystem_device & 0xf;
1836
1837 /*
1838 * These Netmos parts are multiport serial devices with optional
1839 * parallel ports. Even when parallel ports are present, they
1840 * are identified as class SERIAL, which means the serial driver
1841 * will claim them. To prevent this, mark them as class OTHER.
1842 * These combo devices should be claimed by parport_serial.
1843 *
1844 * The subdevice ID is of the form 0x00PS, where <P> is the number
1845 * of parallel ports and <S> is the number of serial ports.
1846 */
1847 switch (dev->device) {
1848 case PCI_DEVICE_ID_NETMOS_9835:
1849 /* Well, this rule doesn't hold for the following 9835 device */
1850 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1851 dev->subsystem_device == 0x0299)
1852 return;
1853 case PCI_DEVICE_ID_NETMOS_9735:
1854 case PCI_DEVICE_ID_NETMOS_9745:
1855 case PCI_DEVICE_ID_NETMOS_9845:
1856 case PCI_DEVICE_ID_NETMOS_9855:
1857 if (num_parallel) {
1858 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1859 "%u serial); changing class SERIAL to OTHER "
1860 "(use parport_serial)\n",
1861 dev->device, num_parallel, num_serial);
1862 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1863 (dev->class & 0xff);
1864 }
1865 }
1866 }
1867 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1868 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1869
1870 static void quirk_e100_interrupt(struct pci_dev *dev)
1871 {
1872 u16 command, pmcsr;
1873 u8 __iomem *csr;
1874 u8 cmd_hi;
1875 int pm;
1876
1877 switch (dev->device) {
1878 /* PCI IDs taken from drivers/net/e100.c */
1879 case 0x1029:
1880 case 0x1030 ... 0x1034:
1881 case 0x1038 ... 0x103E:
1882 case 0x1050 ... 0x1057:
1883 case 0x1059:
1884 case 0x1064 ... 0x106B:
1885 case 0x1091 ... 0x1095:
1886 case 0x1209:
1887 case 0x1229:
1888 case 0x2449:
1889 case 0x2459:
1890 case 0x245D:
1891 case 0x27DC:
1892 break;
1893 default:
1894 return;
1895 }
1896
1897 /*
1898 * Some firmware hands off the e100 with interrupts enabled,
1899 * which can cause a flood of interrupts if packets are
1900 * received before the driver attaches to the device. So
1901 * disable all e100 interrupts here. The driver will
1902 * re-enable them when it's ready.
1903 */
1904 pci_read_config_word(dev, PCI_COMMAND, &command);
1905
1906 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1907 return;
1908
1909 /*
1910 * Check that the device is in the D0 power state. If it's not,
1911 * there is no point to look any further.
1912 */
1913 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1914 if (pm) {
1915 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1916 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1917 return;
1918 }
1919
1920 /* Convert from PCI bus to resource space. */
1921 csr = ioremap(pci_resource_start(dev, 0), 8);
1922 if (!csr) {
1923 dev_warn(&dev->dev, "Can't map e100 registers\n");
1924 return;
1925 }
1926
1927 cmd_hi = readb(csr + 3);
1928 if (cmd_hi == 0) {
1929 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1930 "disabling\n");
1931 writeb(1, csr + 3);
1932 }
1933
1934 iounmap(csr);
1935 }
1936 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1937 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1938
1939 /*
1940 * The 82575 and 82598 may experience data corruption issues when transitioning
1941 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1942 */
1943 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
1944 {
1945 dev_info(&dev->dev, "Disabling L0s\n");
1946 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1947 }
1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1959 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1962
1963 static void fixup_rev1_53c810(struct pci_dev *dev)
1964 {
1965 /* rev 1 ncr53c810 chips don't set the class at all which means
1966 * they don't get their resources remapped. Fix that here.
1967 */
1968
1969 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1970 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1971 dev->class = PCI_CLASS_STORAGE_SCSI;
1972 }
1973 }
1974 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1975
1976 /* Enable 1k I/O space granularity on the Intel P64H2 */
1977 static void quirk_p64h2_1k_io(struct pci_dev *dev)
1978 {
1979 u16 en1k;
1980
1981 pci_read_config_word(dev, 0x40, &en1k);
1982
1983 if (en1k & 0x200) {
1984 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1985 dev->io_window_1k = 1;
1986 }
1987 }
1988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1989
1990 /* Under some circumstances, AER is not linked with extended capabilities.
1991 * Force it to be linked by setting the corresponding control bit in the
1992 * config space.
1993 */
1994 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1995 {
1996 uint8_t b;
1997 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1998 if (!(b & 0x20)) {
1999 pci_write_config_byte(dev, 0xf41, b | 0x20);
2000 dev_info(&dev->dev,
2001 "Linking AER extended capability\n");
2002 }
2003 }
2004 }
2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2006 quirk_nvidia_ck804_pcie_aer_ext_cap);
2007 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2008 quirk_nvidia_ck804_pcie_aer_ext_cap);
2009
2010 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2011 {
2012 /*
2013 * Disable PCI Bus Parking and PCI Master read caching on CX700
2014 * which causes unspecified timing errors with a VT6212L on the PCI
2015 * bus leading to USB2.0 packet loss.
2016 *
2017 * This quirk is only enabled if a second (on the external PCI bus)
2018 * VT6212L is found -- the CX700 core itself also contains a USB
2019 * host controller with the same PCI ID as the VT6212L.
2020 */
2021
2022 /* Count VT6212L instances */
2023 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2024 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2025 uint8_t b;
2026
2027 /* p should contain the first (internal) VT6212L -- see if we have
2028 an external one by searching again */
2029 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2030 if (!p)
2031 return;
2032 pci_dev_put(p);
2033
2034 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2035 if (b & 0x40) {
2036 /* Turn off PCI Bus Parking */
2037 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2038
2039 dev_info(&dev->dev,
2040 "Disabling VIA CX700 PCI parking\n");
2041 }
2042 }
2043
2044 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2045 if (b != 0) {
2046 /* Turn off PCI Master read caching */
2047 pci_write_config_byte(dev, 0x72, 0x0);
2048
2049 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2050 pci_write_config_byte(dev, 0x75, 0x1);
2051
2052 /* Disable "Read FIFO Timer" */
2053 pci_write_config_byte(dev, 0x77, 0x0);
2054
2055 dev_info(&dev->dev,
2056 "Disabling VIA CX700 PCI caching\n");
2057 }
2058 }
2059 }
2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2061
2062 /*
2063 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2064 * VPD end tag will hang the device. This problem was initially
2065 * observed when a vpd entry was created in sysfs
2066 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2067 * will dump 32k of data. Reading a full 32k will cause an access
2068 * beyond the VPD end tag causing the device to hang. Once the device
2069 * is hung, the bnx2 driver will not be able to reset the device.
2070 * We believe that it is legal to read beyond the end tag and
2071 * therefore the solution is to limit the read/write length.
2072 */
2073 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2074 {
2075 /*
2076 * Only disable the VPD capability for 5706, 5706S, 5708,
2077 * 5708S and 5709 rev. A
2078 */
2079 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2080 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2081 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2082 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2083 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2084 (dev->revision & 0xf0) == 0x0)) {
2085 if (dev->vpd)
2086 dev->vpd->len = 0x80;
2087 }
2088 }
2089
2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2091 PCI_DEVICE_ID_NX2_5706,
2092 quirk_brcm_570x_limit_vpd);
2093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2094 PCI_DEVICE_ID_NX2_5706S,
2095 quirk_brcm_570x_limit_vpd);
2096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2097 PCI_DEVICE_ID_NX2_5708,
2098 quirk_brcm_570x_limit_vpd);
2099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2100 PCI_DEVICE_ID_NX2_5708S,
2101 quirk_brcm_570x_limit_vpd);
2102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2103 PCI_DEVICE_ID_NX2_5709,
2104 quirk_brcm_570x_limit_vpd);
2105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2106 PCI_DEVICE_ID_NX2_5709S,
2107 quirk_brcm_570x_limit_vpd);
2108
2109 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2110 {
2111 u32 rev;
2112
2113 pci_read_config_dword(dev, 0xf4, &rev);
2114
2115 /* Only CAP the MRRS if the device is a 5719 A0 */
2116 if (rev == 0x05719000) {
2117 int readrq = pcie_get_readrq(dev);
2118 if (readrq > 2048)
2119 pcie_set_readrq(dev, 2048);
2120 }
2121 }
2122
2123 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2124 PCI_DEVICE_ID_TIGON3_5719,
2125 quirk_brcm_5719_limit_mrrs);
2126
2127 /* Originally in EDAC sources for i82875P:
2128 * Intel tells BIOS developers to hide device 6 which
2129 * configures the overflow device access containing
2130 * the DRBs - this is where we expose device 6.
2131 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2132 */
2133 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2134 {
2135 u8 reg;
2136
2137 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2138 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2139 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2140 }
2141 }
2142
2143 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2144 quirk_unhide_mch_dev6);
2145 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2146 quirk_unhide_mch_dev6);
2147
2148 #ifdef CONFIG_TILEPRO
2149 /*
2150 * The Tilera TILEmpower tilepro platform needs to set the link speed
2151 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2152 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2153 * capability register of the PEX8624 PCIe switch. The switch
2154 * supports link speed auto negotiation, but falsely sets
2155 * the link speed to 5GT/s.
2156 */
2157 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2158 {
2159 if (tile_plx_gen1) {
2160 pci_write_config_dword(dev, 0x98, 0x1);
2161 mdelay(50);
2162 }
2163 }
2164 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2165 #endif /* CONFIG_TILEPRO */
2166
2167 #ifdef CONFIG_PCI_MSI
2168 /* Some chipsets do not support MSI. We cannot easily rely on setting
2169 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2170 * some other busses controlled by the chipset even if Linux is not
2171 * aware of it. Instead of setting the flag on all busses in the
2172 * machine, simply disable MSI globally.
2173 */
2174 static void quirk_disable_all_msi(struct pci_dev *dev)
2175 {
2176 pci_no_msi();
2177 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2178 }
2179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2186
2187 /* Disable MSI on chipsets that are known to not support it */
2188 static void quirk_disable_msi(struct pci_dev *dev)
2189 {
2190 if (dev->subordinate) {
2191 dev_warn(&dev->dev, "MSI quirk detected; "
2192 "subordinate MSI disabled\n");
2193 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2194 }
2195 }
2196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2199
2200 /*
2201 * The APC bridge device in AMD 780 family northbridges has some random
2202 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2203 * we use the possible vendor/device IDs of the host bridge for the
2204 * declared quirk, and search for the APC bridge by slot number.
2205 */
2206 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2207 {
2208 struct pci_dev *apc_bridge;
2209
2210 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2211 if (apc_bridge) {
2212 if (apc_bridge->device == 0x9602)
2213 quirk_disable_msi(apc_bridge);
2214 pci_dev_put(apc_bridge);
2215 }
2216 }
2217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2219
2220 /* Go through the list of Hypertransport capabilities and
2221 * return 1 if a HT MSI capability is found and enabled */
2222 static int msi_ht_cap_enabled(struct pci_dev *dev)
2223 {
2224 int pos, ttl = 48;
2225
2226 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2227 while (pos && ttl--) {
2228 u8 flags;
2229
2230 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2231 &flags) == 0)
2232 {
2233 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2234 flags & HT_MSI_FLAGS_ENABLE ?
2235 "enabled" : "disabled");
2236 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2237 }
2238
2239 pos = pci_find_next_ht_capability(dev, pos,
2240 HT_CAPTYPE_MSI_MAPPING);
2241 }
2242 return 0;
2243 }
2244
2245 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2246 static void quirk_msi_ht_cap(struct pci_dev *dev)
2247 {
2248 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2249 dev_warn(&dev->dev, "MSI quirk detected; "
2250 "subordinate MSI disabled\n");
2251 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2252 }
2253 }
2254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2255 quirk_msi_ht_cap);
2256
2257 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2258 * MSI are supported if the MSI capability set in any of these mappings.
2259 */
2260 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2261 {
2262 struct pci_dev *pdev;
2263
2264 if (!dev->subordinate)
2265 return;
2266
2267 /* check HT MSI cap on this chipset and the root one.
2268 * a single one having MSI is enough to be sure that MSI are supported.
2269 */
2270 pdev = pci_get_slot(dev->bus, 0);
2271 if (!pdev)
2272 return;
2273 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2274 dev_warn(&dev->dev, "MSI quirk detected; "
2275 "subordinate MSI disabled\n");
2276 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2277 }
2278 pci_dev_put(pdev);
2279 }
2280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2281 quirk_nvidia_ck804_msi_ht_cap);
2282
2283 /* Force enable MSI mapping capability on HT bridges */
2284 static void ht_enable_msi_mapping(struct pci_dev *dev)
2285 {
2286 int pos, ttl = 48;
2287
2288 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2289 while (pos && ttl--) {
2290 u8 flags;
2291
2292 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2293 &flags) == 0) {
2294 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2295
2296 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2297 flags | HT_MSI_FLAGS_ENABLE);
2298 }
2299 pos = pci_find_next_ht_capability(dev, pos,
2300 HT_CAPTYPE_MSI_MAPPING);
2301 }
2302 }
2303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2304 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2305 ht_enable_msi_mapping);
2306
2307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2308 ht_enable_msi_mapping);
2309
2310 /* The P5N32-SLI motherboards from Asus have a problem with msi
2311 * for the MCP55 NIC. It is not yet determined whether the msi problem
2312 * also affects other devices. As for now, turn off msi for this device.
2313 */
2314 static void nvenet_msi_disable(struct pci_dev *dev)
2315 {
2316 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2317
2318 if (board_name &&
2319 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2320 strstr(board_name, "P5N32-E SLI"))) {
2321 dev_info(&dev->dev,
2322 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2323 dev->no_msi = 1;
2324 }
2325 }
2326 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2327 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2328 nvenet_msi_disable);
2329
2330 /*
2331 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2332 * config register. This register controls the routing of legacy interrupts
2333 * from devices that route through the MCP55. If this register is misprogramed
2334 * interrupts are only sent to the bsp, unlike conventional systems where the
2335 * irq is broadxast to all online cpus. Not having this register set
2336 * properly prevents kdump from booting up properly, so lets make sure that
2337 * we have it set correctly.
2338 * Note this is an undocumented register.
2339 */
2340 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2341 {
2342 u32 cfg;
2343
2344 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2345 return;
2346
2347 pci_read_config_dword(dev, 0x74, &cfg);
2348
2349 if (cfg & ((1 << 2) | (1 << 15))) {
2350 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2351 cfg &= ~((1 << 2) | (1 << 15));
2352 pci_write_config_dword(dev, 0x74, cfg);
2353 }
2354 }
2355
2356 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2357 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2358 nvbridge_check_legacy_irq_routing);
2359
2360 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2361 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2362 nvbridge_check_legacy_irq_routing);
2363
2364 static int ht_check_msi_mapping(struct pci_dev *dev)
2365 {
2366 int pos, ttl = 48;
2367 int found = 0;
2368
2369 /* check if there is HT MSI cap or enabled on this device */
2370 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2371 while (pos && ttl--) {
2372 u8 flags;
2373
2374 if (found < 1)
2375 found = 1;
2376 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2377 &flags) == 0) {
2378 if (flags & HT_MSI_FLAGS_ENABLE) {
2379 if (found < 2) {
2380 found = 2;
2381 break;
2382 }
2383 }
2384 }
2385 pos = pci_find_next_ht_capability(dev, pos,
2386 HT_CAPTYPE_MSI_MAPPING);
2387 }
2388
2389 return found;
2390 }
2391
2392 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2393 {
2394 struct pci_dev *dev;
2395 int pos;
2396 int i, dev_no;
2397 int found = 0;
2398
2399 dev_no = host_bridge->devfn >> 3;
2400 for (i = dev_no + 1; i < 0x20; i++) {
2401 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2402 if (!dev)
2403 continue;
2404
2405 /* found next host bridge ?*/
2406 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2407 if (pos != 0) {
2408 pci_dev_put(dev);
2409 break;
2410 }
2411
2412 if (ht_check_msi_mapping(dev)) {
2413 found = 1;
2414 pci_dev_put(dev);
2415 break;
2416 }
2417 pci_dev_put(dev);
2418 }
2419
2420 return found;
2421 }
2422
2423 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2424 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2425
2426 static int is_end_of_ht_chain(struct pci_dev *dev)
2427 {
2428 int pos, ctrl_off;
2429 int end = 0;
2430 u16 flags, ctrl;
2431
2432 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2433
2434 if (!pos)
2435 goto out;
2436
2437 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2438
2439 ctrl_off = ((flags >> 10) & 1) ?
2440 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2441 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2442
2443 if (ctrl & (1 << 6))
2444 end = 1;
2445
2446 out:
2447 return end;
2448 }
2449
2450 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2451 {
2452 struct pci_dev *host_bridge;
2453 int pos;
2454 int i, dev_no;
2455 int found = 0;
2456
2457 dev_no = dev->devfn >> 3;
2458 for (i = dev_no; i >= 0; i--) {
2459 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2460 if (!host_bridge)
2461 continue;
2462
2463 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2464 if (pos != 0) {
2465 found = 1;
2466 break;
2467 }
2468 pci_dev_put(host_bridge);
2469 }
2470
2471 if (!found)
2472 return;
2473
2474 /* don't enable end_device/host_bridge with leaf directly here */
2475 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2476 host_bridge_with_leaf(host_bridge))
2477 goto out;
2478
2479 /* root did that ! */
2480 if (msi_ht_cap_enabled(host_bridge))
2481 goto out;
2482
2483 ht_enable_msi_mapping(dev);
2484
2485 out:
2486 pci_dev_put(host_bridge);
2487 }
2488
2489 static void ht_disable_msi_mapping(struct pci_dev *dev)
2490 {
2491 int pos, ttl = 48;
2492
2493 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2494 while (pos && ttl--) {
2495 u8 flags;
2496
2497 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2498 &flags) == 0) {
2499 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2500
2501 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2502 flags & ~HT_MSI_FLAGS_ENABLE);
2503 }
2504 pos = pci_find_next_ht_capability(dev, pos,
2505 HT_CAPTYPE_MSI_MAPPING);
2506 }
2507 }
2508
2509 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2510 {
2511 struct pci_dev *host_bridge;
2512 int pos;
2513 int found;
2514
2515 if (!pci_msi_enabled())
2516 return;
2517
2518 /* check if there is HT MSI cap or enabled on this device */
2519 found = ht_check_msi_mapping(dev);
2520
2521 /* no HT MSI CAP */
2522 if (found == 0)
2523 return;
2524
2525 /*
2526 * HT MSI mapping should be disabled on devices that are below
2527 * a non-Hypertransport host bridge. Locate the host bridge...
2528 */
2529 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2530 if (host_bridge == NULL) {
2531 dev_warn(&dev->dev,
2532 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2533 return;
2534 }
2535
2536 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2537 if (pos != 0) {
2538 /* Host bridge is to HT */
2539 if (found == 1) {
2540 /* it is not enabled, try to enable it */
2541 if (all)
2542 ht_enable_msi_mapping(dev);
2543 else
2544 nv_ht_enable_msi_mapping(dev);
2545 }
2546 goto out;
2547 }
2548
2549 /* HT MSI is not enabled */
2550 if (found == 1)
2551 goto out;
2552
2553 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2554 ht_disable_msi_mapping(dev);
2555
2556 out:
2557 pci_dev_put(host_bridge);
2558 }
2559
2560 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2561 {
2562 return __nv_msi_ht_cap_quirk(dev, 1);
2563 }
2564
2565 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2566 {
2567 return __nv_msi_ht_cap_quirk(dev, 0);
2568 }
2569
2570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2571 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2572
2573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2575
2576 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2577 {
2578 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2579 }
2580 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2581 {
2582 struct pci_dev *p;
2583
2584 /* SB700 MSI issue will be fixed at HW level from revision A21,
2585 * we need check PCI REVISION ID of SMBus controller to get SB700
2586 * revision.
2587 */
2588 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2589 NULL);
2590 if (!p)
2591 return;
2592
2593 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2594 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2595 pci_dev_put(p);
2596 }
2597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2598 PCI_DEVICE_ID_TIGON3_5780,
2599 quirk_msi_intx_disable_bug);
2600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2601 PCI_DEVICE_ID_TIGON3_5780S,
2602 quirk_msi_intx_disable_bug);
2603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2604 PCI_DEVICE_ID_TIGON3_5714,
2605 quirk_msi_intx_disable_bug);
2606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2607 PCI_DEVICE_ID_TIGON3_5714S,
2608 quirk_msi_intx_disable_bug);
2609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2610 PCI_DEVICE_ID_TIGON3_5715,
2611 quirk_msi_intx_disable_bug);
2612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2613 PCI_DEVICE_ID_TIGON3_5715S,
2614 quirk_msi_intx_disable_bug);
2615
2616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2617 quirk_msi_intx_disable_ati_bug);
2618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2619 quirk_msi_intx_disable_ati_bug);
2620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2621 quirk_msi_intx_disable_ati_bug);
2622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2623 quirk_msi_intx_disable_ati_bug);
2624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2625 quirk_msi_intx_disable_ati_bug);
2626
2627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2628 quirk_msi_intx_disable_bug);
2629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2630 quirk_msi_intx_disable_bug);
2631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2632 quirk_msi_intx_disable_bug);
2633
2634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2635 quirk_msi_intx_disable_bug);
2636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2637 quirk_msi_intx_disable_bug);
2638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2639 quirk_msi_intx_disable_bug);
2640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2641 quirk_msi_intx_disable_bug);
2642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2643 quirk_msi_intx_disable_bug);
2644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2645 quirk_msi_intx_disable_bug);
2646 #endif /* CONFIG_PCI_MSI */
2647
2648 /* Allow manual resource allocation for PCI hotplug bridges
2649 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2650 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2651 * kernel fails to allocate resources when hotplug device is
2652 * inserted and PCI bus is rescanned.
2653 */
2654 static void quirk_hotplug_bridge(struct pci_dev *dev)
2655 {
2656 dev->is_hotplug_bridge = 1;
2657 }
2658
2659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2660
2661 /*
2662 * This is a quirk for the Ricoh MMC controller found as a part of
2663 * some mulifunction chips.
2664
2665 * This is very similar and based on the ricoh_mmc driver written by
2666 * Philip Langdale. Thank you for these magic sequences.
2667 *
2668 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2669 * and one or both of cardbus or firewire.
2670 *
2671 * It happens that they implement SD and MMC
2672 * support as separate controllers (and PCI functions). The linux SDHCI
2673 * driver supports MMC cards but the chip detects MMC cards in hardware
2674 * and directs them to the MMC controller - so the SDHCI driver never sees
2675 * them.
2676 *
2677 * To get around this, we must disable the useless MMC controller.
2678 * At that point, the SDHCI controller will start seeing them
2679 * It seems to be the case that the relevant PCI registers to deactivate the
2680 * MMC controller live on PCI function 0, which might be the cardbus controller
2681 * or the firewire controller, depending on the particular chip in question
2682 *
2683 * This has to be done early, because as soon as we disable the MMC controller
2684 * other pci functions shift up one level, e.g. function #2 becomes function
2685 * #1, and this will confuse the pci core.
2686 */
2687
2688 #ifdef CONFIG_MMC_RICOH_MMC
2689 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2690 {
2691 /* disable via cardbus interface */
2692 u8 write_enable;
2693 u8 write_target;
2694 u8 disable;
2695
2696 /* disable must be done via function #0 */
2697 if (PCI_FUNC(dev->devfn))
2698 return;
2699
2700 pci_read_config_byte(dev, 0xB7, &disable);
2701 if (disable & 0x02)
2702 return;
2703
2704 pci_read_config_byte(dev, 0x8E, &write_enable);
2705 pci_write_config_byte(dev, 0x8E, 0xAA);
2706 pci_read_config_byte(dev, 0x8D, &write_target);
2707 pci_write_config_byte(dev, 0x8D, 0xB7);
2708 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2709 pci_write_config_byte(dev, 0x8E, write_enable);
2710 pci_write_config_byte(dev, 0x8D, write_target);
2711
2712 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2713 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2714 }
2715 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2716 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2717
2718 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2719 {
2720 /* disable via firewire interface */
2721 u8 write_enable;
2722 u8 disable;
2723
2724 /* disable must be done via function #0 */
2725 if (PCI_FUNC(dev->devfn))
2726 return;
2727 /*
2728 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2729 * certain types of SD/MMC cards. Lowering the SD base
2730 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2731 *
2732 * 0x150 - SD2.0 mode enable for changing base clock
2733 * frequency to 50Mhz
2734 * 0xe1 - Base clock frequency
2735 * 0x32 - 50Mhz new clock frequency
2736 * 0xf9 - Key register for 0x150
2737 * 0xfc - key register for 0xe1
2738 */
2739 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2740 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2741 pci_write_config_byte(dev, 0xf9, 0xfc);
2742 pci_write_config_byte(dev, 0x150, 0x10);
2743 pci_write_config_byte(dev, 0xf9, 0x00);
2744 pci_write_config_byte(dev, 0xfc, 0x01);
2745 pci_write_config_byte(dev, 0xe1, 0x32);
2746 pci_write_config_byte(dev, 0xfc, 0x00);
2747
2748 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2749 }
2750
2751 pci_read_config_byte(dev, 0xCB, &disable);
2752
2753 if (disable & 0x02)
2754 return;
2755
2756 pci_read_config_byte(dev, 0xCA, &write_enable);
2757 pci_write_config_byte(dev, 0xCA, 0x57);
2758 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2759 pci_write_config_byte(dev, 0xCA, write_enable);
2760
2761 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2762 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2763
2764 }
2765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2766 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2768 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2769 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2771 #endif /*CONFIG_MMC_RICOH_MMC*/
2772
2773 #ifdef CONFIG_DMAR_TABLE
2774 #define VTUNCERRMSK_REG 0x1ac
2775 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2776 /*
2777 * This is a quirk for masking vt-d spec defined errors to platform error
2778 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2779 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2780 * on the RAS config settings of the platform) when a vt-d fault happens.
2781 * The resulting SMI caused the system to hang.
2782 *
2783 * VT-d spec related errors are already handled by the VT-d OS code, so no
2784 * need to report the same error through other channels.
2785 */
2786 static void vtd_mask_spec_errors(struct pci_dev *dev)
2787 {
2788 u32 word;
2789
2790 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2791 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2792 }
2793 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2794 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2795 #endif
2796
2797 static void fixup_ti816x_class(struct pci_dev *dev)
2798 {
2799 /* TI 816x devices do not have class code set when in PCIe boot mode */
2800 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2801 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2802 }
2803 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2804 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2805
2806 /* Some PCIe devices do not work reliably with the claimed maximum
2807 * payload size supported.
2808 */
2809 static void fixup_mpss_256(struct pci_dev *dev)
2810 {
2811 dev->pcie_mpss = 1; /* 256 bytes */
2812 }
2813 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2814 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2816 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2817 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2818 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2819
2820 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2821 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2822 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2823 * until all of the devices are discovered and buses walked, read completion
2824 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2825 * it is possible to hotplug a device with MPS of 256B.
2826 */
2827 static void quirk_intel_mc_errata(struct pci_dev *dev)
2828 {
2829 int err;
2830 u16 rcc;
2831
2832 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2833 return;
2834
2835 /* Intel errata specifies bits to change but does not say what they are.
2836 * Keeping them magical until such time as the registers and values can
2837 * be explained.
2838 */
2839 err = pci_read_config_word(dev, 0x48, &rcc);
2840 if (err) {
2841 dev_err(&dev->dev, "Error attempting to read the read "
2842 "completion coalescing register.\n");
2843 return;
2844 }
2845
2846 if (!(rcc & (1 << 10)))
2847 return;
2848
2849 rcc &= ~(1 << 10);
2850
2851 err = pci_write_config_word(dev, 0x48, rcc);
2852 if (err) {
2853 dev_err(&dev->dev, "Error attempting to write the read "
2854 "completion coalescing register.\n");
2855 return;
2856 }
2857
2858 pr_info_once("Read completion coalescing disabled due to hardware "
2859 "errata relating to 256B MPS.\n");
2860 }
2861 /* Intel 5000 series memory controllers and ports 2-7 */
2862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2876 /* Intel 5100 series memory controllers and ports 2-7 */
2877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2888
2889
2890 static ktime_t fixup_debug_start(struct pci_dev *dev,
2891 void (*fn)(struct pci_dev *dev))
2892 {
2893 ktime_t calltime = ktime_set(0, 0);
2894
2895 dev_dbg(&dev->dev, "calling %pF\n", fn);
2896 if (initcall_debug) {
2897 pr_debug("calling %pF @ %i for %s\n",
2898 fn, task_pid_nr(current), dev_name(&dev->dev));
2899 calltime = ktime_get();
2900 }
2901
2902 return calltime;
2903 }
2904
2905 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2906 void (*fn)(struct pci_dev *dev))
2907 {
2908 ktime_t delta, rettime;
2909 unsigned long long duration;
2910
2911 if (initcall_debug) {
2912 rettime = ktime_get();
2913 delta = ktime_sub(rettime, calltime);
2914 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2915 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2916 fn, duration, dev_name(&dev->dev));
2917 }
2918 }
2919
2920 /*
2921 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2922 * even though no one is handling them (f.e. i915 driver is never loaded).
2923 * Additionally the interrupt destination is not set up properly
2924 * and the interrupt ends up -somewhere-.
2925 *
2926 * These spurious interrupts are "sticky" and the kernel disables
2927 * the (shared) interrupt line after 100.000+ generated interrupts.
2928 *
2929 * Fix it by disabling the still enabled interrupts.
2930 * This resolves crashes often seen on monitor unplug.
2931 */
2932 #define I915_DEIER_REG 0x4400c
2933 static void disable_igfx_irq(struct pci_dev *dev)
2934 {
2935 void __iomem *regs = pci_iomap(dev, 0, 0);
2936 if (regs == NULL) {
2937 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2938 return;
2939 }
2940
2941 /* Check if any interrupt line is still enabled */
2942 if (readl(regs + I915_DEIER_REG) != 0) {
2943 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2944 "disabling\n");
2945
2946 writel(0, regs + I915_DEIER_REG);
2947 }
2948
2949 pci_iounmap(dev, regs);
2950 }
2951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2953
2954 /*
2955 * Some devices may pass our check in pci_intx_mask_supported if
2956 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2957 * support this feature.
2958 */
2959 static void quirk_broken_intx_masking(struct pci_dev *dev)
2960 {
2961 dev->broken_intx_masking = 1;
2962 }
2963 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2964 quirk_broken_intx_masking);
2965 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2966 quirk_broken_intx_masking);
2967
2968 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2969 struct pci_fixup *end)
2970 {
2971 ktime_t calltime;
2972
2973 for (; f < end; f++)
2974 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2975 f->class == (u32) PCI_ANY_ID) &&
2976 (f->vendor == dev->vendor ||
2977 f->vendor == (u16) PCI_ANY_ID) &&
2978 (f->device == dev->device ||
2979 f->device == (u16) PCI_ANY_ID)) {
2980 calltime = fixup_debug_start(dev, f->hook);
2981 f->hook(dev);
2982 fixup_debug_report(dev, calltime, f->hook);
2983 }
2984 }
2985
2986 extern struct pci_fixup __start_pci_fixups_early[];
2987 extern struct pci_fixup __end_pci_fixups_early[];
2988 extern struct pci_fixup __start_pci_fixups_header[];
2989 extern struct pci_fixup __end_pci_fixups_header[];
2990 extern struct pci_fixup __start_pci_fixups_final[];
2991 extern struct pci_fixup __end_pci_fixups_final[];
2992 extern struct pci_fixup __start_pci_fixups_enable[];
2993 extern struct pci_fixup __end_pci_fixups_enable[];
2994 extern struct pci_fixup __start_pci_fixups_resume[];
2995 extern struct pci_fixup __end_pci_fixups_resume[];
2996 extern struct pci_fixup __start_pci_fixups_resume_early[];
2997 extern struct pci_fixup __end_pci_fixups_resume_early[];
2998 extern struct pci_fixup __start_pci_fixups_suspend[];
2999 extern struct pci_fixup __end_pci_fixups_suspend[];
3000
3001 static bool pci_apply_fixup_final_quirks;
3002
3003 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3004 {
3005 struct pci_fixup *start, *end;
3006
3007 switch(pass) {
3008 case pci_fixup_early:
3009 start = __start_pci_fixups_early;
3010 end = __end_pci_fixups_early;
3011 break;
3012
3013 case pci_fixup_header:
3014 start = __start_pci_fixups_header;
3015 end = __end_pci_fixups_header;
3016 break;
3017
3018 case pci_fixup_final:
3019 if (!pci_apply_fixup_final_quirks)
3020 return;
3021 start = __start_pci_fixups_final;
3022 end = __end_pci_fixups_final;
3023 break;
3024
3025 case pci_fixup_enable:
3026 start = __start_pci_fixups_enable;
3027 end = __end_pci_fixups_enable;
3028 break;
3029
3030 case pci_fixup_resume:
3031 start = __start_pci_fixups_resume;
3032 end = __end_pci_fixups_resume;
3033 break;
3034
3035 case pci_fixup_resume_early:
3036 start = __start_pci_fixups_resume_early;
3037 end = __end_pci_fixups_resume_early;
3038 break;
3039
3040 case pci_fixup_suspend:
3041 start = __start_pci_fixups_suspend;
3042 end = __end_pci_fixups_suspend;
3043 break;
3044
3045 default:
3046 /* stupid compiler warning, you would think with an enum... */
3047 return;
3048 }
3049 pci_do_fixups(dev, start, end);
3050 }
3051 EXPORT_SYMBOL(pci_fixup_device);
3052
3053
3054 static int __init pci_apply_final_quirks(void)
3055 {
3056 struct pci_dev *dev = NULL;
3057 u8 cls = 0;
3058 u8 tmp;
3059
3060 if (pci_cache_line_size)
3061 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3062 pci_cache_line_size << 2);
3063
3064 pci_apply_fixup_final_quirks = true;
3065 for_each_pci_dev(dev) {
3066 pci_fixup_device(pci_fixup_final, dev);
3067 /*
3068 * If arch hasn't set it explicitly yet, use the CLS
3069 * value shared by all PCI devices. If there's a
3070 * mismatch, fall back to the default value.
3071 */
3072 if (!pci_cache_line_size) {
3073 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3074 if (!cls)
3075 cls = tmp;
3076 if (!tmp || cls == tmp)
3077 continue;
3078
3079 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3080 "using %u bytes\n", cls << 2, tmp << 2,
3081 pci_dfl_cache_line_size << 2);
3082 pci_cache_line_size = pci_dfl_cache_line_size;
3083 }
3084 }
3085
3086 if (!pci_cache_line_size) {
3087 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3088 cls << 2, pci_dfl_cache_line_size << 2);
3089 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3090 }
3091
3092 return 0;
3093 }
3094
3095 fs_initcall_sync(pci_apply_final_quirks);
3096
3097 /*
3098 * Followings are device-specific reset methods which can be used to
3099 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3100 * not available.
3101 */
3102 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3103 {
3104 int pos;
3105
3106 /* only implement PCI_CLASS_SERIAL_USB at present */
3107 if (dev->class == PCI_CLASS_SERIAL_USB) {
3108 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3109 if (!pos)
3110 return -ENOTTY;
3111
3112 if (probe)
3113 return 0;
3114
3115 pci_write_config_byte(dev, pos + 0x4, 1);
3116 msleep(100);
3117
3118 return 0;
3119 } else {
3120 return -ENOTTY;
3121 }
3122 }
3123
3124 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3125 {
3126 int i;
3127 u16 status;
3128
3129 /*
3130 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3131 *
3132 * The 82599 supports FLR on VFs, but FLR support is reported only
3133 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3134 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3135 */
3136
3137 if (probe)
3138 return 0;
3139
3140 /* Wait for Transaction Pending bit clean */
3141 for (i = 0; i < 4; i++) {
3142 if (i)
3143 msleep((1 << (i - 1)) * 100);
3144
3145 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3146 if (!(status & PCI_EXP_DEVSTA_TRPND))
3147 goto clear;
3148 }
3149
3150 dev_err(&dev->dev, "transaction is not cleared; "
3151 "proceeding with reset anyway\n");
3152
3153 clear:
3154 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3155
3156 msleep(100);
3157
3158 return 0;
3159 }
3160
3161 #include "../gpu/drm/i915/i915_reg.h"
3162 #define MSG_CTL 0x45010
3163 #define NSDE_PWR_STATE 0xd0100
3164 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3165
3166 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3167 {
3168 void __iomem *mmio_base;
3169 unsigned long timeout;
3170 u32 val;
3171
3172 if (probe)
3173 return 0;
3174
3175 mmio_base = pci_iomap(dev, 0, 0);
3176 if (!mmio_base)
3177 return -ENOMEM;
3178
3179 iowrite32(0x00000002, mmio_base + MSG_CTL);
3180
3181 /*
3182 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3183 * driver loaded sets the right bits. However, this's a reset and
3184 * the bits have been set by i915 previously, so we clobber
3185 * SOUTH_CHICKEN2 register directly here.
3186 */
3187 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3188
3189 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3190 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3191
3192 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3193 do {
3194 val = ioread32(mmio_base + PCH_PP_STATUS);
3195 if ((val & 0xb0000000) == 0)
3196 goto reset_complete;
3197 msleep(10);
3198 } while (time_before(jiffies, timeout));
3199 dev_warn(&dev->dev, "timeout during reset\n");
3200
3201 reset_complete:
3202 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3203
3204 pci_iounmap(dev, mmio_base);
3205 return 0;
3206 }
3207
3208 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3209 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3210 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3211
3212 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3213 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3214 reset_intel_82599_sfp_virtfn },
3215 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3216 reset_ivb_igd },
3217 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3218 reset_ivb_igd },
3219 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3220 reset_intel_generic_dev },
3221 { 0 }
3222 };
3223
3224 /*
3225 * These device-specific reset methods are here rather than in a driver
3226 * because when a host assigns a device to a guest VM, the host may need
3227 * to reset the device but probably doesn't have a driver for it.
3228 */
3229 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3230 {
3231 const struct pci_dev_reset_methods *i;
3232
3233 for (i = pci_dev_reset_methods; i->reset; i++) {
3234 if ((i->vendor == dev->vendor ||
3235 i->vendor == (u16)PCI_ANY_ID) &&
3236 (i->device == dev->device ||
3237 i->device == (u16)PCI_ANY_ID))
3238 return i->reset(dev, probe);
3239 }
3240
3241 return -ENOTTY;
3242 }
3243
3244 static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3245 {
3246 if (!PCI_FUNC(dev->devfn))
3247 return pci_dev_get(dev);
3248
3249 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3250 }
3251
3252 static const struct pci_dev_dma_source {
3253 u16 vendor;
3254 u16 device;
3255 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3256 } pci_dev_dma_source[] = {
3257 /*
3258 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3259 *
3260 * Some Ricoh devices use the function 0 source ID for DMA on
3261 * other functions of a multifunction device. The DMA devices
3262 * is therefore function 0, which will have implications of the
3263 * iommu grouping of these devices.
3264 */
3265 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3266 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3267 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3268 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3269 { 0 }
3270 };
3271
3272 /*
3273 * IOMMUs with isolation capabilities need to be programmed with the
3274 * correct source ID of a device. In most cases, the source ID matches
3275 * the device doing the DMA, but sometimes hardware is broken and will
3276 * tag the DMA as being sourced from a different device. This function
3277 * allows that translation. Note that the reference count of the
3278 * returned device is incremented on all paths.
3279 */
3280 struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3281 {
3282 const struct pci_dev_dma_source *i;
3283
3284 for (i = pci_dev_dma_source; i->dma_source; i++) {
3285 if ((i->vendor == dev->vendor ||
3286 i->vendor == (u16)PCI_ANY_ID) &&
3287 (i->device == dev->device ||
3288 i->device == (u16)PCI_ANY_ID))
3289 return i->dma_source(dev);
3290 }
3291
3292 return pci_dev_get(dev);
3293 }
3294
3295 static const struct pci_dev_acs_enabled {
3296 u16 vendor;
3297 u16 device;
3298 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3299 } pci_dev_acs_enabled[] = {
3300 { 0 }
3301 };
3302
3303 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3304 {
3305 const struct pci_dev_acs_enabled *i;
3306 int ret;
3307
3308 /*
3309 * Allow devices that do not expose standard PCIe ACS capabilities
3310 * or control to indicate their support here. Multi-function express
3311 * devices which do not allow internal peer-to-peer between functions,
3312 * but do not implement PCIe ACS may wish to return true here.
3313 */
3314 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3315 if ((i->vendor == dev->vendor ||
3316 i->vendor == (u16)PCI_ANY_ID) &&
3317 (i->device == dev->device ||
3318 i->device == (u16)PCI_ANY_ID)) {
3319 ret = i->acs_enabled(dev, acs_flags);
3320 if (ret >= 0)
3321 return ret;
3322 }
3323 }
3324
3325 return -ENOTTY;
3326 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree