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iwlwifi: add {ack,plpc}_check module parameters
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
blobfd142bee91896ca1ba2a121193c4183f83b89d72
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwlagn_tx_resp *tx_resp,
176 int txq_id, bool is_agg)
177 {
178 u16 status = le16_to_cpu(tx_resp->status.status);
179
180 info->status.rates[0].count = tx_resp->failure_frame + 1;
181 if (is_agg)
182 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
183 info->flags |= iwl_tx_status_to_mac80211(status);
184 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
185 info);
186 if (!iwl_is_tx_success(status))
187 iwlagn_count_tx_err_status(priv, status);
188
189 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
190 "0x%x retries %d\n",
191 txq_id,
192 iwl_get_tx_fail_reason(status), status,
193 le32_to_cpu(tx_resp->rate_n_flags),
194 tx_resp->failure_frame);
195 }
196
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
199
200 const char *iwl_get_agg_tx_fail_reason(u16 status)
201 {
202 status &= AGG_TX_STATUS_MSK;
203 switch (status) {
204 case AGG_TX_STATE_TRANSMITTED:
205 return "SUCCESS";
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
209 AGG_TX_STATE_FAIL(ABORT_MSK);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
218 }
219
220 return "UNKNOWN";
221 }
222 #endif /* CONFIG_IWLWIFI_DEBUG */
223
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
225 struct iwl_ht_agg *agg,
226 struct iwlagn_tx_resp *tx_resp,
227 int txq_id, u16 start_idx)
228 {
229 u16 status;
230 struct agg_tx_status *frame_status = &tx_resp->status;
231 struct ieee80211_hdr *hdr = NULL;
232 int i, sh, idx;
233 u16 seq;
234
235 if (agg->wait_for_ba)
236 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
237
238 agg->frame_count = tx_resp->frame_count;
239 agg->start_idx = start_idx;
240 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
241 agg->bitmap = 0;
242
243 /* # frames attempted by Tx command */
244 if (agg->frame_count == 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
246 idx = start_idx;
247
248 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg->frame_count, agg->start_idx, idx);
250 iwlagn_set_tx_status(priv,
251 IEEE80211_SKB_CB(
252 priv->txq[txq_id].txb[idx].skb),
253 tx_resp, txq_id, true);
254 agg->wait_for_ba = 0;
255 } else {
256 /* Two or more frames were attempted; expect block-ack */
257 u64 bitmap = 0;
258
259 /*
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
263 */
264 int start = agg->start_idx;
265
266 /* Construct bit-map of pending frames within Tx window */
267 for (i = 0; i < agg->frame_count; i++) {
268 u16 sc;
269 status = le16_to_cpu(frame_status[i].status);
270 seq = le16_to_cpu(frame_status[i].sequence);
271 idx = SEQ_TO_INDEX(seq);
272 txq_id = SEQ_TO_QUEUE(seq);
273
274 if (status & AGG_TX_STATUS_MSK)
275 iwlagn_count_agg_tx_err_status(priv, status);
276
277 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
278 AGG_TX_STATE_ABORT_MSK))
279 continue;
280
281 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg->frame_count, txq_id, idx);
283 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status),
286 status & AGG_TX_STATUS_MSK,
287 status & AGG_TX_TRY_MSK);
288
289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
290 if (!hdr) {
291 IWL_ERR(priv,
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx, txq_id);
294 return -1;
295 }
296
297 sc = le16_to_cpu(hdr->seq_ctrl);
298 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
299 IWL_ERR(priv,
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
302 idx, SEQ_TO_SN(sc),
303 hdr->seq_ctrl);
304 return -1;
305 }
306
307 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
308 i, idx, SEQ_TO_SN(sc));
309
310 /*
311 * sh -> how many frames ahead of the starting frame is
312 * the current one?
313 *
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
318 */
319 sh = idx - start;
320
321 /*
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
326 */
327 if (sh >= 64) {
328 /* Shift bitmap by start - idx, wrapped */
329 sh = 0x100 - idx + start;
330 bitmap = bitmap << sh;
331 /* Now idx is the new start so sh = 0 */
332 sh = 0;
333 start = idx;
334 /*
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
337 */
338 } else if (sh <= -64) {
339 sh = 0x100 - start + idx;
340 /*
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
343 */
344 } else if (sh < 0) {
345 /* Shift by how far start is ahead of idx */
346 sh = start - idx;
347 bitmap = bitmap << sh;
348 /* Now idx is the new start so sh = 0 */
349 start = idx;
350 sh = 0;
351 }
352 /* Sequence number start + sh was sent in this batch */
353 bitmap |= 1ULL << sh;
354 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
355 start, (unsigned long long)bitmap);
356 }
357
358 /*
359 * Store the bitmap and possibly the new start, if we wrapped
360 * the buffer above
361 */
362 agg->bitmap = bitmap;
363 agg->start_idx = start;
364 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg->frame_count, agg->start_idx,
366 (unsigned long long)agg->bitmap);
367
368 if (bitmap)
369 agg->wait_for_ba = 1;
370 }
371 return 0;
372 }
373
374 void iwl_check_abort_status(struct iwl_priv *priv,
375 u8 frame_count, u32 status)
376 {
377 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
378 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
380 queue_work(priv->workqueue, &priv->tx_flush);
381 }
382 }
383
384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
385 struct iwl_rx_mem_buffer *rxb)
386 {
387 struct iwl_rx_packet *pkt = rxb_addr(rxb);
388 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
389 int txq_id = SEQ_TO_QUEUE(sequence);
390 int index = SEQ_TO_INDEX(sequence);
391 struct iwl_tx_queue *txq = &priv->txq[txq_id];
392 struct ieee80211_tx_info *info;
393 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
394 u32 status = le16_to_cpu(tx_resp->status.status);
395 int tid;
396 int sta_id;
397 int freed;
398 unsigned long flags;
399
400 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
401 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id,
403 index, txq->q.n_bd, txq->q.write_ptr,
404 txq->q.read_ptr);
405 return;
406 }
407
408 txq->time_stamp = jiffies;
409 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
410 memset(&info->status, 0, sizeof(info->status));
411
412 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
413 IWLAGN_TX_RES_TID_POS;
414 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
415 IWLAGN_TX_RES_RA_POS;
416
417 spin_lock_irqsave(&priv->sta_lock, flags);
418 if (txq->sched_retry) {
419 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
420 struct iwl_ht_agg *agg;
421
422 agg = &priv->stations[sta_id].tid[tid].agg;
423 /*
424 * If the BT kill count is non-zero, we'll get this
425 * notification again.
426 */
427 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
428 priv->cfg->bt_params &&
429 priv->cfg->bt_params->advanced_bt_coexist) {
430 IWL_WARN(priv, "receive reply tx with bt_kill\n");
431 }
432 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
433
434 /* check if BAR is needed */
435 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
436 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
437
438 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
439 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
440 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
441 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
442 scd_ssn , index, txq_id, txq->swq_id);
443
444 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
445 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
446
447 if (priv->mac80211_registered &&
448 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
449 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
450 iwl_wake_queue(priv, txq);
451 }
452 } else {
453 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
454 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
455 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
456
457 if (priv->mac80211_registered &&
458 (iwl_queue_space(&txq->q) > txq->q.low_mark))
459 iwl_wake_queue(priv, txq);
460 }
461
462 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
463
464 iwl_check_abort_status(priv, tx_resp->frame_count, status);
465 spin_unlock_irqrestore(&priv->sta_lock, flags);
466 }
467
468 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
469 {
470 /* init calibration handlers */
471 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
472 iwlagn_rx_calib_result;
473 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
474 iwlagn_rx_calib_complete;
475 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
476
477 /* set up notification wait support */
478 spin_lock_init(&priv->_agn.notif_wait_lock);
479 INIT_LIST_HEAD(&priv->_agn.notif_waits);
480 init_waitqueue_head(&priv->_agn.notif_waitq);
481 }
482
483 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
484 {
485 /* in agn, the tx power calibration is done in uCode */
486 priv->disable_tx_power_cal = 1;
487 }
488
489 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
490 {
491 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
492 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
493 }
494
495 int iwlagn_send_tx_power(struct iwl_priv *priv)
496 {
497 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
498 u8 tx_ant_cfg_cmd;
499
500 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
501 "TX Power requested while scanning!\n"))
502 return -EAGAIN;
503
504 /* half dBm need to multiply */
505 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
506
507 if (priv->tx_power_lmt_in_half_dbm &&
508 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
509 /*
510 * For the newer devices which using enhanced/extend tx power
511 * table in EEPROM, the format is in half dBm. driver need to
512 * convert to dBm format before report to mac80211.
513 * By doing so, there is a possibility of 1/2 dBm resolution
514 * lost. driver will perform "round-up" operation before
515 * reporting, but it will cause 1/2 dBm tx power over the
516 * regulatory limit. Perform the checking here, if the
517 * "tx_power_user_lmt" is higher than EEPROM value (in
518 * half-dBm format), lower the tx power based on EEPROM
519 */
520 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
521 }
522 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
523 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
524
525 if (IWL_UCODE_API(priv->ucode_ver) == 1)
526 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
527 else
528 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
529
530 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
531 &tx_power_cmd);
532 }
533
534 void iwlagn_temperature(struct iwl_priv *priv)
535 {
536 /* store temperature from statistics (in Celsius) */
537 priv->temperature =
538 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
539 iwl_tt_handler(priv);
540 }
541
542 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
543 {
544 struct iwl_eeprom_calib_hdr {
545 u8 version;
546 u8 pa_type;
547 u16 voltage;
548 } *hdr;
549
550 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
551 EEPROM_CALIB_ALL);
552 return hdr->version;
553
554 }
555
556 /*
557 * EEPROM
558 */
559 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
560 {
561 u16 offset = 0;
562
563 if ((address & INDIRECT_ADDRESS) == 0)
564 return address;
565
566 switch (address & INDIRECT_TYPE_MSK) {
567 case INDIRECT_HOST:
568 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
569 break;
570 case INDIRECT_GENERAL:
571 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
572 break;
573 case INDIRECT_REGULATORY:
574 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
575 break;
576 case INDIRECT_TXP_LIMIT:
577 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
578 break;
579 case INDIRECT_TXP_LIMIT_SIZE:
580 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
581 break;
582 case INDIRECT_CALIBRATION:
583 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
584 break;
585 case INDIRECT_PROCESS_ADJST:
586 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
587 break;
588 case INDIRECT_OTHERS:
589 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
590 break;
591 default:
592 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
593 address & INDIRECT_TYPE_MSK);
594 break;
595 }
596
597 /* translate the offset from words to byte */
598 return (address & ADDRESS_MSK) + (offset << 1);
599 }
600
601 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
602 size_t offset)
603 {
604 u32 address = eeprom_indirect_address(priv, offset);
605 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
606 return &priv->eeprom[address];
607 }
608
609 struct iwl_mod_params iwlagn_mod_params = {
610 .amsdu_size_8K = 1,
611 .restart_fw = 1,
612 .plcp_check = true,
613 /* the rest are 0 by default */
614 };
615
616 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
617 {
618 unsigned long flags;
619 int i;
620 spin_lock_irqsave(&rxq->lock, flags);
621 INIT_LIST_HEAD(&rxq->rx_free);
622 INIT_LIST_HEAD(&rxq->rx_used);
623 /* Fill the rx_used queue with _all_ of the Rx buffers */
624 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
625 /* In the reset function, these buffers may have been allocated
626 * to an SKB, so we need to unmap and free potential storage */
627 if (rxq->pool[i].page != NULL) {
628 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
629 PAGE_SIZE << priv->hw_params.rx_page_order,
630 PCI_DMA_FROMDEVICE);
631 __iwl_free_pages(priv, rxq->pool[i].page);
632 rxq->pool[i].page = NULL;
633 }
634 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
635 }
636
637 for (i = 0; i < RX_QUEUE_SIZE; i++)
638 rxq->queue[i] = NULL;
639
640 /* Set us so that we have processed and used all buffers, but have
641 * not restocked the Rx queue with fresh buffers */
642 rxq->read = rxq->write = 0;
643 rxq->write_actual = 0;
644 rxq->free_count = 0;
645 spin_unlock_irqrestore(&rxq->lock, flags);
646 }
647
648 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
649 {
650 u32 rb_size;
651 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
652 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
653
654 if (!priv->cfg->base_params->use_isr_legacy)
655 rb_timeout = RX_RB_TIMEOUT;
656
657 if (priv->cfg->mod_params->amsdu_size_8K)
658 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
659 else
660 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
661
662 /* Stop Rx DMA */
663 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
664
665 /* Reset driver's Rx queue write index */
666 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
667
668 /* Tell device where to find RBD circular buffer in DRAM */
669 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
670 (u32)(rxq->bd_dma >> 8));
671
672 /* Tell device where in DRAM to update its Rx status */
673 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
674 rxq->rb_stts_dma >> 4);
675
676 /* Enable Rx DMA
677 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
678 * the credit mechanism in 5000 HW RX FIFO
679 * Direct rx interrupts to hosts
680 * Rx buffer size 4 or 8k
681 * RB timeout 0x10
682 * 256 RBDs
683 */
684 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
685 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
686 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
687 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
688 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
689 rb_size|
690 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
691 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
692
693 /* Set interrupt coalescing timer to default (2048 usecs) */
694 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
695
696 return 0;
697 }
698
699 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
700 {
701 /*
702 * (for documentation purposes)
703 * to set power to V_AUX, do:
704
705 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
706 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
707 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
708 ~APMG_PS_CTRL_MSK_PWR_SRC);
709 */
710
711 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
712 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
713 ~APMG_PS_CTRL_MSK_PWR_SRC);
714 }
715
716 int iwlagn_hw_nic_init(struct iwl_priv *priv)
717 {
718 unsigned long flags;
719 struct iwl_rx_queue *rxq = &priv->rxq;
720 int ret;
721
722 /* nic_init */
723 spin_lock_irqsave(&priv->lock, flags);
724 priv->cfg->ops->lib->apm_ops.init(priv);
725
726 /* Set interrupt coalescing calibration timer to default (512 usecs) */
727 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
728
729 spin_unlock_irqrestore(&priv->lock, flags);
730
731 iwlagn_set_pwr_vmain(priv);
732
733 priv->cfg->ops->lib->apm_ops.config(priv);
734
735 /* Allocate the RX queue, or reset if it is already allocated */
736 if (!rxq->bd) {
737 ret = iwl_rx_queue_alloc(priv);
738 if (ret) {
739 IWL_ERR(priv, "Unable to initialize Rx queue\n");
740 return -ENOMEM;
741 }
742 } else
743 iwlagn_rx_queue_reset(priv, rxq);
744
745 iwlagn_rx_replenish(priv);
746
747 iwlagn_rx_init(priv, rxq);
748
749 spin_lock_irqsave(&priv->lock, flags);
750
751 rxq->need_update = 1;
752 iwl_rx_queue_update_write_ptr(priv, rxq);
753
754 spin_unlock_irqrestore(&priv->lock, flags);
755
756 /* Allocate or reset and init all Tx and Command queues */
757 if (!priv->txq) {
758 ret = iwlagn_txq_ctx_alloc(priv);
759 if (ret)
760 return ret;
761 } else
762 iwlagn_txq_ctx_reset(priv);
763
764 if (priv->cfg->base_params->shadow_reg_enable) {
765 /* enable shadow regs in HW */
766 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
767 0x800FFFFF);
768 }
769
770 set_bit(STATUS_INIT, &priv->status);
771
772 return 0;
773 }
774
775 /**
776 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
777 */
778 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
779 dma_addr_t dma_addr)
780 {
781 return cpu_to_le32((u32)(dma_addr >> 8));
782 }
783
784 /**
785 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
786 *
787 * If there are slots in the RX queue that need to be restocked,
788 * and we have free pre-allocated buffers, fill the ranks as much
789 * as we can, pulling from rx_free.
790 *
791 * This moves the 'write' index forward to catch up with 'processed', and
792 * also updates the memory address in the firmware to reference the new
793 * target buffer.
794 */
795 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
796 {
797 struct iwl_rx_queue *rxq = &priv->rxq;
798 struct list_head *element;
799 struct iwl_rx_mem_buffer *rxb;
800 unsigned long flags;
801
802 spin_lock_irqsave(&rxq->lock, flags);
803 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
804 /* The overwritten rxb must be a used one */
805 rxb = rxq->queue[rxq->write];
806 BUG_ON(rxb && rxb->page);
807
808 /* Get next free Rx buffer, remove from free list */
809 element = rxq->rx_free.next;
810 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
811 list_del(element);
812
813 /* Point to Rx buffer via next RBD in circular buffer */
814 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
815 rxb->page_dma);
816 rxq->queue[rxq->write] = rxb;
817 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
818 rxq->free_count--;
819 }
820 spin_unlock_irqrestore(&rxq->lock, flags);
821 /* If the pre-allocated buffer pool is dropping low, schedule to
822 * refill it */
823 if (rxq->free_count <= RX_LOW_WATERMARK)
824 queue_work(priv->workqueue, &priv->rx_replenish);
825
826
827 /* If we've added more space for the firmware to place data, tell it.
828 * Increment device's write pointer in multiples of 8. */
829 if (rxq->write_actual != (rxq->write & ~0x7)) {
830 spin_lock_irqsave(&rxq->lock, flags);
831 rxq->need_update = 1;
832 spin_unlock_irqrestore(&rxq->lock, flags);
833 iwl_rx_queue_update_write_ptr(priv, rxq);
834 }
835 }
836
837 /**
838 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
839 *
840 * When moving to rx_free an SKB is allocated for the slot.
841 *
842 * Also restock the Rx queue via iwl_rx_queue_restock.
843 * This is called as a scheduled work item (except for during initialization)
844 */
845 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
846 {
847 struct iwl_rx_queue *rxq = &priv->rxq;
848 struct list_head *element;
849 struct iwl_rx_mem_buffer *rxb;
850 struct page *page;
851 unsigned long flags;
852 gfp_t gfp_mask = priority;
853
854 while (1) {
855 spin_lock_irqsave(&rxq->lock, flags);
856 if (list_empty(&rxq->rx_used)) {
857 spin_unlock_irqrestore(&rxq->lock, flags);
858 return;
859 }
860 spin_unlock_irqrestore(&rxq->lock, flags);
861
862 if (rxq->free_count > RX_LOW_WATERMARK)
863 gfp_mask |= __GFP_NOWARN;
864
865 if (priv->hw_params.rx_page_order > 0)
866 gfp_mask |= __GFP_COMP;
867
868 /* Alloc a new receive buffer */
869 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
870 if (!page) {
871 if (net_ratelimit())
872 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
873 "order: %d\n",
874 priv->hw_params.rx_page_order);
875
876 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
877 net_ratelimit())
878 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
879 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
880 rxq->free_count);
881 /* We don't reschedule replenish work here -- we will
882 * call the restock method and if it still needs
883 * more buffers it will schedule replenish */
884 return;
885 }
886
887 spin_lock_irqsave(&rxq->lock, flags);
888
889 if (list_empty(&rxq->rx_used)) {
890 spin_unlock_irqrestore(&rxq->lock, flags);
891 __free_pages(page, priv->hw_params.rx_page_order);
892 return;
893 }
894 element = rxq->rx_used.next;
895 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
896 list_del(element);
897
898 spin_unlock_irqrestore(&rxq->lock, flags);
899
900 BUG_ON(rxb->page);
901 rxb->page = page;
902 /* Get physical address of the RB */
903 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
904 PAGE_SIZE << priv->hw_params.rx_page_order,
905 PCI_DMA_FROMDEVICE);
906 /* dma address must be no more than 36 bits */
907 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
908 /* and also 256 byte aligned! */
909 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
910
911 spin_lock_irqsave(&rxq->lock, flags);
912
913 list_add_tail(&rxb->list, &rxq->rx_free);
914 rxq->free_count++;
915 priv->alloc_rxb_page++;
916
917 spin_unlock_irqrestore(&rxq->lock, flags);
918 }
919 }
920
921 void iwlagn_rx_replenish(struct iwl_priv *priv)
922 {
923 unsigned long flags;
924
925 iwlagn_rx_allocate(priv, GFP_KERNEL);
926
927 spin_lock_irqsave(&priv->lock, flags);
928 iwlagn_rx_queue_restock(priv);
929 spin_unlock_irqrestore(&priv->lock, flags);
930 }
931
932 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
933 {
934 iwlagn_rx_allocate(priv, GFP_ATOMIC);
935
936 iwlagn_rx_queue_restock(priv);
937 }
938
939 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
940 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
941 * This free routine walks the list of POOL entries and if SKB is set to
942 * non NULL it is unmapped and freed
943 */
944 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
945 {
946 int i;
947 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
948 if (rxq->pool[i].page != NULL) {
949 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
950 PAGE_SIZE << priv->hw_params.rx_page_order,
951 PCI_DMA_FROMDEVICE);
952 __iwl_free_pages(priv, rxq->pool[i].page);
953 rxq->pool[i].page = NULL;
954 }
955 }
956
957 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
958 rxq->bd_dma);
959 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
960 rxq->rb_stts, rxq->rb_stts_dma);
961 rxq->bd = NULL;
962 rxq->rb_stts = NULL;
963 }
964
965 int iwlagn_rxq_stop(struct iwl_priv *priv)
966 {
967
968 /* stop Rx DMA */
969 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
970 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
971 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
972
973 return 0;
974 }
975
976 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
977 {
978 int idx = 0;
979 int band_offset = 0;
980
981 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
982 if (rate_n_flags & RATE_MCS_HT_MSK) {
983 idx = (rate_n_flags & 0xff);
984 return idx;
985 /* Legacy rate format, search for match in table */
986 } else {
987 if (band == IEEE80211_BAND_5GHZ)
988 band_offset = IWL_FIRST_OFDM_RATE;
989 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
990 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
991 return idx - band_offset;
992 }
993
994 return -1;
995 }
996
997 /* Calc max signal level (dBm) among 3 possible receivers */
998 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
999 struct iwl_rx_phy_res *rx_resp)
1000 {
1001 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
1002 }
1003
1004 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
1005 {
1006 u32 decrypt_out = 0;
1007
1008 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
1009 RX_RES_STATUS_STATION_FOUND)
1010 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
1011 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
1012
1013 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
1014
1015 /* packet was not encrypted */
1016 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1017 RX_RES_STATUS_SEC_TYPE_NONE)
1018 return decrypt_out;
1019
1020 /* packet was encrypted with unknown alg */
1021 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1022 RX_RES_STATUS_SEC_TYPE_ERR)
1023 return decrypt_out;
1024
1025 /* decryption was not done in HW */
1026 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
1027 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
1028 return decrypt_out;
1029
1030 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
1031
1032 case RX_RES_STATUS_SEC_TYPE_CCMP:
1033 /* alg is CCM: check MIC only */
1034 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1035 /* Bad MIC */
1036 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1037 else
1038 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1039
1040 break;
1041
1042 case RX_RES_STATUS_SEC_TYPE_TKIP:
1043 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1044 /* Bad TTAK */
1045 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1046 break;
1047 }
1048 /* fall through if TTAK OK */
1049 default:
1050 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1051 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1052 else
1053 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1054 break;
1055 }
1056
1057 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1058 decrypt_in, decrypt_out);
1059
1060 return decrypt_out;
1061 }
1062
1063 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1064 struct ieee80211_hdr *hdr,
1065 u16 len,
1066 u32 ampdu_status,
1067 struct iwl_rx_mem_buffer *rxb,
1068 struct ieee80211_rx_status *stats)
1069 {
1070 struct sk_buff *skb;
1071 __le16 fc = hdr->frame_control;
1072
1073 /* We only process data packets if the interface is open */
1074 if (unlikely(!priv->is_open)) {
1075 IWL_DEBUG_DROP_LIMIT(priv,
1076 "Dropping packet while interface is not open.\n");
1077 return;
1078 }
1079
1080 /* In case of HW accelerated crypto and bad decryption, drop */
1081 if (!priv->cfg->mod_params->sw_crypto &&
1082 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1083 return;
1084
1085 skb = dev_alloc_skb(128);
1086 if (!skb) {
1087 IWL_ERR(priv, "dev_alloc_skb failed\n");
1088 return;
1089 }
1090
1091 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1092
1093 iwl_update_stats(priv, false, fc, len);
1094 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1095
1096 ieee80211_rx(priv->hw, skb);
1097 priv->alloc_rxb_page--;
1098 rxb->page = NULL;
1099 }
1100
1101 /* Called for REPLY_RX (legacy ABG frames), or
1102 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1103 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1104 struct iwl_rx_mem_buffer *rxb)
1105 {
1106 struct ieee80211_hdr *header;
1107 struct ieee80211_rx_status rx_status;
1108 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1109 struct iwl_rx_phy_res *phy_res;
1110 __le32 rx_pkt_status;
1111 struct iwl_rx_mpdu_res_start *amsdu;
1112 u32 len;
1113 u32 ampdu_status;
1114 u32 rate_n_flags;
1115
1116 /**
1117 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1118 * REPLY_RX: physical layer info is in this buffer
1119 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1120 * command and cached in priv->last_phy_res
1121 *
1122 * Here we set up local variables depending on which command is
1123 * received.
1124 */
1125 if (pkt->hdr.cmd == REPLY_RX) {
1126 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1127 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1128 + phy_res->cfg_phy_cnt);
1129
1130 len = le16_to_cpu(phy_res->byte_count);
1131 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1132 phy_res->cfg_phy_cnt + len);
1133 ampdu_status = le32_to_cpu(rx_pkt_status);
1134 } else {
1135 if (!priv->_agn.last_phy_res_valid) {
1136 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1137 return;
1138 }
1139 phy_res = &priv->_agn.last_phy_res;
1140 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1141 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1142 len = le16_to_cpu(amsdu->byte_count);
1143 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1144 ampdu_status = iwlagn_translate_rx_status(priv,
1145 le32_to_cpu(rx_pkt_status));
1146 }
1147
1148 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1149 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1150 phy_res->cfg_phy_cnt);
1151 return;
1152 }
1153
1154 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1155 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1156 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1157 le32_to_cpu(rx_pkt_status));
1158 return;
1159 }
1160
1161 /* This will be used in several places later */
1162 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1163
1164 /* rx_status carries information about the packet to mac80211 */
1165 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1166 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1167 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1168 rx_status.freq =
1169 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
1170 rx_status.band);
1171 rx_status.rate_idx =
1172 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1173 rx_status.flag = 0;
1174
1175 /* TSF isn't reliable. In order to allow smooth user experience,
1176 * this W/A doesn't propagate it to the mac80211 */
1177 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU;*/
1178
1179 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1180
1181 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1182 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1183
1184 iwl_dbg_log_rx_data_frame(priv, len, header);
1185 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1186 rx_status.signal, (unsigned long long)rx_status.mactime);
1187
1188 /*
1189 * "antenna number"
1190 *
1191 * It seems that the antenna field in the phy flags value
1192 * is actually a bit field. This is undefined by radiotap,
1193 * it wants an actual antenna number but I always get "7"
1194 * for most legacy frames I receive indicating that the
1195 * same frame was received on all three RX chains.
1196 *
1197 * I think this field should be removed in favor of a
1198 * new 802.11n radiotap field "RX chains" that is defined
1199 * as a bitmask.
1200 */
1201 rx_status.antenna =
1202 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1203 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1204
1205 /* set the preamble flag if appropriate */
1206 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1207 rx_status.flag |= RX_FLAG_SHORTPRE;
1208
1209 /* Set up the HT phy flags */
1210 if (rate_n_flags & RATE_MCS_HT_MSK)
1211 rx_status.flag |= RX_FLAG_HT;
1212 if (rate_n_flags & RATE_MCS_HT40_MSK)
1213 rx_status.flag |= RX_FLAG_40MHZ;
1214 if (rate_n_flags & RATE_MCS_SGI_MSK)
1215 rx_status.flag |= RX_FLAG_SHORT_GI;
1216
1217 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1218 rxb, &rx_status);
1219 }
1220
1221 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1222 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1223 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1224 struct iwl_rx_mem_buffer *rxb)
1225 {
1226 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1227 priv->_agn.last_phy_res_valid = true;
1228 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1229 sizeof(struct iwl_rx_phy_res));
1230 }
1231
1232 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1233 struct ieee80211_vif *vif,
1234 enum ieee80211_band band,
1235 struct iwl_scan_channel *scan_ch)
1236 {
1237 const struct ieee80211_supported_band *sband;
1238 u16 passive_dwell = 0;
1239 u16 active_dwell = 0;
1240 int added = 0;
1241 u16 channel = 0;
1242
1243 sband = iwl_get_hw_mode(priv, band);
1244 if (!sband) {
1245 IWL_ERR(priv, "invalid band\n");
1246 return added;
1247 }
1248
1249 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1250 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1251
1252 if (passive_dwell <= active_dwell)
1253 passive_dwell = active_dwell + 1;
1254
1255 channel = iwl_get_single_channel_number(priv, band);
1256 if (channel) {
1257 scan_ch->channel = cpu_to_le16(channel);
1258 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1259 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1260 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1261 /* Set txpower levels to defaults */
1262 scan_ch->dsp_atten = 110;
1263 if (band == IEEE80211_BAND_5GHZ)
1264 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1265 else
1266 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1267 added++;
1268 } else
1269 IWL_ERR(priv, "no valid channel found\n");
1270 return added;
1271 }
1272
1273 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1274 struct ieee80211_vif *vif,
1275 enum ieee80211_band band,
1276 u8 is_active, u8 n_probes,
1277 struct iwl_scan_channel *scan_ch)
1278 {
1279 struct ieee80211_channel *chan;
1280 const struct ieee80211_supported_band *sband;
1281 const struct iwl_channel_info *ch_info;
1282 u16 passive_dwell = 0;
1283 u16 active_dwell = 0;
1284 int added, i;
1285 u16 channel;
1286
1287 sband = iwl_get_hw_mode(priv, band);
1288 if (!sband)
1289 return 0;
1290
1291 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1292 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1293
1294 if (passive_dwell <= active_dwell)
1295 passive_dwell = active_dwell + 1;
1296
1297 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1298 chan = priv->scan_request->channels[i];
1299
1300 if (chan->band != band)
1301 continue;
1302
1303 channel = chan->hw_value;
1304 scan_ch->channel = cpu_to_le16(channel);
1305
1306 ch_info = iwl_get_channel_info(priv, band, channel);
1307 if (!is_channel_valid(ch_info)) {
1308 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1309 channel);
1310 continue;
1311 }
1312
1313 if (!is_active || is_channel_passive(ch_info) ||
1314 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1315 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1316 else
1317 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1318
1319 if (n_probes)
1320 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1321
1322 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1323 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1324
1325 /* Set txpower levels to defaults */
1326 scan_ch->dsp_atten = 110;
1327
1328 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1329 * power level:
1330 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1331 */
1332 if (band == IEEE80211_BAND_5GHZ)
1333 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1334 else
1335 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1336
1337 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1338 channel, le32_to_cpu(scan_ch->type),
1339 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1340 "ACTIVE" : "PASSIVE",
1341 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1342 active_dwell : passive_dwell);
1343
1344 scan_ch++;
1345 added++;
1346 }
1347
1348 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1349 return added;
1350 }
1351
1352 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1353 {
1354 struct iwl_host_cmd cmd = {
1355 .id = REPLY_SCAN_CMD,
1356 .len = sizeof(struct iwl_scan_cmd),
1357 .flags = CMD_SIZE_HUGE,
1358 };
1359 struct iwl_scan_cmd *scan;
1360 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1361 u32 rate_flags = 0;
1362 u16 cmd_len;
1363 u16 rx_chain = 0;
1364 enum ieee80211_band band;
1365 u8 n_probes = 0;
1366 u8 rx_ant = priv->hw_params.valid_rx_ant;
1367 u8 rate;
1368 bool is_active = false;
1369 int chan_mod;
1370 u8 active_chains;
1371 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1372 int ret;
1373
1374 lockdep_assert_held(&priv->mutex);
1375
1376 if (vif)
1377 ctx = iwl_rxon_ctx_from_vif(vif);
1378
1379 if (!priv->scan_cmd) {
1380 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1381 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1382 if (!priv->scan_cmd) {
1383 IWL_DEBUG_SCAN(priv,
1384 "fail to allocate memory for scan\n");
1385 return -ENOMEM;
1386 }
1387 }
1388 scan = priv->scan_cmd;
1389 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1390
1391 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1392 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1393
1394 if (iwl_is_any_associated(priv)) {
1395 u16 interval = 0;
1396 u32 extra;
1397 u32 suspend_time = 100;
1398 u32 scan_suspend_time = 100;
1399
1400 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1401 if (priv->is_internal_short_scan)
1402 interval = 0;
1403 else
1404 interval = vif->bss_conf.beacon_int;
1405
1406 scan->suspend_time = 0;
1407 scan->max_out_time = cpu_to_le32(200 * 1024);
1408 if (!interval)
1409 interval = suspend_time;
1410
1411 extra = (suspend_time / interval) << 22;
1412 scan_suspend_time = (extra |
1413 ((suspend_time % interval) * 1024));
1414 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1415 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1416 scan_suspend_time, interval);
1417 }
1418
1419 if (priv->is_internal_short_scan) {
1420 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1421 } else if (priv->scan_request->n_ssids) {
1422 int i, p = 0;
1423 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1424 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1425 /* always does wildcard anyway */
1426 if (!priv->scan_request->ssids[i].ssid_len)
1427 continue;
1428 scan->direct_scan[p].id = WLAN_EID_SSID;
1429 scan->direct_scan[p].len =
1430 priv->scan_request->ssids[i].ssid_len;
1431 memcpy(scan->direct_scan[p].ssid,
1432 priv->scan_request->ssids[i].ssid,
1433 priv->scan_request->ssids[i].ssid_len);
1434 n_probes++;
1435 p++;
1436 }
1437 is_active = true;
1438 } else
1439 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1440
1441 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1442 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1443 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1444
1445 switch (priv->scan_band) {
1446 case IEEE80211_BAND_2GHZ:
1447 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1448 chan_mod = le32_to_cpu(
1449 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1450 RXON_FLG_CHANNEL_MODE_MSK)
1451 >> RXON_FLG_CHANNEL_MODE_POS;
1452 if (chan_mod == CHANNEL_MODE_PURE_40) {
1453 rate = IWL_RATE_6M_PLCP;
1454 } else {
1455 rate = IWL_RATE_1M_PLCP;
1456 rate_flags = RATE_MCS_CCK_MSK;
1457 }
1458 /*
1459 * Internal scans are passive, so we can indiscriminately set
1460 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1461 */
1462 if (priv->cfg->bt_params &&
1463 priv->cfg->bt_params->advanced_bt_coexist)
1464 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1465 break;
1466 case IEEE80211_BAND_5GHZ:
1467 rate = IWL_RATE_6M_PLCP;
1468 break;
1469 default:
1470 IWL_WARN(priv, "Invalid scan band\n");
1471 return -EIO;
1472 }
1473
1474 /*
1475 * If active scanning is requested but a certain channel is
1476 * marked passive, we can do active scanning if we detect
1477 * transmissions.
1478 *
1479 * There is an issue with some firmware versions that triggers
1480 * a sysassert on a "good CRC threshold" of zero (== disabled),
1481 * on a radar channel even though this means that we should NOT
1482 * send probes.
1483 *
1484 * The "good CRC threshold" is the number of frames that we
1485 * need to receive during our dwell time on a channel before
1486 * sending out probes -- setting this to a huge value will
1487 * mean we never reach it, but at the same time work around
1488 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1489 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1490 */
1491 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1492 IWL_GOOD_CRC_TH_NEVER;
1493
1494 band = priv->scan_band;
1495
1496 if (priv->cfg->scan_rx_antennas[band])
1497 rx_ant = priv->cfg->scan_rx_antennas[band];
1498
1499 if (band == IEEE80211_BAND_2GHZ &&
1500 priv->cfg->bt_params &&
1501 priv->cfg->bt_params->advanced_bt_coexist) {
1502 /* transmit 2.4 GHz probes only on first antenna */
1503 scan_tx_antennas = first_antenna(scan_tx_antennas);
1504 }
1505
1506 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1507 scan_tx_antennas);
1508 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1509 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1510
1511 /* In power save mode use one chain, otherwise use all chains */
1512 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1513 /* rx_ant has been set to all valid chains previously */
1514 active_chains = rx_ant &
1515 ((u8)(priv->chain_noise_data.active_chains));
1516 if (!active_chains)
1517 active_chains = rx_ant;
1518
1519 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1520 priv->chain_noise_data.active_chains);
1521
1522 rx_ant = first_antenna(active_chains);
1523 }
1524 if (priv->cfg->bt_params &&
1525 priv->cfg->bt_params->advanced_bt_coexist &&
1526 priv->bt_full_concurrent) {
1527 /* operated as 1x1 in full concurrency mode */
1528 rx_ant = first_antenna(rx_ant);
1529 }
1530
1531 /* MIMO is not used here, but value is required */
1532 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1533 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1534 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1535 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1536 scan->rx_chain = cpu_to_le16(rx_chain);
1537 if (!priv->is_internal_short_scan) {
1538 cmd_len = iwl_fill_probe_req(priv,
1539 (struct ieee80211_mgmt *)scan->data,
1540 vif->addr,
1541 priv->scan_request->ie,
1542 priv->scan_request->ie_len,
1543 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1544 } else {
1545 /* use bcast addr, will not be transmitted but must be valid */
1546 cmd_len = iwl_fill_probe_req(priv,
1547 (struct ieee80211_mgmt *)scan->data,
1548 iwl_bcast_addr, NULL, 0,
1549 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1550
1551 }
1552 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1553
1554 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1555 RXON_FILTER_BCON_AWARE_MSK);
1556
1557 if (priv->is_internal_short_scan) {
1558 scan->channel_count =
1559 iwl_get_single_channel_for_scan(priv, vif, band,
1560 (void *)&scan->data[le16_to_cpu(
1561 scan->tx_cmd.len)]);
1562 } else {
1563 scan->channel_count =
1564 iwl_get_channels_for_scan(priv, vif, band,
1565 is_active, n_probes,
1566 (void *)&scan->data[le16_to_cpu(
1567 scan->tx_cmd.len)]);
1568 }
1569 if (scan->channel_count == 0) {
1570 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1571 return -EIO;
1572 }
1573
1574 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1575 scan->channel_count * sizeof(struct iwl_scan_channel);
1576 cmd.data = scan;
1577 scan->len = cpu_to_le16(cmd.len);
1578
1579 /* set scan bit here for PAN params */
1580 set_bit(STATUS_SCAN_HW, &priv->status);
1581
1582 if (priv->cfg->ops->hcmd->set_pan_params) {
1583 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1584 if (ret)
1585 return ret;
1586 }
1587
1588 ret = iwl_send_cmd_sync(priv, &cmd);
1589 if (ret) {
1590 clear_bit(STATUS_SCAN_HW, &priv->status);
1591 if (priv->cfg->ops->hcmd->set_pan_params)
1592 priv->cfg->ops->hcmd->set_pan_params(priv);
1593 }
1594
1595 return ret;
1596 }
1597
1598 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1599 struct ieee80211_vif *vif, bool add)
1600 {
1601 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1602
1603 if (add)
1604 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1605 vif->bss_conf.bssid,
1606 &vif_priv->ibss_bssid_sta_id);
1607 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1608 vif->bss_conf.bssid);
1609 }
1610
1611 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1612 int sta_id, int tid, int freed)
1613 {
1614 lockdep_assert_held(&priv->sta_lock);
1615
1616 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1617 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1618 else {
1619 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1620 priv->stations[sta_id].tid[tid].tfds_in_queue,
1621 freed);
1622 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1623 }
1624 }
1625
1626 #define IWL_FLUSH_WAIT_MS 2000
1627
1628 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1629 {
1630 struct iwl_tx_queue *txq;
1631 struct iwl_queue *q;
1632 int cnt;
1633 unsigned long now = jiffies;
1634 int ret = 0;
1635
1636 /* waiting for all the tx frames complete might take a while */
1637 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1638 if (cnt == priv->cmd_queue)
1639 continue;
1640 txq = &priv->txq[cnt];
1641 q = &txq->q;
1642 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1643 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1644 msleep(1);
1645
1646 if (q->read_ptr != q->write_ptr) {
1647 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1648 ret = -ETIMEDOUT;
1649 break;
1650 }
1651 }
1652 return ret;
1653 }
1654
1655 #define IWL_TX_QUEUE_MSK 0xfffff
1656
1657 /**
1658 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1659 *
1660 * pre-requirements:
1661 * 1. acquire mutex before calling
1662 * 2. make sure rf is on and not in exit state
1663 */
1664 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1665 {
1666 struct iwl_txfifo_flush_cmd flush_cmd;
1667 struct iwl_host_cmd cmd = {
1668 .id = REPLY_TXFIFO_FLUSH,
1669 .len = sizeof(struct iwl_txfifo_flush_cmd),
1670 .flags = CMD_SYNC,
1671 .data = &flush_cmd,
1672 };
1673
1674 might_sleep();
1675
1676 memset(&flush_cmd, 0, sizeof(flush_cmd));
1677 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1678 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1679 if (priv->cfg->sku & IWL_SKU_N)
1680 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1681
1682 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1683 flush_cmd.fifo_control);
1684 flush_cmd.flush_control = cpu_to_le16(flush_control);
1685
1686 return iwl_send_cmd(priv, &cmd);
1687 }
1688
1689 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1690 {
1691 mutex_lock(&priv->mutex);
1692 ieee80211_stop_queues(priv->hw);
1693 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1694 IWL_ERR(priv, "flush request fail\n");
1695 goto done;
1696 }
1697 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1698 iwlagn_wait_tx_queue_empty(priv);
1699 done:
1700 ieee80211_wake_queues(priv->hw);
1701 mutex_unlock(&priv->mutex);
1702 }
1703
1704 /*
1705 * BT coex
1706 */
1707 /*
1708 * Macros to access the lookup table.
1709 *
1710 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1711 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1712 *
1713 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1714 *
1715 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1716 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1717 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1718 *
1719 * These macros encode that format.
1720 */
1721 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1722 wifi_txrx, wifi_sh_ant_req) \
1723 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1724 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1725
1726 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1727 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1728 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1729 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1730 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1731 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1732 wifi_sh_ant_req))))
1733 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1734 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1735 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1736 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1737 wifi_sh_ant_req))
1738 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1739 wifi_req, wifi_prio, wifi_txrx, \
1740 wifi_sh_ant_req) \
1741 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1742 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1743 wifi_sh_ant_req))
1744
1745 #define LUT_WLAN_KILL_OP(lut, op, val) \
1746 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1747 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1748 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1749 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1750 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1751 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1752 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1753 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1754 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1755 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1756 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1757 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1758 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1759
1760 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1761 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1762 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1763 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1764 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1765 wifi_req, wifi_prio, wifi_txrx, \
1766 wifi_sh_ant_req))))
1767 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1768 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1769 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1770 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1771 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1772 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1773 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1774 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1775
1776 static const __le32 iwlagn_def_3w_lookup[12] = {
1777 cpu_to_le32(0xaaaaaaaa),
1778 cpu_to_le32(0xaaaaaaaa),
1779 cpu_to_le32(0xaeaaaaaa),
1780 cpu_to_le32(0xaaaaaaaa),
1781 cpu_to_le32(0xcc00ff28),
1782 cpu_to_le32(0x0000aaaa),
1783 cpu_to_le32(0xcc00aaaa),
1784 cpu_to_le32(0x0000aaaa),
1785 cpu_to_le32(0xc0004000),
1786 cpu_to_le32(0x00004000),
1787 cpu_to_le32(0xf0005000),
1788 cpu_to_le32(0xf0005000),
1789 };
1790
1791 static const __le32 iwlagn_concurrent_lookup[12] = {
1792 cpu_to_le32(0xaaaaaaaa),
1793 cpu_to_le32(0xaaaaaaaa),
1794 cpu_to_le32(0xaaaaaaaa),
1795 cpu_to_le32(0xaaaaaaaa),
1796 cpu_to_le32(0xaaaaaaaa),
1797 cpu_to_le32(0xaaaaaaaa),
1798 cpu_to_le32(0xaaaaaaaa),
1799 cpu_to_le32(0xaaaaaaaa),
1800 cpu_to_le32(0x00000000),
1801 cpu_to_le32(0x00000000),
1802 cpu_to_le32(0x00000000),
1803 cpu_to_le32(0x00000000),
1804 };
1805
1806 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1807 {
1808 struct iwl_basic_bt_cmd basic = {
1809 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1810 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1811 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1812 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1813 };
1814 struct iwl6000_bt_cmd bt_cmd_6000;
1815 struct iwl2000_bt_cmd bt_cmd_2000;
1816 int ret;
1817
1818 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1819 sizeof(basic.bt3_lookup_table));
1820
1821 if (priv->cfg->bt_params) {
1822 if (priv->cfg->bt_params->bt_session_2) {
1823 bt_cmd_2000.prio_boost = cpu_to_le32(
1824 priv->cfg->bt_params->bt_prio_boost);
1825 bt_cmd_2000.tx_prio_boost = 0;
1826 bt_cmd_2000.rx_prio_boost = 0;
1827 } else {
1828 bt_cmd_6000.prio_boost =
1829 priv->cfg->bt_params->bt_prio_boost;
1830 bt_cmd_6000.tx_prio_boost = 0;
1831 bt_cmd_6000.rx_prio_boost = 0;
1832 }
1833 } else {
1834 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1835 return;
1836 }
1837
1838 basic.kill_ack_mask = priv->kill_ack_mask;
1839 basic.kill_cts_mask = priv->kill_cts_mask;
1840 basic.valid = priv->bt_valid;
1841
1842 /*
1843 * Configure BT coex mode to "no coexistence" when the
1844 * user disabled BT coexistence, we have no interface
1845 * (might be in monitor mode), or the interface is in
1846 * IBSS mode (no proper uCode support for coex then).
1847 */
1848 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1849 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1850 } else {
1851 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1852 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1853 if (priv->cfg->bt_params &&
1854 priv->cfg->bt_params->bt_sco_disable)
1855 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1856
1857 if (priv->bt_ch_announce)
1858 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1859 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags);
1860 }
1861 priv->bt_enable_flag = basic.flags;
1862 if (priv->bt_full_concurrent)
1863 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1864 sizeof(iwlagn_concurrent_lookup));
1865 else
1866 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1867 sizeof(iwlagn_def_3w_lookup));
1868
1869 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1870 basic.flags ? "active" : "disabled",
1871 priv->bt_full_concurrent ?
1872 "full concurrency" : "3-wire");
1873
1874 if (priv->cfg->bt_params->bt_session_2) {
1875 memcpy(&bt_cmd_2000.basic, &basic,
1876 sizeof(basic));
1877 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1878 sizeof(bt_cmd_2000), &bt_cmd_2000);
1879 } else {
1880 memcpy(&bt_cmd_6000.basic, &basic,
1881 sizeof(basic));
1882 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1883 sizeof(bt_cmd_6000), &bt_cmd_6000);
1884 }
1885 if (ret)
1886 IWL_ERR(priv, "failed to send BT Coex Config\n");
1887
1888 }
1889
1890 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1891 {
1892 struct iwl_priv *priv =
1893 container_of(work, struct iwl_priv, bt_traffic_change_work);
1894 struct iwl_rxon_context *ctx;
1895 int smps_request = -1;
1896
1897 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1898 /* bt coex disabled */
1899 return;
1900 }
1901
1902 /*
1903 * Note: bt_traffic_load can be overridden by scan complete and
1904 * coex profile notifications. Ignore that since only bad consequence
1905 * can be not matching debug print with actual state.
1906 */
1907 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1908 priv->bt_traffic_load);
1909
1910 switch (priv->bt_traffic_load) {
1911 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1912 if (priv->bt_status)
1913 smps_request = IEEE80211_SMPS_DYNAMIC;
1914 else
1915 smps_request = IEEE80211_SMPS_AUTOMATIC;
1916 break;
1917 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1918 smps_request = IEEE80211_SMPS_DYNAMIC;
1919 break;
1920 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1921 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1922 smps_request = IEEE80211_SMPS_STATIC;
1923 break;
1924 default:
1925 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1926 priv->bt_traffic_load);
1927 break;
1928 }
1929
1930 mutex_lock(&priv->mutex);
1931
1932 /*
1933 * We can not send command to firmware while scanning. When the scan
1934 * complete we will schedule this work again. We do check with mutex
1935 * locked to prevent new scan request to arrive. We do not check
1936 * STATUS_SCANNING to avoid race when queue_work two times from
1937 * different notifications, but quit and not perform any work at all.
1938 */
1939 if (test_bit(STATUS_SCAN_HW, &priv->status))
1940 goto out;
1941
1942 if (priv->cfg->ops->lib->update_chain_flags)
1943 priv->cfg->ops->lib->update_chain_flags(priv);
1944
1945 if (smps_request != -1) {
1946 for_each_context(priv, ctx) {
1947 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1948 ieee80211_request_smps(ctx->vif, smps_request);
1949 }
1950 }
1951 out:
1952 mutex_unlock(&priv->mutex);
1953 }
1954
1955 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1956 struct iwl_bt_uart_msg *uart_msg)
1957 {
1958 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1959 "Update Req = 0x%X",
1960 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1961 BT_UART_MSG_FRAME1MSGTYPE_POS,
1962 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1963 BT_UART_MSG_FRAME1SSN_POS,
1964 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1965 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1966
1967 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1968 "Chl_SeqN = 0x%X, In band = 0x%X",
1969 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1970 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1971 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1972 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1973 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1974 BT_UART_MSG_FRAME2CHLSEQN_POS,
1975 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1976 BT_UART_MSG_FRAME2INBAND_POS);
1977
1978 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1979 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1980 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1981 BT_UART_MSG_FRAME3SCOESCO_POS,
1982 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1983 BT_UART_MSG_FRAME3SNIFF_POS,
1984 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1985 BT_UART_MSG_FRAME3A2DP_POS,
1986 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1987 BT_UART_MSG_FRAME3ACL_POS,
1988 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1989 BT_UART_MSG_FRAME3MASTER_POS,
1990 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1991 BT_UART_MSG_FRAME3OBEX_POS);
1992
1993 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1994 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1995 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1996
1997 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1998 "eSCO Retransmissions = 0x%X",
1999 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
2000 BT_UART_MSG_FRAME5TXACTIVITY_POS,
2001 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
2002 BT_UART_MSG_FRAME5RXACTIVITY_POS,
2003 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
2004 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
2005
2006 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
2007 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
2008 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
2009 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
2010 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
2011
2012 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = "
2013 "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
2014 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
2015 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
2016 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
2017 BT_UART_MSG_FRAME7PAGE_POS,
2018 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
2019 BT_UART_MSG_FRAME7INQUIRY_POS,
2020 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
2021 BT_UART_MSG_FRAME7CONNECTABLE_POS);
2022 }
2023
2024 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
2025 struct iwl_bt_uart_msg *uart_msg)
2026 {
2027 u8 kill_msk;
2028 static const __le32 bt_kill_ack_msg[2] = {
2029 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
2030 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2031 static const __le32 bt_kill_cts_msg[2] = {
2032 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
2033 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2034
2035 kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
2036 ? 1 : 0;
2037 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
2038 priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
2039 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
2040 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
2041 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
2042 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
2043
2044 /* schedule to send runtime bt_config */
2045 queue_work(priv->workqueue, &priv->bt_runtime_config);
2046 }
2047 }
2048
2049 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
2050 struct iwl_rx_mem_buffer *rxb)
2051 {
2052 unsigned long flags;
2053 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2054 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
2055 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
2056
2057 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
2058 /* bt coex disabled */
2059 return;
2060 }
2061
2062 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
2063 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
2064 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
2065 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
2066 coex->bt_ci_compliance);
2067 iwlagn_print_uartmsg(priv, uart_msg);
2068
2069 priv->last_bt_traffic_load = priv->bt_traffic_load;
2070 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2071 if (priv->bt_status != coex->bt_status ||
2072 priv->last_bt_traffic_load != coex->bt_traffic_load) {
2073 if (coex->bt_status) {
2074 /* BT on */
2075 if (!priv->bt_ch_announce)
2076 priv->bt_traffic_load =
2077 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2078 else
2079 priv->bt_traffic_load =
2080 coex->bt_traffic_load;
2081 } else {
2082 /* BT off */
2083 priv->bt_traffic_load =
2084 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2085 }
2086 priv->bt_status = coex->bt_status;
2087 queue_work(priv->workqueue,
2088 &priv->bt_traffic_change_work);
2089 }
2090 }
2091
2092 iwlagn_set_kill_msk(priv, uart_msg);
2093
2094 /* FIXME: based on notification, adjust the prio_boost */
2095
2096 spin_lock_irqsave(&priv->lock, flags);
2097 priv->bt_ci_compliance = coex->bt_ci_compliance;
2098 spin_unlock_irqrestore(&priv->lock, flags);
2099 }
2100
2101 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2102 {
2103 iwlagn_rx_handler_setup(priv);
2104 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2105 iwlagn_bt_coex_profile_notif;
2106 }
2107
2108 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2109 {
2110 iwlagn_setup_deferred_work(priv);
2111
2112 INIT_WORK(&priv->bt_traffic_change_work,
2113 iwlagn_bt_traffic_change_work);
2114 }
2115
2116 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2117 {
2118 cancel_work_sync(&priv->bt_traffic_change_work);
2119 }
2120
2121 static bool is_single_rx_stream(struct iwl_priv *priv)
2122 {
2123 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
2124 priv->current_ht_config.single_chain_sufficient;
2125 }
2126
2127 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
2128 #define IWL_NUM_RX_CHAINS_SINGLE 2
2129 #define IWL_NUM_IDLE_CHAINS_DUAL 2
2130 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
2131
2132 /*
2133 * Determine how many receiver/antenna chains to use.
2134 *
2135 * More provides better reception via diversity. Fewer saves power
2136 * at the expense of throughput, but only when not in powersave to
2137 * start with.
2138 *
2139 * MIMO (dual stream) requires at least 2, but works better with 3.
2140 * This does not determine *which* chains to use, just how many.
2141 */
2142 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2143 {
2144 if (priv->cfg->bt_params &&
2145 priv->cfg->bt_params->advanced_bt_coexist &&
2146 (priv->bt_full_concurrent ||
2147 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2148 /*
2149 * only use chain 'A' in bt high traffic load or
2150 * full concurrency mode
2151 */
2152 return IWL_NUM_RX_CHAINS_SINGLE;
2153 }
2154 /* # of Rx chains to use when expecting MIMO. */
2155 if (is_single_rx_stream(priv))
2156 return IWL_NUM_RX_CHAINS_SINGLE;
2157 else
2158 return IWL_NUM_RX_CHAINS_MULTIPLE;
2159 }
2160
2161 /*
2162 * When we are in power saving mode, unless device support spatial
2163 * multiplexing power save, use the active count for rx chain count.
2164 */
2165 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2166 {
2167 /* # Rx chains when idling, depending on SMPS mode */
2168 switch (priv->current_ht_config.smps) {
2169 case IEEE80211_SMPS_STATIC:
2170 case IEEE80211_SMPS_DYNAMIC:
2171 return IWL_NUM_IDLE_CHAINS_SINGLE;
2172 case IEEE80211_SMPS_OFF:
2173 return active_cnt;
2174 default:
2175 WARN(1, "invalid SMPS mode %d",
2176 priv->current_ht_config.smps);
2177 return active_cnt;
2178 }
2179 }
2180
2181 /* up to 4 chains */
2182 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2183 {
2184 u8 res;
2185 res = (chain_bitmap & BIT(0)) >> 0;
2186 res += (chain_bitmap & BIT(1)) >> 1;
2187 res += (chain_bitmap & BIT(2)) >> 2;
2188 res += (chain_bitmap & BIT(3)) >> 3;
2189 return res;
2190 }
2191
2192 /**
2193 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2194 *
2195 * Selects how many and which Rx receivers/antennas/chains to use.
2196 * This should not be used for scan command ... it puts data in wrong place.
2197 */
2198 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2199 {
2200 bool is_single = is_single_rx_stream(priv);
2201 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2202 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2203 u32 active_chains;
2204 u16 rx_chain;
2205
2206 /* Tell uCode which antennas are actually connected.
2207 * Before first association, we assume all antennas are connected.
2208 * Just after first association, iwl_chain_noise_calibration()
2209 * checks which antennas actually *are* connected. */
2210 if (priv->chain_noise_data.active_chains)
2211 active_chains = priv->chain_noise_data.active_chains;
2212 else
2213 active_chains = priv->hw_params.valid_rx_ant;
2214
2215 if (priv->cfg->bt_params &&
2216 priv->cfg->bt_params->advanced_bt_coexist &&
2217 (priv->bt_full_concurrent ||
2218 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2219 /*
2220 * only use chain 'A' in bt high traffic load or
2221 * full concurrency mode
2222 */
2223 active_chains = first_antenna(active_chains);
2224 }
2225
2226 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2227
2228 /* How many receivers should we use? */
2229 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2230 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2231
2232
2233 /* correct rx chain count according hw settings
2234 * and chain noise calibration
2235 */
2236 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2237 if (valid_rx_cnt < active_rx_cnt)
2238 active_rx_cnt = valid_rx_cnt;
2239
2240 if (valid_rx_cnt < idle_rx_cnt)
2241 idle_rx_cnt = valid_rx_cnt;
2242
2243 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2244 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2245
2246 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2247
2248 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2249 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2250 else
2251 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2252
2253 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2254 ctx->staging.rx_chain,
2255 active_rx_cnt, idle_rx_cnt);
2256
2257 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2258 active_rx_cnt < idle_rx_cnt);
2259 }
2260
2261 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2262 {
2263 int i;
2264 u8 ind = ant;
2265
2266 if (priv->band == IEEE80211_BAND_2GHZ &&
2267 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2268 return 0;
2269
2270 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2271 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2272 if (valid & BIT(ind))
2273 return ind;
2274 }
2275 return ant;
2276 }
2277
2278 static const char *get_csr_string(int cmd)
2279 {
2280 switch (cmd) {
2281 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2282 IWL_CMD(CSR_INT_COALESCING);
2283 IWL_CMD(CSR_INT);
2284 IWL_CMD(CSR_INT_MASK);
2285 IWL_CMD(CSR_FH_INT_STATUS);
2286 IWL_CMD(CSR_GPIO_IN);
2287 IWL_CMD(CSR_RESET);
2288 IWL_CMD(CSR_GP_CNTRL);
2289 IWL_CMD(CSR_HW_REV);
2290 IWL_CMD(CSR_EEPROM_REG);
2291 IWL_CMD(CSR_EEPROM_GP);
2292 IWL_CMD(CSR_OTP_GP_REG);
2293 IWL_CMD(CSR_GIO_REG);
2294 IWL_CMD(CSR_GP_UCODE_REG);
2295 IWL_CMD(CSR_GP_DRIVER_REG);
2296 IWL_CMD(CSR_UCODE_DRV_GP1);
2297 IWL_CMD(CSR_UCODE_DRV_GP2);
2298 IWL_CMD(CSR_LED_REG);
2299 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2300 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2301 IWL_CMD(CSR_ANA_PLL_CFG);
2302 IWL_CMD(CSR_HW_REV_WA_REG);
2303 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2304 default:
2305 return "UNKNOWN";
2306 }
2307 }
2308
2309 void iwl_dump_csr(struct iwl_priv *priv)
2310 {
2311 int i;
2312 static const u32 csr_tbl[] = {
2313 CSR_HW_IF_CONFIG_REG,
2314 CSR_INT_COALESCING,
2315 CSR_INT,
2316 CSR_INT_MASK,
2317 CSR_FH_INT_STATUS,
2318 CSR_GPIO_IN,
2319 CSR_RESET,
2320 CSR_GP_CNTRL,
2321 CSR_HW_REV,
2322 CSR_EEPROM_REG,
2323 CSR_EEPROM_GP,
2324 CSR_OTP_GP_REG,
2325 CSR_GIO_REG,
2326 CSR_GP_UCODE_REG,
2327 CSR_GP_DRIVER_REG,
2328 CSR_UCODE_DRV_GP1,
2329 CSR_UCODE_DRV_GP2,
2330 CSR_LED_REG,
2331 CSR_DRAM_INT_TBL_REG,
2332 CSR_GIO_CHICKEN_BITS,
2333 CSR_ANA_PLL_CFG,
2334 CSR_HW_REV_WA_REG,
2335 CSR_DBG_HPET_MEM_REG
2336 };
2337 IWL_ERR(priv, "CSR values:\n");
2338 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2339 "CSR_INT_PERIODIC_REG)\n");
2340 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2341 IWL_ERR(priv, " %25s: 0X%08x\n",
2342 get_csr_string(csr_tbl[i]),
2343 iwl_read32(priv, csr_tbl[i]));
2344 }
2345 }
2346
2347 static const char *get_fh_string(int cmd)
2348 {
2349 switch (cmd) {
2350 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2351 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2352 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2353 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2354 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2355 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2356 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2357 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2358 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2359 default:
2360 return "UNKNOWN";
2361 }
2362 }
2363
2364 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2365 {
2366 int i;
2367 #ifdef CONFIG_IWLWIFI_DEBUG
2368 int pos = 0;
2369 size_t bufsz = 0;
2370 #endif
2371 static const u32 fh_tbl[] = {
2372 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2373 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2374 FH_RSCSR_CHNL0_WPTR,
2375 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2376 FH_MEM_RSSR_SHARED_CTRL_REG,
2377 FH_MEM_RSSR_RX_STATUS_REG,
2378 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2379 FH_TSSR_TX_STATUS_REG,
2380 FH_TSSR_TX_ERROR_REG
2381 };
2382 #ifdef CONFIG_IWLWIFI_DEBUG
2383 if (display) {
2384 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2385 *buf = kmalloc(bufsz, GFP_KERNEL);
2386 if (!*buf)
2387 return -ENOMEM;
2388 pos += scnprintf(*buf + pos, bufsz - pos,
2389 "FH register values:\n");
2390 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2391 pos += scnprintf(*buf + pos, bufsz - pos,
2392 " %34s: 0X%08x\n",
2393 get_fh_string(fh_tbl[i]),
2394 iwl_read_direct32(priv, fh_tbl[i]));
2395 }
2396 return pos;
2397 }
2398 #endif
2399 IWL_ERR(priv, "FH register values:\n");
2400 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2401 IWL_ERR(priv, " %34s: 0X%08x\n",
2402 get_fh_string(fh_tbl[i]),
2403 iwl_read_direct32(priv, fh_tbl[i]));
2404 }
2405 return 0;
2406 }
2407
2408 /* notification wait support */
2409 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2410 struct iwl_notification_wait *wait_entry,
2411 void (*fn)(struct iwl_priv *priv,
2412 struct iwl_rx_packet *pkt),
2413 u8 cmd)
2414 {
2415 wait_entry->fn = fn;
2416 wait_entry->cmd = cmd;
2417 wait_entry->triggered = false;
2418
2419 spin_lock_bh(&priv->_agn.notif_wait_lock);
2420 list_add(&wait_entry->list, &priv->_agn.notif_waits);
2421 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2422 }
2423
2424 signed long iwlagn_wait_notification(struct iwl_priv *priv,
2425 struct iwl_notification_wait *wait_entry,
2426 unsigned long timeout)
2427 {
2428 int ret;
2429
2430 ret = wait_event_timeout(priv->_agn.notif_waitq,
2431 &wait_entry->triggered,
2432 timeout);
2433
2434 spin_lock_bh(&priv->_agn.notif_wait_lock);
2435 list_del(&wait_entry->list);
2436 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2437
2438 return ret;
2439 }
2440
2441 void iwlagn_remove_notification(struct iwl_priv *priv,
2442 struct iwl_notification_wait *wait_entry)
2443 {
2444 spin_lock_bh(&priv->_agn.notif_wait_lock);
2445 list_del(&wait_entry->list);
2446 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2447 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree