1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
28 #include "rtsx_transport.h"
29 #include "rtsx_scsi.h"
30 #include "rtsx_card.h"
33 #define SD_MAX_RETRY_COUNT 3
35 static u16 REG_SD_CFG1
;
36 static u16 REG_SD_CFG2
;
37 static u16 REG_SD_CFG3
;
38 static u16 REG_SD_STAT1
;
39 static u16 REG_SD_STAT2
;
40 static u16 REG_SD_BUS_STAT
;
41 static u16 REG_SD_PAD_CTL
;
42 static u16 REG_SD_SAMPLE_POINT_CTL
;
43 static u16 REG_SD_PUSH_POINT_CTL
;
44 static u16 REG_SD_CMD0
;
45 static u16 REG_SD_CMD1
;
46 static u16 REG_SD_CMD2
;
47 static u16 REG_SD_CMD3
;
48 static u16 REG_SD_CMD4
;
49 static u16 REG_SD_CMD5
;
50 static u16 REG_SD_BYTE_CNT_L
;
51 static u16 REG_SD_BYTE_CNT_H
;
52 static u16 REG_SD_BLOCK_CNT_L
;
53 static u16 REG_SD_BLOCK_CNT_H
;
54 static u16 REG_SD_TRANSFER
;
55 static u16 REG_SD_VPCLK0_CTL
;
56 static u16 REG_SD_VPCLK1_CTL
;
57 static u16 REG_SD_DCMPS0_CTL
;
58 static u16 REG_SD_DCMPS1_CTL
;
60 static inline void sd_set_err_code(struct rtsx_chip
*chip
, u8 err_code
)
62 struct sd_info
*sd_card
= &(chip
->sd_card
);
64 sd_card
->err_code
|= err_code
;
67 static inline void sd_clr_err_code(struct rtsx_chip
*chip
)
69 struct sd_info
*sd_card
= &(chip
->sd_card
);
71 sd_card
->err_code
= 0;
74 static inline int sd_check_err_code(struct rtsx_chip
*chip
, u8 err_code
)
76 struct sd_info
*sd_card
= &(chip
->sd_card
);
78 return sd_card
->err_code
& err_code
;
81 static void sd_init_reg_addr(struct rtsx_chip
*chip
)
83 if (CHECK_PID(chip
, 0x5209)) {
84 REG_SD_CFG1
= SD_CFG1
;
85 REG_SD_CFG2
= SD_CFG2
;
86 REG_SD_CFG3
= SD_CFG3
;
87 REG_SD_STAT1
= SD_STAT1
;
88 REG_SD_STAT2
= SD_STAT2
;
89 REG_SD_BUS_STAT
= SD_BUS_STAT
;
90 REG_SD_PAD_CTL
= SD_PAD_CTL
;
91 REG_SD_SAMPLE_POINT_CTL
= SD_SAMPLE_POINT_CTL
;
92 REG_SD_PUSH_POINT_CTL
= SD_PUSH_POINT_CTL
;
93 REG_SD_CMD0
= SD_CMD0
;
94 REG_SD_CMD1
= SD_CMD1
;
95 REG_SD_CMD2
= SD_CMD2
;
96 REG_SD_CMD3
= SD_CMD3
;
97 REG_SD_CMD4
= SD_CMD4
;
98 REG_SD_CMD5
= SD_CMD5
;
99 REG_SD_BYTE_CNT_L
= SD_BYTE_CNT_L
;
100 REG_SD_BYTE_CNT_H
= SD_BYTE_CNT_H
;
101 REG_SD_BLOCK_CNT_L
= SD_BLOCK_CNT_L
;
102 REG_SD_BLOCK_CNT_H
= SD_BLOCK_CNT_H
;
103 REG_SD_TRANSFER
= SD_TRANSFER
;
104 REG_SD_VPCLK0_CTL
= SD_VPCLK0_CTL
;
105 REG_SD_VPCLK1_CTL
= SD_VPCLK1_CTL
;
106 REG_SD_DCMPS0_CTL
= SD_DCMPS0_CTL
;
107 REG_SD_DCMPS1_CTL
= SD_DCMPS1_CTL
;
109 REG_SD_CFG1
= 0xFD31;
110 REG_SD_CFG2
= 0xFD33;
111 REG_SD_CFG3
= 0xFD3E;
112 REG_SD_STAT1
= 0xFD30;
116 REG_SD_SAMPLE_POINT_CTL
= 0;
117 REG_SD_PUSH_POINT_CTL
= 0;
118 REG_SD_CMD0
= 0xFD34;
119 REG_SD_CMD1
= 0xFD35;
120 REG_SD_CMD2
= 0xFD36;
121 REG_SD_CMD3
= 0xFD37;
122 REG_SD_CMD4
= 0xFD38;
123 REG_SD_CMD5
= 0xFD5A;
124 REG_SD_BYTE_CNT_L
= 0xFD39;
125 REG_SD_BYTE_CNT_H
= 0xFD3A;
126 REG_SD_BLOCK_CNT_L
= 0xFD3B;
127 REG_SD_BLOCK_CNT_H
= 0xFD3C;
128 REG_SD_TRANSFER
= 0xFD32;
129 REG_SD_VPCLK0_CTL
= 0;
130 REG_SD_VPCLK1_CTL
= 0;
131 REG_SD_DCMPS0_CTL
= 0;
132 REG_SD_DCMPS1_CTL
= 0;
136 static int sd_check_data0_status(struct rtsx_chip
*chip
)
140 if (CHECK_PID(chip
, 0x5209)) {
141 RTSX_READ_REG(chip
, REG_SD_BUS_STAT
, &stat
);
143 RTSX_READ_REG(chip
, REG_SD_STAT1
, &stat
);
146 if (!(stat
& SD_DAT0_STATUS
)) {
147 sd_set_err_code(chip
, SD_BUSY
);
148 TRACE_RET(chip
, STATUS_FAIL
);
151 return STATUS_SUCCESS
;
154 static int sd_send_cmd_get_rsp(struct rtsx_chip
*chip
, u8 cmd_idx
,
155 u32 arg
, u8 rsp_type
, u8
*rsp
, int rsp_len
)
157 struct sd_info
*sd_card
= &(chip
->sd_card
);
165 sd_clr_err_code(chip
);
167 RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx
, arg
);
169 if (rsp_type
== SD_RSP_TYPE_R1b
)
176 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | cmd_idx
);
177 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, (u8
)(arg
>> 24));
178 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, (u8
)(arg
>> 16));
179 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, (u8
)(arg
>> 8));
180 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, (u8
)arg
);
182 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, rsp_type
);
183 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
184 0x01, PINGPONG_BUFFER
);
185 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
,
186 0xFF, SD_TM_CMD_RSP
| SD_TRANSFER_START
);
187 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
188 SD_TRANSFER_END
| SD_STAT_IDLE
, SD_TRANSFER_END
| SD_STAT_IDLE
);
190 if (rsp_type
== SD_RSP_TYPE_R2
) {
191 for (reg_addr
= PPBUF_BASE2
; reg_addr
< PPBUF_BASE2
+ 16; reg_addr
++) {
192 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
195 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
196 for (reg_addr
= REG_SD_CMD0
; reg_addr
<= REG_SD_CMD4
; reg_addr
++) {
197 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
202 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_STAT1
, 0, 0);
204 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
208 rtsx_read_register(chip
, REG_SD_STAT1
, &val
);
209 RTSX_DEBUGP("SD_STAT1: 0x%x\n", val
);
211 if (CHECK_PID(chip
, 0x5209)) {
212 rtsx_read_register(chip
, REG_SD_STAT2
, &val
);
213 RTSX_DEBUGP("SD_STAT2: 0x%x\n", val
);
215 if (val
& SD_RSP_80CLK_TIMEOUT
) {
216 rtsx_clear_sd_error(chip
);
217 sd_set_err_code(chip
, SD_RSP_TIMEOUT
);
218 TRACE_RET(chip
, STATUS_FAIL
);
221 rtsx_read_register(chip
, REG_SD_BUS_STAT
, &val
);
222 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val
);
224 rtsx_read_register(chip
, REG_SD_CFG3
, &val
);
225 RTSX_DEBUGP("SD_CFG3: 0x%x\n", val
);
228 if (retval
== -ETIMEDOUT
) {
229 if (rsp_type
& SD_WAIT_BUSY_END
) {
230 retval
= sd_check_data0_status(chip
);
231 if (retval
!= STATUS_SUCCESS
) {
232 rtsx_clear_sd_error(chip
);
233 TRACE_RET(chip
, retval
);
236 sd_set_err_code(chip
, SD_TO_ERR
);
238 retval
= STATUS_TIMEDOUT
;
240 retval
= STATUS_FAIL
;
242 rtsx_clear_sd_error(chip
);
244 TRACE_RET(chip
, retval
);
247 if (rsp_type
== SD_RSP_TYPE_R0
)
248 return STATUS_SUCCESS
;
250 ptr
= rtsx_get_cmd_data(chip
) + 1;
252 if ((ptr
[0] & 0xC0) != 0) {
253 sd_set_err_code(chip
, SD_STS_ERR
);
254 TRACE_RET(chip
, STATUS_FAIL
);
257 if (!(rsp_type
& SD_NO_CHECK_CRC7
)) {
258 if (ptr
[stat_idx
] & SD_CRC7_ERR
) {
259 if (cmd_idx
== WRITE_MULTIPLE_BLOCK
) {
260 sd_set_err_code(chip
, SD_CRC_ERR
);
261 TRACE_RET(chip
, STATUS_FAIL
);
263 if (rty_cnt
< SD_MAX_RETRY_COUNT
) {
268 sd_set_err_code(chip
, SD_CRC_ERR
);
269 TRACE_RET(chip
, STATUS_FAIL
);
274 if ((rsp_type
== SD_RSP_TYPE_R1
) || (rsp_type
== SD_RSP_TYPE_R1b
)) {
275 if ((cmd_idx
!= SEND_RELATIVE_ADDR
) && (cmd_idx
!= SEND_IF_COND
)) {
276 if (cmd_idx
!= STOP_TRANSMISSION
) {
278 TRACE_RET(chip
, STATUS_FAIL
);
281 #ifdef SUPPORT_SD_LOCK
287 RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr
[1]);
288 TRACE_RET(chip
, STATUS_FAIL
);
291 RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr
[2]);
292 TRACE_RET(chip
, STATUS_FAIL
);
295 RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr
[3]);
296 TRACE_RET(chip
, STATUS_FAIL
);
299 sd_card
->sd_data_buf_ready
= 1;
301 sd_card
->sd_data_buf_ready
= 0;
307 memcpy(rsp
, ptr
, rsp_len
);
309 return STATUS_SUCCESS
;
312 static int sd_read_data(struct rtsx_chip
*chip
,
313 u8 trans_mode
, u8
*cmd
, int cmd_len
, u16 byte_cnt
,
314 u16 blk_cnt
, u8 bus_width
, u8
*buf
, int buf_len
,
317 struct sd_info
*sd_card
= &(chip
->sd_card
);
321 sd_clr_err_code(chip
);
327 TRACE_RET(chip
, STATUS_FAIL
);
333 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd
[0] - 0x40);
334 for (i
= 0; i
< (cmd_len
< 6 ? cmd_len
: 6); i
++) {
335 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
+ i
, 0xFF, cmd
[i
]);
338 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, (u8
)byte_cnt
);
339 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, (u8
)(byte_cnt
>> 8));
340 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, (u8
)blk_cnt
);
341 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, (u8
)(blk_cnt
>> 8));
343 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, bus_width
);
345 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
346 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
347 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
348 if (trans_mode
!= SD_TM_AUTO_TUNING
) {
349 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
351 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF, trans_mode
| SD_TRANSFER_START
);
352 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
354 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
356 if (retval
== -ETIMEDOUT
) {
357 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
358 SD_RSP_TYPE_R1
, NULL
, 0);
361 TRACE_RET(chip
, STATUS_FAIL
);
364 if (buf
&& buf_len
) {
365 retval
= rtsx_read_ppbuf(chip
, buf
, buf_len
);
366 if (retval
!= STATUS_SUCCESS
) {
367 TRACE_RET(chip
, STATUS_FAIL
);
371 return STATUS_SUCCESS
;
374 static int sd_write_data(struct rtsx_chip
*chip
, u8 trans_mode
,
375 u8
*cmd
, int cmd_len
, u16 byte_cnt
, u16 blk_cnt
, u8 bus_width
,
376 u8
*buf
, int buf_len
, int timeout
)
378 struct sd_info
*sd_card
= &(chip
->sd_card
);
382 sd_clr_err_code(chip
);
388 /* This function can't write data more than one page */
389 TRACE_RET(chip
, STATUS_FAIL
);
392 if (buf
&& buf_len
) {
393 retval
= rtsx_write_ppbuf(chip
, buf
, buf_len
);
394 if (retval
!= STATUS_SUCCESS
) {
395 TRACE_RET(chip
, STATUS_FAIL
);
402 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd
[0] - 0x40);
403 for (i
= 0; i
< (cmd_len
< 6 ? cmd_len
: 6); i
++) {
404 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
405 REG_SD_CMD0
+ i
, 0xFF, cmd
[i
]);
408 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, (u8
)byte_cnt
);
409 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, (u8
)(byte_cnt
>> 8));
410 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, (u8
)blk_cnt
);
411 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, (u8
)(blk_cnt
>> 8));
413 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, bus_width
);
415 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
416 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
417 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
419 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF, trans_mode
| SD_TRANSFER_START
);
420 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
422 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
424 if (retval
== -ETIMEDOUT
) {
425 sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
426 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
429 TRACE_RET(chip
, STATUS_FAIL
);
432 return STATUS_SUCCESS
;
435 static int sd_check_csd(struct rtsx_chip
*chip
, char check_wp
)
437 struct sd_info
*sd_card
= &(chip
->sd_card
);
440 u8 csd_ver
, trans_speed
;
443 for (i
= 0; i
< 6; i
++) {
444 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
445 sd_set_err_code(chip
, SD_NO_CARD
);
446 TRACE_RET(chip
, STATUS_FAIL
);
449 retval
= sd_send_cmd_get_rsp(chip
, SEND_CSD
, sd_card
->sd_addr
, SD_RSP_TYPE_R2
, rsp
, 16);
450 if (retval
== STATUS_SUCCESS
)
455 TRACE_RET(chip
, STATUS_FAIL
);
458 memcpy(sd_card
->raw_csd
, rsp
+ 1, 15);
460 if (CHECK_PID(chip
, 0x5209)) {
461 RTSX_READ_REG(chip
, REG_SD_CMD5
, sd_card
->raw_csd
+ 15);
464 RTSX_DEBUGP("CSD Response:\n");
465 RTSX_DUMP(sd_card
->raw_csd
, 16);
467 csd_ver
= (rsp
[1] & 0xc0) >> 6;
468 RTSX_DEBUGP("csd_ver = %d\n", csd_ver
);
470 trans_speed
= rsp
[4];
471 if ((trans_speed
& 0x07) == 0x02) {
472 if ((trans_speed
& 0xf8) >= 0x30) {
473 if (chip
->asic_code
) {
474 sd_card
->sd_clock
= 47;
476 sd_card
->sd_clock
= CLK_50
;
478 } else if ((trans_speed
& 0xf8) == 0x28) {
479 if (chip
->asic_code
) {
480 sd_card
->sd_clock
= 39;
482 sd_card
->sd_clock
= CLK_40
;
484 } else if ((trans_speed
& 0xf8) == 0x20) {
485 if (chip
->asic_code
) {
486 sd_card
->sd_clock
= 29;
488 sd_card
->sd_clock
= CLK_30
;
490 } else if ((trans_speed
& 0xf8) >= 0x10) {
491 if (chip
->asic_code
) {
492 sd_card
->sd_clock
= 23;
494 sd_card
->sd_clock
= CLK_20
;
496 } else if ((trans_speed
& 0x08) >= 0x08) {
497 if (chip
->asic_code
) {
498 sd_card
->sd_clock
= 19;
500 sd_card
->sd_clock
= CLK_20
;
503 TRACE_RET(chip
, STATUS_FAIL
);
506 TRACE_RET(chip
, STATUS_FAIL
);
509 if (CHK_MMC_SECTOR_MODE(sd_card
)) {
510 sd_card
->capacity
= 0;
512 if ((!CHK_SD_HCXC(sd_card
)) || (csd_ver
== 0)) {
513 u8 blk_size
, c_size_mult
;
515 blk_size
= rsp
[6] & 0x0F;
516 c_size
= ((u16
)(rsp
[7] & 0x03) << 10)
518 + ((u16
)(rsp
[9] & 0xC0) >> 6);
519 c_size_mult
= (u8
)((rsp
[10] & 0x03) << 1);
520 c_size_mult
+= (rsp
[11] & 0x80) >> 7;
521 sd_card
->capacity
= (((u32
)(c_size
+ 1)) * (1 << (c_size_mult
+ 2))) << (blk_size
- 9);
523 u32 total_sector
= 0;
524 total_sector
= (((u32
)rsp
[8] & 0x3f) << 16) |
525 ((u32
)rsp
[9] << 8) | (u32
)rsp
[10];
526 sd_card
->capacity
= (total_sector
+ 1) << 10;
531 if (rsp
[15] & 0x30) {
532 chip
->card_wp
|= SD_CARD
;
534 RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp
[15]);
537 return STATUS_SUCCESS
;
540 static int sd_set_sample_push_timing(struct rtsx_chip
*chip
)
542 struct sd_info
*sd_card
= &(chip
->sd_card
);
544 if (CHECK_PID(chip
, 0x5209)) {
545 if (CHK_SD_SDR104(sd_card
) || CHK_SD_SDR50(sd_card
)) {
546 RTSX_WRITE_REG(chip
, SD_CFG1
, 0x0C | SD_ASYNC_FIFO_NOT_RST
,
547 SD_30_MODE
| SD_ASYNC_FIFO_NOT_RST
);
548 RTSX_WRITE_REG(chip
, CLK_CTL
, CLK_LOW_FREQ
, CLK_LOW_FREQ
);
549 RTSX_WRITE_REG(chip
, CARD_CLK_SOURCE
, 0xFF,
550 CRC_VAR_CLK0
| SD30_FIX_CLK
| SAMPLE_VAR_CLK1
);
551 RTSX_WRITE_REG(chip
, CLK_CTL
, CLK_LOW_FREQ
, 0);
552 } else if (CHK_SD_DDR50(sd_card
) || CHK_MMC_DDR52(sd_card
)) {
553 RTSX_WRITE_REG(chip
, SD_CFG1
, 0x0C | SD_ASYNC_FIFO_NOT_RST
,
554 SD_DDR_MODE
| SD_ASYNC_FIFO_NOT_RST
);
555 RTSX_WRITE_REG(chip
, CLK_CTL
, CLK_LOW_FREQ
, CLK_LOW_FREQ
);
556 RTSX_WRITE_REG(chip
, CARD_CLK_SOURCE
, 0xFF,
557 CRC_VAR_CLK0
| SD30_FIX_CLK
| SAMPLE_VAR_CLK1
);
558 RTSX_WRITE_REG(chip
, CLK_CTL
, CLK_LOW_FREQ
, 0);
559 RTSX_WRITE_REG(chip
, SD_PUSH_POINT_CTL
, DDR_VAR_TX_CMD_DAT
,
561 RTSX_WRITE_REG(chip
, SD_SAMPLE_POINT_CTL
, DDR_VAR_RX_DAT
| DDR_VAR_RX_CMD
,
562 DDR_VAR_RX_DAT
| DDR_VAR_RX_CMD
);
566 RTSX_WRITE_REG(chip
, SD_CFG1
, 0x0C, SD_20_MODE
);
567 RTSX_WRITE_REG(chip
, CLK_CTL
, CLK_LOW_FREQ
, CLK_LOW_FREQ
);
568 RTSX_WRITE_REG(chip
, CARD_CLK_SOURCE
, 0xFF,
569 CRC_FIX_CLK
| SD30_VAR_CLK0
| SAMPLE_VAR_CLK1
);
570 RTSX_WRITE_REG(chip
, CLK_CTL
, CLK_LOW_FREQ
, 0);
572 if ((chip
->sd_ctl
& SD_PUSH_POINT_CTL_MASK
) == SD_PUSH_POINT_AUTO
) {
573 val
= SD20_TX_NEG_EDGE
;
574 } else if ((chip
->sd_ctl
& SD_PUSH_POINT_CTL_MASK
) == SD_PUSH_POINT_DELAY
) {
575 val
= SD20_TX_14_AHEAD
;
577 val
= SD20_TX_NEG_EDGE
;
579 RTSX_WRITE_REG(chip
, SD_PUSH_POINT_CTL
, SD20_TX_SEL_MASK
, val
);
581 if ((chip
->sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) == SD_SAMPLE_POINT_AUTO
) {
582 if (chip
->asic_code
) {
583 if (CHK_SD_HS(sd_card
) || CHK_MMC_52M(sd_card
)) {
584 val
= SD20_RX_14_DELAY
;
586 val
= SD20_RX_POS_EDGE
;
589 val
= SD20_RX_14_DELAY
;
591 } else if ((chip
->sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) == SD_SAMPLE_POINT_DELAY
) {
592 val
= SD20_RX_14_DELAY
;
594 val
= SD20_RX_POS_EDGE
;
596 RTSX_WRITE_REG(chip
, SD_SAMPLE_POINT_CTL
, SD20_RX_SEL_MASK
, val
);
601 if ((chip
->sd_ctl
& SD_PUSH_POINT_CTL_MASK
) == SD_PUSH_POINT_DELAY
) {
605 if ((chip
->sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) == SD_SAMPLE_POINT_AUTO
) {
606 if (chip
->asic_code
) {
607 if (CHK_SD_HS(sd_card
) || CHK_MMC_52M(sd_card
)) {
621 } else if ((chip
->sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) == SD_SAMPLE_POINT_DELAY
) {
629 RTSX_WRITE_REG(chip
, REG_SD_CFG1
, 0x1C, val
);
632 return STATUS_SUCCESS
;
635 static void sd_choose_proper_clock(struct rtsx_chip
*chip
)
637 struct sd_info
*sd_card
= &(chip
->sd_card
);
639 if (CHK_SD_SDR104(sd_card
)) {
640 if (chip
->asic_code
) {
641 sd_card
->sd_clock
= chip
->asic_sd_sdr104_clk
;
643 sd_card
->sd_clock
= chip
->fpga_sd_sdr104_clk
;
645 } else if (CHK_SD_DDR50(sd_card
)) {
646 if (chip
->asic_code
) {
647 sd_card
->sd_clock
= chip
->asic_sd_ddr50_clk
;
649 sd_card
->sd_clock
= chip
->fpga_sd_ddr50_clk
;
651 } else if (CHK_SD_SDR50(sd_card
)) {
652 if (chip
->asic_code
) {
653 sd_card
->sd_clock
= chip
->asic_sd_sdr50_clk
;
655 sd_card
->sd_clock
= chip
->fpga_sd_sdr50_clk
;
657 } else if (CHK_SD_HS(sd_card
)) {
658 if (chip
->asic_code
) {
659 sd_card
->sd_clock
= chip
->asic_sd_hs_clk
;
661 sd_card
->sd_clock
= chip
->fpga_sd_hs_clk
;
663 } else if (CHK_MMC_52M(sd_card
) || CHK_MMC_DDR52(sd_card
)) {
664 if (chip
->asic_code
) {
665 sd_card
->sd_clock
= chip
->asic_mmc_52m_clk
;
667 sd_card
->sd_clock
= chip
->fpga_mmc_52m_clk
;
669 } else if (CHK_MMC_26M(sd_card
)) {
670 if (chip
->asic_code
) {
671 sd_card
->sd_clock
= 48;
673 sd_card
->sd_clock
= CLK_50
;
678 static int sd_set_clock_divider(struct rtsx_chip
*chip
, u8 clk_div
)
680 u8 mask
= 0, val
= 0;
682 if (CHECK_PID(chip
, 0x5209)) {
683 mask
= SD_CLK_DIVIDE_MASK
;
687 if (clk_div
== SD_CLK_DIVIDE_0
) {
689 } else if (clk_div
== SD_CLK_DIVIDE_128
) {
691 } else if (clk_div
== SD_CLK_DIVIDE_256
) {
696 RTSX_WRITE_REG(chip
, REG_SD_CFG1
, mask
, val
);
698 return STATUS_SUCCESS
;
701 static int sd_set_init_para(struct rtsx_chip
*chip
)
703 struct sd_info
*sd_card
= &(chip
->sd_card
);
706 retval
= sd_set_sample_push_timing(chip
);
707 if (retval
!= STATUS_SUCCESS
) {
708 TRACE_RET(chip
, STATUS_FAIL
);
711 sd_choose_proper_clock(chip
);
713 retval
= switch_clock(chip
, sd_card
->sd_clock
);
714 if (retval
!= STATUS_SUCCESS
) {
715 TRACE_RET(chip
, STATUS_FAIL
);
718 return STATUS_SUCCESS
;
721 int sd_select_card(struct rtsx_chip
*chip
, int select
)
723 struct sd_info
*sd_card
= &(chip
->sd_card
);
725 u8 cmd_idx
, cmd_type
;
729 cmd_idx
= SELECT_CARD
;
730 cmd_type
= SD_RSP_TYPE_R1
;
731 addr
= sd_card
->sd_addr
;
733 cmd_idx
= DESELECT_CARD
;
734 cmd_type
= SD_RSP_TYPE_R0
;
738 retval
= sd_send_cmd_get_rsp(chip
, cmd_idx
, addr
, cmd_type
, NULL
, 0);
739 if (retval
!= STATUS_SUCCESS
) {
740 TRACE_RET(chip
, STATUS_FAIL
);
743 return STATUS_SUCCESS
;
746 #ifdef SUPPORT_SD_LOCK
747 static int sd_update_lock_status(struct rtsx_chip
*chip
)
749 struct sd_info
*sd_card
= &(chip
->sd_card
);
753 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, rsp
, 5);
754 if (retval
!= STATUS_SUCCESS
) {
755 TRACE_RET(chip
, STATUS_FAIL
);
759 sd_card
->sd_lock_status
|= SD_LOCKED
;
761 sd_card
->sd_lock_status
&= ~SD_LOCKED
;
764 RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", sd_card
->sd_lock_status
);
767 TRACE_RET(chip
, STATUS_FAIL
);
770 return STATUS_SUCCESS
;
774 static int sd_wait_state_data_ready(struct rtsx_chip
*chip
, u8 state
, u8 data_ready
, int polling_cnt
)
776 struct sd_info
*sd_card
= &(chip
->sd_card
);
780 for (i
= 0; i
< polling_cnt
; i
++) {
781 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
782 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, rsp
, 5);
783 if (retval
!= STATUS_SUCCESS
) {
784 TRACE_RET(chip
, STATUS_FAIL
);
787 if (((rsp
[3] & 0x1E) == state
) && ((rsp
[3] & 0x01) == data_ready
)) {
788 return STATUS_SUCCESS
;
792 TRACE_RET(chip
, STATUS_FAIL
);
795 static int sd_change_bank_voltage(struct rtsx_chip
*chip
, u8 voltage
)
799 if (voltage
== SD_IO_3V3
) {
800 if (chip
->asic_code
) {
801 retval
= rtsx_write_phy_register(chip
, 0x08, 0x4FC0 | chip
->phy_voltage
);
802 if (retval
!= STATUS_SUCCESS
) {
803 TRACE_RET(chip
, STATUS_FAIL
);
806 RTSX_WRITE_REG(chip
, SD_PAD_CTL
, SD_IO_USING_1V8
, 0);
808 } else if (voltage
== SD_IO_1V8
) {
809 if (chip
->asic_code
) {
810 retval
= rtsx_write_phy_register(chip
, 0x08, 0x4C40 | chip
->phy_voltage
);
811 if (retval
!= STATUS_SUCCESS
) {
812 TRACE_RET(chip
, STATUS_FAIL
);
815 RTSX_WRITE_REG(chip
, SD_PAD_CTL
, SD_IO_USING_1V8
, SD_IO_USING_1V8
);
818 TRACE_RET(chip
, STATUS_FAIL
);
821 return STATUS_SUCCESS
;
824 static int sd_voltage_switch(struct rtsx_chip
*chip
)
829 RTSX_WRITE_REG(chip
, SD_BUS_STAT
, SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, SD_CLK_TOGGLE_EN
);
831 retval
= sd_send_cmd_get_rsp(chip
, VOLTAGE_SWITCH
, 0, SD_RSP_TYPE_R1
, NULL
, 0);
832 if (retval
!= STATUS_SUCCESS
) {
833 TRACE_RET(chip
, STATUS_FAIL
);
836 udelay(chip
->sd_voltage_switch_delay
);
838 RTSX_READ_REG(chip
, SD_BUS_STAT
, &stat
);
839 if (stat
& (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
840 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) {
841 TRACE_RET(chip
, STATUS_FAIL
);
844 RTSX_WRITE_REG(chip
, SD_BUS_STAT
, 0xFF, SD_CLK_FORCE_STOP
);
845 retval
= sd_change_bank_voltage(chip
, SD_IO_1V8
);
846 if (retval
!= STATUS_SUCCESS
) {
847 TRACE_RET(chip
, STATUS_FAIL
);
851 RTSX_WRITE_REG(chip
, SD_BUS_STAT
, 0xFF, SD_CLK_TOGGLE_EN
);
854 RTSX_READ_REG(chip
, SD_BUS_STAT
, &stat
);
855 if ((stat
& (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
856 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) !=
857 (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
858 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) {
859 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat
);
860 rtsx_write_register(chip
, SD_BUS_STAT
, SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
861 rtsx_write_register(chip
, CARD_CLK_EN
, 0xFF, 0);
862 TRACE_RET(chip
, STATUS_FAIL
);
865 RTSX_WRITE_REG(chip
, SD_BUS_STAT
, SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
867 return STATUS_SUCCESS
;
870 static int sd_reset_dcm(struct rtsx_chip
*chip
, u8 tune_dir
)
872 if (tune_dir
== TUNE_RX
) {
873 RTSX_WRITE_REG(chip
, DCM_DRP_CTL
, 0xFF, DCM_RESET
| DCM_RX
);
874 RTSX_WRITE_REG(chip
, DCM_DRP_CTL
, 0xFF, DCM_RX
);
876 RTSX_WRITE_REG(chip
, DCM_DRP_CTL
, 0xFF, DCM_RESET
| DCM_TX
);
877 RTSX_WRITE_REG(chip
, DCM_DRP_CTL
, 0xFF, DCM_TX
);
880 return STATUS_SUCCESS
;
883 static int sd_change_phase(struct rtsx_chip
*chip
, u8 sample_point
, u8 tune_dir
)
885 struct sd_info
*sd_card
= &(chip
->sd_card
);
886 u16 SD_VP_CTL
, SD_DCMPS_CTL
;
891 RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
892 sample_point
, tune_dir
);
894 if (tune_dir
== TUNE_RX
) {
895 SD_VP_CTL
= SD_VPRX_CTL
;
896 SD_DCMPS_CTL
= SD_DCMPS_RX_CTL
;
897 if (CHK_SD_DDR50(sd_card
)) {
901 SD_VP_CTL
= SD_VPTX_CTL
;
902 SD_DCMPS_CTL
= SD_DCMPS_TX_CTL
;
905 if (chip
->asic_code
) {
906 RTSX_WRITE_REG(chip
, CLK_CTL
, CHANGE_CLK
, CHANGE_CLK
);
907 RTSX_WRITE_REG(chip
, SD_VP_CTL
, 0x1F, sample_point
);
908 RTSX_WRITE_REG(chip
, SD_VPCLK0_CTL
, PHASE_NOT_RESET
, 0);
909 RTSX_WRITE_REG(chip
, SD_VPCLK0_CTL
, PHASE_NOT_RESET
, PHASE_NOT_RESET
);
910 RTSX_WRITE_REG(chip
, CLK_CTL
, CHANGE_CLK
, 0);
912 #ifdef CONFIG_RTS_PSTOR_DEBUG
913 rtsx_read_register(chip
, SD_VP_CTL
, &val
);
914 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val
);
915 rtsx_read_register(chip
, SD_DCMPS_CTL
, &val
);
916 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val
);
920 RTSX_WRITE_REG(chip
, SD_VP_CTL
, PHASE_CHANGE
, PHASE_CHANGE
);
922 RTSX_WRITE_REG(chip
, SD_VP_CTL
, 0xFF,
923 PHASE_CHANGE
| PHASE_NOT_RESET
| sample_point
);
925 RTSX_WRITE_REG(chip
, CLK_CTL
, CHANGE_CLK
, CHANGE_CLK
);
927 RTSX_WRITE_REG(chip
, SD_VP_CTL
, 0xFF,
928 PHASE_NOT_RESET
| sample_point
);
933 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SD_DCMPS_CTL
, DCMPS_CHANGE
, DCMPS_CHANGE
);
934 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SD_DCMPS_CTL
, DCMPS_CHANGE_DONE
, DCMPS_CHANGE_DONE
);
935 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
936 if (retval
!= STATUS_SUCCESS
) {
937 TRACE_GOTO(chip
, Fail
);
940 val
= *rtsx_get_cmd_data(chip
);
941 if (val
& DCMPS_ERROR
) {
942 TRACE_GOTO(chip
, Fail
);
944 if ((val
& DCMPS_CURRENT_PHASE
) != sample_point
) {
945 TRACE_GOTO(chip
, Fail
);
947 RTSX_WRITE_REG(chip
, SD_DCMPS_CTL
, DCMPS_CHANGE
, 0);
949 RTSX_WRITE_REG(chip
, SD_VP_CTL
, PHASE_CHANGE
, 0);
951 RTSX_WRITE_REG(chip
, CLK_CTL
, CHANGE_CLK
, 0);
956 RTSX_WRITE_REG(chip
, SD_CFG1
, SD_ASYNC_FIFO_NOT_RST
, 0);
958 return STATUS_SUCCESS
;
961 #ifdef CONFIG_RTS_PSTOR_DEBUG
962 rtsx_read_register(chip
, SD_VP_CTL
, &val
);
963 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val
);
964 rtsx_read_register(chip
, SD_DCMPS_CTL
, &val
);
965 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val
);
968 rtsx_write_register(chip
, SD_DCMPS_CTL
, DCMPS_CHANGE
, 0);
969 rtsx_write_register(chip
, SD_VP_CTL
, PHASE_CHANGE
, 0);
971 sd_reset_dcm(chip
, tune_dir
);
975 static int sd_check_spec(struct rtsx_chip
*chip
, u8 bus_width
)
977 struct sd_info
*sd_card
= &(chip
->sd_card
);
981 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
982 if (retval
!= STATUS_SUCCESS
) {
983 TRACE_RET(chip
, STATUS_FAIL
);
986 cmd
[0] = 0x40 | SEND_SCR
;
992 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 8, 1, bus_width
, buf
, 8, 250);
993 if (retval
!= STATUS_SUCCESS
) {
994 rtsx_clear_sd_error(chip
);
995 TRACE_RET(chip
, STATUS_FAIL
);
998 memcpy(sd_card
->raw_scr
, buf
, 8);
1000 if ((buf
[0] & 0x0F) == 0) {
1001 TRACE_RET(chip
, STATUS_FAIL
);
1004 return STATUS_SUCCESS
;
1007 static int sd_query_switch_result(struct rtsx_chip
*chip
, u8 func_group
, u8 func_to_switch
,
1008 u8
*buf
, int buf_len
)
1010 u8 support_mask
= 0, query_switch
= 0, switch_busy
= 0;
1011 int support_offset
= 0, query_switch_offset
= 0, check_busy_offset
= 0;
1013 if (func_group
== SD_FUNC_GROUP_1
) {
1014 support_offset
= FUNCTION_GROUP1_SUPPORT_OFFSET
;
1015 query_switch_offset
= FUNCTION_GROUP1_QUERY_SWITCH_OFFSET
;
1016 check_busy_offset
= FUNCTION_GROUP1_CHECK_BUSY_OFFSET
;
1018 switch (func_to_switch
) {
1020 support_mask
= HS_SUPPORT_MASK
;
1021 query_switch
= HS_QUERY_SWITCH_OK
;
1022 switch_busy
= HS_SWITCH_BUSY
;
1026 support_mask
= SDR50_SUPPORT_MASK
;
1027 query_switch
= SDR50_QUERY_SWITCH_OK
;
1028 switch_busy
= SDR50_SWITCH_BUSY
;
1031 case SDR104_SUPPORT
:
1032 support_mask
= SDR104_SUPPORT_MASK
;
1033 query_switch
= SDR104_QUERY_SWITCH_OK
;
1034 switch_busy
= SDR104_SWITCH_BUSY
;
1038 support_mask
= DDR50_SUPPORT_MASK
;
1039 query_switch
= DDR50_QUERY_SWITCH_OK
;
1040 switch_busy
= DDR50_SWITCH_BUSY
;
1044 TRACE_RET(chip
, STATUS_FAIL
);
1046 } else if (func_group
== SD_FUNC_GROUP_3
) {
1047 support_offset
= FUNCTION_GROUP3_SUPPORT_OFFSET
;
1048 query_switch_offset
= FUNCTION_GROUP3_QUERY_SWITCH_OFFSET
;
1049 check_busy_offset
= FUNCTION_GROUP3_CHECK_BUSY_OFFSET
;
1051 switch (func_to_switch
) {
1052 case DRIVING_TYPE_A
:
1053 support_mask
= DRIVING_TYPE_A_MASK
;
1054 query_switch
= TYPE_A_QUERY_SWITCH_OK
;
1055 switch_busy
= TYPE_A_SWITCH_BUSY
;
1058 case DRIVING_TYPE_C
:
1059 support_mask
= DRIVING_TYPE_C_MASK
;
1060 query_switch
= TYPE_C_QUERY_SWITCH_OK
;
1061 switch_busy
= TYPE_C_SWITCH_BUSY
;
1064 case DRIVING_TYPE_D
:
1065 support_mask
= DRIVING_TYPE_D_MASK
;
1066 query_switch
= TYPE_D_QUERY_SWITCH_OK
;
1067 switch_busy
= TYPE_D_SWITCH_BUSY
;
1071 TRACE_RET(chip
, STATUS_FAIL
);
1073 } else if (func_group
== SD_FUNC_GROUP_4
) {
1074 support_offset
= FUNCTION_GROUP4_SUPPORT_OFFSET
;
1075 query_switch_offset
= FUNCTION_GROUP4_QUERY_SWITCH_OFFSET
;
1076 check_busy_offset
= FUNCTION_GROUP4_CHECK_BUSY_OFFSET
;
1078 switch (func_to_switch
) {
1079 case CURRENT_LIMIT_400
:
1080 support_mask
= CURRENT_LIMIT_400_MASK
;
1081 query_switch
= CURRENT_LIMIT_400_QUERY_SWITCH_OK
;
1082 switch_busy
= CURRENT_LIMIT_400_SWITCH_BUSY
;
1085 case CURRENT_LIMIT_600
:
1086 support_mask
= CURRENT_LIMIT_600_MASK
;
1087 query_switch
= CURRENT_LIMIT_600_QUERY_SWITCH_OK
;
1088 switch_busy
= CURRENT_LIMIT_600_SWITCH_BUSY
;
1091 case CURRENT_LIMIT_800
:
1092 support_mask
= CURRENT_LIMIT_800_MASK
;
1093 query_switch
= CURRENT_LIMIT_800_QUERY_SWITCH_OK
;
1094 switch_busy
= CURRENT_LIMIT_800_SWITCH_BUSY
;
1098 TRACE_RET(chip
, STATUS_FAIL
);
1101 TRACE_RET(chip
, STATUS_FAIL
);
1104 if (func_group
== SD_FUNC_GROUP_1
) {
1105 if (!(buf
[support_offset
] & support_mask
) ||
1106 ((buf
[query_switch_offset
] & 0x0F) != query_switch
)) {
1107 TRACE_RET(chip
, STATUS_FAIL
);
1111 /* Check 'Busy Status' */
1112 if ((buf
[DATA_STRUCTURE_VER_OFFSET
] == 0x01) &&
1113 ((buf
[check_busy_offset
] & switch_busy
) == switch_busy
)) {
1114 TRACE_RET(chip
, STATUS_FAIL
);
1117 return STATUS_SUCCESS
;
1120 static int sd_check_switch_mode(struct rtsx_chip
*chip
, u8 mode
,
1121 u8 func_group
, u8 func_to_switch
, u8 bus_width
)
1123 struct sd_info
*sd_card
= &(chip
->sd_card
);
1127 RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1128 mode
, func_group
, func_to_switch
);
1130 cmd
[0] = 0x40 | SWITCH
;
1133 if (func_group
== SD_FUNC_GROUP_1
) {
1136 cmd
[4] = 0xF0 + func_to_switch
;
1137 } else if (func_group
== SD_FUNC_GROUP_3
) {
1139 cmd
[3] = 0xF0 + func_to_switch
;
1141 } else if (func_group
== SD_FUNC_GROUP_4
) {
1143 cmd
[3] = 0x0F + (func_to_switch
<< 4);
1146 cmd
[1] = SD_CHECK_MODE
;
1152 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 64, 1, bus_width
, buf
, 64, 250);
1153 if (retval
!= STATUS_SUCCESS
) {
1154 rtsx_clear_sd_error(chip
);
1155 TRACE_RET(chip
, STATUS_FAIL
);
1160 if (func_group
== NO_ARGUMENT
) {
1161 sd_card
->func_group1_mask
= buf
[0x0D];
1162 sd_card
->func_group2_mask
= buf
[0x0B];
1163 sd_card
->func_group3_mask
= buf
[0x09];
1164 sd_card
->func_group4_mask
= buf
[0x07];
1166 RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf
[0x0D]);
1167 RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf
[0x0B]);
1168 RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf
[0x09]);
1169 RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf
[0x07]);
1171 /* Maximum current consumption, check whether current is acceptable;
1172 * bit[511:496] = 0x0000 means some error happaned.
1174 u16 cc
= ((u16
)buf
[0] << 8) | buf
[1];
1175 RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc
);
1176 if ((cc
== 0) || (cc
> 800)) {
1177 TRACE_RET(chip
, STATUS_FAIL
);
1179 retval
= sd_query_switch_result(chip
, func_group
, func_to_switch
, buf
, 64);
1180 if (retval
!= STATUS_SUCCESS
) {
1181 TRACE_RET(chip
, STATUS_FAIL
);
1184 if ((cc
> 400) || (func_to_switch
> CURRENT_LIMIT_400
)) {
1185 RTSX_WRITE_REG(chip
, OCPPARA2
, SD_OCP_THD_MASK
, chip
->sd_800mA_ocp_thd
);
1186 RTSX_WRITE_REG(chip
, CARD_PWR_CTL
, PMOS_STRG_MASK
, PMOS_STRG_800mA
);
1190 return STATUS_SUCCESS
;
1193 static u8
downgrade_switch_mode(u8 func_group
, u8 func_to_switch
)
1195 if (func_group
== SD_FUNC_GROUP_1
) {
1196 if (func_to_switch
> HS_SUPPORT
) {
1199 } else if (func_group
== SD_FUNC_GROUP_4
) {
1200 if (func_to_switch
> CURRENT_LIMIT_200
) {
1205 return func_to_switch
;
1208 static int sd_check_switch(struct rtsx_chip
*chip
,
1209 u8 func_group
, u8 func_to_switch
, u8 bus_width
)
1213 int switch_good
= 0;
1215 for (i
= 0; i
< 3; i
++) {
1216 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
1217 sd_set_err_code(chip
, SD_NO_CARD
);
1218 TRACE_RET(chip
, STATUS_FAIL
);
1221 retval
= sd_check_switch_mode(chip
, SD_CHECK_MODE
, func_group
,
1222 func_to_switch
, bus_width
);
1223 if (retval
== STATUS_SUCCESS
) {
1226 retval
= sd_check_switch_mode(chip
, SD_SWITCH_MODE
,
1227 func_group
, func_to_switch
, bus_width
);
1228 if (retval
== STATUS_SUCCESS
) {
1233 RTSX_READ_REG(chip
, SD_STAT1
, &stat
);
1234 if (stat
& SD_CRC16_ERR
) {
1235 RTSX_DEBUGP("SD CRC16 error when switching mode\n");
1236 TRACE_RET(chip
, STATUS_FAIL
);
1240 func_to_switch
= downgrade_switch_mode(func_group
, func_to_switch
);
1246 TRACE_RET(chip
, STATUS_FAIL
);
1249 return STATUS_SUCCESS
;
1252 static int sd_switch_function(struct rtsx_chip
*chip
, u8 bus_width
)
1254 struct sd_info
*sd_card
= &(chip
->sd_card
);
1257 u8 func_to_switch
= 0;
1259 /* Get supported functions */
1260 retval
= sd_check_switch_mode(chip
, SD_CHECK_MODE
,
1261 NO_ARGUMENT
, NO_ARGUMENT
, bus_width
);
1262 if (retval
!= STATUS_SUCCESS
) {
1263 TRACE_RET(chip
, STATUS_FAIL
);
1266 sd_card
->func_group1_mask
&= ~(sd_card
->sd_switch_fail
);
1268 /* Function Group 1: Access Mode */
1269 for (i
= 0; i
< 4; i
++) {
1270 switch ((u8
)(chip
->sd_speed_prior
>> (i
*8))) {
1271 case SDR104_SUPPORT
:
1272 if ((sd_card
->func_group1_mask
& SDR104_SUPPORT_MASK
)
1273 && chip
->sdr104_en
) {
1274 func_to_switch
= SDR104_SUPPORT
;
1279 if ((sd_card
->func_group1_mask
& DDR50_SUPPORT_MASK
)
1280 && chip
->ddr50_en
) {
1281 func_to_switch
= DDR50_SUPPORT
;
1286 if ((sd_card
->func_group1_mask
& SDR50_SUPPORT_MASK
)
1287 && chip
->sdr50_en
) {
1288 func_to_switch
= SDR50_SUPPORT
;
1293 if (sd_card
->func_group1_mask
& HS_SUPPORT_MASK
) {
1294 func_to_switch
= HS_SUPPORT
;
1303 if (func_to_switch
) {
1307 RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch
);
1309 #ifdef SUPPORT_SD_LOCK
1310 if ((sd_card
->sd_lock_status
& SD_SDR_RST
)
1311 && (DDR50_SUPPORT
== func_to_switch
)
1312 && (sd_card
->func_group1_mask
& SDR50_SUPPORT_MASK
)) {
1313 func_to_switch
= SDR50_SUPPORT
;
1314 RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n");
1318 if (func_to_switch
) {
1319 retval
= sd_check_switch(chip
, SD_FUNC_GROUP_1
, func_to_switch
, bus_width
);
1320 if (retval
!= STATUS_SUCCESS
) {
1321 if (func_to_switch
== SDR104_SUPPORT
) {
1322 sd_card
->sd_switch_fail
= SDR104_SUPPORT_MASK
;
1323 } else if (func_to_switch
== DDR50_SUPPORT
) {
1324 sd_card
->sd_switch_fail
=
1325 SDR104_SUPPORT_MASK
| DDR50_SUPPORT_MASK
;
1326 } else if (func_to_switch
== SDR50_SUPPORT
) {
1327 sd_card
->sd_switch_fail
=
1328 SDR104_SUPPORT_MASK
| DDR50_SUPPORT_MASK
|
1331 TRACE_RET(chip
, STATUS_FAIL
);
1334 if (func_to_switch
== SDR104_SUPPORT
) {
1335 SET_SD_SDR104(sd_card
);
1336 } else if (func_to_switch
== DDR50_SUPPORT
) {
1337 SET_SD_DDR50(sd_card
);
1338 } else if (func_to_switch
== SDR50_SUPPORT
) {
1339 SET_SD_SDR50(sd_card
);
1345 if (CHK_SD_DDR50(sd_card
)) {
1346 RTSX_WRITE_REG(chip
, SD_PUSH_POINT_CTL
, 0x06, 0x04);
1347 retval
= sd_set_sample_push_timing(chip
);
1348 if (retval
!= STATUS_SUCCESS
) {
1349 TRACE_RET(chip
, STATUS_FAIL
);
1353 if (!func_to_switch
|| (func_to_switch
== HS_SUPPORT
)) {
1354 /* Do not try to switch current limit if the card doesn't
1355 * support UHS mode or we don't want it to support UHS mode
1357 return STATUS_SUCCESS
;
1360 /* Function Group 4: Current Limit */
1361 func_to_switch
= 0xFF;
1363 for (i
= 0; i
< 4; i
++) {
1364 switch ((u8
)(chip
->sd_current_prior
>> (i
*8))) {
1365 case CURRENT_LIMIT_800
:
1366 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_800_MASK
) {
1367 func_to_switch
= CURRENT_LIMIT_800
;
1371 case CURRENT_LIMIT_600
:
1372 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_600_MASK
) {
1373 func_to_switch
= CURRENT_LIMIT_600
;
1377 case CURRENT_LIMIT_400
:
1378 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_400_MASK
) {
1379 func_to_switch
= CURRENT_LIMIT_400
;
1383 case CURRENT_LIMIT_200
:
1384 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_200_MASK
) {
1385 func_to_switch
= CURRENT_LIMIT_200
;
1393 if (func_to_switch
!= 0xFF) {
1398 RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch
);
1400 if (func_to_switch
<= CURRENT_LIMIT_800
) {
1401 retval
= sd_check_switch(chip
, SD_FUNC_GROUP_4
, func_to_switch
, bus_width
);
1402 if (retval
!= STATUS_SUCCESS
) {
1403 if (sd_check_err_code(chip
, SD_NO_CARD
)) {
1404 TRACE_RET(chip
, STATUS_FAIL
);
1407 RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval
);
1410 if (CHK_SD_DDR50(sd_card
)) {
1411 RTSX_WRITE_REG(chip
, SD_PUSH_POINT_CTL
, 0x06, 0);
1414 return STATUS_SUCCESS
;
1417 static int sd_wait_data_idle(struct rtsx_chip
*chip
)
1419 int retval
= STATUS_TIMEDOUT
;
1423 for (i
= 0; i
< 100; i
++) {
1424 RTSX_READ_REG(chip
, SD_DATA_STATE
, &val
);
1425 if (val
& SD_DATA_IDLE
) {
1426 retval
= STATUS_SUCCESS
;
1431 RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val
);
1436 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1441 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1442 if (retval
!= STATUS_SUCCESS
) {
1443 TRACE_RET(chip
, STATUS_FAIL
);
1446 cmd
[0] = 0x40 | SEND_TUNING_PATTERN
;
1452 retval
= sd_read_data(chip
, SD_TM_AUTO_TUNING
,
1453 cmd
, 5, 0x40, 1, SD_BUS_WIDTH_4
, NULL
, 0, 100);
1454 if (retval
!= STATUS_SUCCESS
) {
1455 (void)sd_wait_data_idle(chip
);
1457 rtsx_clear_sd_error(chip
);
1458 TRACE_RET(chip
, STATUS_FAIL
);
1461 return STATUS_SUCCESS
;
1464 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1466 struct sd_info
*sd_card
= &(chip
->sd_card
);
1470 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1471 if (retval
!= STATUS_SUCCESS
) {
1472 TRACE_RET(chip
, STATUS_FAIL
);
1475 RTSX_DEBUGP("sd ddr tuning rx\n");
1477 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
1478 if (retval
!= STATUS_SUCCESS
) {
1479 TRACE_RET(chip
, STATUS_FAIL
);
1482 cmd
[0] = 0x40 | SD_STATUS
;
1488 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
,
1489 cmd
, 5, 64, 1, SD_BUS_WIDTH_4
, NULL
, 0, 100);
1490 if (retval
!= STATUS_SUCCESS
) {
1491 (void)sd_wait_data_idle(chip
);
1493 rtsx_clear_sd_error(chip
);
1494 TRACE_RET(chip
, STATUS_FAIL
);
1497 return STATUS_SUCCESS
;
1500 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1502 struct sd_info
*sd_card
= &(chip
->sd_card
);
1504 u8 cmd
[5], bus_width
;
1506 if (CHK_MMC_8BIT(sd_card
)) {
1507 bus_width
= SD_BUS_WIDTH_8
;
1508 } else if (CHK_MMC_4BIT(sd_card
)) {
1509 bus_width
= SD_BUS_WIDTH_4
;
1511 bus_width
= SD_BUS_WIDTH_1
;
1514 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1515 if (retval
!= STATUS_SUCCESS
) {
1516 TRACE_RET(chip
, STATUS_FAIL
);
1519 RTSX_DEBUGP("mmc ddr tuning rx\n");
1521 cmd
[0] = 0x40 | SEND_EXT_CSD
;
1527 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
,
1528 cmd
, 5, 0x200, 1, bus_width
, NULL
, 0, 100);
1529 if (retval
!= STATUS_SUCCESS
) {
1530 (void)sd_wait_data_idle(chip
);
1532 rtsx_clear_sd_error(chip
);
1533 TRACE_RET(chip
, STATUS_FAIL
);
1536 return STATUS_SUCCESS
;
1539 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1541 struct sd_info
*sd_card
= &(chip
->sd_card
);
1544 retval
= sd_change_phase(chip
, sample_point
, TUNE_TX
);
1545 if (retval
!= STATUS_SUCCESS
) {
1546 TRACE_RET(chip
, STATUS_FAIL
);
1549 RTSX_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, SD_RSP_80CLK_TIMEOUT_EN
);
1551 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
1552 SD_RSP_TYPE_R1
, NULL
, 0);
1553 if (retval
!= STATUS_SUCCESS
) {
1554 if (sd_check_err_code(chip
, SD_RSP_TIMEOUT
)) {
1555 rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1556 TRACE_RET(chip
, STATUS_FAIL
);
1560 RTSX_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1562 return STATUS_SUCCESS
;
1565 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1567 struct sd_info
*sd_card
= &(chip
->sd_card
);
1569 u8 cmd
[5], bus_width
;
1571 retval
= sd_change_phase(chip
, sample_point
, TUNE_TX
);
1572 if (retval
!= STATUS_SUCCESS
) {
1573 TRACE_RET(chip
, STATUS_FAIL
);
1576 if (CHK_SD(sd_card
)) {
1577 bus_width
= SD_BUS_WIDTH_4
;
1579 if (CHK_MMC_8BIT(sd_card
)) {
1580 bus_width
= SD_BUS_WIDTH_8
;
1581 } else if (CHK_MMC_4BIT(sd_card
)) {
1582 bus_width
= SD_BUS_WIDTH_4
;
1584 bus_width
= SD_BUS_WIDTH_1
;
1588 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
1589 if (retval
!= STATUS_SUCCESS
) {
1590 TRACE_RET(chip
, STATUS_FAIL
);
1593 RTSX_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, SD_RSP_80CLK_TIMEOUT_EN
);
1595 cmd
[0] = 0x40 | PROGRAM_CSD
;
1601 retval
= sd_write_data(chip
, SD_TM_AUTO_WRITE_2
,
1602 cmd
, 5, 16, 1, bus_width
, sd_card
->raw_csd
, 16, 100);
1603 if (retval
!= STATUS_SUCCESS
) {
1604 rtsx_clear_sd_error(chip
);
1605 rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1606 TRACE_RET(chip
, STATUS_FAIL
);
1609 RTSX_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1611 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
1613 return STATUS_SUCCESS
;
1616 static u8
sd_search_final_phase(struct rtsx_chip
*chip
, u32 phase_map
, u8 tune_dir
)
1618 struct sd_info
*sd_card
= &(chip
->sd_card
);
1619 struct timing_phase_path path
[MAX_PHASE
+ 1];
1620 int i
, j
, cont_path_cnt
;
1621 int new_block
, max_len
, final_path_idx
;
1622 u8 final_phase
= 0xFF;
1624 if (phase_map
== 0xFFFFFFFF) {
1625 if (tune_dir
== TUNE_RX
) {
1626 final_phase
= (u8
)chip
->sd_default_rx_phase
;
1628 final_phase
= (u8
)chip
->sd_default_tx_phase
;
1637 for (i
= 0; i
< MAX_PHASE
+ 1; i
++) {
1638 if (phase_map
& (1 << i
)) {
1641 j
= cont_path_cnt
++;
1649 if (cont_path_cnt
) {
1650 int idx
= cont_path_cnt
- 1;
1651 path
[idx
].len
= path
[idx
].end
- path
[idx
].start
+ 1;
1652 path
[idx
].mid
= path
[idx
].start
+ path
[idx
].len
/ 2;
1657 if (cont_path_cnt
== 0) {
1658 RTSX_DEBUGP("No continuous phase path\n");
1661 int idx
= cont_path_cnt
- 1;
1662 path
[idx
].len
= path
[idx
].end
- path
[idx
].start
+ 1;
1663 path
[idx
].mid
= path
[idx
].start
+ path
[idx
].len
/ 2;
1666 if ((path
[0].start
== 0) && (path
[cont_path_cnt
- 1].end
== MAX_PHASE
)) {
1667 path
[0].start
= path
[cont_path_cnt
- 1].start
- MAX_PHASE
- 1;
1668 path
[0].len
+= path
[cont_path_cnt
- 1].len
;
1669 path
[0].mid
= path
[0].start
+ path
[0].len
/ 2;
1670 if (path
[0].mid
< 0) {
1671 path
[0].mid
+= MAX_PHASE
+ 1;
1679 for (i
= 0; i
< cont_path_cnt
; i
++) {
1680 if (path
[i
].len
> max_len
) {
1681 max_len
= path
[i
].len
;
1682 final_phase
= (u8
)path
[i
].mid
;
1686 RTSX_DEBUGP("path[%d].start = %d\n", i
, path
[i
].start
);
1687 RTSX_DEBUGP("path[%d].end = %d\n", i
, path
[i
].end
);
1688 RTSX_DEBUGP("path[%d].len = %d\n", i
, path
[i
].len
);
1689 RTSX_DEBUGP("path[%d].mid = %d\n", i
, path
[i
].mid
);
1693 if (tune_dir
== TUNE_TX
) {
1694 if (CHK_SD_SDR104(sd_card
)) {
1696 int temp_mid
= (max_len
- 16) / 2;
1697 int temp_final_phase
=
1698 path
[final_path_idx
].end
- (max_len
- (6 + temp_mid
));
1700 if (temp_final_phase
< 0) {
1701 final_phase
= (u8
)(temp_final_phase
+ MAX_PHASE
+ 1);
1703 final_phase
= (u8
)temp_final_phase
;
1706 } else if (CHK_SD_SDR50(sd_card
)) {
1708 int temp_mid
= (max_len
- 13) / 2;
1709 int temp_final_phase
=
1710 path
[final_path_idx
].end
- (max_len
- (3 + temp_mid
));
1712 if (temp_final_phase
< 0) {
1713 final_phase
= (u8
)(temp_final_phase
+ MAX_PHASE
+ 1);
1715 final_phase
= (u8
)temp_final_phase
;
1722 RTSX_DEBUGP("Final chosen phase: %d\n", final_phase
);
1726 static int sd_tuning_rx(struct rtsx_chip
*chip
)
1728 struct sd_info
*sd_card
= &(chip
->sd_card
);
1731 u32 raw_phase_map
[3], phase_map
;
1733 int (*tuning_cmd
)(struct rtsx_chip
*chip
, u8 sample_point
);
1735 if (CHK_SD(sd_card
)) {
1736 if (CHK_SD_DDR50(sd_card
)) {
1737 tuning_cmd
= sd_ddr_tuning_rx_cmd
;
1739 tuning_cmd
= sd_sdr_tuning_rx_cmd
;
1742 if (CHK_MMC_DDR52(sd_card
)) {
1743 tuning_cmd
= mmc_ddr_tunning_rx_cmd
;
1745 TRACE_RET(chip
, STATUS_FAIL
);
1749 for (i
= 0; i
< 3; i
++) {
1750 raw_phase_map
[i
] = 0;
1751 for (j
= MAX_PHASE
; j
>= 0; j
--) {
1752 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
1753 sd_set_err_code(chip
, SD_NO_CARD
);
1754 TRACE_RET(chip
, STATUS_FAIL
);
1757 retval
= tuning_cmd(chip
, (u8
)j
);
1758 if (retval
== STATUS_SUCCESS
) {
1759 raw_phase_map
[i
] |= 1 << j
;
1764 phase_map
= raw_phase_map
[0] & raw_phase_map
[1] & raw_phase_map
[2];
1765 for (i
= 0; i
< 3; i
++) {
1766 RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i
, raw_phase_map
[i
]);
1768 RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map
);
1770 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_RX
);
1771 if (final_phase
== 0xFF) {
1772 TRACE_RET(chip
, STATUS_FAIL
);
1775 retval
= sd_change_phase(chip
, final_phase
, TUNE_RX
);
1776 if (retval
!= STATUS_SUCCESS
) {
1777 TRACE_RET(chip
, STATUS_FAIL
);
1780 return STATUS_SUCCESS
;
1783 static int sd_ddr_pre_tuning_tx(struct rtsx_chip
*chip
)
1785 struct sd_info
*sd_card
= &(chip
->sd_card
);
1791 RTSX_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, SD_RSP_80CLK_TIMEOUT_EN
);
1794 for (i
= MAX_PHASE
; i
>= 0; i
--) {
1795 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
1796 sd_set_err_code(chip
, SD_NO_CARD
);
1797 rtsx_write_register(chip
, SD_CFG3
,
1798 SD_RSP_80CLK_TIMEOUT_EN
, 0);
1799 TRACE_RET(chip
, STATUS_FAIL
);
1802 retval
= sd_change_phase(chip
, (u8
)i
, TUNE_TX
);
1803 if (retval
!= STATUS_SUCCESS
) {
1807 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
1808 SD_RSP_TYPE_R1
, NULL
, 0);
1809 if ((retval
== STATUS_SUCCESS
) || !sd_check_err_code(chip
, SD_RSP_TIMEOUT
)) {
1810 phase_map
|= 1 << i
;
1814 RTSX_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1816 RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map
);
1818 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_TX
);
1819 if (final_phase
== 0xFF) {
1820 TRACE_RET(chip
, STATUS_FAIL
);
1823 retval
= sd_change_phase(chip
, final_phase
, TUNE_TX
);
1824 if (retval
!= STATUS_SUCCESS
) {
1825 TRACE_RET(chip
, STATUS_FAIL
);
1828 RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase
);
1830 return STATUS_SUCCESS
;
1833 static int sd_tuning_tx(struct rtsx_chip
*chip
)
1835 struct sd_info
*sd_card
= &(chip
->sd_card
);
1838 u32 raw_phase_map
[3], phase_map
;
1840 int (*tuning_cmd
)(struct rtsx_chip
*chip
, u8 sample_point
);
1842 if (CHK_SD(sd_card
)) {
1843 if (CHK_SD_DDR50(sd_card
)) {
1844 tuning_cmd
= sd_ddr_tuning_tx_cmd
;
1846 tuning_cmd
= sd_sdr_tuning_tx_cmd
;
1849 if (CHK_MMC_DDR52(sd_card
)) {
1850 tuning_cmd
= sd_ddr_tuning_tx_cmd
;
1852 TRACE_RET(chip
, STATUS_FAIL
);
1856 for (i
= 0; i
< 3; i
++) {
1857 raw_phase_map
[i
] = 0;
1858 for (j
= MAX_PHASE
; j
>= 0; j
--) {
1859 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
1860 sd_set_err_code(chip
, SD_NO_CARD
);
1861 rtsx_write_register(chip
, SD_CFG3
,
1862 SD_RSP_80CLK_TIMEOUT_EN
, 0);
1863 TRACE_RET(chip
, STATUS_FAIL
);
1866 retval
= tuning_cmd(chip
, (u8
)j
);
1867 if (retval
== STATUS_SUCCESS
) {
1868 raw_phase_map
[i
] |= 1 << j
;
1873 phase_map
= raw_phase_map
[0] & raw_phase_map
[1] & raw_phase_map
[2];
1874 for (i
= 0; i
< 3; i
++) {
1875 RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", i
, raw_phase_map
[i
]);
1877 RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map
);
1879 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_TX
);
1880 if (final_phase
== 0xFF) {
1881 TRACE_RET(chip
, STATUS_FAIL
);
1884 retval
= sd_change_phase(chip
, final_phase
, TUNE_TX
);
1885 if (retval
!= STATUS_SUCCESS
) {
1886 TRACE_RET(chip
, STATUS_FAIL
);
1889 return STATUS_SUCCESS
;
1892 static int sd_sdr_tuning(struct rtsx_chip
*chip
)
1896 retval
= sd_tuning_tx(chip
);
1897 if (retval
!= STATUS_SUCCESS
) {
1898 TRACE_RET(chip
, STATUS_FAIL
);
1901 retval
= sd_tuning_rx(chip
);
1902 if (retval
!= STATUS_SUCCESS
) {
1903 TRACE_RET(chip
, STATUS_FAIL
);
1906 return STATUS_SUCCESS
;
1909 static int sd_ddr_tuning(struct rtsx_chip
*chip
)
1913 if (!(chip
->sd_ctl
& SD_DDR_TX_PHASE_SET_BY_USER
)) {
1914 retval
= sd_ddr_pre_tuning_tx(chip
);
1915 if (retval
!= STATUS_SUCCESS
) {
1916 TRACE_RET(chip
, STATUS_FAIL
);
1919 retval
= sd_change_phase(chip
, (u8
)chip
->sd_ddr_tx_phase
, TUNE_TX
);
1920 if (retval
!= STATUS_SUCCESS
) {
1921 TRACE_RET(chip
, STATUS_FAIL
);
1925 retval
= sd_tuning_rx(chip
);
1926 if (retval
!= STATUS_SUCCESS
) {
1927 TRACE_RET(chip
, STATUS_FAIL
);
1930 if (!(chip
->sd_ctl
& SD_DDR_TX_PHASE_SET_BY_USER
)) {
1931 retval
= sd_tuning_tx(chip
);
1932 if (retval
!= STATUS_SUCCESS
) {
1933 TRACE_RET(chip
, STATUS_FAIL
);
1937 return STATUS_SUCCESS
;
1940 static int mmc_ddr_tuning(struct rtsx_chip
*chip
)
1944 if (!(chip
->sd_ctl
& MMC_DDR_TX_PHASE_SET_BY_USER
)) {
1945 retval
= sd_ddr_pre_tuning_tx(chip
);
1946 if (retval
!= STATUS_SUCCESS
) {
1947 TRACE_RET(chip
, STATUS_FAIL
);
1950 retval
= sd_change_phase(chip
, (u8
)chip
->mmc_ddr_tx_phase
, TUNE_TX
);
1951 if (retval
!= STATUS_SUCCESS
) {
1952 TRACE_RET(chip
, STATUS_FAIL
);
1956 retval
= sd_tuning_rx(chip
);
1957 if (retval
!= STATUS_SUCCESS
) {
1958 TRACE_RET(chip
, STATUS_FAIL
);
1961 if (!(chip
->sd_ctl
& MMC_DDR_TX_PHASE_SET_BY_USER
)) {
1962 retval
= sd_tuning_tx(chip
);
1963 if (retval
!= STATUS_SUCCESS
) {
1964 TRACE_RET(chip
, STATUS_FAIL
);
1968 return STATUS_SUCCESS
;
1971 int sd_switch_clock(struct rtsx_chip
*chip
)
1973 struct sd_info
*sd_card
= &(chip
->sd_card
);
1977 retval
= select_card(chip
, SD_CARD
);
1978 if (retval
!= STATUS_SUCCESS
) {
1979 TRACE_RET(chip
, STATUS_FAIL
);
1982 if (CHECK_PID(chip
, 0x5209) &&
1983 (CHK_SD30_SPEED(sd_card
) || CHK_MMC_DDR52(sd_card
))) {
1984 if (sd_card
->need_retune
&& (sd_card
->sd_clock
!= chip
->cur_clk
)) {
1986 sd_card
->need_retune
= 0;
1990 retval
= switch_clock(chip
, sd_card
->sd_clock
);
1991 if (retval
!= STATUS_SUCCESS
) {
1992 TRACE_RET(chip
, STATUS_FAIL
);
1996 if (CHK_SD(sd_card
)) {
1997 if (CHK_SD_DDR50(sd_card
)) {
1998 retval
= sd_ddr_tuning(chip
);
2000 retval
= sd_sdr_tuning(chip
);
2003 if (CHK_MMC_DDR52(sd_card
)) {
2004 retval
= mmc_ddr_tuning(chip
);
2008 if (retval
!= STATUS_SUCCESS
) {
2009 TRACE_RET(chip
, STATUS_FAIL
);
2013 return STATUS_SUCCESS
;
2016 static int sd_prepare_reset(struct rtsx_chip
*chip
)
2018 struct sd_info
*sd_card
= &(chip
->sd_card
);
2021 if (chip
->asic_code
) {
2022 sd_card
->sd_clock
= 29;
2024 sd_card
->sd_clock
= CLK_30
;
2027 sd_card
->sd_type
= 0;
2028 sd_card
->seq_mode
= 0;
2029 sd_card
->sd_data_buf_ready
= 0;
2030 sd_card
->capacity
= 0;
2032 #ifdef SUPPORT_SD_LOCK
2033 sd_card
->sd_lock_status
= 0;
2034 sd_card
->sd_erase_status
= 0;
2037 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
2040 retval
= sd_set_init_para(chip
);
2041 if (retval
!= STATUS_SUCCESS
) {
2042 TRACE_RET(chip
, retval
);
2045 if (CHECK_PID(chip
, 0x5209)) {
2046 RTSX_WRITE_REG(chip
, REG_SD_CFG1
, 0xFF,
2047 SD_CLK_DIVIDE_128
| SD_20_MODE
| SD_BUS_WIDTH_1
);
2048 RTSX_WRITE_REG(chip
, SD_SAMPLE_POINT_CTL
, 0xFF, SD20_RX_POS_EDGE
);
2049 RTSX_WRITE_REG(chip
, SD_PUSH_POINT_CTL
, 0xFF, 0);
2051 RTSX_WRITE_REG(chip
, REG_SD_CFG1
, 0xFF, 0x40);
2054 RTSX_WRITE_REG(chip
, CARD_STOP
, SD_STOP
| SD_CLR_ERR
, SD_STOP
| SD_CLR_ERR
);
2056 retval
= select_card(chip
, SD_CARD
);
2057 if (retval
!= STATUS_SUCCESS
) {
2058 TRACE_RET(chip
, STATUS_FAIL
);
2061 return STATUS_SUCCESS
;
2064 static int sd_pull_ctl_disable(struct rtsx_chip
*chip
)
2066 if (CHECK_PID(chip
, 0x5209)) {
2067 RTSX_WRITE_REG(chip
, CARD_PULL_CTL1
, 0xFF, 0x55);
2068 RTSX_WRITE_REG(chip
, CARD_PULL_CTL2
, 0xFF, 0x55);
2069 RTSX_WRITE_REG(chip
, CARD_PULL_CTL3
, 0xFF, 0xD5);
2070 } else if (CHECK_PID(chip
, 0x5208)) {
2071 RTSX_WRITE_REG(chip
, CARD_PULL_CTL1
, 0xFF,
2072 XD_D3_PD
| SD_D7_PD
| SD_CLK_PD
| SD_D5_PD
);
2073 RTSX_WRITE_REG(chip
, CARD_PULL_CTL2
, 0xFF,
2074 SD_D6_PD
| SD_D0_PD
| SD_D1_PD
| XD_D5_PD
);
2075 RTSX_WRITE_REG(chip
, CARD_PULL_CTL3
, 0xFF,
2076 SD_D4_PD
| XD_CE_PD
| XD_CLE_PD
| XD_CD_PU
);
2077 RTSX_WRITE_REG(chip
, CARD_PULL_CTL4
, 0xFF,
2078 XD_RDY_PD
| SD_D3_PD
| SD_D2_PD
| XD_ALE_PD
);
2079 RTSX_WRITE_REG(chip
, CARD_PULL_CTL5
, 0xFF,
2080 MS_INS_PU
| SD_WP_PD
| SD_CD_PU
| SD_CMD_PD
);
2081 RTSX_WRITE_REG(chip
, CARD_PULL_CTL6
, 0xFF, MS_D5_PD
| MS_D4_PD
);
2082 } else if (CHECK_PID(chip
, 0x5288)) {
2083 if (CHECK_BARO_PKG(chip
, QFN
)) {
2084 RTSX_WRITE_REG(chip
, CARD_PULL_CTL1
, 0xFF, 0x55);
2085 RTSX_WRITE_REG(chip
, CARD_PULL_CTL2
, 0xFF, 0x55);
2086 RTSX_WRITE_REG(chip
, CARD_PULL_CTL3
, 0xFF, 0x4B);
2087 RTSX_WRITE_REG(chip
, CARD_PULL_CTL4
, 0xFF, 0x69);
2091 return STATUS_SUCCESS
;
2094 int sd_pull_ctl_enable(struct rtsx_chip
*chip
)
2098 rtsx_init_cmd(chip
);
2100 if (CHECK_PID(chip
, 0x5209)) {
2101 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF, 0xAA);
2102 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF, 0xAA);
2103 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF, 0xE9);
2104 } else if (CHECK_PID(chip
, 0x5208)) {
2105 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF,
2106 XD_D3_PD
| SD_DAT7_PU
| SD_CLK_NP
| SD_D5_PU
);
2107 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF,
2108 SD_D6_PU
| SD_D0_PU
| SD_D1_PU
| XD_D5_PD
);
2109 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF,
2110 SD_D4_PU
| XD_CE_PD
| XD_CLE_PD
| XD_CD_PU
);
2111 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF,
2112 XD_RDY_PD
| SD_D3_PU
| SD_D2_PU
| XD_ALE_PD
);
2113 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL5
, 0xFF,
2114 MS_INS_PU
| SD_WP_PU
| SD_CD_PU
| SD_CMD_PU
);
2115 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL6
, 0xFF, MS_D5_PD
| MS_D4_PD
);
2116 } else if (CHECK_PID(chip
, 0x5288)) {
2117 if (CHECK_BARO_PKG(chip
, QFN
)) {
2118 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF, 0xA8);
2119 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF, 0x5A);
2120 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF, 0x95);
2121 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF, 0xAA);
2125 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
2127 TRACE_RET(chip
, STATUS_FAIL
);
2130 return STATUS_SUCCESS
;
2133 static int sd_init_power(struct rtsx_chip
*chip
)
2137 if (CHECK_PID(chip
, 0x5209)) {
2138 RTSX_WRITE_REG(chip
, PWR_GATE_CTRL
, LDO3318_PWR_MASK
, LDO_OFF
);
2141 retval
= sd_power_off_card3v3(chip
);
2142 if (retval
!= STATUS_SUCCESS
) {
2143 TRACE_RET(chip
, STATUS_FAIL
);
2146 if (!chip
->ft2_fast_mode
) {
2150 retval
= enable_card_clock(chip
, SD_CARD
);
2151 if (retval
!= STATUS_SUCCESS
) {
2152 TRACE_RET(chip
, STATUS_FAIL
);
2155 if (chip
->asic_code
) {
2156 retval
= sd_pull_ctl_enable(chip
);
2157 if (retval
!= STATUS_SUCCESS
) {
2158 TRACE_RET(chip
, STATUS_FAIL
);
2161 RTSX_WRITE_REG(chip
, FPGA_PULL_CTL
, FPGA_SD_PULL_CTL_BIT
| 0x20, 0);
2164 if (chip
->ft2_fast_mode
) {
2165 if (CHECK_PID(chip
, 0x5209)) {
2166 RTSX_WRITE_REG(chip
, PWR_GATE_CTRL
, LDO3318_PWR_MASK
, LDO_ON
);
2169 retval
= card_power_on(chip
, SD_CARD
);
2170 if (retval
!= STATUS_SUCCESS
) {
2171 TRACE_RET(chip
, STATUS_FAIL
);
2176 if (chip
->ocp_stat
& (SD_OC_NOW
| SD_OC_EVER
)) {
2177 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip
->ocp_stat
);
2178 TRACE_RET(chip
, STATUS_FAIL
);
2183 RTSX_WRITE_REG(chip
, CARD_OE
, SD_OUTPUT_EN
, SD_OUTPUT_EN
);
2185 return STATUS_SUCCESS
;
2188 static int sd_dummy_clock(struct rtsx_chip
*chip
)
2190 if (CHECK_PID(chip
, 0x5209)) {
2191 RTSX_WRITE_REG(chip
, SD_BUS_STAT
, SD_CLK_TOGGLE_EN
, SD_CLK_TOGGLE_EN
);
2193 RTSX_WRITE_REG(chip
, SD_BUS_STAT
, SD_CLK_TOGGLE_EN
, 0x00);
2195 RTSX_WRITE_REG(chip
, REG_SD_CFG3
, 0x01, 0x01);
2197 RTSX_WRITE_REG(chip
, REG_SD_CFG3
, 0x01, 0);
2200 return STATUS_SUCCESS
;
2203 static int sd_read_lba0(struct rtsx_chip
*chip
)
2205 struct sd_info
*sd_card
= &(chip
->sd_card
);
2207 u8 cmd
[5], bus_width
;
2209 cmd
[0] = 0x40 | READ_SINGLE_BLOCK
;
2215 if (CHK_SD(sd_card
)) {
2216 bus_width
= SD_BUS_WIDTH_4
;
2218 if (CHK_MMC_8BIT(sd_card
)) {
2219 bus_width
= SD_BUS_WIDTH_8
;
2220 } else if (CHK_MMC_4BIT(sd_card
)) {
2221 bus_width
= SD_BUS_WIDTH_4
;
2223 bus_width
= SD_BUS_WIDTH_1
;
2227 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
,
2228 5, 512, 1, bus_width
, NULL
, 0, 100);
2229 if (retval
!= STATUS_SUCCESS
) {
2230 rtsx_clear_sd_error(chip
);
2231 TRACE_RET(chip
, STATUS_FAIL
);
2234 return STATUS_SUCCESS
;
2237 static int sd_check_wp_state(struct rtsx_chip
*chip
)
2239 struct sd_info
*sd_card
= &(chip
->sd_card
);
2245 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
,
2246 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2247 if (retval
!= STATUS_SUCCESS
) {
2248 TRACE_RET(chip
, STATUS_FAIL
);
2251 cmd
[0] = 0x40 | SD_STATUS
;
2257 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 64, 1, SD_BUS_WIDTH_4
, buf
, 64, 250);
2258 if (retval
!= STATUS_SUCCESS
) {
2259 rtsx_clear_sd_error(chip
);
2261 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2262 TRACE_RET(chip
, STATUS_FAIL
);
2265 RTSX_DEBUGP("ACMD13:\n");
2268 sd_card_type
= ((u16
)buf
[2] << 8) | buf
[3];
2269 RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type
);
2270 if ((sd_card_type
== 0x0001) || (sd_card_type
== 0x0002)) {
2271 /* ROM card or OTP */
2272 chip
->card_wp
|= SD_CARD
;
2275 /* Check SD Machanical Write-Protect Switch */
2276 val
= rtsx_readl(chip
, RTSX_BIPR
);
2277 if (val
& SD_WRITE_PROTECT
) {
2278 chip
->card_wp
|= SD_CARD
;
2281 return STATUS_SUCCESS
;
2284 static int reset_sd(struct rtsx_chip
*chip
)
2286 struct sd_info
*sd_card
= &(chip
->sd_card
);
2287 int retval
, i
= 0, j
= 0, k
= 0, hi_cap_flow
= 0;
2288 int sd_dont_switch
= 0;
2289 int support_1v8
= 0;
2292 u8 switch_bus_width
;
2305 #ifdef SUPPORT_SD_LOCK
2306 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
)
2307 goto SD_UNLOCK_ENTRY
;
2310 retval
= sd_prepare_reset(chip
);
2311 if (retval
!= STATUS_SUCCESS
) {
2312 TRACE_RET(chip
, STATUS_FAIL
);
2315 retval
= sd_dummy_clock(chip
);
2316 if (retval
!= STATUS_SUCCESS
) {
2317 TRACE_RET(chip
, STATUS_FAIL
);
2320 if (CHK_SDIO_EXIST(chip
) && !CHK_SDIO_IGNORED(chip
) && try_sdio
) {
2323 for (; rty_cnt
< chip
->sdio_retry_cnt
; rty_cnt
++) {
2324 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
2325 sd_set_err_code(chip
, SD_NO_CARD
);
2326 TRACE_RET(chip
, STATUS_FAIL
);
2329 retval
= sd_send_cmd_get_rsp(chip
, IO_SEND_OP_COND
, 0, SD_RSP_TYPE_R4
, rsp
, 5);
2330 if (retval
== STATUS_SUCCESS
) {
2331 int func_num
= (rsp
[1] >> 4) & 0x07;
2333 RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num
);
2335 TRACE_RET(chip
, STATUS_FAIL
);
2341 sd_init_power(chip
);
2343 sd_dummy_clock(chip
);
2346 RTSX_DEBUGP("Normal card!\n");
2349 /* Start Initialization Process of SD Card */
2351 retval
= sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
, NULL
, 0);
2352 if (retval
!= STATUS_SUCCESS
) {
2353 TRACE_RET(chip
, STATUS_FAIL
);
2358 retval
= sd_send_cmd_get_rsp(chip
, SEND_IF_COND
, 0x000001AA, SD_RSP_TYPE_R7
, rsp
, 5);
2359 if (retval
== STATUS_SUCCESS
) {
2360 if ((rsp
[4] == 0xAA) && ((rsp
[3] & 0x0f) == 0x01)) {
2362 if (CHECK_PID(chip
, 0x5209)) {
2364 voltage
= SUPPORT_VOLTAGE
|
2365 SUPPORT_HIGH_AND_EXTENDED_CAPACITY
;
2367 voltage
= SUPPORT_VOLTAGE
|
2368 SUPPORT_HIGH_AND_EXTENDED_CAPACITY
|
2369 SUPPORT_MAX_POWER_PERMANCE
| SUPPORT_1V8
;
2372 voltage
= SUPPORT_VOLTAGE
| 0x40000000;
2378 voltage
= SUPPORT_VOLTAGE
;
2380 retval
= sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
, NULL
, 0);
2381 if (retval
!= STATUS_SUCCESS
) {
2382 TRACE_RET(chip
, STATUS_FAIL
);
2389 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, 0, SD_RSP_TYPE_R1
, NULL
, 0);
2390 if (retval
!= STATUS_SUCCESS
) {
2391 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
2392 sd_set_err_code(chip
, SD_NO_CARD
);
2393 TRACE_RET(chip
, STATUS_FAIL
);
2400 TRACE_RET(chip
, STATUS_FAIL
);
2404 retval
= sd_send_cmd_get_rsp(chip
, SD_APP_OP_COND
, voltage
, SD_RSP_TYPE_R3
, rsp
, 5);
2405 if (retval
!= STATUS_SUCCESS
) {
2410 TRACE_RET(chip
, STATUS_FAIL
);
2416 } while (!(rsp
[1] & 0x80) && (i
< 255));
2419 TRACE_RET(chip
, STATUS_FAIL
);
2423 if (rsp
[1] & 0x40) {
2424 SET_SD_HCXC(sd_card
);
2426 CLR_SD_HCXC(sd_card
);
2428 if (CHECK_PID(chip
, 0x5209) && CHK_SD_HCXC(sd_card
) && !sd20_mode
) {
2429 support_1v8
= (rsp
[1] & 0x01) ? 1 : 0;
2434 CLR_SD_HCXC(sd_card
);
2437 RTSX_DEBUGP("support_1v8 = %d\n", support_1v8
);
2440 retval
= sd_voltage_switch(chip
);
2441 if (retval
!= STATUS_SUCCESS
) {
2442 TRACE_RET(chip
, STATUS_FAIL
);
2446 retval
= sd_send_cmd_get_rsp(chip
, ALL_SEND_CID
, 0, SD_RSP_TYPE_R2
, NULL
, 0);
2447 if (retval
!= STATUS_SUCCESS
) {
2448 TRACE_RET(chip
, STATUS_FAIL
);
2451 for (i
= 0; i
< 3; i
++) {
2452 retval
= sd_send_cmd_get_rsp(chip
, SEND_RELATIVE_ADDR
, 0, SD_RSP_TYPE_R6
, rsp
, 5);
2453 if (retval
!= STATUS_SUCCESS
) {
2454 TRACE_RET(chip
, STATUS_FAIL
);
2457 sd_card
->sd_addr
= (u32
)rsp
[1] << 24;
2458 sd_card
->sd_addr
+= (u32
)rsp
[2] << 16;
2460 if (sd_card
->sd_addr
) {
2465 retval
= sd_check_csd(chip
, 1);
2466 if (retval
!= STATUS_SUCCESS
) {
2467 TRACE_RET(chip
, STATUS_FAIL
);
2470 retval
= sd_select_card(chip
, 1);
2471 if (retval
!= STATUS_SUCCESS
) {
2472 TRACE_RET(chip
, STATUS_FAIL
);
2475 #ifdef SUPPORT_SD_LOCK
2477 retval
= sd_update_lock_status(chip
);
2478 if (retval
!= STATUS_SUCCESS
) {
2479 TRACE_RET(chip
, STATUS_FAIL
);
2482 if (sd_card
->sd_lock_status
& SD_LOCKED
) {
2483 sd_card
->sd_lock_status
|= (SD_LOCK_1BIT_MODE
| SD_PWD_EXIST
);
2484 return STATUS_SUCCESS
;
2485 } else if (!(sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
)) {
2486 sd_card
->sd_lock_status
&= ~SD_PWD_EXIST
;
2490 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2491 if (retval
!= STATUS_SUCCESS
) {
2492 TRACE_RET(chip
, STATUS_FAIL
);
2494 retval
= sd_send_cmd_get_rsp(chip
, SET_CLR_CARD_DETECT
, 0, SD_RSP_TYPE_R1
, NULL
, 0);
2495 if (retval
!= STATUS_SUCCESS
) {
2496 TRACE_RET(chip
, STATUS_FAIL
);
2500 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2501 if (retval
!= STATUS_SUCCESS
) {
2502 TRACE_RET(chip
, STATUS_FAIL
);
2504 retval
= sd_send_cmd_get_rsp(chip
, SET_BUS_WIDTH
, 2, SD_RSP_TYPE_R1
, NULL
, 0);
2505 if (retval
!= STATUS_SUCCESS
) {
2506 TRACE_RET(chip
, STATUS_FAIL
);
2509 switch_bus_width
= SD_BUS_WIDTH_4
;
2511 switch_bus_width
= SD_BUS_WIDTH_1
;
2514 retval
= sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200, SD_RSP_TYPE_R1
, NULL
, 0);
2515 if (retval
!= STATUS_SUCCESS
) {
2516 TRACE_RET(chip
, STATUS_FAIL
);
2519 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
2520 if (retval
!= STATUS_SUCCESS
) {
2521 TRACE_RET(chip
, STATUS_FAIL
);
2524 if (!(sd_card
->raw_csd
[4] & 0x40))
2527 if (!sd_dont_switch
) {
2529 /* Set sd_switch_fail here, because we needn't
2530 * switch to UHS mode
2532 sd_card
->sd_switch_fail
= SDR104_SUPPORT_MASK
|
2533 DDR50_SUPPORT_MASK
| SDR50_SUPPORT_MASK
;
2536 /* Check the card whether follow SD1.1 spec or higher */
2537 retval
= sd_check_spec(chip
, switch_bus_width
);
2538 if (retval
== STATUS_SUCCESS
) {
2539 retval
= sd_switch_function(chip
, switch_bus_width
);
2540 if (retval
!= STATUS_SUCCESS
) {
2541 if (CHECK_PID(chip
, 0x5209)) {
2542 sd_change_bank_voltage(chip
, SD_IO_3V3
);
2544 sd_init_power(chip
);
2552 if (CHECK_PID(chip
, 0x5209)) {
2553 sd_change_bank_voltage(chip
, SD_IO_3V3
);
2555 sd_init_power(chip
);
2565 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2566 if (retval
!= STATUS_SUCCESS
) {
2567 TRACE_RET(chip
, STATUS_FAIL
);
2569 retval
= sd_send_cmd_get_rsp(chip
, SET_BUS_WIDTH
, 2, SD_RSP_TYPE_R1
, NULL
, 0);
2570 if (retval
!= STATUS_SUCCESS
) {
2571 TRACE_RET(chip
, STATUS_FAIL
);
2575 #ifdef SUPPORT_SD_LOCK
2576 sd_card
->sd_lock_status
&= ~SD_LOCK_1BIT_MODE
;
2579 if (!sd20_mode
&& CHK_SD30_SPEED(sd_card
)) {
2582 RTSX_WRITE_REG(chip
, SD30_DRIVE_SEL
, 0x07, chip
->sd30_drive_sel_1v8
);
2584 retval
= sd_set_init_para(chip
);
2585 if (retval
!= STATUS_SUCCESS
) {
2586 TRACE_RET(chip
, STATUS_FAIL
);
2589 if (CHK_SD_DDR50(sd_card
)) {
2590 retval
= sd_ddr_tuning(chip
);
2592 retval
= sd_sdr_tuning(chip
);
2595 if (retval
!= STATUS_SUCCESS
) {
2597 TRACE_RET(chip
, STATUS_FAIL
);
2599 retval
= sd_init_power(chip
);
2600 if (retval
!= STATUS_SUCCESS
) {
2601 TRACE_RET(chip
, STATUS_FAIL
);
2609 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2611 if (CHK_SD_DDR50(sd_card
)) {
2612 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
2613 if (retval
!= STATUS_SUCCESS
) {
2619 retval
= sd_read_lba0(chip
);
2620 if (retval
!= STATUS_SUCCESS
) {
2622 TRACE_RET(chip
, STATUS_FAIL
);
2624 retval
= sd_init_power(chip
);
2625 if (retval
!= STATUS_SUCCESS
) {
2626 TRACE_RET(chip
, STATUS_FAIL
);
2636 retval
= sd_check_wp_state(chip
);
2637 if (retval
!= STATUS_SUCCESS
) {
2638 TRACE_RET(chip
, STATUS_FAIL
);
2641 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 4;
2643 #ifdef SUPPORT_SD_LOCK
2644 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
) {
2645 RTSX_WRITE_REG(chip
, REG_SD_BLOCK_CNT_H
, 0xFF, 0x02);
2646 RTSX_WRITE_REG(chip
, REG_SD_BLOCK_CNT_L
, 0xFF, 0x00);
2650 return STATUS_SUCCESS
;
2654 static int mmc_test_switch_bus(struct rtsx_chip
*chip
, u8 width
)
2656 struct sd_info
*sd_card
= &(chip
->sd_card
);
2658 u8 buf
[8] = {0}, bus_width
, *ptr
;
2662 retval
= sd_send_cmd_get_rsp(chip
, BUSTEST_W
, 0, SD_RSP_TYPE_R1
, NULL
, 0);
2663 if (retval
!= STATUS_SUCCESS
) {
2664 TRACE_RET(chip
, SWITCH_FAIL
);
2667 if (width
== MMC_8BIT_BUS
) {
2672 bus_width
= SD_BUS_WIDTH_8
;
2677 bus_width
= SD_BUS_WIDTH_4
;
2680 if (!CHECK_PID(chip
, 0x5209)) {
2681 retval
= rtsx_write_register(chip
, REG_SD_CFG3
, 0x02, 0x02);
2682 if (retval
!= STATUS_SUCCESS
)
2683 TRACE_RET(chip
, SWITCH_ERR
);
2686 retval
= sd_write_data(chip
, SD_TM_AUTO_WRITE_3
,
2687 NULL
, 0, byte_cnt
, 1, bus_width
, buf
, len
, 100);
2688 if (retval
!= STATUS_SUCCESS
) {
2689 if (CHECK_PID(chip
, 0x5209)) {
2690 u8 val1
= 0, val2
= 0;
2691 rtsx_read_register(chip
, REG_SD_STAT1
, &val1
);
2692 rtsx_read_register(chip
, REG_SD_STAT2
, &val2
);
2693 rtsx_clear_sd_error(chip
);
2694 if ((val1
& 0xE0) || val2
) {
2695 TRACE_RET(chip
, SWITCH_ERR
);
2698 rtsx_clear_sd_error(chip
);
2699 rtsx_write_register(chip
, REG_SD_CFG3
, 0x02, 0);
2700 TRACE_RET(chip
, SWITCH_ERR
);
2704 if (!CHECK_PID(chip
, 0x5209)) {
2705 retval
= rtsx_write_register(chip
, REG_SD_CFG3
, 0x02, 0);
2706 if (retval
!= STATUS_SUCCESS
)
2707 TRACE_RET(chip
, SWITCH_ERR
);
2710 RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R
);
2712 rtsx_init_cmd(chip
);
2714 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | BUSTEST_R
);
2716 if (width
== MMC_8BIT_BUS
) {
2717 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0x08);
2719 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0x04);
2722 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, 1);
2723 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, 0);
2725 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
2726 SD_CALCULATE_CRC7
| SD_NO_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
2727 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
2728 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
2729 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF, SD_TM_NORMAL_READ
| SD_TRANSFER_START
);
2730 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
2732 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
, 0, 0);
2733 if (width
== MMC_8BIT_BUS
) {
2734 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 1, 0, 0);
2737 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
2739 rtsx_clear_sd_error(chip
);
2740 TRACE_RET(chip
, SWITCH_ERR
);
2743 ptr
= rtsx_get_cmd_data(chip
) + 1;
2745 if (width
== MMC_8BIT_BUS
) {
2746 RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr
[0], ptr
[1]);
2747 if ((ptr
[0] == 0xAA) && (ptr
[1] == 0x55)) {
2751 if (CHK_MMC_DDR52(sd_card
)) {
2756 retval
= sd_send_cmd_get_rsp(chip
, SWITCH
, arg
, SD_RSP_TYPE_R1b
, rsp
, 5);
2757 if ((retval
== STATUS_SUCCESS
) && !(rsp
[4] & MMC_SWITCH_ERR
)) {
2758 return SWITCH_SUCCESS
;
2762 RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr
[0]);
2763 if (ptr
[0] == 0xA5) {
2767 if (CHK_MMC_DDR52(sd_card
)) {
2772 retval
= sd_send_cmd_get_rsp(chip
, SWITCH
, arg
, SD_RSP_TYPE_R1b
, rsp
, 5);
2773 if ((retval
== STATUS_SUCCESS
) && !(rsp
[4] & MMC_SWITCH_ERR
)) {
2774 return SWITCH_SUCCESS
;
2779 TRACE_RET(chip
, SWITCH_FAIL
);
2783 static int mmc_switch_timing_bus(struct rtsx_chip
*chip
, int switch_ddr
)
2785 struct sd_info
*sd_card
= &(chip
->sd_card
);
2787 u8
*ptr
, card_type
, card_type_mask
= 0;
2789 CLR_MMC_HS(sd_card
);
2791 RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD
);
2793 rtsx_init_cmd(chip
);
2795 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | SEND_EXT_CSD
);
2796 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, 0);
2797 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, 0);
2798 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, 0);
2799 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, 0);
2801 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0);
2802 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, 2);
2803 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, 1);
2804 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, 0);
2806 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
2807 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
2808 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
2809 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
2810 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF, SD_TM_NORMAL_READ
| SD_TRANSFER_START
);
2811 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
2813 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 196, 0xFF, 0);
2814 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 212, 0xFF, 0);
2815 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 213, 0xFF, 0);
2816 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 214, 0xFF, 0);
2817 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 215, 0xFF, 0);
2819 retval
= rtsx_send_cmd(chip
, SD_CARD
, 1000);
2821 if (retval
== -ETIMEDOUT
) {
2822 rtsx_clear_sd_error(chip
);
2823 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
2824 SD_RSP_TYPE_R1
, NULL
, 0);
2826 TRACE_RET(chip
, STATUS_FAIL
);
2829 ptr
= rtsx_get_cmd_data(chip
);
2830 if (ptr
[0] & SD_TRANSFER_ERR
) {
2831 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2832 TRACE_RET(chip
, STATUS_FAIL
);
2835 if (CHK_MMC_SECTOR_MODE(sd_card
)) {
2836 sd_card
->capacity
= ((u32
)ptr
[5] << 24) | ((u32
)ptr
[4] << 16) |
2837 ((u32
)ptr
[3] << 8) | ((u32
)ptr
[2]);
2840 if (CHECK_PID(chip
, 0x5209)) {
2841 #ifdef SUPPORT_SD_LOCK
2842 if (!(sd_card
->sd_lock_status
& SD_SDR_RST
) &&
2843 (chip
->sd_ctl
& SUPPORT_MMC_DDR_MODE
)) {
2844 card_type_mask
= 0x07;
2846 card_type_mask
= 0x03;
2849 if (chip
->sd_ctl
& SUPPORT_MMC_DDR_MODE
) {
2850 card_type_mask
= 0x07;
2852 card_type_mask
= 0x03;
2856 card_type_mask
= 0x03;
2858 card_type
= ptr
[1] & card_type_mask
;
2862 if (card_type
& 0x04) {
2864 SET_MMC_DDR52(sd_card
);
2866 SET_MMC_52M(sd_card
);
2868 } else if (card_type
& 0x02) {
2869 SET_MMC_52M(sd_card
);
2871 SET_MMC_26M(sd_card
);
2874 retval
= sd_send_cmd_get_rsp(chip
, SWITCH
,
2875 0x03B90100, SD_RSP_TYPE_R1b
, rsp
, 5);
2876 if ((retval
!= STATUS_SUCCESS
) || (rsp
[4] & MMC_SWITCH_ERR
)) {
2877 CLR_MMC_HS(sd_card
);
2881 sd_choose_proper_clock(chip
);
2882 retval
= switch_clock(chip
, sd_card
->sd_clock
);
2883 if (retval
!= STATUS_SUCCESS
) {
2884 TRACE_RET(chip
, STATUS_FAIL
);
2887 /* Test Bus Procedure */
2888 retval
= mmc_test_switch_bus(chip
, MMC_8BIT_BUS
);
2889 if (retval
== SWITCH_SUCCESS
) {
2890 SET_MMC_8BIT(sd_card
);
2891 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 8;
2892 #ifdef SUPPORT_SD_LOCK
2893 sd_card
->sd_lock_status
&= ~SD_LOCK_1BIT_MODE
;
2895 } else if (retval
== SWITCH_FAIL
) {
2896 retval
= mmc_test_switch_bus(chip
, MMC_4BIT_BUS
);
2897 if (retval
== SWITCH_SUCCESS
) {
2898 SET_MMC_4BIT(sd_card
);
2899 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 4;
2900 #ifdef SUPPORT_SD_LOCK
2901 sd_card
->sd_lock_status
&= ~SD_LOCK_1BIT_MODE
;
2903 } else if (retval
== SWITCH_FAIL
) {
2904 CLR_MMC_8BIT(sd_card
);
2905 CLR_MMC_4BIT(sd_card
);
2907 TRACE_RET(chip
, STATUS_FAIL
);
2910 TRACE_RET(chip
, STATUS_FAIL
);
2913 return STATUS_SUCCESS
;
2917 static int reset_mmc(struct rtsx_chip
*chip
)
2919 struct sd_info
*sd_card
= &(chip
->sd_card
);
2920 int retval
, i
= 0, j
= 0, k
= 0;
2926 #ifdef SUPPORT_SD_LOCK
2927 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
)
2928 goto MMC_UNLOCK_ENTRY
;
2932 retval
= sd_prepare_reset(chip
);
2933 if (retval
!= STATUS_SUCCESS
) {
2934 TRACE_RET(chip
, retval
);
2940 retval
= sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
, NULL
, 0);
2941 if (retval
!= STATUS_SUCCESS
) {
2942 TRACE_RET(chip
, STATUS_FAIL
);
2946 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
2947 sd_set_err_code(chip
, SD_NO_CARD
);
2948 TRACE_RET(chip
, STATUS_FAIL
);
2951 retval
= sd_send_cmd_get_rsp(chip
, SEND_OP_COND
,
2952 (SUPPORT_VOLTAGE
|0x40000000), SD_RSP_TYPE_R3
, rsp
, 5);
2953 if (retval
!= STATUS_SUCCESS
) {
2954 if (sd_check_err_code(chip
, SD_BUSY
) || sd_check_err_code(chip
, SD_TO_ERR
)) {
2957 sd_clr_err_code(chip
);
2960 TRACE_RET(chip
, STATUS_FAIL
);
2965 sd_clr_err_code(chip
);
2968 TRACE_RET(chip
, STATUS_FAIL
);
2975 } while (!(rsp
[1] & 0x80) && (i
< 255));
2978 TRACE_RET(chip
, STATUS_FAIL
);
2981 if ((rsp
[1] & 0x60) == 0x40) {
2982 SET_MMC_SECTOR_MODE(sd_card
);
2984 CLR_MMC_SECTOR_MODE(sd_card
);
2987 retval
= sd_send_cmd_get_rsp(chip
, ALL_SEND_CID
, 0, SD_RSP_TYPE_R2
, NULL
, 0);
2988 if (retval
!= STATUS_SUCCESS
) {
2989 TRACE_RET(chip
, STATUS_FAIL
);
2992 sd_card
->sd_addr
= 0x00100000;
2993 retval
= sd_send_cmd_get_rsp(chip
, SET_RELATIVE_ADDR
, sd_card
->sd_addr
, SD_RSP_TYPE_R6
, rsp
, 5);
2994 if (retval
!= STATUS_SUCCESS
) {
2995 TRACE_RET(chip
, STATUS_FAIL
);
2998 retval
= sd_check_csd(chip
, 1);
2999 if (retval
!= STATUS_SUCCESS
) {
3000 TRACE_RET(chip
, STATUS_FAIL
);
3003 spec_ver
= (sd_card
->raw_csd
[0] & 0x3C) >> 2;
3005 retval
= sd_select_card(chip
, 1);
3006 if (retval
!= STATUS_SUCCESS
) {
3007 TRACE_RET(chip
, STATUS_FAIL
);
3010 retval
= sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200, SD_RSP_TYPE_R1
, NULL
, 0);
3011 if (retval
!= STATUS_SUCCESS
) {
3012 TRACE_RET(chip
, STATUS_FAIL
);
3015 #ifdef SUPPORT_SD_LOCK
3017 retval
= sd_update_lock_status(chip
);
3018 if (retval
!= STATUS_SUCCESS
) {
3019 TRACE_RET(chip
, STATUS_FAIL
);
3023 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
3024 if (retval
!= STATUS_SUCCESS
) {
3025 TRACE_RET(chip
, STATUS_FAIL
);
3028 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 1;
3030 if (!sd_card
->mmc_dont_switch_bus
) {
3031 if (spec_ver
== 4) {
3033 retval
= mmc_switch_timing_bus(chip
, switch_ddr
);
3034 if (retval
!= STATUS_SUCCESS
) {
3035 retval
= sd_init_power(chip
);
3036 if (retval
!= STATUS_SUCCESS
)
3037 TRACE_RET(chip
, STATUS_FAIL
);
3038 sd_card
->mmc_dont_switch_bus
= 1;
3039 TRACE_GOTO(chip
, Switch_Fail
);
3043 if (CHK_MMC_SECTOR_MODE(sd_card
) && (sd_card
->capacity
== 0)) {
3044 TRACE_RET(chip
, STATUS_FAIL
);
3047 if (switch_ddr
&& CHK_MMC_DDR52(sd_card
)) {
3048 retval
= sd_set_init_para(chip
);
3049 if (retval
!= STATUS_SUCCESS
) {
3050 TRACE_RET(chip
, STATUS_FAIL
);
3053 retval
= mmc_ddr_tuning(chip
);
3054 if (retval
!= STATUS_SUCCESS
) {
3055 retval
= sd_init_power(chip
);
3056 if (retval
!= STATUS_SUCCESS
) {
3057 TRACE_RET(chip
, STATUS_FAIL
);
3060 TRACE_GOTO(chip
, Switch_Fail
);
3063 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
3064 if (retval
== STATUS_SUCCESS
) {
3065 retval
= sd_read_lba0(chip
);
3066 if (retval
!= STATUS_SUCCESS
) {
3067 retval
= sd_init_power(chip
);
3068 if (retval
!= STATUS_SUCCESS
) {
3069 TRACE_RET(chip
, STATUS_FAIL
);
3072 TRACE_GOTO(chip
, Switch_Fail
);
3078 #ifdef SUPPORT_SD_LOCK
3079 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
) {
3080 RTSX_WRITE_REG(chip
, REG_SD_BLOCK_CNT_H
, 0xFF, 0x02);
3081 RTSX_WRITE_REG(chip
, REG_SD_BLOCK_CNT_L
, 0xFF, 0x00);
3085 temp
= rtsx_readl(chip
, RTSX_BIPR
);
3086 if (temp
& SD_WRITE_PROTECT
) {
3087 chip
->card_wp
|= SD_CARD
;
3090 return STATUS_SUCCESS
;
3093 int reset_sd_card(struct rtsx_chip
*chip
)
3095 struct sd_info
*sd_card
= &(chip
->sd_card
);
3098 sd_init_reg_addr(chip
);
3100 memset(sd_card
, 0, sizeof(struct sd_info
));
3101 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
3103 retval
= enable_card_clock(chip
, SD_CARD
);
3104 if (retval
!= STATUS_SUCCESS
) {
3105 TRACE_RET(chip
, STATUS_FAIL
);
3108 if (chip
->ignore_sd
&& CHK_SDIO_EXIST(chip
) && !CHK_SDIO_IGNORED(chip
)) {
3109 if (chip
->asic_code
) {
3110 retval
= sd_pull_ctl_enable(chip
);
3111 if (retval
!= STATUS_SUCCESS
) {
3112 TRACE_RET(chip
, STATUS_FAIL
);
3115 retval
= rtsx_write_register(chip
, FPGA_PULL_CTL
,
3116 FPGA_SD_PULL_CTL_BIT
| 0x20, 0);
3117 if (retval
!= STATUS_SUCCESS
) {
3118 TRACE_RET(chip
, STATUS_FAIL
);
3121 retval
= card_share_mode(chip
, SD_CARD
);
3122 if (retval
!= STATUS_SUCCESS
) {
3123 TRACE_RET(chip
, STATUS_FAIL
);
3127 TRACE_RET(chip
, STATUS_FAIL
);
3130 retval
= sd_init_power(chip
);
3131 if (retval
!= STATUS_SUCCESS
) {
3132 TRACE_RET(chip
, STATUS_FAIL
);
3135 if (chip
->sd_ctl
& RESET_MMC_FIRST
) {
3136 retval
= reset_mmc(chip
);
3137 if (retval
!= STATUS_SUCCESS
) {
3138 if (sd_check_err_code(chip
, SD_NO_CARD
))
3139 TRACE_RET(chip
, STATUS_FAIL
);
3141 retval
= reset_sd(chip
);
3142 if (retval
!= STATUS_SUCCESS
) {
3143 if (CHECK_PID(chip
, 0x5209))
3144 sd_change_bank_voltage(chip
, SD_IO_3V3
);
3146 TRACE_RET(chip
, STATUS_FAIL
);
3150 retval
= reset_sd(chip
);
3151 if (retval
!= STATUS_SUCCESS
) {
3152 if (sd_check_err_code(chip
, SD_NO_CARD
))
3153 TRACE_RET(chip
, STATUS_FAIL
);
3155 if (CHECK_PID(chip
, 0x5209)) {
3156 retval
= sd_change_bank_voltage(chip
, SD_IO_3V3
);
3157 if (retval
!= STATUS_SUCCESS
)
3158 TRACE_RET(chip
, STATUS_FAIL
);
3162 TRACE_RET(chip
, STATUS_FAIL
);
3164 retval
= reset_mmc(chip
);
3165 if (retval
!= STATUS_SUCCESS
)
3166 TRACE_RET(chip
, STATUS_FAIL
);
3171 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
3172 if (retval
!= STATUS_SUCCESS
) {
3173 TRACE_RET(chip
, STATUS_FAIL
);
3175 RTSX_WRITE_REG(chip
, REG_SD_BYTE_CNT_L
, 0xFF, 0);
3176 RTSX_WRITE_REG(chip
, REG_SD_BYTE_CNT_H
, 0xFF, 2);
3178 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
;
3180 retval
= sd_set_init_para(chip
);
3181 if (retval
!= STATUS_SUCCESS
) {
3182 TRACE_RET(chip
, STATUS_FAIL
);
3185 RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card
->sd_type
);
3187 return STATUS_SUCCESS
;
3190 static int reset_mmc_only(struct rtsx_chip
*chip
)
3192 struct sd_info
*sd_card
= &(chip
->sd_card
);
3195 sd_card
->sd_type
= 0;
3196 sd_card
->seq_mode
= 0;
3197 sd_card
->sd_data_buf_ready
= 0;
3198 sd_card
->capacity
= 0;
3199 sd_card
->sd_switch_fail
= 0;
3201 #ifdef SUPPORT_SD_LOCK
3202 sd_card
->sd_lock_status
= 0;
3203 sd_card
->sd_erase_status
= 0;
3206 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
= 0;
3208 retval
= enable_card_clock(chip
, SD_CARD
);
3209 if (retval
!= STATUS_SUCCESS
) {
3210 TRACE_RET(chip
, STATUS_FAIL
);
3213 retval
= sd_init_power(chip
);
3214 if (retval
!= STATUS_SUCCESS
) {
3215 TRACE_RET(chip
, STATUS_FAIL
);
3218 retval
= reset_mmc(chip
);
3219 if (retval
!= STATUS_SUCCESS
) {
3220 TRACE_RET(chip
, STATUS_FAIL
);
3223 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
3224 if (retval
!= STATUS_SUCCESS
) {
3225 TRACE_RET(chip
, STATUS_FAIL
);
3227 RTSX_WRITE_REG(chip
, REG_SD_BYTE_CNT_L
, 0xFF, 0);
3228 RTSX_WRITE_REG(chip
, REG_SD_BYTE_CNT_H
, 0xFF, 2);
3230 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
;
3232 retval
= sd_set_init_para(chip
);
3233 if (retval
!= STATUS_SUCCESS
) {
3234 TRACE_RET(chip
, STATUS_FAIL
);
3237 RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", sd_card
->sd_type
);
3239 return STATUS_SUCCESS
;
3242 #define WAIT_DATA_READY_RTY_CNT 255
3244 static int wait_data_buf_ready(struct rtsx_chip
*chip
)
3246 struct sd_info
*sd_card
= &(chip
->sd_card
);
3249 for (i
= 0; i
< WAIT_DATA_READY_RTY_CNT
; i
++) {
3250 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
3251 sd_set_err_code(chip
, SD_NO_CARD
);
3252 TRACE_RET(chip
, STATUS_FAIL
);
3255 sd_card
->sd_data_buf_ready
= 0;
3257 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
3258 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3259 if (retval
!= STATUS_SUCCESS
) {
3260 TRACE_RET(chip
, STATUS_FAIL
);
3263 if (sd_card
->sd_data_buf_ready
) {
3264 return sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
3265 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3269 sd_set_err_code(chip
, SD_TO_ERR
);
3271 TRACE_RET(chip
, STATUS_FAIL
);
3274 void sd_stop_seq_mode(struct rtsx_chip
*chip
)
3276 struct sd_info
*sd_card
= &(chip
->sd_card
);
3279 if (sd_card
->seq_mode
) {
3280 retval
= sd_switch_clock(chip
);
3281 if (retval
!= STATUS_SUCCESS
) {
3285 retval
= sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
, 0,
3286 SD_RSP_TYPE_R1b
, NULL
, 0);
3287 if (retval
!= STATUS_SUCCESS
) {
3288 sd_set_err_code(chip
, SD_STS_ERR
);
3290 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
3291 if (retval
!= STATUS_SUCCESS
) {
3292 sd_set_err_code(chip
, SD_STS_ERR
);
3294 sd_card
->seq_mode
= 0;
3296 rtsx_write_register(chip
, RBCTL
, RB_FLUSH
, RB_FLUSH
);
3300 static inline int sd_auto_tune_clock(struct rtsx_chip
*chip
)
3302 struct sd_info
*sd_card
= &(chip
->sd_card
);
3305 if (chip
->asic_code
) {
3306 if (sd_card
->sd_clock
> 30) {
3307 sd_card
->sd_clock
-= 20;
3310 switch (sd_card
->sd_clock
) {
3312 sd_card
->sd_clock
= CLK_150
;
3316 sd_card
->sd_clock
= CLK_120
;
3320 sd_card
->sd_clock
= CLK_100
;
3324 sd_card
->sd_clock
= CLK_80
;
3328 sd_card
->sd_clock
= CLK_60
;
3332 sd_card
->sd_clock
= CLK_50
;
3340 retval
= sd_switch_clock(chip
);
3341 if (retval
!= STATUS_SUCCESS
) {
3342 TRACE_RET(chip
, STATUS_FAIL
);
3345 return STATUS_SUCCESS
;
3348 int sd_rw(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
, u32 start_sector
, u16 sector_cnt
)
3350 struct sd_info
*sd_card
= &(chip
->sd_card
);
3355 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3356 RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt
,
3357 (sector_cnt
> 1) ? "sectors" : "sector", start_sector
);
3359 RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt
,
3360 (sector_cnt
> 1) ? "sectors" : "sector", start_sector
);
3363 sd_card
->cleanup_counter
= 0;
3365 if (!(chip
->card_ready
& SD_CARD
)) {
3366 sd_card
->seq_mode
= 0;
3368 retval
= reset_sd_card(chip
);
3369 if (retval
== STATUS_SUCCESS
) {
3370 chip
->card_ready
|= SD_CARD
;
3371 chip
->card_fail
&= ~SD_CARD
;
3373 chip
->card_ready
&= ~SD_CARD
;
3374 chip
->card_fail
|= SD_CARD
;
3375 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
3376 chip
->rw_need_retry
= 1;
3377 TRACE_RET(chip
, STATUS_FAIL
);
3381 if (!CHK_SD_HCXC(sd_card
) && !CHK_MMC_SECTOR_MODE(sd_card
)) {
3382 data_addr
= start_sector
<< 9;
3384 data_addr
= start_sector
;
3387 sd_clr_err_code(chip
);
3389 retval
= sd_switch_clock(chip
);
3390 if (retval
!= STATUS_SUCCESS
) {
3391 sd_set_err_code(chip
, SD_IO_ERR
);
3392 TRACE_GOTO(chip
, RW_FAIL
);
3395 if (sd_card
->seq_mode
&& ((sd_card
->pre_dir
!= srb
->sc_data_direction
)
3396 || ((sd_card
->pre_sec_addr
+ sd_card
->pre_sec_cnt
) != start_sector
))) {
3397 if ((sd_card
->pre_sec_cnt
< 0x80)
3398 && (sd_card
->pre_dir
== DMA_FROM_DEVICE
)
3399 && !CHK_SD30_SPEED(sd_card
)
3400 && !CHK_SD_HS(sd_card
)
3401 && !CHK_MMC_HS(sd_card
)) {
3402 sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
3403 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3406 retval
= sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
,
3407 0, SD_RSP_TYPE_R1b
, NULL
, 0);
3408 if (retval
!= STATUS_SUCCESS
) {
3409 chip
->rw_need_retry
= 1;
3410 sd_set_err_code(chip
, SD_STS_ERR
);
3411 TRACE_GOTO(chip
, RW_FAIL
);
3414 sd_card
->seq_mode
= 0;
3416 retval
= rtsx_write_register(chip
, RBCTL
, RB_FLUSH
, RB_FLUSH
);
3417 if (retval
!= STATUS_SUCCESS
) {
3418 sd_set_err_code(chip
, SD_IO_ERR
);
3419 TRACE_GOTO(chip
, RW_FAIL
);
3422 if ((sd_card
->pre_sec_cnt
< 0x80)
3423 && !CHK_SD30_SPEED(sd_card
)
3424 && !CHK_SD_HS(sd_card
)
3425 && !CHK_MMC_HS(sd_card
)) {
3426 sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
3427 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3431 rtsx_init_cmd(chip
);
3433 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0x00);
3434 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, 0x02);
3435 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, (u8
)sector_cnt
);
3436 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, (u8
)(sector_cnt
>> 8));
3438 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
3440 if (CHK_MMC_8BIT(sd_card
)) {
3441 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_8
);
3442 } else if (CHK_MMC_4BIT(sd_card
) || CHK_SD(sd_card
)) {
3443 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_4
);
3445 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_1
);
3448 if (sd_card
->seq_mode
) {
3449 cfg2
= SD_NO_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
3450 SD_NO_CHECK_CRC7
| SD_RSP_LEN_0
;
3451 if (CHECK_PID(chip
, 0x5209)) {
3452 if (!CHK_SD30_SPEED(sd_card
)) {
3453 cfg2
|= SD_NO_CHECK_WAIT_CRC_TO
;
3456 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, cfg2
);
3458 trans_dma_enable(srb
->sc_data_direction
, chip
, sector_cnt
* 512, DMA_512
);
3460 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3461 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3462 SD_TM_AUTO_READ_3
| SD_TRANSFER_START
);
3464 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3465 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
3468 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
3470 rtsx_send_cmd_no_wait(chip
);
3472 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3473 RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK
);
3474 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF,
3475 0x40 | READ_MULTIPLE_BLOCK
);
3476 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, (u8
)(data_addr
>> 24));
3477 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, (u8
)(data_addr
>> 16));
3478 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, (u8
)(data_addr
>> 8));
3479 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, (u8
)data_addr
);
3481 cfg2
= SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
3482 SD_CHECK_CRC7
| SD_RSP_LEN_6
;
3483 if (CHECK_PID(chip
, 0x5209)) {
3484 if (!CHK_SD30_SPEED(sd_card
)) {
3485 cfg2
|= SD_NO_CHECK_WAIT_CRC_TO
;
3488 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, cfg2
);
3490 trans_dma_enable(srb
->sc_data_direction
, chip
, sector_cnt
* 512, DMA_512
);
3492 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3493 SD_TM_AUTO_READ_2
| SD_TRANSFER_START
);
3494 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
3495 SD_TRANSFER_END
, SD_TRANSFER_END
);
3497 rtsx_send_cmd_no_wait(chip
);
3499 retval
= rtsx_send_cmd(chip
, SD_CARD
, 50);
3501 rtsx_clear_sd_error(chip
);
3503 chip
->rw_need_retry
= 1;
3504 sd_set_err_code(chip
, SD_TO_ERR
);
3505 TRACE_GOTO(chip
, RW_FAIL
);
3508 retval
= wait_data_buf_ready(chip
);
3509 if (retval
!= STATUS_SUCCESS
) {
3510 chip
->rw_need_retry
= 1;
3511 sd_set_err_code(chip
, SD_TO_ERR
);
3512 TRACE_GOTO(chip
, RW_FAIL
);
3515 retval
= sd_send_cmd_get_rsp(chip
, WRITE_MULTIPLE_BLOCK
,
3516 data_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3517 if (retval
!= STATUS_SUCCESS
) {
3518 chip
->rw_need_retry
= 1;
3519 TRACE_GOTO(chip
, RW_FAIL
);
3522 rtsx_init_cmd(chip
);
3524 cfg2
= SD_NO_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
3525 SD_NO_CHECK_CRC7
| SD_RSP_LEN_0
;
3526 if (CHECK_PID(chip
, 0x5209)) {
3527 if (!CHK_SD30_SPEED(sd_card
)) {
3528 cfg2
|= SD_NO_CHECK_WAIT_CRC_TO
;
3531 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, cfg2
);
3533 trans_dma_enable(srb
->sc_data_direction
, chip
, sector_cnt
* 512, DMA_512
);
3535 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3536 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
3537 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
3538 SD_TRANSFER_END
, SD_TRANSFER_END
);
3540 rtsx_send_cmd_no_wait(chip
);
3543 sd_card
->seq_mode
= 1;
3546 retval
= rtsx_transfer_data(chip
, SD_CARD
, scsi_sglist(srb
), scsi_bufflen(srb
),
3547 scsi_sg_count(srb
), srb
->sc_data_direction
, chip
->sd_timeout
);
3552 sd_card
->seq_mode
= 0;
3554 if (retval
== -ETIMEDOUT
) {
3555 err
= STATUS_TIMEDOUT
;
3560 rtsx_read_register(chip
, REG_SD_STAT1
, &stat
);
3561 rtsx_clear_sd_error(chip
);
3562 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
3563 chip
->rw_need_retry
= 0;
3564 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3565 TRACE_RET(chip
, STATUS_FAIL
);
3568 chip
->rw_need_retry
= 1;
3570 retval
= sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
, 0, SD_RSP_TYPE_R1b
, NULL
, 0);
3571 if (retval
!= STATUS_SUCCESS
) {
3572 sd_set_err_code(chip
, SD_STS_ERR
);
3573 TRACE_GOTO(chip
, RW_FAIL
);
3576 if (stat
& (SD_CRC7_ERR
| SD_CRC16_ERR
| SD_CRC_WRITE_ERR
)) {
3577 RTSX_DEBUGP("SD CRC error, tune clock!\n");
3578 sd_set_err_code(chip
, SD_CRC_ERR
);
3579 TRACE_GOTO(chip
, RW_FAIL
);
3582 if (err
== STATUS_TIMEDOUT
) {
3583 sd_set_err_code(chip
, SD_TO_ERR
);
3584 TRACE_GOTO(chip
, RW_FAIL
);
3587 TRACE_RET(chip
, err
);
3590 sd_card
->pre_sec_addr
= start_sector
;
3591 sd_card
->pre_sec_cnt
= sector_cnt
;
3592 sd_card
->pre_dir
= srb
->sc_data_direction
;
3594 return STATUS_SUCCESS
;
3597 sd_card
->seq_mode
= 0;
3599 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
3600 chip
->rw_need_retry
= 0;
3601 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3602 TRACE_RET(chip
, STATUS_FAIL
);
3605 if (sd_check_err_code(chip
, SD_CRC_ERR
)) {
3606 if (CHK_MMC_4BIT(sd_card
) || CHK_MMC_8BIT(sd_card
)) {
3607 sd_card
->mmc_dont_switch_bus
= 1;
3608 reset_mmc_only(chip
);
3609 sd_card
->mmc_dont_switch_bus
= 0;
3611 sd_card
->need_retune
= 1;
3612 sd_auto_tune_clock(chip
);
3614 } else if (sd_check_err_code(chip
, SD_TO_ERR
| SD_STS_ERR
)) {
3615 retval
= reset_sd_card(chip
);
3616 if (retval
!= STATUS_SUCCESS
) {
3617 chip
->card_ready
&= ~SD_CARD
;
3618 chip
->card_fail
|= SD_CARD
;
3619 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
3623 TRACE_RET(chip
, STATUS_FAIL
);
3627 int soft_reset_sd_card(struct rtsx_chip
*chip
)
3629 return reset_sd(chip
);
3632 int ext_sd_send_cmd_get_rsp(struct rtsx_chip
*chip
, u8 cmd_idx
,
3633 u32 arg
, u8 rsp_type
, u8
*rsp
, int rsp_len
, int special_check
)
3642 RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx
);
3644 if (rsp_type
== SD_RSP_TYPE_R1b
) {
3650 rtsx_init_cmd(chip
);
3652 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | cmd_idx
);
3653 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, (u8
)(arg
>> 24));
3654 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, (u8
)(arg
>> 16));
3655 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, (u8
)(arg
>> 8));
3656 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, (u8
)arg
);
3658 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, rsp_type
);
3659 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
3660 0x01, PINGPONG_BUFFER
);
3661 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
,
3662 0xFF, SD_TM_CMD_RSP
| SD_TRANSFER_START
);
3663 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
3665 if (rsp_type
== SD_RSP_TYPE_R2
) {
3666 for (reg_addr
= PPBUF_BASE2
; reg_addr
< PPBUF_BASE2
+ 16; reg_addr
++) {
3667 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
3670 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
3671 for (reg_addr
= REG_SD_CMD0
; reg_addr
<= REG_SD_CMD4
; reg_addr
++) {
3672 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
3676 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_CMD5
, 0, 0);
3678 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_STAT1
, 0, 0);
3680 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
3682 if (retval
== -ETIMEDOUT
) {
3683 rtsx_clear_sd_error(chip
);
3685 if (rsp_type
& SD_WAIT_BUSY_END
) {
3686 retval
= sd_check_data0_status(chip
);
3687 if (retval
!= STATUS_SUCCESS
) {
3688 TRACE_RET(chip
, retval
);
3691 sd_set_err_code(chip
, SD_TO_ERR
);
3694 TRACE_RET(chip
, STATUS_FAIL
);
3697 if (rsp_type
== SD_RSP_TYPE_R0
) {
3698 return STATUS_SUCCESS
;
3701 ptr
= rtsx_get_cmd_data(chip
) + 1;
3703 if ((ptr
[0] & 0xC0) != 0) {
3704 sd_set_err_code(chip
, SD_STS_ERR
);
3705 TRACE_RET(chip
, STATUS_FAIL
);
3708 if (!(rsp_type
& SD_NO_CHECK_CRC7
)) {
3709 if (ptr
[stat_idx
] & SD_CRC7_ERR
) {
3710 if (cmd_idx
== WRITE_MULTIPLE_BLOCK
) {
3711 sd_set_err_code(chip
, SD_CRC_ERR
);
3712 TRACE_RET(chip
, STATUS_FAIL
);
3714 if (rty_cnt
< SD_MAX_RETRY_COUNT
) {
3719 sd_set_err_code(chip
, SD_CRC_ERR
);
3720 TRACE_RET(chip
, STATUS_FAIL
);
3725 if ((cmd_idx
== SELECT_CARD
) || (cmd_idx
== APP_CMD
) ||
3726 (cmd_idx
== SEND_STATUS
) || (cmd_idx
== STOP_TRANSMISSION
)) {
3727 if ((cmd_idx
!= STOP_TRANSMISSION
) && (special_check
== 0)) {
3728 if (ptr
[1] & 0x80) {
3729 TRACE_RET(chip
, STATUS_FAIL
);
3732 #ifdef SUPPORT_SD_LOCK
3738 TRACE_RET(chip
, STATUS_FAIL
);
3740 if (ptr
[2] & 0xF8) {
3741 TRACE_RET(chip
, STATUS_FAIL
);
3744 if (cmd_idx
== SELECT_CARD
) {
3745 if (rsp_type
== SD_RSP_TYPE_R2
) {
3746 if ((ptr
[3] & 0x1E) != 0x04) {
3747 TRACE_RET(chip
, STATUS_FAIL
);
3749 } else if (rsp_type
== SD_RSP_TYPE_R0
) {
3750 if ((ptr
[3] & 0x1E) != 0x03) {
3751 TRACE_RET(chip
, STATUS_FAIL
);
3757 if (rsp
&& rsp_len
) {
3758 memcpy(rsp
, ptr
, rsp_len
);
3761 return STATUS_SUCCESS
;
3764 int ext_sd_get_rsp(struct rtsx_chip
*chip
, int len
, u8
*rsp
, u8 rsp_type
)
3766 int retval
, rsp_len
;
3769 if (rsp_type
== SD_RSP_TYPE_R0
) {
3770 return STATUS_SUCCESS
;
3773 rtsx_init_cmd(chip
);
3775 if (rsp_type
== SD_RSP_TYPE_R2
) {
3776 for (reg_addr
= PPBUF_BASE2
; reg_addr
< PPBUF_BASE2
+ 16; reg_addr
++) {
3777 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0xFF, 0);
3780 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
3781 for (reg_addr
= REG_SD_CMD0
; reg_addr
<= REG_SD_CMD4
; reg_addr
++) {
3782 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0xFF, 0);
3786 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_CMD5
, 0xFF, 0);
3788 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
3789 if (retval
!= STATUS_SUCCESS
) {
3790 TRACE_RET(chip
, STATUS_FAIL
);
3794 int min_len
= (rsp_len
< len
) ? rsp_len
: len
;
3796 memcpy(rsp
, rtsx_get_cmd_data(chip
), min_len
);
3798 RTSX_DEBUGP("min_len = %d\n", min_len
);
3799 RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3800 rsp
[0], rsp
[1], rsp
[2], rsp
[3]);
3803 return STATUS_SUCCESS
;
3806 int sd_pass_thru_mode(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
3808 struct sd_info
*sd_card
= &(chip
->sd_card
);
3809 unsigned int lun
= SCSI_LUN(srb
);
3832 sd_card
->pre_cmd_err
= 0;
3834 if (!(CHK_BIT(chip
->lun_mc
, lun
))) {
3835 SET_BIT(chip
->lun_mc
, lun
);
3836 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
3837 TRACE_RET(chip
, TRANSPORT_FAILED
);
3840 if ((0x53 != srb
->cmnd
[2]) || (0x44 != srb
->cmnd
[3]) || (0x20 != srb
->cmnd
[4]) ||
3841 (0x43 != srb
->cmnd
[5]) || (0x61 != srb
->cmnd
[6]) ||
3842 (0x72 != srb
->cmnd
[7]) || (0x64 != srb
->cmnd
[8])) {
3843 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
3844 TRACE_RET(chip
, TRANSPORT_FAILED
);
3847 switch (srb
->cmnd
[1] & 0x0F) {
3849 sd_card
->sd_pass_thru_en
= 0;
3853 sd_card
->sd_pass_thru_en
= 1;
3857 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
3858 TRACE_RET(chip
, TRANSPORT_FAILED
);
3861 buf
[5] = (1 == CHK_SD(sd_card
)) ? 0x01 : 0x02;
3862 if (chip
->card_wp
& SD_CARD
) {
3866 buf
[6] = (u8
)(sd_card
->sd_addr
>> 16);
3867 buf
[7] = (u8
)(sd_card
->sd_addr
>> 24);
3869 buf
[15] = chip
->max_lun
;
3871 len
= min(18, (int)scsi_bufflen(srb
));
3872 rtsx_stor_set_xfer_buf(buf
, len
, srb
);
3874 return TRANSPORT_GOOD
;
3877 static inline int get_rsp_type(struct scsi_cmnd
*srb
, u8
*rsp_type
, int *rsp_len
)
3879 if (!rsp_type
|| !rsp_len
) {
3883 switch (srb
->cmnd
[10]) {
3885 *rsp_type
= SD_RSP_TYPE_R0
;
3890 *rsp_type
= SD_RSP_TYPE_R1
;
3895 *rsp_type
= SD_RSP_TYPE_R1b
;
3900 *rsp_type
= SD_RSP_TYPE_R2
;
3905 *rsp_type
= SD_RSP_TYPE_R3
;
3913 return STATUS_SUCCESS
;
3916 int sd_execute_no_data(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
3918 struct sd_info
*sd_card
= &(chip
->sd_card
);
3919 unsigned int lun
= SCSI_LUN(srb
);
3920 int retval
, rsp_len
;
3921 u8 cmd_idx
, rsp_type
;
3922 u8 standby
= 0, acmd
= 0;
3925 if (!sd_card
->sd_pass_thru_en
) {
3926 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
3927 TRACE_RET(chip
, TRANSPORT_FAILED
);
3930 retval
= sd_switch_clock(chip
);
3931 if (retval
!= STATUS_SUCCESS
) {
3932 TRACE_RET(chip
, TRANSPORT_FAILED
);
3935 if (sd_card
->pre_cmd_err
) {
3936 sd_card
->pre_cmd_err
= 0;
3937 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
3938 TRACE_RET(chip
, TRANSPORT_FAILED
);
3941 cmd_idx
= srb
->cmnd
[2] & 0x3F;
3942 if (srb
->cmnd
[1] & 0x02) {
3945 if (srb
->cmnd
[1] & 0x01) {
3949 arg
= ((u32
)srb
->cmnd
[3] << 24) | ((u32
)srb
->cmnd
[4] << 16) |
3950 ((u32
)srb
->cmnd
[5] << 8) | srb
->cmnd
[6];
3952 retval
= get_rsp_type(srb
, &rsp_type
, &rsp_len
);
3953 if (retval
!= STATUS_SUCCESS
) {
3954 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
3955 TRACE_RET(chip
, TRANSPORT_FAILED
);
3957 sd_card
->last_rsp_type
= rsp_type
;
3959 retval
= sd_switch_clock(chip
);
3960 if (retval
!= STATUS_SUCCESS
) {
3961 TRACE_RET(chip
, TRANSPORT_FAILED
);
3964 #ifdef SUPPORT_SD_LOCK
3965 if ((sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) == 0) {
3966 if (CHK_MMC_8BIT(sd_card
)) {
3967 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_8
);
3968 if (retval
!= STATUS_SUCCESS
) {
3969 TRACE_RET(chip
, TRANSPORT_FAILED
);
3971 } else if (CHK_SD(sd_card
) || CHK_MMC_4BIT(sd_card
)) {
3972 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_4
);
3973 if (retval
!= STATUS_SUCCESS
) {
3974 TRACE_RET(chip
, TRANSPORT_FAILED
);
3979 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_4
);
3980 if (retval
!= STATUS_SUCCESS
) {
3981 TRACE_RET(chip
, TRANSPORT_FAILED
);
3986 retval
= sd_select_card(chip
, 0);
3987 if (retval
!= STATUS_SUCCESS
) {
3988 TRACE_GOTO(chip
, SD_Execute_Cmd_Failed
);
3993 retval
= ext_sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
3994 SD_RSP_TYPE_R1
, NULL
, 0, 0);
3995 if (retval
!= STATUS_SUCCESS
) {
3996 TRACE_GOTO(chip
, SD_Execute_Cmd_Failed
);
4000 retval
= ext_sd_send_cmd_get_rsp(chip
, cmd_idx
, arg
, rsp_type
,
4001 sd_card
->rsp
, rsp_len
, 0);
4002 if (retval
!= STATUS_SUCCESS
) {
4003 TRACE_GOTO(chip
, SD_Execute_Cmd_Failed
);
4007 retval
= sd_select_card(chip
, 1);
4008 if (retval
!= STATUS_SUCCESS
) {
4009 TRACE_GOTO(chip
, SD_Execute_Cmd_Failed
);
4013 #ifdef SUPPORT_SD_LOCK
4014 retval
= sd_update_lock_status(chip
);
4015 if (retval
!= STATUS_SUCCESS
) {
4016 TRACE_GOTO(chip
, SD_Execute_Cmd_Failed
);
4020 scsi_set_resid(srb
, 0);
4021 return TRANSPORT_GOOD
;
4023 SD_Execute_Cmd_Failed
:
4024 sd_card
->pre_cmd_err
= 1;
4025 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
4026 release_sd_card(chip
);
4027 do_reset_sd_card(chip
);
4028 if (!(chip
->card_ready
& SD_CARD
)) {
4029 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
4032 TRACE_RET(chip
, TRANSPORT_FAILED
);
4035 int sd_execute_read_data(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4037 struct sd_info
*sd_card
= &(chip
->sd_card
);
4038 unsigned int lun
= SCSI_LUN(srb
);
4039 int retval
, rsp_len
, i
;
4040 int cmd13_checkbit
= 0, read_err
= 0;
4041 u8 cmd_idx
, rsp_type
, bus_width
;
4042 u8 send_cmd12
= 0, standby
= 0, acmd
= 0;
4045 if (!sd_card
->sd_pass_thru_en
) {
4046 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4047 TRACE_RET(chip
, TRANSPORT_FAILED
);
4050 if (sd_card
->pre_cmd_err
) {
4051 sd_card
->pre_cmd_err
= 0;
4052 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4053 TRACE_RET(chip
, TRANSPORT_FAILED
);
4056 retval
= sd_switch_clock(chip
);
4057 if (retval
!= STATUS_SUCCESS
) {
4058 TRACE_RET(chip
, TRANSPORT_FAILED
);
4061 cmd_idx
= srb
->cmnd
[2] & 0x3F;
4062 if (srb
->cmnd
[1] & 0x04) {
4065 if (srb
->cmnd
[1] & 0x02) {
4068 if (srb
->cmnd
[1] & 0x01) {
4072 data_len
= ((u32
)srb
->cmnd
[7] << 16) | ((u32
)srb
->cmnd
[8] << 8) | srb
->cmnd
[9];
4074 retval
= get_rsp_type(srb
, &rsp_type
, &rsp_len
);
4075 if (retval
!= STATUS_SUCCESS
) {
4076 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4077 TRACE_RET(chip
, TRANSPORT_FAILED
);
4079 sd_card
->last_rsp_type
= rsp_type
;
4081 retval
= sd_switch_clock(chip
);
4082 if (retval
!= STATUS_SUCCESS
) {
4083 TRACE_RET(chip
, TRANSPORT_FAILED
);
4086 #ifdef SUPPORT_SD_LOCK
4087 if ((sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) == 0) {
4088 if (CHK_MMC_8BIT(sd_card
)) {
4089 bus_width
= SD_BUS_WIDTH_8
;
4090 } else if (CHK_SD(sd_card
) || CHK_MMC_4BIT(sd_card
)) {
4091 bus_width
= SD_BUS_WIDTH_4
;
4093 bus_width
= SD_BUS_WIDTH_1
;
4096 bus_width
= SD_BUS_WIDTH_4
;
4098 RTSX_DEBUGP("bus_width = %d\n", bus_width
);
4100 bus_width
= SD_BUS_WIDTH_4
;
4103 if (data_len
< 512) {
4104 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, data_len
,
4105 SD_RSP_TYPE_R1
, NULL
, 0, 0);
4106 if (retval
!= STATUS_SUCCESS
) {
4107 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4112 retval
= sd_select_card(chip
, 0);
4113 if (retval
!= STATUS_SUCCESS
) {
4114 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4119 retval
= ext_sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
4120 SD_RSP_TYPE_R1
, NULL
, 0, 0);
4121 if (retval
!= STATUS_SUCCESS
) {
4122 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4126 if (data_len
<= 512) {
4129 u16 byte_cnt
, blk_cnt
;
4132 byte_cnt
= ((u16
)(srb
->cmnd
[8] & 0x03) << 8) | srb
->cmnd
[9];
4135 cmd
[0] = 0x40 | cmd_idx
;
4136 cmd
[1] = srb
->cmnd
[3];
4137 cmd
[2] = srb
->cmnd
[4];
4138 cmd
[3] = srb
->cmnd
[5];
4139 cmd
[4] = srb
->cmnd
[6];
4141 buf
= kmalloc(data_len
, GFP_KERNEL
);
4143 TRACE_RET(chip
, TRANSPORT_ERROR
);
4146 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, byte_cnt
,
4147 blk_cnt
, bus_width
, buf
, data_len
, 2000);
4148 if (retval
!= STATUS_SUCCESS
) {
4151 rtsx_clear_sd_error(chip
);
4152 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4155 min_len
= min(data_len
, scsi_bufflen(srb
));
4156 rtsx_stor_set_xfer_buf(buf
, min_len
, srb
);
4159 } else if (!(data_len
& 0x1FF)) {
4160 rtsx_init_cmd(chip
);
4162 trans_dma_enable(DMA_FROM_DEVICE
, chip
, data_len
, DMA_512
);
4164 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, 0x02);
4165 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0x00);
4166 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
,
4167 0xFF, (srb
->cmnd
[7] & 0xFE) >> 1);
4168 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
,
4169 0xFF, (u8
)((data_len
& 0x0001FE00) >> 9));
4171 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | cmd_idx
);
4172 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, srb
->cmnd
[3]);
4173 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, srb
->cmnd
[4]);
4174 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, srb
->cmnd
[5]);
4175 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, srb
->cmnd
[6]);
4177 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, bus_width
);
4178 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, rsp_type
);
4180 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
,
4181 0xFF, SD_TM_AUTO_READ_2
| SD_TRANSFER_START
);
4182 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
4184 rtsx_send_cmd_no_wait(chip
);
4186 retval
= rtsx_transfer_data(chip
, SD_CARD
, scsi_sglist(srb
), scsi_bufflen(srb
),
4187 scsi_sg_count(srb
), DMA_FROM_DEVICE
, 10000);
4190 rtsx_clear_sd_error(chip
);
4191 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4195 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4198 retval
= ext_sd_get_rsp(chip
, rsp_len
, sd_card
->rsp
, rsp_type
);
4199 if (retval
!= STATUS_SUCCESS
) {
4200 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4204 retval
= sd_select_card(chip
, 1);
4205 if (retval
!= STATUS_SUCCESS
) {
4206 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4211 retval
= ext_sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
,
4212 0, SD_RSP_TYPE_R1b
, NULL
, 0, 0);
4213 if (retval
!= STATUS_SUCCESS
) {
4214 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4218 if (data_len
< 512) {
4219 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200,
4220 SD_RSP_TYPE_R1
, NULL
, 0, 0);
4221 if (retval
!= STATUS_SUCCESS
) {
4222 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4225 retval
= rtsx_write_register(chip
, SD_BYTE_CNT_H
, 0xFF, 0x02);
4226 if (retval
!= STATUS_SUCCESS
) {
4227 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4229 retval
= rtsx_write_register(chip
, SD_BYTE_CNT_L
, 0xFF, 0x00);
4230 if (retval
!= STATUS_SUCCESS
) {
4231 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4235 if ((srb
->cmnd
[1] & 0x02) || (srb
->cmnd
[1] & 0x04)) {
4239 for (i
= 0; i
< 3; i
++) {
4240 retval
= ext_sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
4241 SD_RSP_TYPE_R1
, NULL
, 0, cmd13_checkbit
);
4242 if (retval
== STATUS_SUCCESS
) {
4246 if (retval
!= STATUS_SUCCESS
) {
4247 TRACE_GOTO(chip
, SD_Execute_Read_Cmd_Failed
);
4250 scsi_set_resid(srb
, 0);
4251 return TRANSPORT_GOOD
;
4253 SD_Execute_Read_Cmd_Failed
:
4254 sd_card
->pre_cmd_err
= 1;
4255 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
4257 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR
);
4259 release_sd_card(chip
);
4260 do_reset_sd_card(chip
);
4261 if (!(chip
->card_ready
& SD_CARD
)) {
4262 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
4265 TRACE_RET(chip
, TRANSPORT_FAILED
);
4268 int sd_execute_write_data(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4270 struct sd_info
*sd_card
= &(chip
->sd_card
);
4271 unsigned int lun
= SCSI_LUN(srb
);
4272 int retval
, rsp_len
, i
;
4273 int cmd13_checkbit
= 0, write_err
= 0;
4274 u8 cmd_idx
, rsp_type
;
4275 u8 send_cmd12
= 0, standby
= 0, acmd
= 0;
4277 #ifdef SUPPORT_SD_LOCK
4278 int lock_cmd_fail
= 0;
4279 u8 sd_lock_state
= 0;
4280 u8 lock_cmd_type
= 0;
4283 if (!sd_card
->sd_pass_thru_en
) {
4284 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4285 TRACE_RET(chip
, TRANSPORT_FAILED
);
4288 if (sd_card
->pre_cmd_err
) {
4289 sd_card
->pre_cmd_err
= 0;
4290 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4291 TRACE_RET(chip
, TRANSPORT_FAILED
);
4294 retval
= sd_switch_clock(chip
);
4295 if (retval
!= STATUS_SUCCESS
) {
4296 TRACE_RET(chip
, TRANSPORT_FAILED
);
4299 cmd_idx
= srb
->cmnd
[2] & 0x3F;
4300 if (srb
->cmnd
[1] & 0x04) {
4303 if (srb
->cmnd
[1] & 0x02) {
4306 if (srb
->cmnd
[1] & 0x01) {
4310 data_len
= ((u32
)srb
->cmnd
[7] << 16) | ((u32
)srb
->cmnd
[8] << 8) | srb
->cmnd
[9];
4311 arg
= ((u32
)srb
->cmnd
[3] << 24) | ((u32
)srb
->cmnd
[4] << 16) |
4312 ((u32
)srb
->cmnd
[5] << 8) | srb
->cmnd
[6];
4314 #ifdef SUPPORT_SD_LOCK
4315 if (cmd_idx
== LOCK_UNLOCK
) {
4316 sd_lock_state
= sd_card
->sd_lock_status
;
4317 sd_lock_state
&= SD_LOCKED
;
4321 retval
= get_rsp_type(srb
, &rsp_type
, &rsp_len
);
4322 if (retval
!= STATUS_SUCCESS
) {
4323 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4324 TRACE_RET(chip
, TRANSPORT_FAILED
);
4326 sd_card
->last_rsp_type
= rsp_type
;
4328 retval
= sd_switch_clock(chip
);
4329 if (retval
!= STATUS_SUCCESS
) {
4330 TRACE_RET(chip
, TRANSPORT_FAILED
);
4333 #ifdef SUPPORT_SD_LOCK
4334 if ((sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) == 0) {
4335 if (CHK_MMC_8BIT(sd_card
)) {
4336 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_8
);
4337 if (retval
!= STATUS_SUCCESS
) {
4338 TRACE_RET(chip
, TRANSPORT_FAILED
);
4340 } else if (CHK_SD(sd_card
) || CHK_MMC_4BIT(sd_card
)) {
4341 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_4
);
4342 if (retval
!= STATUS_SUCCESS
) {
4343 TRACE_RET(chip
, TRANSPORT_FAILED
);
4348 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_4
);
4349 if (retval
!= STATUS_SUCCESS
) {
4350 TRACE_RET(chip
, TRANSPORT_FAILED
);
4354 if (data_len
< 512) {
4355 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, data_len
,
4356 SD_RSP_TYPE_R1
, NULL
, 0, 0);
4357 if (retval
!= STATUS_SUCCESS
) {
4358 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4363 retval
= sd_select_card(chip
, 0);
4364 if (retval
!= STATUS_SUCCESS
) {
4365 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4370 retval
= ext_sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
4371 SD_RSP_TYPE_R1
, NULL
, 0, 0);
4372 if (retval
!= STATUS_SUCCESS
) {
4373 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4377 retval
= ext_sd_send_cmd_get_rsp(chip
, cmd_idx
, arg
, rsp_type
,
4378 sd_card
->rsp
, rsp_len
, 0);
4379 if (retval
!= STATUS_SUCCESS
) {
4380 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4383 if (data_len
<= 512) {
4387 buf
= kmalloc(data_len
, GFP_KERNEL
);
4389 TRACE_RET(chip
, TRANSPORT_ERROR
);
4392 rtsx_stor_get_xfer_buf(buf
, data_len
, srb
);
4394 #ifdef SUPPORT_SD_LOCK
4395 if (cmd_idx
== LOCK_UNLOCK
) {
4396 lock_cmd_type
= buf
[0] & 0x0F;
4400 if (data_len
> 256) {
4401 rtsx_init_cmd(chip
);
4402 for (i
= 0; i
< 256; i
++) {
4403 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
4404 PPBUF_BASE2
+ i
, 0xFF, buf
[i
]);
4406 retval
= rtsx_send_cmd(chip
, 0, 250);
4407 if (retval
!= STATUS_SUCCESS
) {
4409 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4412 rtsx_init_cmd(chip
);
4413 for (i
= 256; i
< data_len
; i
++) {
4414 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
4415 PPBUF_BASE2
+ i
, 0xFF, buf
[i
]);
4417 retval
= rtsx_send_cmd(chip
, 0, 250);
4418 if (retval
!= STATUS_SUCCESS
) {
4420 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4423 rtsx_init_cmd(chip
);
4424 for (i
= 0; i
< data_len
; i
++) {
4425 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
4426 PPBUF_BASE2
+ i
, 0xFF, buf
[i
]);
4428 retval
= rtsx_send_cmd(chip
, 0, 250);
4429 if (retval
!= STATUS_SUCCESS
) {
4431 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4437 rtsx_init_cmd(chip
);
4439 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, srb
->cmnd
[8] & 0x03);
4440 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, srb
->cmnd
[9]);
4441 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, 0x00);
4442 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, 0x01);
4443 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
4445 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
4446 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
4447 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
4449 retval
= rtsx_send_cmd(chip
, SD_CARD
, 250);
4450 } else if (!(data_len
& 0x1FF)) {
4451 rtsx_init_cmd(chip
);
4453 trans_dma_enable(DMA_TO_DEVICE
, chip
, data_len
, DMA_512
);
4455 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, 0x02);
4456 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0x00);
4457 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
,
4458 0xFF, (srb
->cmnd
[7] & 0xFE) >> 1);
4459 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
,
4460 0xFF, (u8
)((data_len
& 0x0001FE00) >> 9));
4462 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF, SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
4463 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
, SD_TRANSFER_END
);
4465 rtsx_send_cmd_no_wait(chip
);
4467 retval
= rtsx_transfer_data(chip
, SD_CARD
, scsi_sglist(srb
), scsi_bufflen(srb
),
4468 scsi_sg_count(srb
), DMA_TO_DEVICE
, 10000);
4471 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4476 rtsx_clear_sd_error(chip
);
4477 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4480 #ifdef SUPPORT_SD_LOCK
4481 if (cmd_idx
== LOCK_UNLOCK
) {
4482 if (lock_cmd_type
== SD_ERASE
) {
4483 sd_card
->sd_erase_status
= SD_UNDER_ERASING
;
4484 scsi_set_resid(srb
, 0);
4485 return TRANSPORT_GOOD
;
4488 rtsx_init_cmd(chip
);
4489 if (CHECK_PID(chip
, 0x5209)) {
4490 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SD_BUS_STAT
, SD_DAT0_STATUS
, SD_DAT0_STATUS
);
4492 rtsx_add_cmd(chip
, CHECK_REG_CMD
, 0xFD30, 0x02, 0x02);
4494 rtsx_send_cmd(chip
, SD_CARD
, 250);
4496 retval
= sd_update_lock_status(chip
);
4497 if (retval
!= STATUS_SUCCESS
) {
4498 RTSX_DEBUGP("Lock command fail!\n");
4502 #endif /* SUPPORT_SD_LOCK */
4505 retval
= sd_select_card(chip
, 1);
4506 if (retval
!= STATUS_SUCCESS
) {
4507 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4512 retval
= ext_sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
,
4513 0, SD_RSP_TYPE_R1b
, NULL
, 0, 0);
4514 if (retval
!= STATUS_SUCCESS
) {
4515 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4519 if (data_len
< 512) {
4520 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200,
4521 SD_RSP_TYPE_R1
, NULL
, 0, 0);
4522 if (retval
!= STATUS_SUCCESS
) {
4523 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4526 retval
= rtsx_write_register(chip
, SD_BYTE_CNT_H
, 0xFF, 0x02);
4527 if (retval
!= STATUS_SUCCESS
) {
4528 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4530 rtsx_write_register(chip
, SD_BYTE_CNT_L
, 0xFF, 0x00);
4531 if (retval
!= STATUS_SUCCESS
) {
4532 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4536 if ((srb
->cmnd
[1] & 0x02) || (srb
->cmnd
[1] & 0x04)) {
4540 for (i
= 0; i
< 3; i
++) {
4541 retval
= ext_sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
4542 SD_RSP_TYPE_R1
, NULL
, 0, cmd13_checkbit
);
4543 if (retval
== STATUS_SUCCESS
) {
4547 if (retval
!= STATUS_SUCCESS
) {
4548 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4551 #ifdef SUPPORT_SD_LOCK
4552 if (cmd_idx
== LOCK_UNLOCK
) {
4553 if (!lock_cmd_fail
) {
4554 RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type
);
4555 if (lock_cmd_type
& SD_CLR_PWD
) {
4556 sd_card
->sd_lock_status
&= ~SD_PWD_EXIST
;
4558 if (lock_cmd_type
& SD_SET_PWD
) {
4559 sd_card
->sd_lock_status
|= SD_PWD_EXIST
;
4563 RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4564 sd_lock_state
, sd_card
->sd_lock_status
);
4565 if (sd_lock_state
^ (sd_card
->sd_lock_status
& SD_LOCKED
)) {
4566 sd_card
->sd_lock_notify
= 1;
4567 if (sd_lock_state
) {
4568 if (sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) {
4569 sd_card
->sd_lock_status
|= (SD_UNLOCK_POW_ON
| SD_SDR_RST
);
4570 if (CHK_SD(sd_card
)) {
4571 retval
= reset_sd(chip
);
4572 if (retval
!= STATUS_SUCCESS
) {
4573 sd_card
->sd_lock_status
&= ~(SD_UNLOCK_POW_ON
| SD_SDR_RST
);
4574 TRACE_GOTO(chip
, SD_Execute_Write_Cmd_Failed
);
4578 sd_card
->sd_lock_status
&= ~(SD_UNLOCK_POW_ON
| SD_SDR_RST
);
4584 if (lock_cmd_fail
) {
4585 scsi_set_resid(srb
, 0);
4586 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
4587 TRACE_RET(chip
, TRANSPORT_FAILED
);
4589 #endif /* SUPPORT_SD_LOCK */
4591 scsi_set_resid(srb
, 0);
4592 return TRANSPORT_GOOD
;
4594 SD_Execute_Write_Cmd_Failed
:
4595 sd_card
->pre_cmd_err
= 1;
4596 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
4598 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_WRITE_ERR
);
4600 release_sd_card(chip
);
4601 do_reset_sd_card(chip
);
4602 if (!(chip
->card_ready
& SD_CARD
)) {
4603 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
4606 TRACE_RET(chip
, TRANSPORT_FAILED
);
4609 int sd_get_cmd_rsp(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4611 struct sd_info
*sd_card
= &(chip
->sd_card
);
4612 unsigned int lun
= SCSI_LUN(srb
);
4616 if (!sd_card
->sd_pass_thru_en
) {
4617 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4618 TRACE_RET(chip
, TRANSPORT_FAILED
);
4621 if (sd_card
->pre_cmd_err
) {
4622 sd_card
->pre_cmd_err
= 0;
4623 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4624 TRACE_RET(chip
, TRANSPORT_FAILED
);
4627 data_len
= ((u16
)srb
->cmnd
[7] << 8) | srb
->cmnd
[8];
4629 if (sd_card
->last_rsp_type
== SD_RSP_TYPE_R0
) {
4630 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4631 TRACE_RET(chip
, TRANSPORT_FAILED
);
4632 } else if (sd_card
->last_rsp_type
== SD_RSP_TYPE_R2
) {
4633 count
= (data_len
< 17) ? data_len
: 17;
4635 count
= (data_len
< 6) ? data_len
: 6;
4637 rtsx_stor_set_xfer_buf(sd_card
->rsp
, count
, srb
);
4639 RTSX_DEBUGP("Response length: %d\n", data_len
);
4640 RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n",
4641 sd_card
->rsp
[0], sd_card
->rsp
[1], sd_card
->rsp
[2], sd_card
->rsp
[3]);
4643 scsi_set_resid(srb
, 0);
4644 return TRANSPORT_GOOD
;
4647 int sd_hw_rst(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4649 struct sd_info
*sd_card
= &(chip
->sd_card
);
4650 unsigned int lun
= SCSI_LUN(srb
);
4653 if (!sd_card
->sd_pass_thru_en
) {
4654 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4655 TRACE_RET(chip
, TRANSPORT_FAILED
);
4658 if (sd_card
->pre_cmd_err
) {
4659 sd_card
->pre_cmd_err
= 0;
4660 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4661 TRACE_RET(chip
, TRANSPORT_FAILED
);
4664 if ((0x53 != srb
->cmnd
[2]) || (0x44 != srb
->cmnd
[3]) || (0x20 != srb
->cmnd
[4]) ||
4665 (0x43 != srb
->cmnd
[5]) || (0x61 != srb
->cmnd
[6]) ||
4666 (0x72 != srb
->cmnd
[7]) || (0x64 != srb
->cmnd
[8])) {
4667 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4668 TRACE_RET(chip
, TRANSPORT_FAILED
);
4671 switch (srb
->cmnd
[1] & 0x0F) {
4673 #ifdef SUPPORT_SD_LOCK
4674 if (0x64 == srb
->cmnd
[9]) {
4675 sd_card
->sd_lock_status
|= SD_SDR_RST
;
4678 retval
= reset_sd_card(chip
);
4679 if (retval
!= STATUS_SUCCESS
) {
4680 #ifdef SUPPORT_SD_LOCK
4681 sd_card
->sd_lock_status
&= ~SD_SDR_RST
;
4683 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
4684 sd_card
->pre_cmd_err
= 1;
4685 TRACE_RET(chip
, TRANSPORT_FAILED
);
4687 #ifdef SUPPORT_SD_LOCK
4688 sd_card
->sd_lock_status
&= ~SD_SDR_RST
;
4693 retval
= soft_reset_sd_card(chip
);
4694 if (retval
!= STATUS_SUCCESS
) {
4695 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
4696 sd_card
->pre_cmd_err
= 1;
4697 TRACE_RET(chip
, TRANSPORT_FAILED
);
4702 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4703 TRACE_RET(chip
, TRANSPORT_FAILED
);
4706 scsi_set_resid(srb
, 0);
4707 return TRANSPORT_GOOD
;
4711 void sd_cleanup_work(struct rtsx_chip
*chip
)
4713 struct sd_info
*sd_card
= &(chip
->sd_card
);
4715 if (sd_card
->seq_mode
) {
4716 RTSX_DEBUGP("SD: stop transmission\n");
4717 sd_stop_seq_mode(chip
);
4718 sd_card
->cleanup_counter
= 0;
4722 int sd_power_off_card3v3(struct rtsx_chip
*chip
)
4726 retval
= disable_card_clock(chip
, SD_CARD
);
4727 if (retval
!= STATUS_SUCCESS
) {
4728 TRACE_RET(chip
, STATUS_FAIL
);
4731 RTSX_WRITE_REG(chip
, CARD_OE
, SD_OUTPUT_EN
, 0);
4733 if (!chip
->ft2_fast_mode
) {
4734 retval
= card_power_off(chip
, SD_CARD
);
4735 if (retval
!= STATUS_SUCCESS
) {
4736 TRACE_RET(chip
, STATUS_FAIL
);
4742 if (chip
->asic_code
) {
4743 retval
= sd_pull_ctl_disable(chip
);
4744 if (retval
!= STATUS_SUCCESS
) {
4745 TRACE_RET(chip
, STATUS_FAIL
);
4748 RTSX_WRITE_REG(chip
, FPGA_PULL_CTL
,
4749 FPGA_SD_PULL_CTL_BIT
| 0x20, FPGA_SD_PULL_CTL_BIT
);
4752 return STATUS_SUCCESS
;
4755 int release_sd_card(struct rtsx_chip
*chip
)
4757 struct sd_info
*sd_card
= &(chip
->sd_card
);
4760 RTSX_DEBUGP("release_sd_card\n");
4762 chip
->card_ready
&= ~SD_CARD
;
4763 chip
->card_fail
&= ~SD_CARD
;
4764 chip
->card_wp
&= ~SD_CARD
;
4769 #ifdef SUPPORT_SD_LOCK
4770 sd_card
->sd_lock_status
= 0;
4771 sd_card
->sd_erase_status
= 0;
4774 memset(sd_card
->raw_csd
, 0, 16);
4775 memset(sd_card
->raw_scr
, 0, 8);
4777 retval
= sd_power_off_card3v3(chip
);
4778 if (retval
!= STATUS_SUCCESS
) {
4779 TRACE_RET(chip
, STATUS_FAIL
);
4782 if (CHECK_PID(chip
, 0x5209)) {
4783 retval
= sd_change_bank_voltage(chip
, SD_IO_3V3
);
4784 if (retval
!= STATUS_SUCCESS
) {
4785 TRACE_RET(chip
, STATUS_FAIL
);
4788 if (CHK_SD30_SPEED(sd_card
)) {
4789 RTSX_WRITE_REG(chip
, SD30_DRIVE_SEL
, 0x07, chip
->sd30_drive_sel_3v3
);
4792 RTSX_WRITE_REG(chip
, OCPPARA2
, SD_OCP_THD_MASK
, chip
->sd_400mA_ocp_thd
);
4795 return STATUS_SUCCESS
;