2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
37 #include <linux/mlx4/device.h>
38 #include <linux/mlx4/cmd.h>
44 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
,
45 u64 mac
, u64 clear
, u8 mode
)
47 return mlx4_cmd(dev
, (mac
| (clear
<< 63)), port
, mode
,
48 MLX4_CMD_SET_MCAST_FLTR
, MLX4_CMD_TIME_CLASS_B
);
51 int mlx4_SET_VLAN_FLTR(struct mlx4_dev
*dev
, u8 port
, struct vlan_group
*grp
)
53 struct mlx4_cmd_mailbox
*mailbox
;
54 struct mlx4_set_vlan_fltr_mbox
*filter
;
61 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
63 return PTR_ERR(mailbox
);
65 filter
= mailbox
->buf
;
67 memset(filter
, 0, sizeof *filter
);
68 for (i
= VLAN_FLTR_SIZE
- 1; i
>= 0; i
--) {
70 for (j
= 0; j
< 32; j
++)
71 if (vlan_group_get_device(grp
, index
++))
73 filter
->entry
[i
] = cpu_to_be32(entry
);
76 /* When no vlans are configured we block all vlans */
77 memset(filter
, 0, sizeof(*filter
));
79 err
= mlx4_cmd(dev
, mailbox
->dma
, port
, 0, MLX4_CMD_SET_VLAN_FLTR
,
80 MLX4_CMD_TIME_CLASS_B
);
81 mlx4_free_cmd_mailbox(dev
, mailbox
);
86 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
87 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
)
89 struct mlx4_cmd_mailbox
*mailbox
;
90 struct mlx4_set_port_general_context
*context
;
94 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
96 return PTR_ERR(mailbox
);
97 context
= mailbox
->buf
;
98 memset(context
, 0, sizeof *context
);
100 context
->flags
= SET_PORT_GEN_ALL_VALID
;
101 context
->mtu
= cpu_to_be16(mtu
);
102 context
->pptx
= (pptx
* (!pfctx
)) << 7;
103 context
->pfctx
= pfctx
;
104 context
->pprx
= (pprx
* (!pfcrx
)) << 7;
105 context
->pfcrx
= pfcrx
;
107 in_mod
= MLX4_SET_PORT_GENERAL
<< 8 | port
;
108 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
109 MLX4_CMD_TIME_CLASS_B
);
111 mlx4_free_cmd_mailbox(dev
, mailbox
);
115 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
118 struct mlx4_cmd_mailbox
*mailbox
;
119 struct mlx4_set_port_rqp_calc_context
*context
;
123 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
125 return PTR_ERR(mailbox
);
126 context
= mailbox
->buf
;
127 memset(context
, 0, sizeof *context
);
129 context
->base_qpn
= cpu_to_be32(base_qpn
);
130 context
->promisc
= cpu_to_be32(promisc
<< SET_PORT_PROMISC_EN_SHIFT
| base_qpn
);
131 context
->mcast
= cpu_to_be32(1 << SET_PORT_PROMISC_MODE_SHIFT
| base_qpn
);
132 context
->intra_no_vlan
= 0;
133 context
->no_vlan
= MLX4_NO_VLAN_IDX
;
134 context
->intra_vlan_miss
= 0;
135 context
->vlan_miss
= MLX4_VLAN_MISS_IDX
;
137 in_mod
= MLX4_SET_PORT_RQP_CALC
<< 8 | port
;
138 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
139 MLX4_CMD_TIME_CLASS_B
);
141 mlx4_free_cmd_mailbox(dev
, mailbox
);
145 int mlx4_en_QUERY_PORT(struct mlx4_en_dev
*mdev
, u8 port
)
147 struct mlx4_en_query_port_context
*qport_context
;
148 struct mlx4_en_priv
*priv
= netdev_priv(mdev
->pndev
[port
]);
149 struct mlx4_en_port_state
*state
= &priv
->port_state
;
150 struct mlx4_cmd_mailbox
*mailbox
;
153 mailbox
= mlx4_alloc_cmd_mailbox(mdev
->dev
);
155 return PTR_ERR(mailbox
);
156 memset(mailbox
->buf
, 0, sizeof(*qport_context
));
157 err
= mlx4_cmd_box(mdev
->dev
, 0, mailbox
->dma
, port
, 0,
158 MLX4_CMD_QUERY_PORT
, MLX4_CMD_TIME_CLASS_B
);
161 qport_context
= mailbox
->buf
;
163 /* This command is always accessed from Ethtool context
164 * already synchronized, no need in locking */
165 state
->link_state
= !!(qport_context
->link_up
& MLX4_EN_LINK_UP_MASK
);
166 if ((qport_context
->link_speed
& MLX4_EN_SPEED_MASK
) ==
168 state
->link_speed
= 1000;
170 state
->link_speed
= 10000;
171 state
->transciver
= qport_context
->transceiver
;
174 mlx4_free_cmd_mailbox(mdev
->dev
, mailbox
);
178 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev
*mdev
, u8 port
, u8 reset
)
180 struct mlx4_en_stat_out_mbox
*mlx4_en_stats
;
181 struct mlx4_en_priv
*priv
= netdev_priv(mdev
->pndev
[port
]);
182 struct net_device_stats
*stats
= &priv
->stats
;
183 struct mlx4_cmd_mailbox
*mailbox
;
184 u64 in_mod
= reset
<< 8 | port
;
188 mailbox
= mlx4_alloc_cmd_mailbox(mdev
->dev
);
190 return PTR_ERR(mailbox
);
191 memset(mailbox
->buf
, 0, sizeof(*mlx4_en_stats
));
192 err
= mlx4_cmd_box(mdev
->dev
, 0, mailbox
->dma
, in_mod
, 0,
193 MLX4_CMD_DUMP_ETH_STATS
, MLX4_CMD_TIME_CLASS_B
);
197 mlx4_en_stats
= mailbox
->buf
;
199 spin_lock_bh(&priv
->stats_lock
);
201 stats
->rx_packets
= 0;
203 for (i
= 0; i
< priv
->rx_ring_num
; i
++) {
204 stats
->rx_packets
+= priv
->rx_ring
[i
].packets
;
205 stats
->rx_bytes
+= priv
->rx_ring
[i
].bytes
;
207 stats
->tx_packets
= 0;
209 for (i
= 0; i
< priv
->tx_ring_num
; i
++) {
210 stats
->tx_packets
+= priv
->tx_ring
[i
].packets
;
211 stats
->tx_bytes
+= priv
->tx_ring
[i
].bytes
;
214 stats
->rx_errors
= be64_to_cpu(mlx4_en_stats
->PCS
) +
215 be32_to_cpu(mlx4_en_stats
->RdropLength
) +
216 be32_to_cpu(mlx4_en_stats
->RJBBR
) +
217 be32_to_cpu(mlx4_en_stats
->RCRC
) +
218 be32_to_cpu(mlx4_en_stats
->RRUNT
);
219 stats
->tx_errors
= be32_to_cpu(mlx4_en_stats
->TDROP
);
220 stats
->multicast
= be64_to_cpu(mlx4_en_stats
->MCAST_prio_0
) +
221 be64_to_cpu(mlx4_en_stats
->MCAST_prio_1
) +
222 be64_to_cpu(mlx4_en_stats
->MCAST_prio_2
) +
223 be64_to_cpu(mlx4_en_stats
->MCAST_prio_3
) +
224 be64_to_cpu(mlx4_en_stats
->MCAST_prio_4
) +
225 be64_to_cpu(mlx4_en_stats
->MCAST_prio_5
) +
226 be64_to_cpu(mlx4_en_stats
->MCAST_prio_6
) +
227 be64_to_cpu(mlx4_en_stats
->MCAST_prio_7
) +
228 be64_to_cpu(mlx4_en_stats
->MCAST_novlan
);
229 stats
->collisions
= 0;
230 stats
->rx_length_errors
= be32_to_cpu(mlx4_en_stats
->RdropLength
);
231 stats
->rx_over_errors
= be32_to_cpu(mlx4_en_stats
->RdropOvflw
);
232 stats
->rx_crc_errors
= be32_to_cpu(mlx4_en_stats
->RCRC
);
233 stats
->rx_frame_errors
= 0;
234 stats
->rx_fifo_errors
= be32_to_cpu(mlx4_en_stats
->RdropOvflw
);
235 stats
->rx_missed_errors
= be32_to_cpu(mlx4_en_stats
->RdropOvflw
);
236 stats
->tx_aborted_errors
= 0;
237 stats
->tx_carrier_errors
= 0;
238 stats
->tx_fifo_errors
= 0;
239 stats
->tx_heartbeat_errors
= 0;
240 stats
->tx_window_errors
= 0;
242 priv
->pkstats
.broadcast
=
243 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_0
) +
244 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_1
) +
245 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_2
) +
246 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_3
) +
247 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_4
) +
248 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_5
) +
249 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_6
) +
250 be64_to_cpu(mlx4_en_stats
->RBCAST_prio_7
) +
251 be64_to_cpu(mlx4_en_stats
->RBCAST_novlan
);
252 priv
->pkstats
.rx_prio
[0] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_0
);
253 priv
->pkstats
.rx_prio
[1] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_1
);
254 priv
->pkstats
.rx_prio
[2] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_2
);
255 priv
->pkstats
.rx_prio
[3] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_3
);
256 priv
->pkstats
.rx_prio
[4] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_4
);
257 priv
->pkstats
.rx_prio
[5] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_5
);
258 priv
->pkstats
.rx_prio
[6] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_6
);
259 priv
->pkstats
.rx_prio
[7] = be64_to_cpu(mlx4_en_stats
->RTOT_prio_7
);
260 priv
->pkstats
.tx_prio
[0] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_0
);
261 priv
->pkstats
.tx_prio
[1] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_1
);
262 priv
->pkstats
.tx_prio
[2] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_2
);
263 priv
->pkstats
.tx_prio
[3] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_3
);
264 priv
->pkstats
.tx_prio
[4] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_4
);
265 priv
->pkstats
.tx_prio
[5] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_5
);
266 priv
->pkstats
.tx_prio
[6] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_6
);
267 priv
->pkstats
.tx_prio
[7] = be64_to_cpu(mlx4_en_stats
->TTOT_prio_7
);
268 spin_unlock_bh(&priv
->stats_lock
);
271 mlx4_free_cmd_mailbox(mdev
->dev
, mailbox
);