2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c.h>
18 #include <linux/gpio.h>
19 #include <linux/leds.h>
20 #include <linux/input.h>
21 #include <linux/delay.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/spi/flash.h>
25 #include <linux/spi/spi.h>
26 #include <linux/mfd/mc13892.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/consumer.h>
30 #include <mach/common.h>
31 #include <mach/hardware.h>
32 #include <mach/iomux-mx51.h>
34 #include <mach/mxc_ehci.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/ulpi.h>
38 #include <mach/ulpi.h>
41 #include <asm/setup.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
45 #include <asm/mach-types.h>
47 #include "devices-imx51.h"
50 #include "cpu_op-mx51.h"
52 #define MX51_USB_CTRL_1_OFFSET 0x10
53 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
54 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
56 #define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
57 #define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
59 #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
60 #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
62 #define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
64 static iomux_v3_cfg_t mx51efika_pads
[] = {
66 MX51_PAD_UART1_RXD__UART1_RXD
,
67 MX51_PAD_UART1_TXD__UART1_TXD
,
68 MX51_PAD_UART1_RTS__UART1_RTS
,
69 MX51_PAD_UART1_CTS__UART1_CTS
,
72 MX51_PAD_SD1_CMD__SD1_CMD
,
73 MX51_PAD_SD1_CLK__SD1_CLK
,
74 MX51_PAD_SD1_DATA0__SD1_DATA0
,
75 MX51_PAD_SD1_DATA1__SD1_DATA1
,
76 MX51_PAD_SD1_DATA2__SD1_DATA2
,
77 MX51_PAD_SD1_DATA3__SD1_DATA3
,
80 MX51_PAD_SD2_CMD__SD2_CMD
,
81 MX51_PAD_SD2_CLK__SD2_CLK
,
82 MX51_PAD_SD2_DATA0__SD2_DATA0
,
83 MX51_PAD_SD2_DATA1__SD2_DATA1
,
84 MX51_PAD_SD2_DATA2__SD2_DATA2
,
85 MX51_PAD_SD2_DATA3__SD2_DATA3
,
88 MX51_PAD_GPIO1_0__SD1_CD
,
89 MX51_PAD_GPIO1_1__SD1_WP
,
90 MX51_PAD_GPIO1_7__SD2_WP
,
91 MX51_PAD_GPIO1_8__SD2_CD
,
94 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI
,
95 MX51_PAD_CSPI1_MISO__ECSPI1_MISO
,
96 MX51_PAD_CSPI1_SS0__GPIO4_24
,
97 MX51_PAD_CSPI1_SS1__GPIO4_25
,
98 MX51_PAD_CSPI1_RDY__ECSPI1_RDY
,
99 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK
,
100 MX51_PAD_GPIO1_6__GPIO1_6
,
103 MX51_PAD_USBH1_CLK__USBH1_CLK
,
104 MX51_PAD_USBH1_DIR__USBH1_DIR
,
105 MX51_PAD_USBH1_NXT__USBH1_NXT
,
106 MX51_PAD_USBH1_DATA0__USBH1_DATA0
,
107 MX51_PAD_USBH1_DATA1__USBH1_DATA1
,
108 MX51_PAD_USBH1_DATA2__USBH1_DATA2
,
109 MX51_PAD_USBH1_DATA3__USBH1_DATA3
,
110 MX51_PAD_USBH1_DATA4__USBH1_DATA4
,
111 MX51_PAD_USBH1_DATA5__USBH1_DATA5
,
112 MX51_PAD_USBH1_DATA6__USBH1_DATA6
,
113 MX51_PAD_USBH1_DATA7__USBH1_DATA7
,
116 MX51_PAD_GPIO1_5__GPIO1_5
,
119 MX51_PAD_EIM_A22__GPIO2_16
,
120 MX51_PAD_EIM_A16__GPIO2_10
,
123 MX51_PAD_EIM_D27__GPIO2_9
,
127 static const struct imxuart_platform_data uart_pdata
= {
128 .flags
= IMXUART_HAVE_RTSCTS
,
131 /* This function is board specific as the bit mask for the plldiv will also
132 * be different for other Freescale SoCs, thus a common bitmask is not
133 * possible and cannot get place in /plat-mxc/ehci.c.
135 static int initialize_otg_port(struct platform_device
*pdev
)
138 void __iomem
*usb_base
;
139 void __iomem
*usbother_base
;
140 usb_base
= ioremap(MX51_OTG_BASE_ADDR
, SZ_4K
);
143 usbother_base
= (void __iomem
*)(usb_base
+ MX5_USBOTHER_REGS_OFFSET
);
145 /* Set the PHY clock to 19.2MHz */
146 v
= __raw_readl(usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
147 v
&= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK
;
148 v
|= MX51_USB_PLL_DIV_19_2_MHZ
;
149 __raw_writel(v
, usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
154 return mx51_initialize_usb_hw(pdev
->id
, MXC_EHCI_INTERNAL_PHY
);
157 static struct mxc_usbh_platform_data dr_utmi_config
= {
158 .init
= initialize_otg_port
,
159 .portsc
= MXC_EHCI_UTMI_16BIT
,
162 static int initialize_usbh1_port(struct platform_device
*pdev
)
164 iomux_v3_cfg_t usbh1stp
= MX51_PAD_USBH1_STP__USBH1_STP
;
165 iomux_v3_cfg_t usbh1gpio
= MX51_PAD_USBH1_STP__GPIO1_27
;
167 void __iomem
*usb_base
;
168 void __iomem
*socregs_base
;
170 mxc_iomux_v3_setup_pad(usbh1gpio
);
171 gpio_request(EFIKAMX_USBH1_STP
, "usbh1_stp");
172 gpio_direction_output(EFIKAMX_USBH1_STP
, 0);
174 gpio_set_value(EFIKAMX_USBH1_STP
, 1);
177 usb_base
= ioremap(MX51_OTG_BASE_ADDR
, SZ_4K
);
178 socregs_base
= (void __iomem
*)(usb_base
+ MX5_USBOTHER_REGS_OFFSET
);
180 /* The clock for the USBH1 ULPI port will come externally */
182 v
= __raw_readl(socregs_base
+ MX51_USB_CTRL_1_OFFSET
);
183 __raw_writel(v
| MX51_USB_CTRL_UH1_EXT_CLK_EN
,
184 socregs_base
+ MX51_USB_CTRL_1_OFFSET
);
188 gpio_free(EFIKAMX_USBH1_STP
);
189 mxc_iomux_v3_setup_pad(usbh1stp
);
193 return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD
);
196 static struct mxc_usbh_platform_data usbh1_config
= {
197 .init
= initialize_usbh1_port
,
198 .portsc
= MXC_EHCI_MODE_ULPI
,
201 static void mx51_efika_hubreset(void)
203 gpio_request(EFIKAMX_USB_HUB_RESET
, "usb_hub_rst");
204 gpio_direction_output(EFIKAMX_USB_HUB_RESET
, 1);
206 gpio_set_value(EFIKAMX_USB_HUB_RESET
, 0);
208 gpio_set_value(EFIKAMX_USB_HUB_RESET
, 1);
211 static void __init
mx51_efika_usb(void)
213 mx51_efika_hubreset();
215 /* pulling it low, means no USB at all... */
216 gpio_request(EFIKA_USB_PHY_RESET
, "usb_phy_reset");
217 gpio_direction_output(EFIKA_USB_PHY_RESET
, 0);
219 gpio_set_value(EFIKA_USB_PHY_RESET
, 1);
221 usbh1_config
.otg
= imx_otg_ulpi_create(ULPI_OTG_DRVVBUS
|
222 ULPI_OTG_DRVVBUS_EXT
| ULPI_OTG_EXTVBUSIND
);
224 mxc_register_device(&mxc_usbdr_host_device
, &dr_utmi_config
);
225 if (usbh1_config
.otg
)
226 mxc_register_device(&mxc_usbh1_device
, &usbh1_config
);
229 static struct mtd_partition mx51_efika_spi_nor_partitions
[] = {
237 .offset
= MTDPART_OFS_APPEND
,
242 static struct flash_platform_data mx51_efika_spi_flash_data
= {
244 .parts
= mx51_efika_spi_nor_partitions
,
245 .nr_parts
= ARRAY_SIZE(mx51_efika_spi_nor_partitions
),
246 .type
= "sst25vf032b",
249 static struct regulator_consumer_supply sw1_consumers
[] = {
255 static struct regulator_consumer_supply vdig_consumers
[] = {
257 REGULATOR_SUPPLY("VDDA", "1-000a"),
258 REGULATOR_SUPPLY("VDDD", "1-000a"),
261 static struct regulator_consumer_supply vvideo_consumers
[] = {
263 REGULATOR_SUPPLY("VDDIO", "1-000a"),
266 static struct regulator_consumer_supply vsd_consumers
[] = {
267 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
268 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
271 static struct regulator_consumer_supply pwgt1_consumer
[] = {
277 static struct regulator_consumer_supply pwgt2_consumer
[] = {
283 static struct regulator_consumer_supply coincell_consumer
[] = {
285 .supply
= "coincell",
289 static struct regulator_init_data sw1_init
= {
294 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
295 .valid_modes_mask
= 0,
300 .mode
= REGULATOR_MODE_NORMAL
,
304 .num_consumer_supplies
= ARRAY_SIZE(sw1_consumers
),
305 .consumer_supplies
= sw1_consumers
,
308 static struct regulator_init_data sw2_init
= {
313 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
318 .mode
= REGULATOR_MODE_NORMAL
,
324 static struct regulator_init_data sw3_init
= {
329 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
335 static struct regulator_init_data sw4_init
= {
340 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
346 static struct regulator_init_data viohi_init
= {
354 static struct regulator_init_data vusb_init
= {
362 static struct regulator_init_data swbst_init
= {
368 static struct regulator_init_data vdig_init
= {
374 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
378 .num_consumer_supplies
= ARRAY_SIZE(vdig_consumers
),
379 .consumer_supplies
= vdig_consumers
,
382 static struct regulator_init_data vpll_init
= {
388 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
394 static struct regulator_init_data vusb2_init
= {
399 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
,
405 static struct regulator_init_data vvideo_init
= {
411 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
415 .num_consumer_supplies
= ARRAY_SIZE(vvideo_consumers
),
416 .consumer_supplies
= vvideo_consumers
,
419 static struct regulator_init_data vaudio_init
= {
425 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
430 static struct regulator_init_data vsd_init
= {
436 REGULATOR_CHANGE_VOLTAGE
,
439 .num_consumer_supplies
= ARRAY_SIZE(vsd_consumers
),
440 .consumer_supplies
= vsd_consumers
,
443 static struct regulator_init_data vcam_init
= {
449 REGULATOR_CHANGE_VOLTAGE
|
450 REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS
,
451 .valid_modes_mask
= REGULATOR_MODE_FAST
| REGULATOR_MODE_NORMAL
,
456 static struct regulator_init_data vgen1_init
= {
462 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
468 static struct regulator_init_data vgen2_init
= {
474 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
480 static struct regulator_init_data vgen3_init
= {
486 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
492 static struct regulator_init_data gpo1_init
= {
498 static struct regulator_init_data gpo2_init
= {
504 static struct regulator_init_data gpo3_init
= {
510 static struct regulator_init_data gpo4_init
= {
516 static struct regulator_init_data pwgt1_init
= {
518 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
521 .num_consumer_supplies
= ARRAY_SIZE(pwgt1_consumer
),
522 .consumer_supplies
= pwgt1_consumer
,
525 static struct regulator_init_data pwgt2_init
= {
527 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
530 .num_consumer_supplies
= ARRAY_SIZE(pwgt2_consumer
),
531 .consumer_supplies
= pwgt2_consumer
,
534 static struct regulator_init_data vcoincell_init
= {
540 REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_STATUS
,
542 .num_consumer_supplies
= ARRAY_SIZE(coincell_consumer
),
543 .consumer_supplies
= coincell_consumer
,
546 static struct mc13xxx_regulator_init_data mx51_efika_regulators
[] = {
547 { .id
= MC13892_SW1
, .init_data
= &sw1_init
},
548 { .id
= MC13892_SW2
, .init_data
= &sw2_init
},
549 { .id
= MC13892_SW3
, .init_data
= &sw3_init
},
550 { .id
= MC13892_SW4
, .init_data
= &sw4_init
},
551 { .id
= MC13892_SWBST
, .init_data
= &swbst_init
},
552 { .id
= MC13892_VIOHI
, .init_data
= &viohi_init
},
553 { .id
= MC13892_VPLL
, .init_data
= &vpll_init
},
554 { .id
= MC13892_VDIG
, .init_data
= &vdig_init
},
555 { .id
= MC13892_VSD
, .init_data
= &vsd_init
},
556 { .id
= MC13892_VUSB2
, .init_data
= &vusb2_init
},
557 { .id
= MC13892_VVIDEO
, .init_data
= &vvideo_init
},
558 { .id
= MC13892_VAUDIO
, .init_data
= &vaudio_init
},
559 { .id
= MC13892_VCAM
, .init_data
= &vcam_init
},
560 { .id
= MC13892_VGEN1
, .init_data
= &vgen1_init
},
561 { .id
= MC13892_VGEN2
, .init_data
= &vgen2_init
},
562 { .id
= MC13892_VGEN3
, .init_data
= &vgen3_init
},
563 { .id
= MC13892_VUSB
, .init_data
= &vusb_init
},
564 { .id
= MC13892_GPO1
, .init_data
= &gpo1_init
},
565 { .id
= MC13892_GPO2
, .init_data
= &gpo2_init
},
566 { .id
= MC13892_GPO3
, .init_data
= &gpo3_init
},
567 { .id
= MC13892_GPO4
, .init_data
= &gpo4_init
},
568 { .id
= MC13892_PWGT1SPI
, .init_data
= &pwgt1_init
},
569 { .id
= MC13892_PWGT2SPI
, .init_data
= &pwgt2_init
},
570 { .id
= MC13892_VCOINCELL
, .init_data
= &vcoincell_init
},
573 static struct mc13xxx_platform_data mx51_efika_mc13892_data
= {
574 .flags
= MC13XXX_USE_RTC
| MC13XXX_USE_REGULATOR
,
576 .num_regulators
= ARRAY_SIZE(mx51_efika_regulators
),
577 .regulators
= mx51_efika_regulators
,
581 static struct spi_board_info mx51_efika_spi_board_info
[] __initdata
= {
583 .modalias
= "m25p80",
584 .max_speed_hz
= 25000000,
587 .platform_data
= &mx51_efika_spi_flash_data
,
591 .modalias
= "mc13892",
592 .max_speed_hz
= 1000000,
595 .platform_data
= &mx51_efika_mc13892_data
,
596 .irq
= gpio_to_irq(EFIKAMX_PMIC
),
600 static int mx51_efika_spi_cs
[] = {
605 static const struct spi_imx_master mx51_efika_spi_pdata __initconst
= {
606 .chipselect
= mx51_efika_spi_cs
,
607 .num_chipselect
= ARRAY_SIZE(mx51_efika_spi_cs
),
610 void __init
efika_board_common_init(void)
612 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads
,
613 ARRAY_SIZE(mx51efika_pads
));
614 imx51_add_imx_uart(0, &uart_pdata
);
616 imx51_add_sdhci_esdhc_imx(0, NULL
);
618 /* FIXME: comes from original code. check this. */
619 if (mx51_revision() < IMX_CHIP_REVISION_2_0
)
620 sw2_init
.constraints
.state_mem
.uV
= 1100000;
621 else if (mx51_revision() == IMX_CHIP_REVISION_2_0
) {
622 sw2_init
.constraints
.state_mem
.uV
= 1250000;
623 sw1_init
.constraints
.state_mem
.uV
= 1000000;
625 if (machine_is_mx51_efikasb())
626 vgen1_init
.constraints
.max_uV
= 1200000;
628 gpio_request(EFIKAMX_PMIC
, "pmic irq");
629 gpio_direction_input(EFIKAMX_PMIC
);
630 spi_register_board_info(mx51_efika_spi_board_info
,
631 ARRAY_SIZE(mx51_efika_spi_board_info
));
632 imx51_add_ecspi(0, &mx51_efika_spi_pdata
);
634 #if defined(CONFIG_CPU_FREQ_IMX)
635 get_cpu_op
= mx51_get_cpu_op
;