drivers/ide/cmd64x.c

   1 /*
   2  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
   3  *           Due to massive hardware bugs, UltraDMA is only supported
   4  *           on the 646U2 and not on the 646U.
   5  *
   6  * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
   7  * Copyright (C) 1998           David S. Miller (davem@redhat.com)
   8  *
   9  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
  10  * Copyright (C) 2007,2009      MontaVista Software, Inc. <source@mvista.com>
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 #include <linux/ide.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/io.h>
  20
  21 #define DRV_NAME "cmd64x"
  22
  23 #define CMD_DEBUG 0
  24
  25 #if CMD_DEBUG
  26 #define cmdprintk(x...) printk(x)
  27 #else
  28 #define cmdprintk(x...)
  29 #endif
  30
  31 /*
  32  * CMD64x specific registers definition.
  33  */
  34 #define CFR             0x50
  35 #define   CFR_INTR_CH0          0x04
  36
  37 #define CMDTIM          0x52
  38 #define ARTTIM0         0x53
  39 #define DRWTIM0         0x54
  40 #define ARTTIM1         0x55
  41 #define DRWTIM1         0x56
  42 #define ARTTIM23        0x57
  43 #define   ARTTIM23_DIS_RA2      0x04
  44 #define   ARTTIM23_DIS_RA3      0x08
  45 #define   ARTTIM23_INTR_CH1     0x10
  46 #define DRWTIM2         0x58
  47 #define BRST            0x59
  48 #define DRWTIM3         0x5b
  49
  50 #define BMIDECR0        0x70
  51 #define MRDMODE         0x71
  52 #define   MRDMODE_INTR_CH0      0x04
  53 #define   MRDMODE_INTR_CH1      0x08
  54 #define UDIDETCR0       0x73
  55 #define DTPR0           0x74
  56 #define BMIDECR1        0x78
  57 #define BMIDECSR        0x79
  58 #define UDIDETCR1       0x7B
  59 #define DTPR1           0x7C
  60
  61 static u8 quantize_timing(int timing, int quant)
  62 {
  63         return (timing + quant - 1) / quant;
  64 }
  65
  66 /*
  67  * This routine calculates active/recovery counts and then writes them into
  68  * the chipset registers.
  69  */
  70 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
  71 {
  72         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  73         int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
  74         u8  cycle_count, active_count, recovery_count, drwtim;
  75         static const u8 recovery_values[] =
  76                 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
  77         static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
  78
  79         cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
  80                   cycle_time, active_time);
  81
  82         cycle_count     = quantize_timing( cycle_time, clock_time);
  83         active_count    = quantize_timing(active_time, clock_time);
  84         recovery_count  = cycle_count - active_count;
  85
  86         /*
  87          * In case we've got too long recovery phase, try to lengthen
  88          * the active phase
  89          */
  90         if (recovery_count > 16) {
  91                 active_count += recovery_count - 16;
  92                 recovery_count = 16;
  93         }
  94         if (active_count > 16)          /* shouldn't actually happen... */
  95                 active_count = 16;
  96
  97         cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
  98                   cycle_count, active_count, recovery_count);
  99
 100         /*
 101          * Convert values to internal chipset representation
 102          */
 103         recovery_count = recovery_values[recovery_count];
 104         active_count  &= 0x0f;
 105
 106         /* Program the active/recovery counts into the DRWTIM register */
 107         drwtim = (active_count << 4) | recovery_count;
 108         (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
 109         cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
 110 }
 111
 112 /*
 113  * This routine writes into the chipset registers
 114  * PIO setup/active/recovery timings.
 115  */
 116 static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
 117 {
 118         ide_hwif_t *hwif        = drive->hwif;
 119         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 120         struct ide_timing *t    = ide_timing_find_mode(XFER_PIO_0 + pio);
 121         unsigned long setup_count;
 122         unsigned int cycle_time;
 123         u8 arttim = 0;
 124
 125         static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
 126         static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
 127
 128         cycle_time = ide_pio_cycle_time(drive, pio);
 129
 130         program_cycle_times(drive, cycle_time, t->active);
 131
 132         setup_count = quantize_timing(t->setup,
 133                         1000 / (ide_pci_clk ? ide_pci_clk : 33));
 134
 135         /*
 136          * The primary channel has individual address setup timing registers
 137          * for each drive and the hardware selects the slowest timing itself.
 138          * The secondary channel has one common register and we have to select
 139          * the slowest address setup timing ourselves.
 140          */
 141         if (hwif->channel) {
 142                 ide_drive_t *pair = ide_get_pair_dev(drive);
 143
 144                 ide_set_drivedata(drive, (void *)setup_count);
 145
 146                 if (pair)
 147                         setup_count = max_t(u8, setup_count,
 148                                         (unsigned long)ide_get_drivedata(pair));
 149         }
 150
 151         if (setup_count > 5)            /* shouldn't actually happen... */
 152                 setup_count = 5;
 153         cmdprintk("Final address setup count: %d\n", setup_count);
 154
 155         /*
 156          * Program the address setup clocks into the ARTTIM registers.
 157          * Avoid clearing the secondary channel's interrupt bit.
 158          */
 159         (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
 160         if (hwif->channel)
 161                 arttim &= ~ARTTIM23_INTR_CH1;
 162         arttim &= ~0xc0;
 163         arttim |= setup_values[setup_count];
 164         (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
 165         cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
 166 }
 167
 168 /*
 169  * Attempts to set drive's PIO mode.
 170  * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 171  */
 172
 173 static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
 174 {
 175         /*
 176          * Filter out the prefetch control values
 177          * to prevent PIO5 from being programmed
 178          */
 179         if (pio == 8 || pio == 9)
 180                 return;
 181
 182         cmd64x_tune_pio(drive, pio);
 183 }
 184
 185 static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
 186 {
 187         ide_hwif_t *hwif        = drive->hwif;
 188         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 189         u8 unit                 = drive->dn & 0x01;
 190         u8 regU = 0, pciU       = hwif->channel ? UDIDETCR1 : UDIDETCR0;
 191
 192         if (speed >= XFER_SW_DMA_0) {
 193                 (void) pci_read_config_byte(dev, pciU, &regU);
 194                 regU &= ~(unit ? 0xCA : 0x35);
 195         }
 196
 197         switch(speed) {
 198         case XFER_UDMA_5:
 199                 regU |= unit ? 0x0A : 0x05;
 200                 break;
 201         case XFER_UDMA_4:
 202                 regU |= unit ? 0x4A : 0x15;
 203                 break;
 204         case XFER_UDMA_3:
 205                 regU |= unit ? 0x8A : 0x25;
 206                 break;
 207         case XFER_UDMA_2:
 208                 regU |= unit ? 0x42 : 0x11;
 209                 break;
 210         case XFER_UDMA_1:
 211                 regU |= unit ? 0x82 : 0x21;
 212                 break;
 213         case XFER_UDMA_0:
 214                 regU |= unit ? 0xC2 : 0x31;
 215                 break;
 216         case XFER_MW_DMA_2:
 217                 program_cycle_times(drive, 120, 70);
 218                 break;
 219         case XFER_MW_DMA_1:
 220                 program_cycle_times(drive, 150, 80);
 221                 break;
 222         case XFER_MW_DMA_0:
 223                 program_cycle_times(drive, 480, 215);
 224                 break;
 225         }
 226
 227         if (speed >= XFER_SW_DMA_0)
 228                 (void) pci_write_config_byte(dev, pciU, regU);
 229 }
 230
 231 static void cmd648_clear_irq(ide_drive_t *drive)
 232 {
 233         ide_hwif_t *hwif        = drive->hwif;
 234         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 235         unsigned long base      = pci_resource_start(dev, 4);
 236         u8  irq_mask            = hwif->channel ? MRDMODE_INTR_CH1 :
 237                                                   MRDMODE_INTR_CH0;
 238         u8  mrdmode             = inb(base + 1);
 239
 240         /* clear the interrupt bit */
 241         outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
 242              base + 1);
 243 }
 244
 245 static void cmd64x_clear_irq(ide_drive_t *drive)
 246 {
 247         ide_hwif_t *hwif        = drive->hwif;
 248         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 249         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 250         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 251                                                   CFR_INTR_CH0;
 252         u8  irq_stat            = 0;
 253
 254         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 255         /* clear the interrupt bit */
 256         (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
 257 }
 258
 259 static int cmd648_test_irq(ide_hwif_t *hwif)
 260 {
 261         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 262         unsigned long base      = pci_resource_start(dev, 4);
 263         u8 irq_mask             = hwif->channel ? MRDMODE_INTR_CH1 :
 264                                                   MRDMODE_INTR_CH0;
 265         u8 mrdmode              = inb(base + 1);
 266
 267         pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
 268                  hwif->name, mrdmode, irq_mask);
 269
 270         return (mrdmode & irq_mask) ? 1 : 0;
 271 }
 272
 273 static int cmd64x_test_irq(ide_hwif_t *hwif)
 274 {
 275         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 276         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 277         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 278                                                   CFR_INTR_CH0;
 279         u8  irq_stat            = 0;
 280
 281         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 282
 283         pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
 284                  hwif->name, irq_stat, irq_mask);
 285
 286         return (irq_stat & irq_mask) ? 1 : 0;
 287 }
 288
 289 /*
 290  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 291  * event order for DMA transfers.
 292  */
 293
 294 static int cmd646_1_dma_end(ide_drive_t *drive)
 295 {
 296         ide_hwif_t *hwif = drive->hwif;
 297         u8 dma_stat = 0, dma_cmd = 0;
 298
 299         /* get DMA status */
 300         dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 301         /* read DMA command state */
 302         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 303         /* stop DMA */
 304         outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
 305         /* clear the INTR & ERROR bits */
 306         outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
 307         /* verify good DMA status */
 308         return (dma_stat & 7) != 4;
 309 }
 310
 311 static int init_chipset_cmd64x(struct pci_dev *dev)
 312 {
 313         u8 mrdmode = 0;
 314
 315         /* Set a good latency timer and cache line size value. */
 316         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 317         /* FIXME: pci_set_master() to ensure a good latency timer value */
 318
 319         /*
 320          * Enable interrupts, select MEMORY READ LINE for reads.
 321          *
 322          * NOTE: although not mentioned in the PCI0646U specs,
 323          * bits 0-1 are write only and won't be read back as
 324          * set or not -- PCI0646U2 specs clarify this point.
 325          */
 326         (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
 327         mrdmode &= ~0x30;
 328         (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
 329
 330         return 0;
 331 }
 332
 333 static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
 334 {
 335         struct pci_dev  *dev    = to_pci_dev(hwif->dev);
 336         u8 bmidecsr = 0, mask   = hwif->channel ? 0x02 : 0x01;
 337
 338         switch (dev->device) {
 339         case PCI_DEVICE_ID_CMD_648:
 340         case PCI_DEVICE_ID_CMD_649:
 341                 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
 342                 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 343         default:
 344                 return ATA_CBL_PATA40;
 345         }
 346 }
 347
 348 static const struct ide_port_ops cmd64x_port_ops = {
 349         .set_pio_mode           = cmd64x_set_pio_mode,
 350         .set_dma_mode           = cmd64x_set_dma_mode,
 351         .clear_irq              = cmd64x_clear_irq,
 352         .test_irq               = cmd64x_test_irq,
 353         .cable_detect           = cmd64x_cable_detect,
 354 };
 355
 356 static const struct ide_port_ops cmd648_port_ops = {
 357         .set_pio_mode           = cmd64x_set_pio_mode,
 358         .set_dma_mode           = cmd64x_set_dma_mode,
 359         .clear_irq              = cmd648_clear_irq,
 360         .test_irq               = cmd648_test_irq,
 361         .cable_detect           = cmd64x_cable_detect,
 362 };
 363
 364 static const struct ide_dma_ops cmd646_rev1_dma_ops = {
 365         .dma_host_set           = ide_dma_host_set,
 366         .dma_setup              = ide_dma_setup,
 367         .dma_start              = ide_dma_start,
 368         .dma_end                = cmd646_1_dma_end,
 369         .dma_test_irq           = ide_dma_test_irq,
 370         .dma_lost_irq           = ide_dma_lost_irq,
 371         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 372         .dma_sff_read_status    = ide_dma_sff_read_status,
 373 };
 374
 375 static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
 376         {       /* 0: CMD643 */
 377                 .name           = DRV_NAME,
 378                 .init_chipset   = init_chipset_cmd64x,
 379                 .enablebits     = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
 380                 .port_ops       = &cmd64x_port_ops,
 381                 .host_flags     = IDE_HFLAG_CLEAR_SIMPLEX |
 382                                   IDE_HFLAG_ABUSE_PREFETCH |
 383                                   IDE_HFLAG_SERIALIZE,
 384                 .pio_mask       = ATA_PIO5,
 385                 .mwdma_mask     = ATA_MWDMA2,
 386                 .udma_mask      = 0x00, /* no udma */
 387         },
 388         {       /* 1: CMD646 */
 389                 .name           = DRV_NAME,
 390                 .init_chipset   = init_chipset_cmd64x,
 391                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 392                 .port_ops       = &cmd648_port_ops,
 393                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH |
 394                                   IDE_HFLAG_SERIALIZE,
 395                 .pio_mask       = ATA_PIO5,
 396                 .mwdma_mask     = ATA_MWDMA2,
 397                 .udma_mask      = ATA_UDMA2,
 398         },
 399         {       /* 2: CMD648 */
 400                 .name           = DRV_NAME,
 401                 .init_chipset   = init_chipset_cmd64x,
 402                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 403                 .port_ops       = &cmd648_port_ops,
 404                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH,
 405                 .pio_mask       = ATA_PIO5,
 406                 .mwdma_mask     = ATA_MWDMA2,
 407                 .udma_mask      = ATA_UDMA4,
 408         },
 409         {       /* 3: CMD649 */
 410                 .name           = DRV_NAME,
 411                 .init_chipset   = init_chipset_cmd64x,
 412                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 413                 .port_ops       = &cmd648_port_ops,
 414                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH,
 415                 .pio_mask       = ATA_PIO5,
 416                 .mwdma_mask     = ATA_MWDMA2,
 417                 .udma_mask      = ATA_UDMA5,
 418         }
 419 };
 420
 421 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 422 {
 423         struct ide_port_info d;
 424         u8 idx = id->driver_data;
 425
 426         d = cmd64x_chipsets[idx];
 427
 428         if (idx == 1) {
 429                 /*
 430                  * UltraDMA only supported on PCI646U and PCI646U2, which
 431                  * correspond to revisions 0x03, 0x05 and 0x07 respectively.
 432                  * Actually, although the CMD tech support people won't
 433                  * tell me the details, the 0x03 revision cannot support
 434                  * UDMA correctly without hardware modifications, and even
 435                  * then it only works with Quantum disks due to some
 436                  * hold time assumptions in the 646U part which are fixed
 437                  * in the 646U2.
 438                  *
 439                  * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
 440                  */
 441                 if (dev->revision < 5) {
 442                         d.udma_mask = 0x00;
 443                         /*
 444                          * The original PCI0646 didn't have the primary
 445                          * channel enable bit, it appeared starting with
 446                          * PCI0646U (i.e. revision ID 3).
 447                          */
 448                         if (dev->revision < 3) {
 449                                 d.enablebits[0].reg = 0;
 450                                 d.port_ops = &cmd64x_port_ops;
 451                                 if (dev->revision == 1)
 452                                         d.dma_ops = &cmd646_rev1_dma_ops;
 453                         }
 454                 }
 455         }
 456
 457         return ide_pci_init_one(dev, &d, NULL);
 458 }
 459
 460 static const struct pci_device_id cmd64x_pci_tbl[] = {
 461         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
 462         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
 463         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
 464         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
 465         { 0, },
 466 };
 467 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
 468
 469 static struct pci_driver cmd64x_pci_driver = {
 470         .name           = "CMD64x_IDE",
 471         .id_table       = cmd64x_pci_tbl,
 472         .probe          = cmd64x_init_one,
 473         .remove         = ide_pci_remove,
 474         .suspend        = ide_pci_suspend,
 475         .resume         = ide_pci_resume,
 476 };
 477
 478 static int __init cmd64x_ide_init(void)
 479 {
 480         return ide_pci_register_driver(&cmd64x_pci_driver);
 481 }
 482
 483 static void __exit cmd64x_ide_exit(void)
 484 {
 485         pci_unregister_driver(&cmd64x_pci_driver);
 486 }
 487
 488 module_init(cmd64x_ide_init);
 489 module_exit(cmd64x_ide_exit);
 490
 491 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
 492 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
 493 MODULE_LICENSE("GPL");