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drm/radeon/kms/pm: add a proper pm profile init function for fusion
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
blob1d603a3335db65b4bf425228a8f98221d01fcd48
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
45 {
46 u16 ctl, v;
47 int cap, err;
48
49 cap = pci_pcie_cap(rdev->pdev);
50 if (!cap)
51 return;
52
53 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
54 if (err)
55 return;
56
57 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
58
59 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
60 * to avoid hangs or perfomance issues
61 */
62 if ((v == 0) || (v == 6) || (v == 7)) {
63 ctl &= ~PCI_EXP_DEVCTL_READRQ;
64 ctl |= (2 << 12);
65 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
66 }
67 }
68
69 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
70 {
71 /* enable the pflip int */
72 radeon_irq_kms_pflip_irq_get(rdev, crtc);
73 }
74
75 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
76 {
77 /* disable the pflip int */
78 radeon_irq_kms_pflip_irq_put(rdev, crtc);
79 }
80
81 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
82 {
83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
84 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
85
86 /* Lock the graphics update lock */
87 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
88 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
89
90 /* update the scanout addresses */
91 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
92 upper_32_bits(crtc_base));
93 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
94 (u32)crtc_base);
95
96 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
97 upper_32_bits(crtc_base));
98 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
99 (u32)crtc_base);
100
101 /* Wait for update_pending to go high. */
102 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
103 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
104
105 /* Unlock the lock, so double-buffering can take place inside vblank */
106 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
107 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
108
109 /* Return current update_pending status: */
110 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
111 }
112
113 /* get temperature in millidegrees */
114 int evergreen_get_temp(struct radeon_device *rdev)
115 {
116 u32 temp, toffset;
117 int actual_temp = 0;
118
119 if (rdev->family == CHIP_JUNIPER) {
120 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
121 TOFFSET_SHIFT;
122 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
123 TS0_ADC_DOUT_SHIFT;
124
125 if (toffset & 0x100)
126 actual_temp = temp / 2 - (0x200 - toffset);
127 else
128 actual_temp = temp / 2 + toffset;
129
130 actual_temp = actual_temp * 1000;
131
132 } else {
133 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
134 ASIC_T_SHIFT;
135
136 if (temp & 0x400)
137 actual_temp = -256;
138 else if (temp & 0x200)
139 actual_temp = 255;
140 else if (temp & 0x100) {
141 actual_temp = temp & 0x1ff;
142 actual_temp |= ~0x1ff;
143 } else
144 actual_temp = temp & 0xff;
145
146 actual_temp = (actual_temp * 1000) / 2;
147 }
148
149 return actual_temp;
150 }
151
152 int sumo_get_temp(struct radeon_device *rdev)
153 {
154 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
155 int actual_temp = temp - 49;
156
157 return actual_temp * 1000;
158 }
159
160 void sumo_pm_init_profile(struct radeon_device *rdev)
161 {
162 int idx;
163
164 /* default */
165 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
166 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
167 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
168 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
169
170 /* low,mid sh/mh */
171 if (rdev->flags & RADEON_IS_MOBILITY)
172 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
173 else
174 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
175
176 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
177 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
178 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
179 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
180
181 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
182 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
183 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
184 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
185
186 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
187 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
188 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
189 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
190
191 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
192 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
193 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
194 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
195
196 /* high sh/mh */
197 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
198 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
199 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
200 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
201 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
202 rdev->pm.power_state[idx].num_clock_modes - 1;
203
204 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
205 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
206 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
207 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
208 rdev->pm.power_state[idx].num_clock_modes - 1;
209 }
210
211 void evergreen_pm_misc(struct radeon_device *rdev)
212 {
213 int req_ps_idx = rdev->pm.requested_power_state_index;
214 int req_cm_idx = rdev->pm.requested_clock_mode_index;
215 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
216 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
217
218 if (voltage->type == VOLTAGE_SW) {
219 /* 0xff01 is a flag rather then an actual voltage */
220 if (voltage->voltage == 0xff01)
221 return;
222 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
223 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
224 rdev->pm.current_vddc = voltage->voltage;
225 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
226 }
227 /* 0xff01 is a flag rather then an actual voltage */
228 if (voltage->vddci == 0xff01)
229 return;
230 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
231 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
232 rdev->pm.current_vddci = voltage->vddci;
233 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
234 }
235 }
236 }
237
238 void evergreen_pm_prepare(struct radeon_device *rdev)
239 {
240 struct drm_device *ddev = rdev->ddev;
241 struct drm_crtc *crtc;
242 struct radeon_crtc *radeon_crtc;
243 u32 tmp;
244
245 /* disable any active CRTCs */
246 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
247 radeon_crtc = to_radeon_crtc(crtc);
248 if (radeon_crtc->enabled) {
249 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
250 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
251 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
252 }
253 }
254 }
255
256 void evergreen_pm_finish(struct radeon_device *rdev)
257 {
258 struct drm_device *ddev = rdev->ddev;
259 struct drm_crtc *crtc;
260 struct radeon_crtc *radeon_crtc;
261 u32 tmp;
262
263 /* enable any active CRTCs */
264 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
265 radeon_crtc = to_radeon_crtc(crtc);
266 if (radeon_crtc->enabled) {
267 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
268 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
269 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
270 }
271 }
272 }
273
274 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
275 {
276 bool connected = false;
277
278 switch (hpd) {
279 case RADEON_HPD_1:
280 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
281 connected = true;
282 break;
283 case RADEON_HPD_2:
284 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
285 connected = true;
286 break;
287 case RADEON_HPD_3:
288 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
289 connected = true;
290 break;
291 case RADEON_HPD_4:
292 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
293 connected = true;
294 break;
295 case RADEON_HPD_5:
296 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
297 connected = true;
298 break;
299 case RADEON_HPD_6:
300 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
301 connected = true;
302 break;
303 default:
304 break;
305 }
306
307 return connected;
308 }
309
310 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
311 enum radeon_hpd_id hpd)
312 {
313 u32 tmp;
314 bool connected = evergreen_hpd_sense(rdev, hpd);
315
316 switch (hpd) {
317 case RADEON_HPD_1:
318 tmp = RREG32(DC_HPD1_INT_CONTROL);
319 if (connected)
320 tmp &= ~DC_HPDx_INT_POLARITY;
321 else
322 tmp |= DC_HPDx_INT_POLARITY;
323 WREG32(DC_HPD1_INT_CONTROL, tmp);
324 break;
325 case RADEON_HPD_2:
326 tmp = RREG32(DC_HPD2_INT_CONTROL);
327 if (connected)
328 tmp &= ~DC_HPDx_INT_POLARITY;
329 else
330 tmp |= DC_HPDx_INT_POLARITY;
331 WREG32(DC_HPD2_INT_CONTROL, tmp);
332 break;
333 case RADEON_HPD_3:
334 tmp = RREG32(DC_HPD3_INT_CONTROL);
335 if (connected)
336 tmp &= ~DC_HPDx_INT_POLARITY;
337 else
338 tmp |= DC_HPDx_INT_POLARITY;
339 WREG32(DC_HPD3_INT_CONTROL, tmp);
340 break;
341 case RADEON_HPD_4:
342 tmp = RREG32(DC_HPD4_INT_CONTROL);
343 if (connected)
344 tmp &= ~DC_HPDx_INT_POLARITY;
345 else
346 tmp |= DC_HPDx_INT_POLARITY;
347 WREG32(DC_HPD4_INT_CONTROL, tmp);
348 break;
349 case RADEON_HPD_5:
350 tmp = RREG32(DC_HPD5_INT_CONTROL);
351 if (connected)
352 tmp &= ~DC_HPDx_INT_POLARITY;
353 else
354 tmp |= DC_HPDx_INT_POLARITY;
355 WREG32(DC_HPD5_INT_CONTROL, tmp);
356 break;
357 case RADEON_HPD_6:
358 tmp = RREG32(DC_HPD6_INT_CONTROL);
359 if (connected)
360 tmp &= ~DC_HPDx_INT_POLARITY;
361 else
362 tmp |= DC_HPDx_INT_POLARITY;
363 WREG32(DC_HPD6_INT_CONTROL, tmp);
364 break;
365 default:
366 break;
367 }
368 }
369
370 void evergreen_hpd_init(struct radeon_device *rdev)
371 {
372 struct drm_device *dev = rdev->ddev;
373 struct drm_connector *connector;
374 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
375 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
376
377 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
378 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
379 switch (radeon_connector->hpd.hpd) {
380 case RADEON_HPD_1:
381 WREG32(DC_HPD1_CONTROL, tmp);
382 rdev->irq.hpd[0] = true;
383 break;
384 case RADEON_HPD_2:
385 WREG32(DC_HPD2_CONTROL, tmp);
386 rdev->irq.hpd[1] = true;
387 break;
388 case RADEON_HPD_3:
389 WREG32(DC_HPD3_CONTROL, tmp);
390 rdev->irq.hpd[2] = true;
391 break;
392 case RADEON_HPD_4:
393 WREG32(DC_HPD4_CONTROL, tmp);
394 rdev->irq.hpd[3] = true;
395 break;
396 case RADEON_HPD_5:
397 WREG32(DC_HPD5_CONTROL, tmp);
398 rdev->irq.hpd[4] = true;
399 break;
400 case RADEON_HPD_6:
401 WREG32(DC_HPD6_CONTROL, tmp);
402 rdev->irq.hpd[5] = true;
403 break;
404 default:
405 break;
406 }
407 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
408 }
409 if (rdev->irq.installed)
410 evergreen_irq_set(rdev);
411 }
412
413 void evergreen_hpd_fini(struct radeon_device *rdev)
414 {
415 struct drm_device *dev = rdev->ddev;
416 struct drm_connector *connector;
417
418 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
419 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
420 switch (radeon_connector->hpd.hpd) {
421 case RADEON_HPD_1:
422 WREG32(DC_HPD1_CONTROL, 0);
423 rdev->irq.hpd[0] = false;
424 break;
425 case RADEON_HPD_2:
426 WREG32(DC_HPD2_CONTROL, 0);
427 rdev->irq.hpd[1] = false;
428 break;
429 case RADEON_HPD_3:
430 WREG32(DC_HPD3_CONTROL, 0);
431 rdev->irq.hpd[2] = false;
432 break;
433 case RADEON_HPD_4:
434 WREG32(DC_HPD4_CONTROL, 0);
435 rdev->irq.hpd[3] = false;
436 break;
437 case RADEON_HPD_5:
438 WREG32(DC_HPD5_CONTROL, 0);
439 rdev->irq.hpd[4] = false;
440 break;
441 case RADEON_HPD_6:
442 WREG32(DC_HPD6_CONTROL, 0);
443 rdev->irq.hpd[5] = false;
444 break;
445 default:
446 break;
447 }
448 }
449 }
450
451 /* watermark setup */
452
453 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
454 struct radeon_crtc *radeon_crtc,
455 struct drm_display_mode *mode,
456 struct drm_display_mode *other_mode)
457 {
458 u32 tmp;
459 /*
460 * Line Buffer Setup
461 * There are 3 line buffers, each one shared by 2 display controllers.
462 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
463 * the display controllers. The paritioning is done via one of four
464 * preset allocations specified in bits 2:0:
465 * first display controller
466 * 0 - first half of lb (3840 * 2)
467 * 1 - first 3/4 of lb (5760 * 2)
468 * 2 - whole lb (7680 * 2), other crtc must be disabled
469 * 3 - first 1/4 of lb (1920 * 2)
470 * second display controller
471 * 4 - second half of lb (3840 * 2)
472 * 5 - second 3/4 of lb (5760 * 2)
473 * 6 - whole lb (7680 * 2), other crtc must be disabled
474 * 7 - last 1/4 of lb (1920 * 2)
475 */
476 /* this can get tricky if we have two large displays on a paired group
477 * of crtcs. Ideally for multiple large displays we'd assign them to
478 * non-linked crtcs for maximum line buffer allocation.
479 */
480 if (radeon_crtc->base.enabled && mode) {
481 if (other_mode)
482 tmp = 0; /* 1/2 */
483 else
484 tmp = 2; /* whole */
485 } else
486 tmp = 0;
487
488 /* second controller of the pair uses second half of the lb */
489 if (radeon_crtc->crtc_id % 2)
490 tmp += 4;
491 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
492
493 if (radeon_crtc->base.enabled && mode) {
494 switch (tmp) {
495 case 0:
496 case 4:
497 default:
498 if (ASIC_IS_DCE5(rdev))
499 return 4096 * 2;
500 else
501 return 3840 * 2;
502 case 1:
503 case 5:
504 if (ASIC_IS_DCE5(rdev))
505 return 6144 * 2;
506 else
507 return 5760 * 2;
508 case 2:
509 case 6:
510 if (ASIC_IS_DCE5(rdev))
511 return 8192 * 2;
512 else
513 return 7680 * 2;
514 case 3:
515 case 7:
516 if (ASIC_IS_DCE5(rdev))
517 return 2048 * 2;
518 else
519 return 1920 * 2;
520 }
521 }
522
523 /* controller not enabled, so no lb used */
524 return 0;
525 }
526
527 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
528 {
529 u32 tmp = RREG32(MC_SHARED_CHMAP);
530
531 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
532 case 0:
533 default:
534 return 1;
535 case 1:
536 return 2;
537 case 2:
538 return 4;
539 case 3:
540 return 8;
541 }
542 }
543
544 struct evergreen_wm_params {
545 u32 dram_channels; /* number of dram channels */
546 u32 yclk; /* bandwidth per dram data pin in kHz */
547 u32 sclk; /* engine clock in kHz */
548 u32 disp_clk; /* display clock in kHz */
549 u32 src_width; /* viewport width */
550 u32 active_time; /* active display time in ns */
551 u32 blank_time; /* blank time in ns */
552 bool interlaced; /* mode is interlaced */
553 fixed20_12 vsc; /* vertical scale ratio */
554 u32 num_heads; /* number of active crtcs */
555 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
556 u32 lb_size; /* line buffer allocated to pipe */
557 u32 vtaps; /* vertical scaler taps */
558 };
559
560 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
561 {
562 /* Calculate DRAM Bandwidth and the part allocated to display. */
563 fixed20_12 dram_efficiency; /* 0.7 */
564 fixed20_12 yclk, dram_channels, bandwidth;
565 fixed20_12 a;
566
567 a.full = dfixed_const(1000);
568 yclk.full = dfixed_const(wm->yclk);
569 yclk.full = dfixed_div(yclk, a);
570 dram_channels.full = dfixed_const(wm->dram_channels * 4);
571 a.full = dfixed_const(10);
572 dram_efficiency.full = dfixed_const(7);
573 dram_efficiency.full = dfixed_div(dram_efficiency, a);
574 bandwidth.full = dfixed_mul(dram_channels, yclk);
575 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
576
577 return dfixed_trunc(bandwidth);
578 }
579
580 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
581 {
582 /* Calculate DRAM Bandwidth and the part allocated to display. */
583 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
584 fixed20_12 yclk, dram_channels, bandwidth;
585 fixed20_12 a;
586
587 a.full = dfixed_const(1000);
588 yclk.full = dfixed_const(wm->yclk);
589 yclk.full = dfixed_div(yclk, a);
590 dram_channels.full = dfixed_const(wm->dram_channels * 4);
591 a.full = dfixed_const(10);
592 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
593 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
594 bandwidth.full = dfixed_mul(dram_channels, yclk);
595 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
596
597 return dfixed_trunc(bandwidth);
598 }
599
600 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
601 {
602 /* Calculate the display Data return Bandwidth */
603 fixed20_12 return_efficiency; /* 0.8 */
604 fixed20_12 sclk, bandwidth;
605 fixed20_12 a;
606
607 a.full = dfixed_const(1000);
608 sclk.full = dfixed_const(wm->sclk);
609 sclk.full = dfixed_div(sclk, a);
610 a.full = dfixed_const(10);
611 return_efficiency.full = dfixed_const(8);
612 return_efficiency.full = dfixed_div(return_efficiency, a);
613 a.full = dfixed_const(32);
614 bandwidth.full = dfixed_mul(a, sclk);
615 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
616
617 return dfixed_trunc(bandwidth);
618 }
619
620 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
621 {
622 /* Calculate the DMIF Request Bandwidth */
623 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
624 fixed20_12 disp_clk, bandwidth;
625 fixed20_12 a;
626
627 a.full = dfixed_const(1000);
628 disp_clk.full = dfixed_const(wm->disp_clk);
629 disp_clk.full = dfixed_div(disp_clk, a);
630 a.full = dfixed_const(10);
631 disp_clk_request_efficiency.full = dfixed_const(8);
632 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
633 a.full = dfixed_const(32);
634 bandwidth.full = dfixed_mul(a, disp_clk);
635 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
636
637 return dfixed_trunc(bandwidth);
638 }
639
640 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
641 {
642 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
643 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
644 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
645 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
646
647 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
648 }
649
650 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
651 {
652 /* Calculate the display mode Average Bandwidth
653 * DisplayMode should contain the source and destination dimensions,
654 * timing, etc.
655 */
656 fixed20_12 bpp;
657 fixed20_12 line_time;
658 fixed20_12 src_width;
659 fixed20_12 bandwidth;
660 fixed20_12 a;
661
662 a.full = dfixed_const(1000);
663 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
664 line_time.full = dfixed_div(line_time, a);
665 bpp.full = dfixed_const(wm->bytes_per_pixel);
666 src_width.full = dfixed_const(wm->src_width);
667 bandwidth.full = dfixed_mul(src_width, bpp);
668 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
669 bandwidth.full = dfixed_div(bandwidth, line_time);
670
671 return dfixed_trunc(bandwidth);
672 }
673
674 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
675 {
676 /* First calcualte the latency in ns */
677 u32 mc_latency = 2000; /* 2000 ns. */
678 u32 available_bandwidth = evergreen_available_bandwidth(wm);
679 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
680 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
681 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
682 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
683 (wm->num_heads * cursor_line_pair_return_time);
684 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
685 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
686 fixed20_12 a, b, c;
687
688 if (wm->num_heads == 0)
689 return 0;
690
691 a.full = dfixed_const(2);
692 b.full = dfixed_const(1);
693 if ((wm->vsc.full > a.full) ||
694 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
695 (wm->vtaps >= 5) ||
696 ((wm->vsc.full >= a.full) && wm->interlaced))
697 max_src_lines_per_dst_line = 4;
698 else
699 max_src_lines_per_dst_line = 2;
700
701 a.full = dfixed_const(available_bandwidth);
702 b.full = dfixed_const(wm->num_heads);
703 a.full = dfixed_div(a, b);
704
705 b.full = dfixed_const(1000);
706 c.full = dfixed_const(wm->disp_clk);
707 b.full = dfixed_div(c, b);
708 c.full = dfixed_const(wm->bytes_per_pixel);
709 b.full = dfixed_mul(b, c);
710
711 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
712
713 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
714 b.full = dfixed_const(1000);
715 c.full = dfixed_const(lb_fill_bw);
716 b.full = dfixed_div(c, b);
717 a.full = dfixed_div(a, b);
718 line_fill_time = dfixed_trunc(a);
719
720 if (line_fill_time < wm->active_time)
721 return latency;
722 else
723 return latency + (line_fill_time - wm->active_time);
724
725 }
726
727 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
728 {
729 if (evergreen_average_bandwidth(wm) <=
730 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
731 return true;
732 else
733 return false;
734 };
735
736 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
737 {
738 if (evergreen_average_bandwidth(wm) <=
739 (evergreen_available_bandwidth(wm) / wm->num_heads))
740 return true;
741 else
742 return false;
743 };
744
745 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
746 {
747 u32 lb_partitions = wm->lb_size / wm->src_width;
748 u32 line_time = wm->active_time + wm->blank_time;
749 u32 latency_tolerant_lines;
750 u32 latency_hiding;
751 fixed20_12 a;
752
753 a.full = dfixed_const(1);
754 if (wm->vsc.full > a.full)
755 latency_tolerant_lines = 1;
756 else {
757 if (lb_partitions <= (wm->vtaps + 1))
758 latency_tolerant_lines = 1;
759 else
760 latency_tolerant_lines = 2;
761 }
762
763 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
764
765 if (evergreen_latency_watermark(wm) <= latency_hiding)
766 return true;
767 else
768 return false;
769 }
770
771 static void evergreen_program_watermarks(struct radeon_device *rdev,
772 struct radeon_crtc *radeon_crtc,
773 u32 lb_size, u32 num_heads)
774 {
775 struct drm_display_mode *mode = &radeon_crtc->base.mode;
776 struct evergreen_wm_params wm;
777 u32 pixel_period;
778 u32 line_time = 0;
779 u32 latency_watermark_a = 0, latency_watermark_b = 0;
780 u32 priority_a_mark = 0, priority_b_mark = 0;
781 u32 priority_a_cnt = PRIORITY_OFF;
782 u32 priority_b_cnt = PRIORITY_OFF;
783 u32 pipe_offset = radeon_crtc->crtc_id * 16;
784 u32 tmp, arb_control3;
785 fixed20_12 a, b, c;
786
787 if (radeon_crtc->base.enabled && num_heads && mode) {
788 pixel_period = 1000000 / (u32)mode->clock;
789 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
790 priority_a_cnt = 0;
791 priority_b_cnt = 0;
792
793 wm.yclk = rdev->pm.current_mclk * 10;
794 wm.sclk = rdev->pm.current_sclk * 10;
795 wm.disp_clk = mode->clock;
796 wm.src_width = mode->crtc_hdisplay;
797 wm.active_time = mode->crtc_hdisplay * pixel_period;
798 wm.blank_time = line_time - wm.active_time;
799 wm.interlaced = false;
800 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
801 wm.interlaced = true;
802 wm.vsc = radeon_crtc->vsc;
803 wm.vtaps = 1;
804 if (radeon_crtc->rmx_type != RMX_OFF)
805 wm.vtaps = 2;
806 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
807 wm.lb_size = lb_size;
808 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
809 wm.num_heads = num_heads;
810
811 /* set for high clocks */
812 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
813 /* set for low clocks */
814 /* wm.yclk = low clk; wm.sclk = low clk */
815 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
816
817 /* possibly force display priority to high */
818 /* should really do this at mode validation time... */
819 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
820 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
821 !evergreen_check_latency_hiding(&wm) ||
822 (rdev->disp_priority == 2)) {
823 DRM_DEBUG_KMS("force priority to high\n");
824 priority_a_cnt |= PRIORITY_ALWAYS_ON;
825 priority_b_cnt |= PRIORITY_ALWAYS_ON;
826 }
827
828 a.full = dfixed_const(1000);
829 b.full = dfixed_const(mode->clock);
830 b.full = dfixed_div(b, a);
831 c.full = dfixed_const(latency_watermark_a);
832 c.full = dfixed_mul(c, b);
833 c.full = dfixed_mul(c, radeon_crtc->hsc);
834 c.full = dfixed_div(c, a);
835 a.full = dfixed_const(16);
836 c.full = dfixed_div(c, a);
837 priority_a_mark = dfixed_trunc(c);
838 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
839
840 a.full = dfixed_const(1000);
841 b.full = dfixed_const(mode->clock);
842 b.full = dfixed_div(b, a);
843 c.full = dfixed_const(latency_watermark_b);
844 c.full = dfixed_mul(c, b);
845 c.full = dfixed_mul(c, radeon_crtc->hsc);
846 c.full = dfixed_div(c, a);
847 a.full = dfixed_const(16);
848 c.full = dfixed_div(c, a);
849 priority_b_mark = dfixed_trunc(c);
850 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
851 }
852
853 /* select wm A */
854 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
855 tmp = arb_control3;
856 tmp &= ~LATENCY_WATERMARK_MASK(3);
857 tmp |= LATENCY_WATERMARK_MASK(1);
858 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
859 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
860 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
861 LATENCY_HIGH_WATERMARK(line_time)));
862 /* select wm B */
863 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
864 tmp &= ~LATENCY_WATERMARK_MASK(3);
865 tmp |= LATENCY_WATERMARK_MASK(2);
866 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
867 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
868 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
869 LATENCY_HIGH_WATERMARK(line_time)));
870 /* restore original selection */
871 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
872
873 /* write the priority marks */
874 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
875 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
876
877 }
878
879 void evergreen_bandwidth_update(struct radeon_device *rdev)
880 {
881 struct drm_display_mode *mode0 = NULL;
882 struct drm_display_mode *mode1 = NULL;
883 u32 num_heads = 0, lb_size;
884 int i;
885
886 radeon_update_display_priority(rdev);
887
888 for (i = 0; i < rdev->num_crtc; i++) {
889 if (rdev->mode_info.crtcs[i]->base.enabled)
890 num_heads++;
891 }
892 for (i = 0; i < rdev->num_crtc; i += 2) {
893 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
894 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
895 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
896 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
897 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
898 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
899 }
900 }
901
902 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
903 {
904 unsigned i;
905 u32 tmp;
906
907 for (i = 0; i < rdev->usec_timeout; i++) {
908 /* read MC_STATUS */
909 tmp = RREG32(SRBM_STATUS) & 0x1F00;
910 if (!tmp)
911 return 0;
912 udelay(1);
913 }
914 return -1;
915 }
916
917 /*
918 * GART
919 */
920 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
921 {
922 unsigned i;
923 u32 tmp;
924
925 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
926
927 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
928 for (i = 0; i < rdev->usec_timeout; i++) {
929 /* read MC_STATUS */
930 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
931 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
932 if (tmp == 2) {
933 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
934 return;
935 }
936 if (tmp) {
937 return;
938 }
939 udelay(1);
940 }
941 }
942
943 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
944 {
945 u32 tmp;
946 int r;
947
948 if (rdev->gart.robj == NULL) {
949 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
950 return -EINVAL;
951 }
952 r = radeon_gart_table_vram_pin(rdev);
953 if (r)
954 return r;
955 radeon_gart_restore(rdev);
956 /* Setup L2 cache */
957 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
958 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
959 EFFECTIVE_L2_QUEUE_SIZE(7));
960 WREG32(VM_L2_CNTL2, 0);
961 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
962 /* Setup TLB control */
963 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
964 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
965 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
966 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
967 if (rdev->flags & RADEON_IS_IGP) {
968 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
969 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
970 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
971 } else {
972 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
973 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
974 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
975 }
976 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
977 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
978 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
979 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
980 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
981 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
982 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
983 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
984 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
985 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
986 (u32)(rdev->dummy_page.addr >> 12));
987 WREG32(VM_CONTEXT1_CNTL, 0);
988
989 evergreen_pcie_gart_tlb_flush(rdev);
990 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
991 (unsigned)(rdev->mc.gtt_size >> 20),
992 (unsigned long long)rdev->gart.table_addr);
993 rdev->gart.ready = true;
994 return 0;
995 }
996
997 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
998 {
999 u32 tmp;
1000
1001 /* Disable all tables */
1002 WREG32(VM_CONTEXT0_CNTL, 0);
1003 WREG32(VM_CONTEXT1_CNTL, 0);
1004
1005 /* Setup L2 cache */
1006 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1007 EFFECTIVE_L2_QUEUE_SIZE(7));
1008 WREG32(VM_L2_CNTL2, 0);
1009 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1010 /* Setup TLB control */
1011 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1012 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1013 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1014 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1015 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1016 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1017 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1018 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1019 radeon_gart_table_vram_unpin(rdev);
1020 }
1021
1022 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1023 {
1024 evergreen_pcie_gart_disable(rdev);
1025 radeon_gart_table_vram_free(rdev);
1026 radeon_gart_fini(rdev);
1027 }
1028
1029
1030 void evergreen_agp_enable(struct radeon_device *rdev)
1031 {
1032 u32 tmp;
1033
1034 /* Setup L2 cache */
1035 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1036 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1037 EFFECTIVE_L2_QUEUE_SIZE(7));
1038 WREG32(VM_L2_CNTL2, 0);
1039 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1040 /* Setup TLB control */
1041 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1042 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1043 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1044 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1045 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1046 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1047 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1048 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1049 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1050 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1051 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1052 WREG32(VM_CONTEXT0_CNTL, 0);
1053 WREG32(VM_CONTEXT1_CNTL, 0);
1054 }
1055
1056 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1057 {
1058 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1059 save->vga_control[1] = RREG32(D2VGA_CONTROL);
1060 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1061 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1062 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1063 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1064 if (rdev->num_crtc >= 4) {
1065 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1066 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1067 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1068 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1069 }
1070 if (rdev->num_crtc >= 6) {
1071 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1072 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1073 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1074 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1075 }
1076
1077 /* Stop all video */
1078 WREG32(VGA_RENDER_CONTROL, 0);
1079 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1080 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1081 if (rdev->num_crtc >= 4) {
1082 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1083 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1084 }
1085 if (rdev->num_crtc >= 6) {
1086 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1087 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1088 }
1089 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1090 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1091 if (rdev->num_crtc >= 4) {
1092 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1093 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1094 }
1095 if (rdev->num_crtc >= 6) {
1096 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1097 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1098 }
1099 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1100 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1101 if (rdev->num_crtc >= 4) {
1102 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1103 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1104 }
1105 if (rdev->num_crtc >= 6) {
1106 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1107 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1108 }
1109
1110 WREG32(D1VGA_CONTROL, 0);
1111 WREG32(D2VGA_CONTROL, 0);
1112 if (rdev->num_crtc >= 4) {
1113 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1114 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1115 }
1116 if (rdev->num_crtc >= 6) {
1117 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1118 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1119 }
1120 }
1121
1122 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1123 {
1124 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1125 upper_32_bits(rdev->mc.vram_start));
1126 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1127 upper_32_bits(rdev->mc.vram_start));
1128 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1129 (u32)rdev->mc.vram_start);
1130 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1131 (u32)rdev->mc.vram_start);
1132
1133 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1134 upper_32_bits(rdev->mc.vram_start));
1135 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1136 upper_32_bits(rdev->mc.vram_start));
1137 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1138 (u32)rdev->mc.vram_start);
1139 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1140 (u32)rdev->mc.vram_start);
1141
1142 if (rdev->num_crtc >= 4) {
1143 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1144 upper_32_bits(rdev->mc.vram_start));
1145 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1146 upper_32_bits(rdev->mc.vram_start));
1147 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1148 (u32)rdev->mc.vram_start);
1149 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1150 (u32)rdev->mc.vram_start);
1151
1152 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1153 upper_32_bits(rdev->mc.vram_start));
1154 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1155 upper_32_bits(rdev->mc.vram_start));
1156 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1157 (u32)rdev->mc.vram_start);
1158 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1159 (u32)rdev->mc.vram_start);
1160 }
1161 if (rdev->num_crtc >= 6) {
1162 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1163 upper_32_bits(rdev->mc.vram_start));
1164 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1165 upper_32_bits(rdev->mc.vram_start));
1166 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1167 (u32)rdev->mc.vram_start);
1168 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1169 (u32)rdev->mc.vram_start);
1170
1171 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1172 upper_32_bits(rdev->mc.vram_start));
1173 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1174 upper_32_bits(rdev->mc.vram_start));
1175 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1176 (u32)rdev->mc.vram_start);
1177 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1178 (u32)rdev->mc.vram_start);
1179 }
1180
1181 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1182 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1183 /* Unlock host access */
1184 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1185 mdelay(1);
1186 /* Restore video state */
1187 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1188 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1189 if (rdev->num_crtc >= 4) {
1190 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1191 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1192 }
1193 if (rdev->num_crtc >= 6) {
1194 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1195 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1196 }
1197 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1198 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1199 if (rdev->num_crtc >= 4) {
1200 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1201 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1202 }
1203 if (rdev->num_crtc >= 6) {
1204 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1205 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1206 }
1207 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1208 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1209 if (rdev->num_crtc >= 4) {
1210 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1211 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1212 }
1213 if (rdev->num_crtc >= 6) {
1214 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1215 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1216 }
1217 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1218 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1219 if (rdev->num_crtc >= 4) {
1220 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1221 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1222 }
1223 if (rdev->num_crtc >= 6) {
1224 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1225 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1226 }
1227 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1228 }
1229
1230 void evergreen_mc_program(struct radeon_device *rdev)
1231 {
1232 struct evergreen_mc_save save;
1233 u32 tmp;
1234 int i, j;
1235
1236 /* Initialize HDP */
1237 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1238 WREG32((0x2c14 + j), 0x00000000);
1239 WREG32((0x2c18 + j), 0x00000000);
1240 WREG32((0x2c1c + j), 0x00000000);
1241 WREG32((0x2c20 + j), 0x00000000);
1242 WREG32((0x2c24 + j), 0x00000000);
1243 }
1244 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1245
1246 evergreen_mc_stop(rdev, &save);
1247 if (evergreen_mc_wait_for_idle(rdev)) {
1248 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1249 }
1250 /* Lockout access through VGA aperture*/
1251 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1252 /* Update configuration */
1253 if (rdev->flags & RADEON_IS_AGP) {
1254 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1255 /* VRAM before AGP */
1256 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1257 rdev->mc.vram_start >> 12);
1258 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1259 rdev->mc.gtt_end >> 12);
1260 } else {
1261 /* VRAM after AGP */
1262 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1263 rdev->mc.gtt_start >> 12);
1264 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1265 rdev->mc.vram_end >> 12);
1266 }
1267 } else {
1268 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1269 rdev->mc.vram_start >> 12);
1270 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1271 rdev->mc.vram_end >> 12);
1272 }
1273 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1274 if (rdev->flags & RADEON_IS_IGP) {
1275 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1276 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1277 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1278 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1279 }
1280 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1281 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1282 WREG32(MC_VM_FB_LOCATION, tmp);
1283 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1284 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1285 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1286 if (rdev->flags & RADEON_IS_AGP) {
1287 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1288 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1289 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1290 } else {
1291 WREG32(MC_VM_AGP_BASE, 0);
1292 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1293 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1294 }
1295 if (evergreen_mc_wait_for_idle(rdev)) {
1296 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1297 }
1298 evergreen_mc_resume(rdev, &save);
1299 /* we need to own VRAM, so turn off the VGA renderer here
1300 * to stop it overwriting our objects */
1301 rv515_vga_render_disable(rdev);
1302 }
1303
1304 /*
1305 * CP.
1306 */
1307 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1308 {
1309 /* set to DX10/11 mode */
1310 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1311 radeon_ring_write(rdev, 1);
1312 /* FIXME: implement */
1313 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1314 radeon_ring_write(rdev,
1315 #ifdef __BIG_ENDIAN
1316 (2 << 0) |
1317 #endif
1318 (ib->gpu_addr & 0xFFFFFFFC));
1319 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1320 radeon_ring_write(rdev, ib->length_dw);
1321 }
1322
1323
1324 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1325 {
1326 const __be32 *fw_data;
1327 int i;
1328
1329 if (!rdev->me_fw || !rdev->pfp_fw)
1330 return -EINVAL;
1331
1332 r700_cp_stop(rdev);
1333 WREG32(CP_RB_CNTL,
1334 #ifdef __BIG_ENDIAN
1335 BUF_SWAP_32BIT |
1336 #endif
1337 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1338
1339 fw_data = (const __be32 *)rdev->pfp_fw->data;
1340 WREG32(CP_PFP_UCODE_ADDR, 0);
1341 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1342 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1343 WREG32(CP_PFP_UCODE_ADDR, 0);
1344
1345 fw_data = (const __be32 *)rdev->me_fw->data;
1346 WREG32(CP_ME_RAM_WADDR, 0);
1347 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1348 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1349
1350 WREG32(CP_PFP_UCODE_ADDR, 0);
1351 WREG32(CP_ME_RAM_WADDR, 0);
1352 WREG32(CP_ME_RAM_RADDR, 0);
1353 return 0;
1354 }
1355
1356 static int evergreen_cp_start(struct radeon_device *rdev)
1357 {
1358 int r, i;
1359 uint32_t cp_me;
1360
1361 r = radeon_ring_lock(rdev, 7);
1362 if (r) {
1363 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1364 return r;
1365 }
1366 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1367 radeon_ring_write(rdev, 0x1);
1368 radeon_ring_write(rdev, 0x0);
1369 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1370 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1371 radeon_ring_write(rdev, 0);
1372 radeon_ring_write(rdev, 0);
1373 radeon_ring_unlock_commit(rdev);
1374
1375 cp_me = 0xff;
1376 WREG32(CP_ME_CNTL, cp_me);
1377
1378 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1379 if (r) {
1380 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1381 return r;
1382 }
1383
1384 /* setup clear context state */
1385 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1386 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1387
1388 for (i = 0; i < evergreen_default_size; i++)
1389 radeon_ring_write(rdev, evergreen_default_state[i]);
1390
1391 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1392 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1393
1394 /* set clear context state */
1395 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1396 radeon_ring_write(rdev, 0);
1397
1398 /* SQ_VTX_BASE_VTX_LOC */
1399 radeon_ring_write(rdev, 0xc0026f00);
1400 radeon_ring_write(rdev, 0x00000000);
1401 radeon_ring_write(rdev, 0x00000000);
1402 radeon_ring_write(rdev, 0x00000000);
1403
1404 /* Clear consts */
1405 radeon_ring_write(rdev, 0xc0036f00);
1406 radeon_ring_write(rdev, 0x00000bc4);
1407 radeon_ring_write(rdev, 0xffffffff);
1408 radeon_ring_write(rdev, 0xffffffff);
1409 radeon_ring_write(rdev, 0xffffffff);
1410
1411 radeon_ring_write(rdev, 0xc0026900);
1412 radeon_ring_write(rdev, 0x00000316);
1413 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1414 radeon_ring_write(rdev, 0x00000010); /* */
1415
1416 radeon_ring_unlock_commit(rdev);
1417
1418 return 0;
1419 }
1420
1421 int evergreen_cp_resume(struct radeon_device *rdev)
1422 {
1423 u32 tmp;
1424 u32 rb_bufsz;
1425 int r;
1426
1427 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1428 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1429 SOFT_RESET_PA |
1430 SOFT_RESET_SH |
1431 SOFT_RESET_VGT |
1432 SOFT_RESET_SPI |
1433 SOFT_RESET_SX));
1434 RREG32(GRBM_SOFT_RESET);
1435 mdelay(15);
1436 WREG32(GRBM_SOFT_RESET, 0);
1437 RREG32(GRBM_SOFT_RESET);
1438
1439 /* Set ring buffer size */
1440 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1441 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1442 #ifdef __BIG_ENDIAN
1443 tmp |= BUF_SWAP_32BIT;
1444 #endif
1445 WREG32(CP_RB_CNTL, tmp);
1446 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1447
1448 /* Set the write pointer delay */
1449 WREG32(CP_RB_WPTR_DELAY, 0);
1450
1451 /* Initialize the ring buffer's read and write pointers */
1452 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1453 WREG32(CP_RB_RPTR_WR, 0);
1454 rdev->cp.wptr = 0;
1455 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1456
1457 /* set the wb address wether it's enabled or not */
1458 WREG32(CP_RB_RPTR_ADDR,
1459 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1460 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1461 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1462
1463 if (rdev->wb.enabled)
1464 WREG32(SCRATCH_UMSK, 0xff);
1465 else {
1466 tmp |= RB_NO_UPDATE;
1467 WREG32(SCRATCH_UMSK, 0);
1468 }
1469
1470 mdelay(1);
1471 WREG32(CP_RB_CNTL, tmp);
1472
1473 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1474 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1475
1476 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1477
1478 evergreen_cp_start(rdev);
1479 rdev->cp.ready = true;
1480 r = radeon_ring_test(rdev);
1481 if (r) {
1482 rdev->cp.ready = false;
1483 return r;
1484 }
1485 return 0;
1486 }
1487
1488 /*
1489 * Core functions
1490 */
1491 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1492 u32 num_tile_pipes,
1493 u32 num_backends,
1494 u32 backend_disable_mask)
1495 {
1496 u32 backend_map = 0;
1497 u32 enabled_backends_mask = 0;
1498 u32 enabled_backends_count = 0;
1499 u32 cur_pipe;
1500 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1501 u32 cur_backend = 0;
1502 u32 i;
1503 bool force_no_swizzle;
1504
1505 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1506 num_tile_pipes = EVERGREEN_MAX_PIPES;
1507 if (num_tile_pipes < 1)
1508 num_tile_pipes = 1;
1509 if (num_backends > EVERGREEN_MAX_BACKENDS)
1510 num_backends = EVERGREEN_MAX_BACKENDS;
1511 if (num_backends < 1)
1512 num_backends = 1;
1513
1514 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1515 if (((backend_disable_mask >> i) & 1) == 0) {
1516 enabled_backends_mask |= (1 << i);
1517 ++enabled_backends_count;
1518 }
1519 if (enabled_backends_count == num_backends)
1520 break;
1521 }
1522
1523 if (enabled_backends_count == 0) {
1524 enabled_backends_mask = 1;
1525 enabled_backends_count = 1;
1526 }
1527
1528 if (enabled_backends_count != num_backends)
1529 num_backends = enabled_backends_count;
1530
1531 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1532 switch (rdev->family) {
1533 case CHIP_CEDAR:
1534 case CHIP_REDWOOD:
1535 case CHIP_PALM:
1536 case CHIP_SUMO:
1537 case CHIP_SUMO2:
1538 case CHIP_TURKS:
1539 case CHIP_CAICOS:
1540 force_no_swizzle = false;
1541 break;
1542 case CHIP_CYPRESS:
1543 case CHIP_HEMLOCK:
1544 case CHIP_JUNIPER:
1545 case CHIP_BARTS:
1546 default:
1547 force_no_swizzle = true;
1548 break;
1549 }
1550 if (force_no_swizzle) {
1551 bool last_backend_enabled = false;
1552
1553 force_no_swizzle = false;
1554 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1555 if (((enabled_backends_mask >> i) & 1) == 1) {
1556 if (last_backend_enabled)
1557 force_no_swizzle = true;
1558 last_backend_enabled = true;
1559 } else
1560 last_backend_enabled = false;
1561 }
1562 }
1563
1564 switch (num_tile_pipes) {
1565 case 1:
1566 case 3:
1567 case 5:
1568 case 7:
1569 DRM_ERROR("odd number of pipes!\n");
1570 break;
1571 case 2:
1572 swizzle_pipe[0] = 0;
1573 swizzle_pipe[1] = 1;
1574 break;
1575 case 4:
1576 if (force_no_swizzle) {
1577 swizzle_pipe[0] = 0;
1578 swizzle_pipe[1] = 1;
1579 swizzle_pipe[2] = 2;
1580 swizzle_pipe[3] = 3;
1581 } else {
1582 swizzle_pipe[0] = 0;
1583 swizzle_pipe[1] = 2;
1584 swizzle_pipe[2] = 1;
1585 swizzle_pipe[3] = 3;
1586 }
1587 break;
1588 case 6:
1589 if (force_no_swizzle) {
1590 swizzle_pipe[0] = 0;
1591 swizzle_pipe[1] = 1;
1592 swizzle_pipe[2] = 2;
1593 swizzle_pipe[3] = 3;
1594 swizzle_pipe[4] = 4;
1595 swizzle_pipe[5] = 5;
1596 } else {
1597 swizzle_pipe[0] = 0;
1598 swizzle_pipe[1] = 2;
1599 swizzle_pipe[2] = 4;
1600 swizzle_pipe[3] = 1;
1601 swizzle_pipe[4] = 3;
1602 swizzle_pipe[5] = 5;
1603 }
1604 break;
1605 case 8:
1606 if (force_no_swizzle) {
1607 swizzle_pipe[0] = 0;
1608 swizzle_pipe[1] = 1;
1609 swizzle_pipe[2] = 2;
1610 swizzle_pipe[3] = 3;
1611 swizzle_pipe[4] = 4;
1612 swizzle_pipe[5] = 5;
1613 swizzle_pipe[6] = 6;
1614 swizzle_pipe[7] = 7;
1615 } else {
1616 swizzle_pipe[0] = 0;
1617 swizzle_pipe[1] = 2;
1618 swizzle_pipe[2] = 4;
1619 swizzle_pipe[3] = 6;
1620 swizzle_pipe[4] = 1;
1621 swizzle_pipe[5] = 3;
1622 swizzle_pipe[6] = 5;
1623 swizzle_pipe[7] = 7;
1624 }
1625 break;
1626 }
1627
1628 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1629 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1630 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1631
1632 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1633
1634 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1635 }
1636
1637 return backend_map;
1638 }
1639
1640 static void evergreen_gpu_init(struct radeon_device *rdev)
1641 {
1642 u32 cc_rb_backend_disable = 0;
1643 u32 cc_gc_shader_pipe_config;
1644 u32 gb_addr_config = 0;
1645 u32 mc_shared_chmap, mc_arb_ramcfg;
1646 u32 gb_backend_map;
1647 u32 grbm_gfx_index;
1648 u32 sx_debug_1;
1649 u32 smx_dc_ctl0;
1650 u32 sq_config;
1651 u32 sq_lds_resource_mgmt;
1652 u32 sq_gpr_resource_mgmt_1;
1653 u32 sq_gpr_resource_mgmt_2;
1654 u32 sq_gpr_resource_mgmt_3;
1655 u32 sq_thread_resource_mgmt;
1656 u32 sq_thread_resource_mgmt_2;
1657 u32 sq_stack_resource_mgmt_1;
1658 u32 sq_stack_resource_mgmt_2;
1659 u32 sq_stack_resource_mgmt_3;
1660 u32 vgt_cache_invalidation;
1661 u32 hdp_host_path_cntl, tmp;
1662 int i, j, num_shader_engines, ps_thread_count;
1663
1664 switch (rdev->family) {
1665 case CHIP_CYPRESS:
1666 case CHIP_HEMLOCK:
1667 rdev->config.evergreen.num_ses = 2;
1668 rdev->config.evergreen.max_pipes = 4;
1669 rdev->config.evergreen.max_tile_pipes = 8;
1670 rdev->config.evergreen.max_simds = 10;
1671 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1672 rdev->config.evergreen.max_gprs = 256;
1673 rdev->config.evergreen.max_threads = 248;
1674 rdev->config.evergreen.max_gs_threads = 32;
1675 rdev->config.evergreen.max_stack_entries = 512;
1676 rdev->config.evergreen.sx_num_of_sets = 4;
1677 rdev->config.evergreen.sx_max_export_size = 256;
1678 rdev->config.evergreen.sx_max_export_pos_size = 64;
1679 rdev->config.evergreen.sx_max_export_smx_size = 192;
1680 rdev->config.evergreen.max_hw_contexts = 8;
1681 rdev->config.evergreen.sq_num_cf_insts = 2;
1682
1683 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1684 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1685 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1686 break;
1687 case CHIP_JUNIPER:
1688 rdev->config.evergreen.num_ses = 1;
1689 rdev->config.evergreen.max_pipes = 4;
1690 rdev->config.evergreen.max_tile_pipes = 4;
1691 rdev->config.evergreen.max_simds = 10;
1692 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1693 rdev->config.evergreen.max_gprs = 256;
1694 rdev->config.evergreen.max_threads = 248;
1695 rdev->config.evergreen.max_gs_threads = 32;
1696 rdev->config.evergreen.max_stack_entries = 512;
1697 rdev->config.evergreen.sx_num_of_sets = 4;
1698 rdev->config.evergreen.sx_max_export_size = 256;
1699 rdev->config.evergreen.sx_max_export_pos_size = 64;
1700 rdev->config.evergreen.sx_max_export_smx_size = 192;
1701 rdev->config.evergreen.max_hw_contexts = 8;
1702 rdev->config.evergreen.sq_num_cf_insts = 2;
1703
1704 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1705 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1706 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1707 break;
1708 case CHIP_REDWOOD:
1709 rdev->config.evergreen.num_ses = 1;
1710 rdev->config.evergreen.max_pipes = 4;
1711 rdev->config.evergreen.max_tile_pipes = 4;
1712 rdev->config.evergreen.max_simds = 5;
1713 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1714 rdev->config.evergreen.max_gprs = 256;
1715 rdev->config.evergreen.max_threads = 248;
1716 rdev->config.evergreen.max_gs_threads = 32;
1717 rdev->config.evergreen.max_stack_entries = 256;
1718 rdev->config.evergreen.sx_num_of_sets = 4;
1719 rdev->config.evergreen.sx_max_export_size = 256;
1720 rdev->config.evergreen.sx_max_export_pos_size = 64;
1721 rdev->config.evergreen.sx_max_export_smx_size = 192;
1722 rdev->config.evergreen.max_hw_contexts = 8;
1723 rdev->config.evergreen.sq_num_cf_insts = 2;
1724
1725 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1726 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1727 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1728 break;
1729 case CHIP_CEDAR:
1730 default:
1731 rdev->config.evergreen.num_ses = 1;
1732 rdev->config.evergreen.max_pipes = 2;
1733 rdev->config.evergreen.max_tile_pipes = 2;
1734 rdev->config.evergreen.max_simds = 2;
1735 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1736 rdev->config.evergreen.max_gprs = 256;
1737 rdev->config.evergreen.max_threads = 192;
1738 rdev->config.evergreen.max_gs_threads = 16;
1739 rdev->config.evergreen.max_stack_entries = 256;
1740 rdev->config.evergreen.sx_num_of_sets = 4;
1741 rdev->config.evergreen.sx_max_export_size = 128;
1742 rdev->config.evergreen.sx_max_export_pos_size = 32;
1743 rdev->config.evergreen.sx_max_export_smx_size = 96;
1744 rdev->config.evergreen.max_hw_contexts = 4;
1745 rdev->config.evergreen.sq_num_cf_insts = 1;
1746
1747 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1748 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1749 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1750 break;
1751 case CHIP_PALM:
1752 rdev->config.evergreen.num_ses = 1;
1753 rdev->config.evergreen.max_pipes = 2;
1754 rdev->config.evergreen.max_tile_pipes = 2;
1755 rdev->config.evergreen.max_simds = 2;
1756 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1757 rdev->config.evergreen.max_gprs = 256;
1758 rdev->config.evergreen.max_threads = 192;
1759 rdev->config.evergreen.max_gs_threads = 16;
1760 rdev->config.evergreen.max_stack_entries = 256;
1761 rdev->config.evergreen.sx_num_of_sets = 4;
1762 rdev->config.evergreen.sx_max_export_size = 128;
1763 rdev->config.evergreen.sx_max_export_pos_size = 32;
1764 rdev->config.evergreen.sx_max_export_smx_size = 96;
1765 rdev->config.evergreen.max_hw_contexts = 4;
1766 rdev->config.evergreen.sq_num_cf_insts = 1;
1767
1768 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1769 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1770 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1771 break;
1772 case CHIP_SUMO:
1773 rdev->config.evergreen.num_ses = 1;
1774 rdev->config.evergreen.max_pipes = 4;
1775 rdev->config.evergreen.max_tile_pipes = 2;
1776 if (rdev->pdev->device == 0x9648)
1777 rdev->config.evergreen.max_simds = 3;
1778 else if ((rdev->pdev->device == 0x9647) ||
1779 (rdev->pdev->device == 0x964a))
1780 rdev->config.evergreen.max_simds = 4;
1781 else
1782 rdev->config.evergreen.max_simds = 5;
1783 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1784 rdev->config.evergreen.max_gprs = 256;
1785 rdev->config.evergreen.max_threads = 248;
1786 rdev->config.evergreen.max_gs_threads = 32;
1787 rdev->config.evergreen.max_stack_entries = 256;
1788 rdev->config.evergreen.sx_num_of_sets = 4;
1789 rdev->config.evergreen.sx_max_export_size = 256;
1790 rdev->config.evergreen.sx_max_export_pos_size = 64;
1791 rdev->config.evergreen.sx_max_export_smx_size = 192;
1792 rdev->config.evergreen.max_hw_contexts = 8;
1793 rdev->config.evergreen.sq_num_cf_insts = 2;
1794
1795 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1796 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1797 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1798 break;
1799 case CHIP_SUMO2:
1800 rdev->config.evergreen.num_ses = 1;
1801 rdev->config.evergreen.max_pipes = 4;
1802 rdev->config.evergreen.max_tile_pipes = 4;
1803 rdev->config.evergreen.max_simds = 2;
1804 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1805 rdev->config.evergreen.max_gprs = 256;
1806 rdev->config.evergreen.max_threads = 248;
1807 rdev->config.evergreen.max_gs_threads = 32;
1808 rdev->config.evergreen.max_stack_entries = 512;
1809 rdev->config.evergreen.sx_num_of_sets = 4;
1810 rdev->config.evergreen.sx_max_export_size = 256;
1811 rdev->config.evergreen.sx_max_export_pos_size = 64;
1812 rdev->config.evergreen.sx_max_export_smx_size = 192;
1813 rdev->config.evergreen.max_hw_contexts = 8;
1814 rdev->config.evergreen.sq_num_cf_insts = 2;
1815
1816 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1817 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1818 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1819 break;
1820 case CHIP_BARTS:
1821 rdev->config.evergreen.num_ses = 2;
1822 rdev->config.evergreen.max_pipes = 4;
1823 rdev->config.evergreen.max_tile_pipes = 8;
1824 rdev->config.evergreen.max_simds = 7;
1825 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1826 rdev->config.evergreen.max_gprs = 256;
1827 rdev->config.evergreen.max_threads = 248;
1828 rdev->config.evergreen.max_gs_threads = 32;
1829 rdev->config.evergreen.max_stack_entries = 512;
1830 rdev->config.evergreen.sx_num_of_sets = 4;
1831 rdev->config.evergreen.sx_max_export_size = 256;
1832 rdev->config.evergreen.sx_max_export_pos_size = 64;
1833 rdev->config.evergreen.sx_max_export_smx_size = 192;
1834 rdev->config.evergreen.max_hw_contexts = 8;
1835 rdev->config.evergreen.sq_num_cf_insts = 2;
1836
1837 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1838 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1839 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1840 break;
1841 case CHIP_TURKS:
1842 rdev->config.evergreen.num_ses = 1;
1843 rdev->config.evergreen.max_pipes = 4;
1844 rdev->config.evergreen.max_tile_pipes = 4;
1845 rdev->config.evergreen.max_simds = 6;
1846 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1847 rdev->config.evergreen.max_gprs = 256;
1848 rdev->config.evergreen.max_threads = 248;
1849 rdev->config.evergreen.max_gs_threads = 32;
1850 rdev->config.evergreen.max_stack_entries = 256;
1851 rdev->config.evergreen.sx_num_of_sets = 4;
1852 rdev->config.evergreen.sx_max_export_size = 256;
1853 rdev->config.evergreen.sx_max_export_pos_size = 64;
1854 rdev->config.evergreen.sx_max_export_smx_size = 192;
1855 rdev->config.evergreen.max_hw_contexts = 8;
1856 rdev->config.evergreen.sq_num_cf_insts = 2;
1857
1858 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1859 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1860 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1861 break;
1862 case CHIP_CAICOS:
1863 rdev->config.evergreen.num_ses = 1;
1864 rdev->config.evergreen.max_pipes = 4;
1865 rdev->config.evergreen.max_tile_pipes = 2;
1866 rdev->config.evergreen.max_simds = 2;
1867 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1868 rdev->config.evergreen.max_gprs = 256;
1869 rdev->config.evergreen.max_threads = 192;
1870 rdev->config.evergreen.max_gs_threads = 16;
1871 rdev->config.evergreen.max_stack_entries = 256;
1872 rdev->config.evergreen.sx_num_of_sets = 4;
1873 rdev->config.evergreen.sx_max_export_size = 128;
1874 rdev->config.evergreen.sx_max_export_pos_size = 32;
1875 rdev->config.evergreen.sx_max_export_smx_size = 96;
1876 rdev->config.evergreen.max_hw_contexts = 4;
1877 rdev->config.evergreen.sq_num_cf_insts = 1;
1878
1879 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1880 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1881 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1882 break;
1883 }
1884
1885 /* Initialize HDP */
1886 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1887 WREG32((0x2c14 + j), 0x00000000);
1888 WREG32((0x2c18 + j), 0x00000000);
1889 WREG32((0x2c1c + j), 0x00000000);
1890 WREG32((0x2c20 + j), 0x00000000);
1891 WREG32((0x2c24 + j), 0x00000000);
1892 }
1893
1894 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1895
1896 evergreen_fix_pci_max_read_req_size(rdev);
1897
1898 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1899
1900 cc_gc_shader_pipe_config |=
1901 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1902 & EVERGREEN_MAX_PIPES_MASK);
1903 cc_gc_shader_pipe_config |=
1904 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1905 & EVERGREEN_MAX_SIMDS_MASK);
1906
1907 cc_rb_backend_disable =
1908 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1909 & EVERGREEN_MAX_BACKENDS_MASK);
1910
1911
1912 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1913 if (rdev->flags & RADEON_IS_IGP)
1914 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1915 else
1916 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1917
1918 switch (rdev->config.evergreen.max_tile_pipes) {
1919 case 1:
1920 default:
1921 gb_addr_config |= NUM_PIPES(0);
1922 break;
1923 case 2:
1924 gb_addr_config |= NUM_PIPES(1);
1925 break;
1926 case 4:
1927 gb_addr_config |= NUM_PIPES(2);
1928 break;
1929 case 8:
1930 gb_addr_config |= NUM_PIPES(3);
1931 break;
1932 }
1933
1934 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1935 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1936 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1937 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1938 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1939 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1940
1941 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1942 gb_addr_config |= ROW_SIZE(2);
1943 else
1944 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1945
1946 if (rdev->ddev->pdev->device == 0x689e) {
1947 u32 efuse_straps_4;
1948 u32 efuse_straps_3;
1949 u8 efuse_box_bit_131_124;
1950
1951 WREG32(RCU_IND_INDEX, 0x204);
1952 efuse_straps_4 = RREG32(RCU_IND_DATA);
1953 WREG32(RCU_IND_INDEX, 0x203);
1954 efuse_straps_3 = RREG32(RCU_IND_DATA);
1955 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1956
1957 switch(efuse_box_bit_131_124) {
1958 case 0x00:
1959 gb_backend_map = 0x76543210;
1960 break;
1961 case 0x55:
1962 gb_backend_map = 0x77553311;
1963 break;
1964 case 0x56:
1965 gb_backend_map = 0x77553300;
1966 break;
1967 case 0x59:
1968 gb_backend_map = 0x77552211;
1969 break;
1970 case 0x66:
1971 gb_backend_map = 0x77443300;
1972 break;
1973 case 0x99:
1974 gb_backend_map = 0x66552211;
1975 break;
1976 case 0x5a:
1977 gb_backend_map = 0x77552200;
1978 break;
1979 case 0xaa:
1980 gb_backend_map = 0x66442200;
1981 break;
1982 case 0x95:
1983 gb_backend_map = 0x66553311;
1984 break;
1985 default:
1986 DRM_ERROR("bad backend map, using default\n");
1987 gb_backend_map =
1988 evergreen_get_tile_pipe_to_backend_map(rdev,
1989 rdev->config.evergreen.max_tile_pipes,
1990 rdev->config.evergreen.max_backends,
1991 ((EVERGREEN_MAX_BACKENDS_MASK <<
1992 rdev->config.evergreen.max_backends) &
1993 EVERGREEN_MAX_BACKENDS_MASK));
1994 break;
1995 }
1996 } else if (rdev->ddev->pdev->device == 0x68b9) {
1997 u32 efuse_straps_3;
1998 u8 efuse_box_bit_127_124;
1999
2000 WREG32(RCU_IND_INDEX, 0x203);
2001 efuse_straps_3 = RREG32(RCU_IND_DATA);
2002 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
2003
2004 switch(efuse_box_bit_127_124) {
2005 case 0x0:
2006 gb_backend_map = 0x00003210;
2007 break;
2008 case 0x5:
2009 case 0x6:
2010 case 0x9:
2011 case 0xa:
2012 gb_backend_map = 0x00003311;
2013 break;
2014 default:
2015 DRM_ERROR("bad backend map, using default\n");
2016 gb_backend_map =
2017 evergreen_get_tile_pipe_to_backend_map(rdev,
2018 rdev->config.evergreen.max_tile_pipes,
2019 rdev->config.evergreen.max_backends,
2020 ((EVERGREEN_MAX_BACKENDS_MASK <<
2021 rdev->config.evergreen.max_backends) &
2022 EVERGREEN_MAX_BACKENDS_MASK));
2023 break;
2024 }
2025 } else {
2026 switch (rdev->family) {
2027 case CHIP_CYPRESS:
2028 case CHIP_HEMLOCK:
2029 case CHIP_BARTS:
2030 gb_backend_map = 0x66442200;
2031 break;
2032 case CHIP_JUNIPER:
2033 gb_backend_map = 0x00002200;
2034 break;
2035 default:
2036 gb_backend_map =
2037 evergreen_get_tile_pipe_to_backend_map(rdev,
2038 rdev->config.evergreen.max_tile_pipes,
2039 rdev->config.evergreen.max_backends,
2040 ((EVERGREEN_MAX_BACKENDS_MASK <<
2041 rdev->config.evergreen.max_backends) &
2042 EVERGREEN_MAX_BACKENDS_MASK));
2043 }
2044 }
2045
2046 /* setup tiling info dword. gb_addr_config is not adequate since it does
2047 * not have bank info, so create a custom tiling dword.
2048 * bits 3:0 num_pipes
2049 * bits 7:4 num_banks
2050 * bits 11:8 group_size
2051 * bits 15:12 row_size
2052 */
2053 rdev->config.evergreen.tile_config = 0;
2054 switch (rdev->config.evergreen.max_tile_pipes) {
2055 case 1:
2056 default:
2057 rdev->config.evergreen.tile_config |= (0 << 0);
2058 break;
2059 case 2:
2060 rdev->config.evergreen.tile_config |= (1 << 0);
2061 break;
2062 case 4:
2063 rdev->config.evergreen.tile_config |= (2 << 0);
2064 break;
2065 case 8:
2066 rdev->config.evergreen.tile_config |= (3 << 0);
2067 break;
2068 }
2069 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2070 if (rdev->flags & RADEON_IS_IGP)
2071 rdev->config.evergreen.tile_config |= 1 << 4;
2072 else
2073 rdev->config.evergreen.tile_config |=
2074 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2075 rdev->config.evergreen.tile_config |=
2076 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2077 rdev->config.evergreen.tile_config |=
2078 ((gb_addr_config & 0x30000000) >> 28) << 12;
2079
2080 rdev->config.evergreen.backend_map = gb_backend_map;
2081 WREG32(GB_BACKEND_MAP, gb_backend_map);
2082 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2083 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2084 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2085
2086 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2087 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2088
2089 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2090 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2091 u32 sp = cc_gc_shader_pipe_config;
2092 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2093
2094 if (i == num_shader_engines) {
2095 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2096 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2097 }
2098
2099 WREG32(GRBM_GFX_INDEX, gfx);
2100 WREG32(RLC_GFX_INDEX, gfx);
2101
2102 WREG32(CC_RB_BACKEND_DISABLE, rb);
2103 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2104 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2105 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2106 }
2107
2108 grbm_gfx_index |= SE_BROADCAST_WRITES;
2109 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2110 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2111
2112 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2113 WREG32(CGTS_TCC_DISABLE, 0);
2114 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2115 WREG32(CGTS_USER_TCC_DISABLE, 0);
2116
2117 /* set HW defaults for 3D engine */
2118 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2119 ROQ_IB2_START(0x2b)));
2120
2121 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2122
2123 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2124 SYNC_GRADIENT |
2125 SYNC_WALKER |
2126 SYNC_ALIGNER));
2127
2128 sx_debug_1 = RREG32(SX_DEBUG_1);
2129 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2130 WREG32(SX_DEBUG_1, sx_debug_1);
2131
2132
2133 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2134 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2135 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2136 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2137
2138 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2139 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2140 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2141
2142 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2143 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2144 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2145
2146 WREG32(VGT_NUM_INSTANCES, 1);
2147 WREG32(SPI_CONFIG_CNTL, 0);
2148 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2149 WREG32(CP_PERFMON_CNTL, 0);
2150
2151 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2152 FETCH_FIFO_HIWATER(0x4) |
2153 DONE_FIFO_HIWATER(0xe0) |
2154 ALU_UPDATE_FIFO_HIWATER(0x8)));
2155
2156 sq_config = RREG32(SQ_CONFIG);
2157 sq_config &= ~(PS_PRIO(3) |
2158 VS_PRIO(3) |
2159 GS_PRIO(3) |
2160 ES_PRIO(3));
2161 sq_config |= (VC_ENABLE |
2162 EXPORT_SRC_C |
2163 PS_PRIO(0) |
2164 VS_PRIO(1) |
2165 GS_PRIO(2) |
2166 ES_PRIO(3));
2167
2168 switch (rdev->family) {
2169 case CHIP_CEDAR:
2170 case CHIP_PALM:
2171 case CHIP_SUMO:
2172 case CHIP_SUMO2:
2173 case CHIP_CAICOS:
2174 /* no vertex cache */
2175 sq_config &= ~VC_ENABLE;
2176 break;
2177 default:
2178 break;
2179 }
2180
2181 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2182
2183 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2184 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2185 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2186 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2187 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2188 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2189 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2190
2191 switch (rdev->family) {
2192 case CHIP_CEDAR:
2193 case CHIP_PALM:
2194 case CHIP_SUMO:
2195 case CHIP_SUMO2:
2196 ps_thread_count = 96;
2197 break;
2198 default:
2199 ps_thread_count = 128;
2200 break;
2201 }
2202
2203 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2204 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2205 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2206 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2207 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2208 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2209
2210 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2211 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2212 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2213 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2214 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2215 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2216
2217 WREG32(SQ_CONFIG, sq_config);
2218 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2219 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2220 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2221 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2222 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2223 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2224 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2225 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2226 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2227 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2228
2229 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2230 FORCE_EOV_MAX_REZ_CNT(255)));
2231
2232 switch (rdev->family) {
2233 case CHIP_CEDAR:
2234 case CHIP_PALM:
2235 case CHIP_SUMO:
2236 case CHIP_SUMO2:
2237 case CHIP_CAICOS:
2238 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2239 break;
2240 default:
2241 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2242 break;
2243 }
2244 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2245 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2246
2247 WREG32(VGT_GS_VERTEX_REUSE, 16);
2248 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2249 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2250
2251 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2252 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2253
2254 WREG32(CB_PERF_CTR0_SEL_0, 0);
2255 WREG32(CB_PERF_CTR0_SEL_1, 0);
2256 WREG32(CB_PERF_CTR1_SEL_0, 0);
2257 WREG32(CB_PERF_CTR1_SEL_1, 0);
2258 WREG32(CB_PERF_CTR2_SEL_0, 0);
2259 WREG32(CB_PERF_CTR2_SEL_1, 0);
2260 WREG32(CB_PERF_CTR3_SEL_0, 0);
2261 WREG32(CB_PERF_CTR3_SEL_1, 0);
2262
2263 /* clear render buffer base addresses */
2264 WREG32(CB_COLOR0_BASE, 0);
2265 WREG32(CB_COLOR1_BASE, 0);
2266 WREG32(CB_COLOR2_BASE, 0);
2267 WREG32(CB_COLOR3_BASE, 0);
2268 WREG32(CB_COLOR4_BASE, 0);
2269 WREG32(CB_COLOR5_BASE, 0);
2270 WREG32(CB_COLOR6_BASE, 0);
2271 WREG32(CB_COLOR7_BASE, 0);
2272 WREG32(CB_COLOR8_BASE, 0);
2273 WREG32(CB_COLOR9_BASE, 0);
2274 WREG32(CB_COLOR10_BASE, 0);
2275 WREG32(CB_COLOR11_BASE, 0);
2276
2277 /* set the shader const cache sizes to 0 */
2278 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2279 WREG32(i, 0);
2280 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2281 WREG32(i, 0);
2282
2283 tmp = RREG32(HDP_MISC_CNTL);
2284 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2285 WREG32(HDP_MISC_CNTL, tmp);
2286
2287 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2288 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2289
2290 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2291
2292 udelay(50);
2293
2294 }
2295
2296 int evergreen_mc_init(struct radeon_device *rdev)
2297 {
2298 u32 tmp;
2299 int chansize, numchan;
2300
2301 /* Get VRAM informations */
2302 rdev->mc.vram_is_ddr = true;
2303 if (rdev->flags & RADEON_IS_IGP)
2304 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2305 else
2306 tmp = RREG32(MC_ARB_RAMCFG);
2307 if (tmp & CHANSIZE_OVERRIDE) {
2308 chansize = 16;
2309 } else if (tmp & CHANSIZE_MASK) {
2310 chansize = 64;
2311 } else {
2312 chansize = 32;
2313 }
2314 tmp = RREG32(MC_SHARED_CHMAP);
2315 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2316 case 0:
2317 default:
2318 numchan = 1;
2319 break;
2320 case 1:
2321 numchan = 2;
2322 break;
2323 case 2:
2324 numchan = 4;
2325 break;
2326 case 3:
2327 numchan = 8;
2328 break;
2329 }
2330 rdev->mc.vram_width = numchan * chansize;
2331 /* Could aper size report 0 ? */
2332 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2333 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2334 /* Setup GPU memory space */
2335 if (rdev->flags & RADEON_IS_IGP) {
2336 /* size in bytes on fusion */
2337 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2338 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2339 } else {
2340 /* size in MB on evergreen */
2341 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2342 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2343 }
2344 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2345 r700_vram_gtt_location(rdev, &rdev->mc);
2346 radeon_update_bandwidth_info(rdev);
2347
2348 return 0;
2349 }
2350
2351 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2352 {
2353 u32 srbm_status;
2354 u32 grbm_status;
2355 u32 grbm_status_se0, grbm_status_se1;
2356 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2357 int r;
2358
2359 srbm_status = RREG32(SRBM_STATUS);
2360 grbm_status = RREG32(GRBM_STATUS);
2361 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2362 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2363 if (!(grbm_status & GUI_ACTIVE)) {
2364 r100_gpu_lockup_update(lockup, &rdev->cp);
2365 return false;
2366 }
2367 /* force CP activities */
2368 r = radeon_ring_lock(rdev, 2);
2369 if (!r) {
2370 /* PACKET2 NOP */
2371 radeon_ring_write(rdev, 0x80000000);
2372 radeon_ring_write(rdev, 0x80000000);
2373 radeon_ring_unlock_commit(rdev);
2374 }
2375 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2376 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2377 }
2378
2379 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2380 {
2381 struct evergreen_mc_save save;
2382 u32 grbm_reset = 0;
2383
2384 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2385 return 0;
2386
2387 dev_info(rdev->dev, "GPU softreset \n");
2388 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2389 RREG32(GRBM_STATUS));
2390 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2391 RREG32(GRBM_STATUS_SE0));
2392 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2393 RREG32(GRBM_STATUS_SE1));
2394 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2395 RREG32(SRBM_STATUS));
2396 evergreen_mc_stop(rdev, &save);
2397 if (evergreen_mc_wait_for_idle(rdev)) {
2398 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2399 }
2400 /* Disable CP parsing/prefetching */
2401 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2402
2403 /* reset all the gfx blocks */
2404 grbm_reset = (SOFT_RESET_CP |
2405 SOFT_RESET_CB |
2406 SOFT_RESET_DB |
2407 SOFT_RESET_PA |
2408 SOFT_RESET_SC |
2409 SOFT_RESET_SPI |
2410 SOFT_RESET_SH |
2411 SOFT_RESET_SX |
2412 SOFT_RESET_TC |
2413 SOFT_RESET_TA |
2414 SOFT_RESET_VC |
2415 SOFT_RESET_VGT);
2416
2417 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2418 WREG32(GRBM_SOFT_RESET, grbm_reset);
2419 (void)RREG32(GRBM_SOFT_RESET);
2420 udelay(50);
2421 WREG32(GRBM_SOFT_RESET, 0);
2422 (void)RREG32(GRBM_SOFT_RESET);
2423 /* Wait a little for things to settle down */
2424 udelay(50);
2425 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2426 RREG32(GRBM_STATUS));
2427 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2428 RREG32(GRBM_STATUS_SE0));
2429 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2430 RREG32(GRBM_STATUS_SE1));
2431 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2432 RREG32(SRBM_STATUS));
2433 evergreen_mc_resume(rdev, &save);
2434 return 0;
2435 }
2436
2437 int evergreen_asic_reset(struct radeon_device *rdev)
2438 {
2439 return evergreen_gpu_soft_reset(rdev);
2440 }
2441
2442 /* Interrupts */
2443
2444 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2445 {
2446 switch (crtc) {
2447 case 0:
2448 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2449 case 1:
2450 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2451 case 2:
2452 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2453 case 3:
2454 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2455 case 4:
2456 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2457 case 5:
2458 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2459 default:
2460 return 0;
2461 }
2462 }
2463
2464 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2465 {
2466 u32 tmp;
2467
2468 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2469 WREG32(GRBM_INT_CNTL, 0);
2470 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2471 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2472 if (rdev->num_crtc >= 4) {
2473 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2474 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2475 }
2476 if (rdev->num_crtc >= 6) {
2477 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2478 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2479 }
2480
2481 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2482 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2483 if (rdev->num_crtc >= 4) {
2484 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2485 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2486 }
2487 if (rdev->num_crtc >= 6) {
2488 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2489 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2490 }
2491
2492 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2493 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2494
2495 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2496 WREG32(DC_HPD1_INT_CONTROL, tmp);
2497 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2498 WREG32(DC_HPD2_INT_CONTROL, tmp);
2499 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2500 WREG32(DC_HPD3_INT_CONTROL, tmp);
2501 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2502 WREG32(DC_HPD4_INT_CONTROL, tmp);
2503 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2504 WREG32(DC_HPD5_INT_CONTROL, tmp);
2505 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2506 WREG32(DC_HPD6_INT_CONTROL, tmp);
2507
2508 }
2509
2510 int evergreen_irq_set(struct radeon_device *rdev)
2511 {
2512 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2513 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2514 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2515 u32 grbm_int_cntl = 0;
2516 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2517
2518 if (!rdev->irq.installed) {
2519 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2520 return -EINVAL;
2521 }
2522 /* don't enable anything if the ih is disabled */
2523 if (!rdev->ih.enabled) {
2524 r600_disable_interrupts(rdev);
2525 /* force the active interrupt state to all disabled */
2526 evergreen_disable_interrupt_state(rdev);
2527 return 0;
2528 }
2529
2530 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2531 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2532 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2533 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2534 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2535 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2536
2537 if (rdev->irq.sw_int) {
2538 DRM_DEBUG("evergreen_irq_set: sw int\n");
2539 cp_int_cntl |= RB_INT_ENABLE;
2540 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2541 }
2542 if (rdev->irq.crtc_vblank_int[0] ||
2543 rdev->irq.pflip[0]) {
2544 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2545 crtc1 |= VBLANK_INT_MASK;
2546 }
2547 if (rdev->irq.crtc_vblank_int[1] ||
2548 rdev->irq.pflip[1]) {
2549 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2550 crtc2 |= VBLANK_INT_MASK;
2551 }
2552 if (rdev->irq.crtc_vblank_int[2] ||
2553 rdev->irq.pflip[2]) {
2554 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2555 crtc3 |= VBLANK_INT_MASK;
2556 }
2557 if (rdev->irq.crtc_vblank_int[3] ||
2558 rdev->irq.pflip[3]) {
2559 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2560 crtc4 |= VBLANK_INT_MASK;
2561 }
2562 if (rdev->irq.crtc_vblank_int[4] ||
2563 rdev->irq.pflip[4]) {
2564 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2565 crtc5 |= VBLANK_INT_MASK;
2566 }
2567 if (rdev->irq.crtc_vblank_int[5] ||
2568 rdev->irq.pflip[5]) {
2569 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2570 crtc6 |= VBLANK_INT_MASK;
2571 }
2572 if (rdev->irq.hpd[0]) {
2573 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2574 hpd1 |= DC_HPDx_INT_EN;
2575 }
2576 if (rdev->irq.hpd[1]) {
2577 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2578 hpd2 |= DC_HPDx_INT_EN;
2579 }
2580 if (rdev->irq.hpd[2]) {
2581 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2582 hpd3 |= DC_HPDx_INT_EN;
2583 }
2584 if (rdev->irq.hpd[3]) {
2585 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2586 hpd4 |= DC_HPDx_INT_EN;
2587 }
2588 if (rdev->irq.hpd[4]) {
2589 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2590 hpd5 |= DC_HPDx_INT_EN;
2591 }
2592 if (rdev->irq.hpd[5]) {
2593 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2594 hpd6 |= DC_HPDx_INT_EN;
2595 }
2596 if (rdev->irq.gui_idle) {
2597 DRM_DEBUG("gui idle\n");
2598 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2599 }
2600
2601 WREG32(CP_INT_CNTL, cp_int_cntl);
2602 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2603
2604 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2605 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2606 if (rdev->num_crtc >= 4) {
2607 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2608 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2609 }
2610 if (rdev->num_crtc >= 6) {
2611 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2612 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2613 }
2614
2615 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2616 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2617 if (rdev->num_crtc >= 4) {
2618 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2619 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2620 }
2621 if (rdev->num_crtc >= 6) {
2622 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2623 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2624 }
2625
2626 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2627 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2628 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2629 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2630 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2631 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2632
2633 return 0;
2634 }
2635
2636 static void evergreen_irq_ack(struct radeon_device *rdev)
2637 {
2638 u32 tmp;
2639
2640 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2641 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2642 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2643 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2644 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2645 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2646 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2647 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2648 if (rdev->num_crtc >= 4) {
2649 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2650 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2651 }
2652 if (rdev->num_crtc >= 6) {
2653 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2654 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2655 }
2656
2657 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2658 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2659 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2660 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2661 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2662 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2663 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2664 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2665 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2666 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2667 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2668 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2669
2670 if (rdev->num_crtc >= 4) {
2671 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2672 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2673 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2674 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2675 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2676 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2677 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2678 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2679 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2680 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2681 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2682 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2683 }
2684
2685 if (rdev->num_crtc >= 6) {
2686 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2687 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2688 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2689 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2690 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2691 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2692 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2693 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2694 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2695 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2696 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2697 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2698 }
2699
2700 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2701 tmp = RREG32(DC_HPD1_INT_CONTROL);
2702 tmp |= DC_HPDx_INT_ACK;
2703 WREG32(DC_HPD1_INT_CONTROL, tmp);
2704 }
2705 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2706 tmp = RREG32(DC_HPD2_INT_CONTROL);
2707 tmp |= DC_HPDx_INT_ACK;
2708 WREG32(DC_HPD2_INT_CONTROL, tmp);
2709 }
2710 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2711 tmp = RREG32(DC_HPD3_INT_CONTROL);
2712 tmp |= DC_HPDx_INT_ACK;
2713 WREG32(DC_HPD3_INT_CONTROL, tmp);
2714 }
2715 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2716 tmp = RREG32(DC_HPD4_INT_CONTROL);
2717 tmp |= DC_HPDx_INT_ACK;
2718 WREG32(DC_HPD4_INT_CONTROL, tmp);
2719 }
2720 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2721 tmp = RREG32(DC_HPD5_INT_CONTROL);
2722 tmp |= DC_HPDx_INT_ACK;
2723 WREG32(DC_HPD5_INT_CONTROL, tmp);
2724 }
2725 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2726 tmp = RREG32(DC_HPD5_INT_CONTROL);
2727 tmp |= DC_HPDx_INT_ACK;
2728 WREG32(DC_HPD6_INT_CONTROL, tmp);
2729 }
2730 }
2731
2732 void evergreen_irq_disable(struct radeon_device *rdev)
2733 {
2734 r600_disable_interrupts(rdev);
2735 /* Wait and acknowledge irq */
2736 mdelay(1);
2737 evergreen_irq_ack(rdev);
2738 evergreen_disable_interrupt_state(rdev);
2739 }
2740
2741 void evergreen_irq_suspend(struct radeon_device *rdev)
2742 {
2743 evergreen_irq_disable(rdev);
2744 r600_rlc_stop(rdev);
2745 }
2746
2747 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2748 {
2749 u32 wptr, tmp;
2750
2751 if (rdev->wb.enabled)
2752 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2753 else
2754 wptr = RREG32(IH_RB_WPTR);
2755
2756 if (wptr & RB_OVERFLOW) {
2757 /* When a ring buffer overflow happen start parsing interrupt
2758 * from the last not overwritten vector (wptr + 16). Hopefully
2759 * this should allow us to catchup.
2760 */
2761 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2762 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2763 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2764 tmp = RREG32(IH_RB_CNTL);
2765 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2766 WREG32(IH_RB_CNTL, tmp);
2767 }
2768 return (wptr & rdev->ih.ptr_mask);
2769 }
2770
2771 int evergreen_irq_process(struct radeon_device *rdev)
2772 {
2773 u32 wptr;
2774 u32 rptr;
2775 u32 src_id, src_data;
2776 u32 ring_index;
2777 unsigned long flags;
2778 bool queue_hotplug = false;
2779
2780 if (!rdev->ih.enabled || rdev->shutdown)
2781 return IRQ_NONE;
2782
2783 wptr = evergreen_get_ih_wptr(rdev);
2784 rptr = rdev->ih.rptr;
2785 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2786
2787 spin_lock_irqsave(&rdev->ih.lock, flags);
2788 if (rptr == wptr) {
2789 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2790 return IRQ_NONE;
2791 }
2792 restart_ih:
2793 /* Order reading of wptr vs. reading of IH ring data */
2794 rmb();
2795
2796 /* display interrupts */
2797 evergreen_irq_ack(rdev);
2798
2799 rdev->ih.wptr = wptr;
2800 while (rptr != wptr) {
2801 /* wptr/rptr are in bytes! */
2802 ring_index = rptr / 4;
2803 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2804 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2805
2806 switch (src_id) {
2807 case 1: /* D1 vblank/vline */
2808 switch (src_data) {
2809 case 0: /* D1 vblank */
2810 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2811 if (rdev->irq.crtc_vblank_int[0]) {
2812 drm_handle_vblank(rdev->ddev, 0);
2813 rdev->pm.vblank_sync = true;
2814 wake_up(&rdev->irq.vblank_queue);
2815 }
2816 if (rdev->irq.pflip[0])
2817 radeon_crtc_handle_flip(rdev, 0);
2818 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2819 DRM_DEBUG("IH: D1 vblank\n");
2820 }
2821 break;
2822 case 1: /* D1 vline */
2823 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2824 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2825 DRM_DEBUG("IH: D1 vline\n");
2826 }
2827 break;
2828 default:
2829 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2830 break;
2831 }
2832 break;
2833 case 2: /* D2 vblank/vline */
2834 switch (src_data) {
2835 case 0: /* D2 vblank */
2836 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2837 if (rdev->irq.crtc_vblank_int[1]) {
2838 drm_handle_vblank(rdev->ddev, 1);
2839 rdev->pm.vblank_sync = true;
2840 wake_up(&rdev->irq.vblank_queue);
2841 }
2842 if (rdev->irq.pflip[1])
2843 radeon_crtc_handle_flip(rdev, 1);
2844 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2845 DRM_DEBUG("IH: D2 vblank\n");
2846 }
2847 break;
2848 case 1: /* D2 vline */
2849 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2850 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2851 DRM_DEBUG("IH: D2 vline\n");
2852 }
2853 break;
2854 default:
2855 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2856 break;
2857 }
2858 break;
2859 case 3: /* D3 vblank/vline */
2860 switch (src_data) {
2861 case 0: /* D3 vblank */
2862 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2863 if (rdev->irq.crtc_vblank_int[2]) {
2864 drm_handle_vblank(rdev->ddev, 2);
2865 rdev->pm.vblank_sync = true;
2866 wake_up(&rdev->irq.vblank_queue);
2867 }
2868 if (rdev->irq.pflip[2])
2869 radeon_crtc_handle_flip(rdev, 2);
2870 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2871 DRM_DEBUG("IH: D3 vblank\n");
2872 }
2873 break;
2874 case 1: /* D3 vline */
2875 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2876 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2877 DRM_DEBUG("IH: D3 vline\n");
2878 }
2879 break;
2880 default:
2881 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2882 break;
2883 }
2884 break;
2885 case 4: /* D4 vblank/vline */
2886 switch (src_data) {
2887 case 0: /* D4 vblank */
2888 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2889 if (rdev->irq.crtc_vblank_int[3]) {
2890 drm_handle_vblank(rdev->ddev, 3);
2891 rdev->pm.vblank_sync = true;
2892 wake_up(&rdev->irq.vblank_queue);
2893 }
2894 if (rdev->irq.pflip[3])
2895 radeon_crtc_handle_flip(rdev, 3);
2896 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2897 DRM_DEBUG("IH: D4 vblank\n");
2898 }
2899 break;
2900 case 1: /* D4 vline */
2901 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2902 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2903 DRM_DEBUG("IH: D4 vline\n");
2904 }
2905 break;
2906 default:
2907 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2908 break;
2909 }
2910 break;
2911 case 5: /* D5 vblank/vline */
2912 switch (src_data) {
2913 case 0: /* D5 vblank */
2914 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2915 if (rdev->irq.crtc_vblank_int[4]) {
2916 drm_handle_vblank(rdev->ddev, 4);
2917 rdev->pm.vblank_sync = true;
2918 wake_up(&rdev->irq.vblank_queue);
2919 }
2920 if (rdev->irq.pflip[4])
2921 radeon_crtc_handle_flip(rdev, 4);
2922 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2923 DRM_DEBUG("IH: D5 vblank\n");
2924 }
2925 break;
2926 case 1: /* D5 vline */
2927 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2928 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2929 DRM_DEBUG("IH: D5 vline\n");
2930 }
2931 break;
2932 default:
2933 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2934 break;
2935 }
2936 break;
2937 case 6: /* D6 vblank/vline */
2938 switch (src_data) {
2939 case 0: /* D6 vblank */
2940 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2941 if (rdev->irq.crtc_vblank_int[5]) {
2942 drm_handle_vblank(rdev->ddev, 5);
2943 rdev->pm.vblank_sync = true;
2944 wake_up(&rdev->irq.vblank_queue);
2945 }
2946 if (rdev->irq.pflip[5])
2947 radeon_crtc_handle_flip(rdev, 5);
2948 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2949 DRM_DEBUG("IH: D6 vblank\n");
2950 }
2951 break;
2952 case 1: /* D6 vline */
2953 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2954 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2955 DRM_DEBUG("IH: D6 vline\n");
2956 }
2957 break;
2958 default:
2959 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2960 break;
2961 }
2962 break;
2963 case 42: /* HPD hotplug */
2964 switch (src_data) {
2965 case 0:
2966 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2967 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2968 queue_hotplug = true;
2969 DRM_DEBUG("IH: HPD1\n");
2970 }
2971 break;
2972 case 1:
2973 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2974 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2975 queue_hotplug = true;
2976 DRM_DEBUG("IH: HPD2\n");
2977 }
2978 break;
2979 case 2:
2980 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2981 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2982 queue_hotplug = true;
2983 DRM_DEBUG("IH: HPD3\n");
2984 }
2985 break;
2986 case 3:
2987 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2988 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2989 queue_hotplug = true;
2990 DRM_DEBUG("IH: HPD4\n");
2991 }
2992 break;
2993 case 4:
2994 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2995 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2996 queue_hotplug = true;
2997 DRM_DEBUG("IH: HPD5\n");
2998 }
2999 break;
3000 case 5:
3001 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3002 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3003 queue_hotplug = true;
3004 DRM_DEBUG("IH: HPD6\n");
3005 }
3006 break;
3007 default:
3008 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3009 break;
3010 }
3011 break;
3012 case 176: /* CP_INT in ring buffer */
3013 case 177: /* CP_INT in IB1 */
3014 case 178: /* CP_INT in IB2 */
3015 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3016 radeon_fence_process(rdev);
3017 break;
3018 case 181: /* CP EOP event */
3019 DRM_DEBUG("IH: CP EOP\n");
3020 radeon_fence_process(rdev);
3021 break;
3022 case 233: /* GUI IDLE */
3023 DRM_DEBUG("IH: GUI idle\n");
3024 rdev->pm.gui_idle = true;
3025 wake_up(&rdev->irq.idle_queue);
3026 break;
3027 default:
3028 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3029 break;
3030 }
3031
3032 /* wptr/rptr are in bytes! */
3033 rptr += 16;
3034 rptr &= rdev->ih.ptr_mask;
3035 }
3036 /* make sure wptr hasn't changed while processing */
3037 wptr = evergreen_get_ih_wptr(rdev);
3038 if (wptr != rdev->ih.wptr)
3039 goto restart_ih;
3040 if (queue_hotplug)
3041 schedule_work(&rdev->hotplug_work);
3042 rdev->ih.rptr = rptr;
3043 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3044 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3045 return IRQ_HANDLED;
3046 }
3047
3048 static int evergreen_startup(struct radeon_device *rdev)
3049 {
3050 int r;
3051
3052 /* enable pcie gen2 link */
3053 evergreen_pcie_gen2_enable(rdev);
3054
3055 if (ASIC_IS_DCE5(rdev)) {
3056 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3057 r = ni_init_microcode(rdev);
3058 if (r) {
3059 DRM_ERROR("Failed to load firmware!\n");
3060 return r;
3061 }
3062 }
3063 r = ni_mc_load_microcode(rdev);
3064 if (r) {
3065 DRM_ERROR("Failed to load MC firmware!\n");
3066 return r;
3067 }
3068 } else {
3069 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3070 r = r600_init_microcode(rdev);
3071 if (r) {
3072 DRM_ERROR("Failed to load firmware!\n");
3073 return r;
3074 }
3075 }
3076 }
3077
3078 r = r600_vram_scratch_init(rdev);
3079 if (r)
3080 return r;
3081
3082 evergreen_mc_program(rdev);
3083 if (rdev->flags & RADEON_IS_AGP) {
3084 evergreen_agp_enable(rdev);
3085 } else {
3086 r = evergreen_pcie_gart_enable(rdev);
3087 if (r)
3088 return r;
3089 }
3090 evergreen_gpu_init(rdev);
3091
3092 r = evergreen_blit_init(rdev);
3093 if (r) {
3094 r600_blit_fini(rdev);
3095 rdev->asic->copy = NULL;
3096 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3097 }
3098
3099 /* allocate wb buffer */
3100 r = radeon_wb_init(rdev);
3101 if (r)
3102 return r;
3103
3104 /* Enable IRQ */
3105 r = r600_irq_init(rdev);
3106 if (r) {
3107 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3108 radeon_irq_kms_fini(rdev);
3109 return r;
3110 }
3111 evergreen_irq_set(rdev);
3112
3113 r = radeon_ring_init(rdev, rdev->cp.ring_size);
3114 if (r)
3115 return r;
3116 r = evergreen_cp_load_microcode(rdev);
3117 if (r)
3118 return r;
3119 r = evergreen_cp_resume(rdev);
3120 if (r)
3121 return r;
3122
3123 return 0;
3124 }
3125
3126 int evergreen_resume(struct radeon_device *rdev)
3127 {
3128 int r;
3129
3130 /* reset the asic, the gfx blocks are often in a bad state
3131 * after the driver is unloaded or after a resume
3132 */
3133 if (radeon_asic_reset(rdev))
3134 dev_warn(rdev->dev, "GPU reset failed !\n");
3135 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3136 * posting will perform necessary task to bring back GPU into good
3137 * shape.
3138 */
3139 /* post card */
3140 atom_asic_init(rdev->mode_info.atom_context);
3141
3142 r = evergreen_startup(rdev);
3143 if (r) {
3144 DRM_ERROR("evergreen startup failed on resume\n");
3145 return r;
3146 }
3147
3148 r = r600_ib_test(rdev);
3149 if (r) {
3150 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3151 return r;
3152 }
3153
3154 return r;
3155
3156 }
3157
3158 int evergreen_suspend(struct radeon_device *rdev)
3159 {
3160 /* FIXME: we should wait for ring to be empty */
3161 r700_cp_stop(rdev);
3162 rdev->cp.ready = false;
3163 evergreen_irq_suspend(rdev);
3164 radeon_wb_disable(rdev);
3165 evergreen_pcie_gart_disable(rdev);
3166 r600_blit_suspend(rdev);
3167
3168 return 0;
3169 }
3170
3171 /* Plan is to move initialization in that function and use
3172 * helper function so that radeon_device_init pretty much
3173 * do nothing more than calling asic specific function. This
3174 * should also allow to remove a bunch of callback function
3175 * like vram_info.
3176 */
3177 int evergreen_init(struct radeon_device *rdev)
3178 {
3179 int r;
3180
3181 /* This don't do much */
3182 r = radeon_gem_init(rdev);
3183 if (r)
3184 return r;
3185 /* Read BIOS */
3186 if (!radeon_get_bios(rdev)) {
3187 if (ASIC_IS_AVIVO(rdev))
3188 return -EINVAL;
3189 }
3190 /* Must be an ATOMBIOS */
3191 if (!rdev->is_atom_bios) {
3192 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3193 return -EINVAL;
3194 }
3195 r = radeon_atombios_init(rdev);
3196 if (r)
3197 return r;
3198 /* reset the asic, the gfx blocks are often in a bad state
3199 * after the driver is unloaded or after a resume
3200 */
3201 if (radeon_asic_reset(rdev))
3202 dev_warn(rdev->dev, "GPU reset failed !\n");
3203 /* Post card if necessary */
3204 if (!radeon_card_posted(rdev)) {
3205 if (!rdev->bios) {
3206 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3207 return -EINVAL;
3208 }
3209 DRM_INFO("GPU not posted. posting now...\n");
3210 atom_asic_init(rdev->mode_info.atom_context);
3211 }
3212 /* Initialize scratch registers */
3213 r600_scratch_init(rdev);
3214 /* Initialize surface registers */
3215 radeon_surface_init(rdev);
3216 /* Initialize clocks */
3217 radeon_get_clock_info(rdev->ddev);
3218 /* Fence driver */
3219 r = radeon_fence_driver_init(rdev);
3220 if (r)
3221 return r;
3222 /* initialize AGP */
3223 if (rdev->flags & RADEON_IS_AGP) {
3224 r = radeon_agp_init(rdev);
3225 if (r)
3226 radeon_agp_disable(rdev);
3227 }
3228 /* initialize memory controller */
3229 r = evergreen_mc_init(rdev);
3230 if (r)
3231 return r;
3232 /* Memory manager */
3233 r = radeon_bo_init(rdev);
3234 if (r)
3235 return r;
3236
3237 r = radeon_irq_kms_init(rdev);
3238 if (r)
3239 return r;
3240
3241 rdev->cp.ring_obj = NULL;
3242 r600_ring_init(rdev, 1024 * 1024);
3243
3244 rdev->ih.ring_obj = NULL;
3245 r600_ih_ring_init(rdev, 64 * 1024);
3246
3247 r = r600_pcie_gart_init(rdev);
3248 if (r)
3249 return r;
3250
3251 rdev->accel_working = true;
3252 r = evergreen_startup(rdev);
3253 if (r) {
3254 dev_err(rdev->dev, "disabling GPU acceleration\n");
3255 r700_cp_fini(rdev);
3256 r600_irq_fini(rdev);
3257 radeon_wb_fini(rdev);
3258 radeon_irq_kms_fini(rdev);
3259 evergreen_pcie_gart_fini(rdev);
3260 rdev->accel_working = false;
3261 }
3262 if (rdev->accel_working) {
3263 r = radeon_ib_pool_init(rdev);
3264 if (r) {
3265 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3266 rdev->accel_working = false;
3267 }
3268 r = r600_ib_test(rdev);
3269 if (r) {
3270 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3271 rdev->accel_working = false;
3272 }
3273 }
3274 return 0;
3275 }
3276
3277 void evergreen_fini(struct radeon_device *rdev)
3278 {
3279 r600_blit_fini(rdev);
3280 r700_cp_fini(rdev);
3281 r600_irq_fini(rdev);
3282 radeon_wb_fini(rdev);
3283 radeon_ib_pool_fini(rdev);
3284 radeon_irq_kms_fini(rdev);
3285 evergreen_pcie_gart_fini(rdev);
3286 r600_vram_scratch_fini(rdev);
3287 radeon_gem_fini(rdev);
3288 radeon_fence_driver_fini(rdev);
3289 radeon_agp_fini(rdev);
3290 radeon_bo_fini(rdev);
3291 radeon_atombios_fini(rdev);
3292 kfree(rdev->bios);
3293 rdev->bios = NULL;
3294 }
3295
3296 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3297 {
3298 u32 link_width_cntl, speed_cntl;
3299
3300 if (radeon_pcie_gen2 == 0)
3301 return;
3302
3303 if (rdev->flags & RADEON_IS_IGP)
3304 return;
3305
3306 if (!(rdev->flags & RADEON_IS_PCIE))
3307 return;
3308
3309 /* x2 cards have a special sequence */
3310 if (ASIC_IS_X2(rdev))
3311 return;
3312
3313 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3314 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3315 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3316
3317 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3318 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3319 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3320
3321 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3322 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3323 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3324
3325 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3326 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3327 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3328
3329 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3330 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3331 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3332
3333 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3334 speed_cntl |= LC_GEN2_EN_STRAP;
3335 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3336
3337 } else {
3338 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3339 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3340 if (1)
3341 link_width_cntl |= LC_UPCONFIGURE_DIS;
3342 else
3343 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3344 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3345 }
3346 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree