2 * Copyright (C) 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/mtd/partitions.h>
33 #include <linux/gpio.h>
36 #include <mach/board.h>
39 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
45 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
51 static int use_dma
= 1;
52 module_param(use_dma
, int, 0);
54 static int on_flash_bbt
= 0;
55 module_param(on_flash_bbt
, int, 0);
57 /* Register access macros */
58 #define ecc_readl(add, reg) \
59 __raw_readl(add + ATMEL_ECC_##reg)
60 #define ecc_writel(add, reg, value) \
61 __raw_writel((value), add + ATMEL_ECC_##reg)
63 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
65 /* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
70 static struct nand_ecclayout atmel_oobinfo_large
= {
72 .eccpos
= {60, 61, 62, 63},
78 /* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
83 static struct nand_ecclayout atmel_oobinfo_small
= {
85 .eccpos
= {0, 1, 2, 3},
91 struct atmel_nand_host
{
92 struct nand_chip nand_chip
;
94 void __iomem
*io_base
;
96 struct atmel_nand_data
*board
;
100 struct completion comp
;
101 struct dma_chan
*dma_chan
;
104 static int cpu_has_dma(void)
106 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
112 static void atmel_nand_enable(struct atmel_nand_host
*host
)
114 if (host
->board
->enable_pin
)
115 gpio_set_value(host
->board
->enable_pin
, 0);
121 static void atmel_nand_disable(struct atmel_nand_host
*host
)
123 if (host
->board
->enable_pin
)
124 gpio_set_value(host
->board
->enable_pin
, 1);
128 * Hardware specific access to control-lines
130 static void atmel_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
132 struct nand_chip
*nand_chip
= mtd
->priv
;
133 struct atmel_nand_host
*host
= nand_chip
->priv
;
135 if (ctrl
& NAND_CTRL_CHANGE
) {
137 atmel_nand_enable(host
);
139 atmel_nand_disable(host
);
141 if (cmd
== NAND_CMD_NONE
)
145 writeb(cmd
, host
->io_base
+ (1 << host
->board
->cle
));
147 writeb(cmd
, host
->io_base
+ (1 << host
->board
->ale
));
151 * Read the Device Ready pin.
153 static int atmel_nand_device_ready(struct mtd_info
*mtd
)
155 struct nand_chip
*nand_chip
= mtd
->priv
;
156 struct atmel_nand_host
*host
= nand_chip
->priv
;
158 return gpio_get_value(host
->board
->rdy_pin
) ^
159 !!host
->board
->rdy_pin_active_low
;
163 * Minimal-overhead PIO for data access.
165 static void atmel_read_buf8(struct mtd_info
*mtd
, u8
*buf
, int len
)
167 struct nand_chip
*nand_chip
= mtd
->priv
;
169 __raw_readsb(nand_chip
->IO_ADDR_R
, buf
, len
);
172 static void atmel_read_buf16(struct mtd_info
*mtd
, u8
*buf
, int len
)
174 struct nand_chip
*nand_chip
= mtd
->priv
;
176 __raw_readsw(nand_chip
->IO_ADDR_R
, buf
, len
/ 2);
179 static void atmel_write_buf8(struct mtd_info
*mtd
, const u8
*buf
, int len
)
181 struct nand_chip
*nand_chip
= mtd
->priv
;
183 __raw_writesb(nand_chip
->IO_ADDR_W
, buf
, len
);
186 static void atmel_write_buf16(struct mtd_info
*mtd
, const u8
*buf
, int len
)
188 struct nand_chip
*nand_chip
= mtd
->priv
;
190 __raw_writesw(nand_chip
->IO_ADDR_W
, buf
, len
/ 2);
193 static void dma_complete_func(void *completion
)
195 complete(completion
);
198 static int atmel_nand_dma_op(struct mtd_info
*mtd
, void *buf
, int len
,
201 struct dma_device
*dma_dev
;
202 enum dma_ctrl_flags flags
;
203 dma_addr_t dma_src_addr
, dma_dst_addr
, phys_addr
;
204 struct dma_async_tx_descriptor
*tx
= NULL
;
206 struct nand_chip
*chip
= mtd
->priv
;
207 struct atmel_nand_host
*host
= chip
->priv
;
210 enum dma_data_direction dir
= is_read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
212 if (buf
>= high_memory
) {
215 if (((size_t)buf
& PAGE_MASK
) !=
216 ((size_t)(buf
+ len
- 1) & PAGE_MASK
)) {
217 dev_warn(host
->dev
, "Buffer not fit in one page\n");
221 pg
= vmalloc_to_page(buf
);
223 dev_err(host
->dev
, "Failed to vmalloc_to_page\n");
226 p
= page_address(pg
) + ((size_t)buf
& ~PAGE_MASK
);
229 dma_dev
= host
->dma_chan
->device
;
231 flags
= DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
| DMA_COMPL_SKIP_SRC_UNMAP
|
232 DMA_COMPL_SKIP_DEST_UNMAP
;
234 phys_addr
= dma_map_single(dma_dev
->dev
, p
, len
, dir
);
235 if (dma_mapping_error(dma_dev
->dev
, phys_addr
)) {
236 dev_err(host
->dev
, "Failed to dma_map_single\n");
241 dma_src_addr
= host
->io_phys
;
242 dma_dst_addr
= phys_addr
;
244 dma_src_addr
= phys_addr
;
245 dma_dst_addr
= host
->io_phys
;
248 tx
= dma_dev
->device_prep_dma_memcpy(host
->dma_chan
, dma_dst_addr
,
249 dma_src_addr
, len
, flags
);
251 dev_err(host
->dev
, "Failed to prepare DMA memcpy\n");
255 init_completion(&host
->comp
);
256 tx
->callback
= dma_complete_func
;
257 tx
->callback_param
= &host
->comp
;
259 cookie
= tx
->tx_submit(tx
);
260 if (dma_submit_error(cookie
)) {
261 dev_err(host
->dev
, "Failed to do DMA tx_submit\n");
265 dma_async_issue_pending(host
->dma_chan
);
266 wait_for_completion(&host
->comp
);
271 dma_unmap_single(dma_dev
->dev
, phys_addr
, len
, dir
);
274 dev_warn(host
->dev
, "Fall back to CPU I/O\n");
278 static void atmel_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
280 struct nand_chip
*chip
= mtd
->priv
;
281 struct atmel_nand_host
*host
= chip
->priv
;
283 if (use_dma
&& len
> mtd
->oobsize
)
284 /* only use DMA for bigger than oob size: better performances */
285 if (atmel_nand_dma_op(mtd
, buf
, len
, 1) == 0)
288 if (host
->board
->bus_width_16
)
289 atmel_read_buf16(mtd
, buf
, len
);
291 atmel_read_buf8(mtd
, buf
, len
);
294 static void atmel_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
296 struct nand_chip
*chip
= mtd
->priv
;
297 struct atmel_nand_host
*host
= chip
->priv
;
299 if (use_dma
&& len
> mtd
->oobsize
)
300 /* only use DMA for bigger than oob size: better performances */
301 if (atmel_nand_dma_op(mtd
, (void *)buf
, len
, 0) == 0)
304 if (host
->board
->bus_width_16
)
305 atmel_write_buf16(mtd
, buf
, len
);
307 atmel_write_buf8(mtd
, buf
, len
);
313 * function called after a write
315 * mtd: MTD block structure
316 * dat: raw data (unused)
317 * ecc_code: buffer for ECC
319 static int atmel_nand_calculate(struct mtd_info
*mtd
,
320 const u_char
*dat
, unsigned char *ecc_code
)
322 struct nand_chip
*nand_chip
= mtd
->priv
;
323 struct atmel_nand_host
*host
= nand_chip
->priv
;
324 unsigned int ecc_value
;
326 /* get the first 2 ECC bytes */
327 ecc_value
= ecc_readl(host
->ecc
, PR
);
329 ecc_code
[0] = ecc_value
& 0xFF;
330 ecc_code
[1] = (ecc_value
>> 8) & 0xFF;
332 /* get the last 2 ECC bytes */
333 ecc_value
= ecc_readl(host
->ecc
, NPR
) & ATMEL_ECC_NPARITY
;
335 ecc_code
[2] = ecc_value
& 0xFF;
336 ecc_code
[3] = (ecc_value
>> 8) & 0xFF;
342 * HW ECC read page function
344 * mtd: mtd info structure
345 * chip: nand chip info structure
346 * buf: buffer to store read data
348 static int atmel_nand_read_page(struct mtd_info
*mtd
,
349 struct nand_chip
*chip
, uint8_t *buf
, int page
)
351 int eccsize
= chip
->ecc
.size
;
352 int eccbytes
= chip
->ecc
.bytes
;
353 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
355 uint8_t *oob
= chip
->oob_poi
;
360 * Errata: ALE is incorrectly wired up to the ECC controller
361 * on the AP7000, so it will include the address cycles in the
364 * Workaround: Reset the parity registers before reading the
367 if (cpu_is_at32ap7000()) {
368 struct atmel_nand_host
*host
= chip
->priv
;
369 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
373 chip
->read_buf(mtd
, p
, eccsize
);
375 /* move to ECC position if needed */
376 if (eccpos
[0] != 0) {
377 /* This only works on large pages
378 * because the ECC controller waits for
379 * NAND_CMD_RNDOUTSTART after the
381 * anyway, for small pages, the eccpos[0] == 0
383 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
384 mtd
->writesize
+ eccpos
[0], -1);
387 /* the ECC controller needs to read the ECC just after the data */
388 ecc_pos
= oob
+ eccpos
[0];
389 chip
->read_buf(mtd
, ecc_pos
, eccbytes
);
391 /* check if there's an error */
392 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
395 mtd
->ecc_stats
.failed
++;
397 mtd
->ecc_stats
.corrected
+= stat
;
399 /* get back to oob start (end of page) */
400 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
403 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
411 * function called after a read
413 * mtd: MTD block structure
414 * dat: raw data read from the chip
415 * read_ecc: ECC from the chip (unused)
418 * Detect and correct a 1 bit error for a page
420 static int atmel_nand_correct(struct mtd_info
*mtd
, u_char
*dat
,
421 u_char
*read_ecc
, u_char
*isnull
)
423 struct nand_chip
*nand_chip
= mtd
->priv
;
424 struct atmel_nand_host
*host
= nand_chip
->priv
;
425 unsigned int ecc_status
;
426 unsigned int ecc_word
, ecc_bit
;
428 /* get the status from the Status Register */
429 ecc_status
= ecc_readl(host
->ecc
, SR
);
431 /* if there's no error */
432 if (likely(!(ecc_status
& ATMEL_ECC_RECERR
)))
435 /* get error bit offset (4 bits) */
436 ecc_bit
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_BITADDR
;
437 /* get word address (12 bits) */
438 ecc_word
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_WORDADDR
;
441 /* if there are multiple errors */
442 if (ecc_status
& ATMEL_ECC_MULERR
) {
443 /* check if it is a freshly erased block
444 * (filled with 0xff) */
445 if ((ecc_bit
== ATMEL_ECC_BITADDR
)
446 && (ecc_word
== (ATMEL_ECC_WORDADDR
>> 4))) {
447 /* the block has just been erased, return OK */
450 /* it doesn't seems to be a freshly
452 * We can't correct so many errors */
453 dev_dbg(host
->dev
, "atmel_nand : multiple errors detected."
454 " Unable to correct.\n");
458 /* if there's a single bit error : we can correct it */
459 if (ecc_status
& ATMEL_ECC_ECCERR
) {
460 /* there's nothing much to do here.
461 * the bit error is on the ECC itself.
463 dev_dbg(host
->dev
, "atmel_nand : one bit error on ECC code."
464 " Nothing to correct\n");
468 dev_dbg(host
->dev
, "atmel_nand : one bit error on data."
469 " (word offset in the page :"
470 " 0x%x bit offset : 0x%x)\n",
472 /* correct the error */
473 if (nand_chip
->options
& NAND_BUSWIDTH_16
) {
475 ((unsigned short *) dat
)[ecc_word
] ^= (1 << ecc_bit
);
478 dat
[ecc_word
] ^= (1 << ecc_bit
);
480 dev_dbg(host
->dev
, "atmel_nand : error corrected\n");
485 * Enable HW ECC : unused on most chips
487 static void atmel_nand_hwctl(struct mtd_info
*mtd
, int mode
)
489 if (cpu_is_at32ap7000()) {
490 struct nand_chip
*nand_chip
= mtd
->priv
;
491 struct atmel_nand_host
*host
= nand_chip
->priv
;
492 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
496 #ifdef CONFIG_MTD_CMDLINE_PARTS
497 static const char *part_probes
[] = { "cmdlinepart", NULL
};
501 * Probe for the NAND device.
503 static int __init
atmel_nand_probe(struct platform_device
*pdev
)
505 struct atmel_nand_host
*host
;
506 struct mtd_info
*mtd
;
507 struct nand_chip
*nand_chip
;
508 struct resource
*regs
;
509 struct resource
*mem
;
512 #ifdef CONFIG_MTD_PARTITIONS
513 struct mtd_partition
*partitions
= NULL
;
514 int num_partitions
= 0;
517 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
519 printk(KERN_ERR
"atmel_nand: can't get I/O resource mem\n");
523 /* Allocate memory for the device structure (and zero it) */
524 host
= kzalloc(sizeof(struct atmel_nand_host
), GFP_KERNEL
);
526 printk(KERN_ERR
"atmel_nand: failed to allocate device structure.\n");
530 host
->io_phys
= (dma_addr_t
)mem
->start
;
532 host
->io_base
= ioremap(mem
->start
, mem
->end
- mem
->start
+ 1);
533 if (host
->io_base
== NULL
) {
534 printk(KERN_ERR
"atmel_nand: ioremap failed\n");
536 goto err_nand_ioremap
;
540 nand_chip
= &host
->nand_chip
;
541 host
->board
= pdev
->dev
.platform_data
;
542 host
->dev
= &pdev
->dev
;
544 nand_chip
->priv
= host
; /* link the private data structures */
545 mtd
->priv
= nand_chip
;
546 mtd
->owner
= THIS_MODULE
;
548 /* Set address of NAND IO lines */
549 nand_chip
->IO_ADDR_R
= host
->io_base
;
550 nand_chip
->IO_ADDR_W
= host
->io_base
;
551 nand_chip
->cmd_ctrl
= atmel_nand_cmd_ctrl
;
553 if (host
->board
->rdy_pin
)
554 nand_chip
->dev_ready
= atmel_nand_device_ready
;
556 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
557 if (!regs
&& hard_ecc
) {
558 printk(KERN_ERR
"atmel_nand: can't get I/O resource "
559 "regs\nFalling back on software ECC\n");
562 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
; /* enable ECC */
564 nand_chip
->ecc
.mode
= NAND_ECC_NONE
;
565 if (hard_ecc
&& regs
) {
566 host
->ecc
= ioremap(regs
->start
, regs
->end
- regs
->start
+ 1);
567 if (host
->ecc
== NULL
) {
568 printk(KERN_ERR
"atmel_nand: ioremap failed\n");
570 goto err_ecc_ioremap
;
572 nand_chip
->ecc
.mode
= NAND_ECC_HW
;
573 nand_chip
->ecc
.calculate
= atmel_nand_calculate
;
574 nand_chip
->ecc
.correct
= atmel_nand_correct
;
575 nand_chip
->ecc
.hwctl
= atmel_nand_hwctl
;
576 nand_chip
->ecc
.read_page
= atmel_nand_read_page
;
577 nand_chip
->ecc
.bytes
= 4;
580 nand_chip
->chip_delay
= 20; /* 20us command delay time */
582 if (host
->board
->bus_width_16
) /* 16-bit bus width */
583 nand_chip
->options
|= NAND_BUSWIDTH_16
;
585 nand_chip
->read_buf
= atmel_read_buf
;
586 nand_chip
->write_buf
= atmel_write_buf
;
588 platform_set_drvdata(pdev
, host
);
589 atmel_nand_enable(host
);
591 if (host
->board
->det_pin
) {
592 if (gpio_get_value(host
->board
->det_pin
)) {
593 printk(KERN_INFO
"No SmartMedia card inserted.\n");
600 printk(KERN_INFO
"atmel_nand: Use On Flash BBT\n");
601 nand_chip
->options
|= NAND_USE_FLASH_BBT
;
611 dma_cap_set(DMA_MEMCPY
, mask
);
612 host
->dma_chan
= dma_request_channel(mask
, 0, NULL
);
613 if (!host
->dma_chan
) {
614 dev_err(host
->dev
, "Failed to request DMA channel\n");
619 dev_info(host
->dev
, "Using %s for DMA transfers.\n",
620 dma_chan_name(host
->dma_chan
));
622 dev_info(host
->dev
, "No DMA support for NAND access.\n");
624 /* first scan to find the device and get the page size */
625 if (nand_scan_ident(mtd
, 1, NULL
)) {
630 if (nand_chip
->ecc
.mode
== NAND_ECC_HW
) {
631 /* ECC is calculated for the whole page (1 step) */
632 nand_chip
->ecc
.size
= mtd
->writesize
;
634 /* set ECC page size and oob layout */
635 switch (mtd
->writesize
) {
637 nand_chip
->ecc
.layout
= &atmel_oobinfo_small
;
638 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_528
);
641 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
642 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_1056
);
645 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
646 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_2112
);
649 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
650 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_4224
);
653 /* page size not handled by HW ECC */
654 /* switching back to soft ECC */
655 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
656 nand_chip
->ecc
.calculate
= NULL
;
657 nand_chip
->ecc
.correct
= NULL
;
658 nand_chip
->ecc
.hwctl
= NULL
;
659 nand_chip
->ecc
.read_page
= NULL
;
660 nand_chip
->ecc
.postpad
= 0;
661 nand_chip
->ecc
.prepad
= 0;
662 nand_chip
->ecc
.bytes
= 0;
667 /* second phase scan */
668 if (nand_scan_tail(mtd
)) {
673 #ifdef CONFIG_MTD_PARTITIONS
674 #ifdef CONFIG_MTD_CMDLINE_PARTS
675 mtd
->name
= "atmel_nand";
676 num_partitions
= parse_mtd_partitions(mtd
, part_probes
,
679 if (num_partitions
<= 0 && host
->board
->partition_info
)
680 partitions
= host
->board
->partition_info(mtd
->size
,
683 if ((!partitions
) || (num_partitions
== 0)) {
684 printk(KERN_ERR
"atmel_nand: No partitions defined, or unsupported device.\n");
686 goto err_no_partitions
;
689 res
= add_mtd_partitions(mtd
, partitions
, num_partitions
);
691 res
= add_mtd_device(mtd
);
697 #ifdef CONFIG_MTD_PARTITIONS
704 atmel_nand_disable(host
);
705 platform_set_drvdata(pdev
, NULL
);
707 dma_release_channel(host
->dma_chan
);
711 iounmap(host
->io_base
);
718 * Remove a NAND device.
720 static int __exit
atmel_nand_remove(struct platform_device
*pdev
)
722 struct atmel_nand_host
*host
= platform_get_drvdata(pdev
);
723 struct mtd_info
*mtd
= &host
->mtd
;
727 atmel_nand_disable(host
);
733 dma_release_channel(host
->dma_chan
);
735 iounmap(host
->io_base
);
741 static struct platform_driver atmel_nand_driver
= {
742 .remove
= __exit_p(atmel_nand_remove
),
744 .name
= "atmel_nand",
745 .owner
= THIS_MODULE
,
749 static int __init
atmel_nand_init(void)
751 return platform_driver_probe(&atmel_nand_driver
, atmel_nand_probe
);
755 static void __exit
atmel_nand_exit(void)
757 platform_driver_unregister(&atmel_nand_driver
);
761 module_init(atmel_nand_init
);
762 module_exit(atmel_nand_exit
);
764 MODULE_LICENSE("GPL");
765 MODULE_AUTHOR("Rick Bronson");
766 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
767 MODULE_ALIAS("platform:atmel_nand");