drivers/pcmcia/m8xx_pcmcia.c

   1 /*
   2  * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
   3  *
   4  * (C) 1999-2000 Magnus Damm <damm@opensource.se>
   5  * (C) 2001-2002 Montavista Software, Inc.
   6  *     <mlocke@mvista.com>
   7  *
   8  * Support for two slots by Cyclades Corporation
   9  *     <oliver.kurth@cyclades.de>
  10  * Further fixes, v2.6 kernel port
  11  *     <marcelo.tosatti@cyclades.com>
  12  *
  13  * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
  14  *     <vbordug@ru.mvista.com>
  15  *
  16  * "The ExCA standard specifies that socket controllers should provide
  17  * two IO and five memory windows per socket, which can be independently
  18  * configured and positioned in the host address space and mapped to
  19  * arbitrary segments of card address space. " - David A Hinds. 1999
  20  *
  21  * This controller does _not_ meet the ExCA standard.
  22  *
  23  * m8xx pcmcia controller brief info:
  24  * + 8 windows (attrib, mem, i/o)
  25  * + up to two slots (SLOT_A and SLOT_B)
  26  * + inputpins, outputpins, event and mask registers.
  27  * - no offset register. sigh.
  28  *
  29  * Because of the lacking offset register we must map the whole card.
  30  * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
  31  * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
  32  * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
  33  * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
  34  * They are maximum 64KByte each...
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/types.h>
  40 #include <linux/fcntl.h>
  41 #include <linux/string.h>
  42
  43 #include <linux/kernel.h>
  44 #include <linux/errno.h>
  45 #include <linux/slab.h>
  46 #include <linux/timer.h>
  47 #include <linux/ioport.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/fsl_devices.h>
  51 #include <linux/bitops.h>
  52 #include <linux/of_device.h>
  53 #include <linux/of_platform.h>
  54
  55 #include <asm/io.h>
  56 #include <asm/system.h>
  57 #include <asm/time.h>
  58 #include <asm/mpc8xx.h>
  59 #include <asm/8xx_immap.h>
  60 #include <asm/irq.h>
  61 #include <asm/fs_pd.h>
  62
  63 #include <pcmcia/cs_types.h>
  64 #include <pcmcia/cs.h>
  65 #include <pcmcia/ss.h>
  66
  67 #ifdef CONFIG_PCMCIA_DEBUG
  68 static int pc_debug;
  69 module_param(pc_debug, int, 0);
  70 #define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
  71 #else
  72 #define dprintk(args...)
  73 #endif
  74
  75 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
  76 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
  77
  78 static const char *version = "Version 0.06, Aug 2005";
  79 MODULE_LICENSE("Dual MPL/GPL");
  80
  81 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  82
  83 /* The RPX series use SLOT_B */
  84 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
  85 #define CONFIG_PCMCIA_SLOT_B
  86 #define CONFIG_BD_IS_MHZ
  87 #endif
  88
  89 /* The ADS board use SLOT_A */
  90 #ifdef CONFIG_ADS
  91 #define CONFIG_PCMCIA_SLOT_A
  92 #define CONFIG_BD_IS_MHZ
  93 #endif
  94
  95 /* The FADS series are a mess */
  96 #ifdef CONFIG_FADS
  97 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
  98 #define CONFIG_PCMCIA_SLOT_A
  99 #else
 100 #define CONFIG_PCMCIA_SLOT_B
 101 #endif
 102 #endif
 103
 104 #if defined(CONFIG_MPC885ADS)
 105 #define CONFIG_PCMCIA_SLOT_A
 106 #define PCMCIA_GLITCHY_CD
 107 #endif
 108
 109 /* Cyclades ACS uses both slots */
 110 #ifdef CONFIG_PRxK
 111 #define CONFIG_PCMCIA_SLOT_A
 112 #define CONFIG_PCMCIA_SLOT_B
 113 #endif
 114
 115 #endif                          /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
 116
 117 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
 118
 119 #define PCMCIA_SOCKETS_NO 2
 120 /* We have only 8 windows, dualsocket support will be limited. */
 121 #define PCMCIA_MEM_WIN_NO 2
 122 #define PCMCIA_IO_WIN_NO  2
 123 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
 124
 125 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
 126
 127 #define PCMCIA_SOCKETS_NO 1
 128 /* full support for one slot */
 129 #define PCMCIA_MEM_WIN_NO 5
 130 #define PCMCIA_IO_WIN_NO  2
 131
 132 /* define _slot_ to be able to optimize macros */
 133
 134 #ifdef CONFIG_PCMCIA_SLOT_A
 135 #define _slot_ 0
 136 #define PCMCIA_SLOT_MSG "SLOT_A"
 137 #else
 138 #define _slot_ 1
 139 #define PCMCIA_SLOT_MSG "SLOT_B"
 140 #endif
 141
 142 #else
 143 #error m8xx_pcmcia: Bad configuration!
 144 #endif
 145
 146 /* ------------------------------------------------------------------------- */
 147
 148 #define PCMCIA_MEM_WIN_BASE 0xe0000000  /* base address for memory window 0   */
 149 #define PCMCIA_MEM_WIN_SIZE 0x04000000  /* each memory window is 64 MByte     */
 150 #define PCMCIA_IO_WIN_BASE  _IO_BASE    /* base address for io window 0       */
 151 /* ------------------------------------------------------------------------- */
 152
 153 static int pcmcia_schlvl;
 154
 155 static DEFINE_SPINLOCK(events_lock);
 156
 157 #define PCMCIA_SOCKET_KEY_5V 1
 158 #define PCMCIA_SOCKET_KEY_LV 2
 159
 160 /* look up table for pgcrx registers */
 161 static u32 *m8xx_pgcrx[2];
 162
 163 /*
 164  * This structure is used to address each window in the PCMCIA controller.
 165  *
 166  * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
 167  * after pcmcia_win[n]...
 168  */
 169
 170 struct pcmcia_win {
 171         u32 br;
 172         u32 or;
 173 };
 174
 175 /*
 176  * For some reason the hardware guys decided to make both slots share
 177  * some registers.
 178  *
 179  * Could someone invent object oriented hardware ?
 180  *
 181  * The macros are used to get the right bit from the registers.
 182  * SLOT_A : slot = 0
 183  * SLOT_B : slot = 1
 184  */
 185
 186 #define M8XX_PCMCIA_VS1(slot)      (0x80000000 >> (slot << 4))
 187 #define M8XX_PCMCIA_VS2(slot)      (0x40000000 >> (slot << 4))
 188 #define M8XX_PCMCIA_VS_MASK(slot)  (0xc0000000 >> (slot << 4))
 189 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
 190
 191 #define M8XX_PCMCIA_WP(slot)       (0x20000000 >> (slot << 4))
 192 #define M8XX_PCMCIA_CD2(slot)      (0x10000000 >> (slot << 4))
 193 #define M8XX_PCMCIA_CD1(slot)      (0x08000000 >> (slot << 4))
 194 #define M8XX_PCMCIA_BVD2(slot)     (0x04000000 >> (slot << 4))
 195 #define M8XX_PCMCIA_BVD1(slot)     (0x02000000 >> (slot << 4))
 196 #define M8XX_PCMCIA_RDY(slot)      (0x01000000 >> (slot << 4))
 197 #define M8XX_PCMCIA_RDY_L(slot)    (0x00800000 >> (slot << 4))
 198 #define M8XX_PCMCIA_RDY_H(slot)    (0x00400000 >> (slot << 4))
 199 #define M8XX_PCMCIA_RDY_R(slot)    (0x00200000 >> (slot << 4))
 200 #define M8XX_PCMCIA_RDY_F(slot)    (0x00100000 >> (slot << 4))
 201 #define M8XX_PCMCIA_MASK(slot)     (0xFFFF0000 >> (slot << 4))
 202
 203 #define M8XX_PCMCIA_POR_VALID    0x00000001
 204 #define M8XX_PCMCIA_POR_WRPROT   0x00000002
 205 #define M8XX_PCMCIA_POR_ATTRMEM  0x00000010
 206 #define M8XX_PCMCIA_POR_IO       0x00000018
 207 #define M8XX_PCMCIA_POR_16BIT    0x00000040
 208
 209 #define M8XX_PGCRX(slot)  m8xx_pgcrx[slot]
 210
 211 #define M8XX_PGCRX_CXOE    0x00000080
 212 #define M8XX_PGCRX_CXRESET 0x00000040
 213
 214 /* we keep one lookup table per socket to check flags */
 215
 216 #define PCMCIA_EVENTS_MAX 5     /* 4 max at a time + termination */
 217
 218 struct event_table {
 219         u32 regbit;
 220         u32 eventbit;
 221 };
 222
 223 static const char driver_name[] = "m8xx-pcmcia";
 224
 225 struct socket_info {
 226         void (*handler) (void *info, u32 events);
 227         void *info;
 228
 229         u32 slot;
 230         pcmconf8xx_t *pcmcia;
 231         u32 bus_freq;
 232         int hwirq;
 233
 234         socket_state_t state;
 235         struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
 236         struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
 237         struct event_table events[PCMCIA_EVENTS_MAX];
 238         struct pcmcia_socket socket;
 239 };
 240
 241 static struct socket_info socket[PCMCIA_SOCKETS_NO];
 242
 243 /*
 244  * Search this table to see if the windowsize is
 245  * supported...
 246  */
 247
 248 #define M8XX_SIZES_NO 32
 249
 250 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
 251         0x00000001, 0x00000002, 0x00000008, 0x00000004,
 252         0x00000080, 0x00000040, 0x00000010, 0x00000020,
 253         0x00008000, 0x00004000, 0x00001000, 0x00002000,
 254         0x00000100, 0x00000200, 0x00000800, 0x00000400,
 255
 256         0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 257         0x01000000, 0x02000000, 0xffffffff, 0x04000000,
 258         0x00010000, 0x00020000, 0x00080000, 0x00040000,
 259         0x00800000, 0x00400000, 0x00100000, 0x00200000
 260 };
 261
 262 /* ------------------------------------------------------------------------- */
 263
 264 static irqreturn_t m8xx_interrupt(int irq, void *dev);
 265
 266 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
 267
 268 /* ------------------------------------------------------------------------- */
 269 /* board specific stuff:                                                     */
 270 /* voltage_set(), hardware_enable() and hardware_disable()                   */
 271 /* ------------------------------------------------------------------------- */
 272 /* RPX Boards from Embedded Planet                                           */
 273
 274 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
 275
 276 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
 277  * SYPCR is write once only, therefore must the slowest memory be faster
 278  * than the bus monitor or we will get a machine check due to the bus timeout.
 279  */
 280
 281 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
 282
 283 #undef PCMCIA_BMT_LIMIT
 284 #define PCMCIA_BMT_LIMIT (6*8)
 285
 286 static int voltage_set(int slot, int vcc, int vpp)
 287 {
 288         u32 reg = 0;
 289
 290         switch (vcc) {
 291         case 0:
 292                 break;
 293         case 33:
 294                 reg |= BCSR1_PCVCTL4;
 295                 break;
 296         case 50:
 297                 reg |= BCSR1_PCVCTL5;
 298                 break;
 299         default:
 300                 return 1;
 301         }
 302
 303         switch (vpp) {
 304         case 0:
 305                 break;
 306         case 33:
 307         case 50:
 308                 if (vcc == vpp)
 309                         reg |= BCSR1_PCVCTL6;
 310                 else
 311                         return 1;
 312                 break;
 313         case 120:
 314                 reg |= BCSR1_PCVCTL7;
 315         default:
 316                 return 1;
 317         }
 318
 319         if (!((vcc == 50) || (vcc == 0)))
 320                 return 1;
 321
 322         /* first, turn off all power */
 323
 324         out_be32(((u32 *) RPX_CSR_ADDR),
 325                  in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
 326                                                      BCSR1_PCVCTL5 |
 327                                                      BCSR1_PCVCTL6 |
 328                                                      BCSR1_PCVCTL7));
 329
 330         /* enable new powersettings */
 331
 332         out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
 333
 334         return 0;
 335 }
 336
 337 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 338 #define hardware_enable(_slot_) /* No hardware to enable */
 339 #define hardware_disable(_slot_)        /* No hardware to disable */
 340
 341 #endif                          /* CONFIG_RPXCLASSIC */
 342
 343 /* FADS Boards from Motorola                                               */
 344
 345 #if defined(CONFIG_FADS)
 346
 347 #define PCMCIA_BOARD_MSG "FADS"
 348
 349 static int voltage_set(int slot, int vcc, int vpp)
 350 {
 351         u32 reg = 0;
 352
 353         switch (vcc) {
 354         case 0:
 355                 break;
 356         case 33:
 357                 reg |= BCSR1_PCCVCC0;
 358                 break;
 359         case 50:
 360                 reg |= BCSR1_PCCVCC1;
 361                 break;
 362         default:
 363                 return 1;
 364         }
 365
 366         switch (vpp) {
 367         case 0:
 368                 break;
 369         case 33:
 370         case 50:
 371                 if (vcc == vpp)
 372                         reg |= BCSR1_PCCVPP1;
 373                 else
 374                         return 1;
 375                 break;
 376         case 120:
 377                 if ((vcc == 33) || (vcc == 50))
 378                         reg |= BCSR1_PCCVPP0;
 379                 else
 380                         return 1;
 381         default:
 382                 return 1;
 383         }
 384
 385         /* first, turn off all power */
 386         out_be32((u32 *) BCSR1,
 387                  in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
 388                                             BCSR1_PCCVPP_MASK));
 389
 390         /* enable new powersettings */
 391         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
 392
 393         return 0;
 394 }
 395
 396 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 397
 398 static void hardware_enable(int slot)
 399 {
 400         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
 401 }
 402
 403 static void hardware_disable(int slot)
 404 {
 405         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
 406 }
 407
 408 #endif
 409
 410 /* MPC885ADS Boards */
 411
 412 #if defined(CONFIG_MPC885ADS)
 413
 414 #define PCMCIA_BOARD_MSG "MPC885ADS"
 415 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 416
 417 static inline void hardware_enable(int slot)
 418 {
 419         m8xx_pcmcia_ops.hw_ctrl(slot, 1);
 420 }
 421
 422 static inline void hardware_disable(int slot)
 423 {
 424         m8xx_pcmcia_ops.hw_ctrl(slot, 0);
 425 }
 426
 427 static inline int voltage_set(int slot, int vcc, int vpp)
 428 {
 429         return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
 430 }
 431
 432 #endif
 433
 434 /* ------------------------------------------------------------------------- */
 435 /* Motorola MBX860                                                           */
 436
 437 #if defined(CONFIG_MBX)
 438
 439 #define PCMCIA_BOARD_MSG "MBX"
 440
 441 static int voltage_set(int slot, int vcc, int vpp)
 442 {
 443         u8 reg = 0;
 444
 445         switch (vcc) {
 446         case 0:
 447                 break;
 448         case 33:
 449                 reg |= CSR2_VCC_33;
 450                 break;
 451         case 50:
 452                 reg |= CSR2_VCC_50;
 453                 break;
 454         default:
 455                 return 1;
 456         }
 457
 458         switch (vpp) {
 459         case 0:
 460                 break;
 461         case 33:
 462         case 50:
 463                 if (vcc == vpp)
 464                         reg |= CSR2_VPP_VCC;
 465                 else
 466                         return 1;
 467                 break;
 468         case 120:
 469                 if ((vcc == 33) || (vcc == 50))
 470                         reg |= CSR2_VPP_12;
 471                 else
 472                         return 1;
 473         default:
 474                 return 1;
 475         }
 476
 477         /* first, turn off all power */
 478         out_8((u8 *) MBX_CSR2_ADDR,
 479               in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
 480
 481         /* enable new powersettings */
 482         out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg);
 483
 484         return 0;
 485 }
 486
 487 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 488 #define hardware_enable(_slot_) /* No hardware to enable */
 489 #define hardware_disable(_slot_)        /* No hardware to disable */
 490
 491 #endif                          /* CONFIG_MBX */
 492
 493 #if defined(CONFIG_PRxK)
 494 #include <asm/cpld.h>
 495 extern volatile fpga_pc_regs *fpga_pc;
 496
 497 #define PCMCIA_BOARD_MSG "MPC855T"
 498
 499 static int voltage_set(int slot, int vcc, int vpp)
 500 {
 501         u8 reg = 0;
 502         u8 regread;
 503         cpld_regs *ccpld = get_cpld();
 504
 505         switch (vcc) {
 506         case 0:
 507                 break;
 508         case 33:
 509                 reg |= PCMCIA_VCC_33;
 510                 break;
 511         case 50:
 512                 reg |= PCMCIA_VCC_50;
 513                 break;
 514         default:
 515                 return 1;
 516         }
 517
 518         switch (vpp) {
 519         case 0:
 520                 break;
 521         case 33:
 522         case 50:
 523                 if (vcc == vpp)
 524                         reg |= PCMCIA_VPP_VCC;
 525                 else
 526                         return 1;
 527                 break;
 528         case 120:
 529                 if ((vcc == 33) || (vcc == 50))
 530                         reg |= PCMCIA_VPP_12;
 531                 else
 532                         return 1;
 533         default:
 534                 return 1;
 535         }
 536
 537         reg = reg >> (slot << 2);
 538         regread = in_8(&ccpld->fpga_pc_ctl);
 539         if (reg !=
 540             (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
 541                 /* enable new powersettings */
 542                 regread =
 543                     regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
 544                                 (slot << 2));
 545                 out_8(&ccpld->fpga_pc_ctl, reg | regread);
 546                 msleep(100);
 547         }
 548
 549         return 0;
 550 }
 551
 552 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
 553 #define hardware_enable(_slot_) /* No hardware to enable */
 554 #define hardware_disable(_slot_)        /* No hardware to disable */
 555
 556 #endif                          /* CONFIG_PRxK */
 557
 558 static u32 pending_events[PCMCIA_SOCKETS_NO];
 559 static DEFINE_SPINLOCK(pending_event_lock);
 560
 561 static irqreturn_t m8xx_interrupt(int irq, void *dev)
 562 {
 563         struct socket_info *s;
 564         struct event_table *e;
 565         unsigned int i, events, pscr, pipr, per;
 566         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
 567
 568         dprintk("Interrupt!\n");
 569         /* get interrupt sources */
 570
 571         pscr = in_be32(&pcmcia->pcmc_pscr);
 572         pipr = in_be32(&pcmcia->pcmc_pipr);
 573         per = in_be32(&pcmcia->pcmc_per);
 574
 575         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
 576                 s = &socket[i];
 577                 e = &s->events[0];
 578                 events = 0;
 579
 580                 while (e->regbit) {
 581                         if (pscr & e->regbit)
 582                                 events |= e->eventbit;
 583
 584                         e++;
 585                 }
 586
 587                 /*
 588                  * report only if both card detect signals are the same
 589                  * not too nice done,
 590                  * we depend on that CD2 is the bit to the left of CD1...
 591                  */
 592                 if (events & SS_DETECT)
 593                         if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
 594                             (pipr & M8XX_PCMCIA_CD1(i))) {
 595                                 events &= ~SS_DETECT;
 596                         }
 597 #ifdef PCMCIA_GLITCHY_CD
 598                 /*
 599                  * I've experienced CD problems with my ADS board.
 600                  * We make an extra check to see if there was a
 601                  * real change of Card detection.
 602                  */
 603
 604                 if ((events & SS_DETECT) &&
 605                     ((pipr &
 606                       (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
 607                     (s->state.Vcc | s->state.Vpp)) {
 608                         events &= ~SS_DETECT;
 609                         /*printk( "CD glitch workaround - CD = 0x%08x!\n",
 610                            (pipr & (M8XX_PCMCIA_CD2(i)
 611                            | M8XX_PCMCIA_CD1(i)))); */
 612                 }
 613 #endif
 614
 615                 /* call the handler */
 616
 617                 dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
 618                         "pipr = 0x%08x\n", i, events, pscr, pipr);
 619
 620                 if (events) {
 621                         spin_lock(&pending_event_lock);
 622                         pending_events[i] |= events;
 623                         spin_unlock(&pending_event_lock);
 624                         /*
 625                          * Turn off RDY_L bits in the PER mask on
 626                          * CD interrupt receival.
 627                          *
 628                          * They can generate bad interrupts on the
 629                          * ACS4,8,16,32.   - marcelo
 630                          */
 631                         per &= ~M8XX_PCMCIA_RDY_L(0);
 632                         per &= ~M8XX_PCMCIA_RDY_L(1);
 633
 634                         out_be32(&pcmcia->pcmc_per, per);
 635
 636                         if (events)
 637                                 pcmcia_parse_events(&socket[i].socket, events);
 638                 }
 639         }
 640
 641         /* clear the interrupt sources */
 642         out_be32(&pcmcia->pcmc_pscr, pscr);
 643
 644         dprintk("Interrupt done.\n");
 645
 646         return IRQ_HANDLED;
 647 }
 648
 649 static u32 m8xx_get_graycode(u32 size)
 650 {
 651         u32 k;
 652
 653         for (k = 0; k < M8XX_SIZES_NO; k++)
 654                 if (m8xx_size_to_gray[k] == size)
 655                         break;
 656
 657         if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
 658                 k = -1;
 659
 660         return k;
 661 }
 662
 663 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
 664 {
 665         u32 reg, clocks, psst, psl, psht;
 666
 667         if (!ns) {
 668
 669                 /*
 670                  * We get called with IO maps setup to 0ns
 671                  * if not specified by the user.
 672                  * They should be 255ns.
 673                  */
 674
 675                 if (is_io)
 676                         ns = 255;
 677                 else
 678                         ns = 100;       /* fast memory if 0 */
 679         }
 680
 681         /*
 682          * In PSST, PSL, PSHT fields we tell the controller
 683          * timing parameters in CLKOUT clock cycles.
 684          * CLKOUT is the same as GCLK2_50.
 685          */
 686
 687 /* how we want to adjust the timing - in percent */
 688
 689 #define ADJ 180                 /* 80 % longer accesstime - to be sure */
 690
 691         clocks = ((bus_freq / 1000) * ns) / 1000;
 692         clocks = (clocks * ADJ) / (100 * 1000);
 693         if (clocks >= PCMCIA_BMT_LIMIT) {
 694                 printk("Max access time limit reached\n");
 695                 clocks = PCMCIA_BMT_LIMIT - 1;
 696         }
 697
 698         psst = clocks / 7;      /* setup time */
 699         psht = clocks / 7;      /* hold time */
 700         psl = (clocks * 5) / 7; /* strobe length */
 701
 702         psst += clocks - (psst + psht + psl);
 703
 704         reg = psst << 12;
 705         reg |= psl << 7;
 706         reg |= psht << 16;
 707
 708         return reg;
 709 }
 710
 711 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
 712 {
 713         int lsock = container_of(sock, struct socket_info, socket)->slot;
 714         struct socket_info *s = &socket[lsock];
 715         unsigned int pipr, reg;
 716         pcmconf8xx_t *pcmcia = s->pcmcia;
 717
 718         pipr = in_be32(&pcmcia->pcmc_pipr);
 719
 720         *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
 721                            | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
 722         *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
 723
 724         if (s->state.flags & SS_IOCARD)
 725                 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
 726         else {
 727                 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
 728                 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
 729                 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
 730         }
 731
 732         if (s->state.Vcc | s->state.Vpp)
 733                 *value |= SS_POWERON;
 734
 735         /*
 736          * Voltage detection:
 737          * This driver only supports 16-Bit pc-cards.
 738          * Cardbus is not handled here.
 739          *
 740          * To determine what voltage to use we must read the VS1 and VS2 pin.
 741          * Depending on what socket type is present,
 742          * different combinations mean different things.
 743          *
 744          * Card Key  Socket Key   VS1   VS2   Card         Vcc for CIS parse
 745          *
 746          * 5V        5V, LV*      NC    NC    5V only       5V (if available)
 747          *
 748          * 5V        5V, LV*      GND   NC    5 or 3.3V     as low as possible
 749          *
 750          * 5V        5V, LV*      GND   GND   5, 3.3, x.xV  as low as possible
 751          *
 752          * LV*       5V            -     -    shall not fit into socket
 753          *
 754          * LV*       LV*          GND   NC    3.3V only     3.3V
 755          *
 756          * LV*       LV*          NC    GND   x.xV          x.xV (if avail.)
 757          *
 758          * LV*       LV*          GND   GND   3.3 or x.xV   as low as possible
 759          *
 760          * *LV means Low Voltage
 761          *
 762          *
 763          * That gives us the following table:
 764          *
 765          * Socket    VS1  VS2   Voltage
 766          *
 767          * 5V        NC   NC    5V
 768          * 5V        NC   GND   none (should not be possible)
 769          * 5V        GND  NC    >= 3.3V
 770          * 5V        GND  GND   >= x.xV
 771          *
 772          * LV        NC   NC    5V   (if available)
 773          * LV        NC   GND   x.xV (if available)
 774          * LV        GND  NC    3.3V
 775          * LV        GND  GND   >= x.xV
 776          *
 777          * So, how do I determine if I have a 5V or a LV
 778          * socket on my board?  Look at the socket!
 779          *
 780          *
 781          * Socket with 5V key:
 782          * ++--------------------------------------------+
 783          * ||                                            |
 784          * ||                                           ||
 785          * ||                                           ||
 786          * |                                             |
 787          * +---------------------------------------------+
 788          *
 789          * Socket with LV key:
 790          * ++--------------------------------------------+
 791          * ||                                            |
 792          * |                                            ||
 793          * |                                            ||
 794          * |                                             |
 795          * +---------------------------------------------+
 796          *
 797          *
 798          * With other words - LV only cards does not fit
 799          * into the 5V socket!
 800          */
 801
 802         /* read out VS1 and VS2 */
 803
 804         reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
 805             >> M8XX_PCMCIA_VS_SHIFT(lsock);
 806
 807         if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
 808                 switch (reg) {
 809                 case 1:
 810                         *value |= SS_3VCARD;
 811                         break;  /* GND, NC - 3.3V only */
 812                 case 2:
 813                         *value |= SS_XVCARD;
 814                         break;  /* NC. GND - x.xV only */
 815                 };
 816         }
 817
 818         dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
 819         return 0;
 820 }
 821
 822 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
 823 {
 824         int lsock = container_of(sock, struct socket_info, socket)->slot;
 825         struct socket_info *s = &socket[lsock];
 826         struct event_table *e;
 827         unsigned int reg;
 828         unsigned long flags;
 829         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
 830
 831         dprintk("SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
 832                 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
 833                 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 834
 835         /* First, set voltage - bail out if invalid */
 836         if (voltage_set(lsock, state->Vcc, state->Vpp))
 837                 return -EINVAL;
 838
 839         /* Take care of reset... */
 840         if (state->flags & SS_RESET)
 841                 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET);   /* active high */
 842         else
 843                 out_be32(M8XX_PGCRX(lsock),
 844                          in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
 845
 846         /* ... and output enable. */
 847
 848         /* The CxOE signal is connected to a 74541 on the ADS.
 849            I guess most other boards used the ADS as a reference.
 850            I tried to control the CxOE signal with SS_OUTPUT_ENA,
 851            but the reset signal seems connected via the 541.
 852            If the CxOE is left high are some signals tristated and
 853            no pullups are present -> the cards act weird.
 854            So right now the buffers are enabled if the power is on. */
 855
 856         if (state->Vcc || state->Vpp)
 857                 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE);     /* active low */
 858         else
 859                 out_be32(M8XX_PGCRX(lsock),
 860                          in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
 861
 862         /*
 863          * We'd better turn off interrupts before
 864          * we mess with the events-table..
 865          */
 866
 867         spin_lock_irqsave(&events_lock, flags);
 868
 869         /*
 870          * Play around with the interrupt mask to be able to
 871          * give the events the generic pcmcia driver wants us to.
 872          */
 873
 874         e = &s->events[0];
 875         reg = 0;
 876
 877         if (state->csc_mask & SS_DETECT) {
 878                 e->eventbit = SS_DETECT;
 879                 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
 880                                     | M8XX_PCMCIA_CD1(lsock));
 881                 e++;
 882         }
 883         if (state->flags & SS_IOCARD) {
 884                 /*
 885                  * I/O card
 886                  */
 887                 if (state->csc_mask & SS_STSCHG) {
 888                         e->eventbit = SS_STSCHG;
 889                         reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
 890                         e++;
 891                 }
 892                 /*
 893                  * If io_irq is non-zero we should enable irq.
 894                  */
 895                 if (state->io_irq) {
 896                         out_be32(M8XX_PGCRX(lsock),
 897                                  in_be32(M8XX_PGCRX(lsock)) |
 898                                  mk_int_int_mask(s->hwirq) << 24);
 899                         /*
 900                          * Strange thing here:
 901                          * The manual does not tell us which interrupt
 902                          * the sources generate.
 903                          * Anyhow, I found out that RDY_L generates IREQLVL.
 904                          *
 905                          * We use level triggerd interrupts, and they don't
 906                          * have to be cleared in PSCR in the interrupt handler.
 907                          */
 908                         reg |= M8XX_PCMCIA_RDY_L(lsock);
 909                 } else
 910                         out_be32(M8XX_PGCRX(lsock),
 911                                  in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
 912         } else {
 913                 /*
 914                  * Memory card
 915                  */
 916                 if (state->csc_mask & SS_BATDEAD) {
 917                         e->eventbit = SS_BATDEAD;
 918                         reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
 919                         e++;
 920                 }
 921                 if (state->csc_mask & SS_BATWARN) {
 922                         e->eventbit = SS_BATWARN;
 923                         reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
 924                         e++;
 925                 }
 926                 /* What should I trigger on - low/high,raise,fall? */
 927                 if (state->csc_mask & SS_READY) {
 928                         e->eventbit = SS_READY;
 929                         reg |= e->regbit = 0;   //??
 930                         e++;
 931                 }
 932         }
 933
 934         e->regbit = 0;          /* terminate list */
 935
 936         /*
 937          * Clear the status changed .
 938          * Port A and Port B share the same port.
 939          * Writing ones will clear the bits.
 940          */
 941
 942         out_be32(&pcmcia->pcmc_pscr, reg);
 943
 944         /*
 945          * Write the mask.
 946          * Port A and Port B share the same port.
 947          * Need for read-modify-write.
 948          * Ones will enable the interrupt.
 949          */
 950
 951         reg |=
 952             in_be32(&pcmcia->
 953                     pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
 954         out_be32(&pcmcia->pcmc_per, reg);
 955
 956         spin_unlock_irqrestore(&events_lock, flags);
 957
 958         /* copy the struct and modify the copy */
 959
 960         s->state = *state;
 961
 962         return 0;
 963 }
 964
 965 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
 966 {
 967         int lsock = container_of(sock, struct socket_info, socket)->slot;
 968
 969         struct socket_info *s = &socket[lsock];
 970         struct pcmcia_win *w;
 971         unsigned int reg, winnr;
 972         pcmconf8xx_t *pcmcia = s->pcmcia;
 973
 974 #define M8XX_SIZE (io->stop - io->start + 1)
 975 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
 976
 977         dprintk("SetIOMap(%d, %d, %#2.2x, %d ns, "
 978                 "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags,
 979                 io->speed, (unsigned long long)io->start,
 980                 (unsigned long long)io->stop);
 981
 982         if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
 983             || (io->stop > 0xffff) || (io->stop < io->start))
 984                 return -EINVAL;
 985
 986         if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
 987                 return -EINVAL;
 988
 989         if (io->flags & MAP_ACTIVE) {
 990
 991                 dprintk("io->flags & MAP_ACTIVE\n");
 992
 993                 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
 994                     + (lsock * PCMCIA_IO_WIN_NO) + io->map;
 995
 996                 /* setup registers */
 997
 998                 w = (void *)&pcmcia->pcmc_pbr0;
 999                 w += winnr;
1000
1001                 out_be32(&w->or, 0);    /* turn off window first */
1002                 out_be32(&w->br, M8XX_BASE);
1003
1004                 reg <<= 27;
1005                 reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
1006
1007                 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
1008
1009                 if (io->flags & MAP_WRPROT)
1010                         reg |= M8XX_PCMCIA_POR_WRPROT;
1011
1012                 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
1013                 if (io->flags & MAP_16BIT)
1014                         reg |= M8XX_PCMCIA_POR_16BIT;
1015
1016                 if (io->flags & MAP_ACTIVE)
1017                         reg |= M8XX_PCMCIA_POR_VALID;
1018
1019                 out_be32(&w->or, reg);
1020
1021                 dprintk("Socket %u: Mapped io window %u at %#8.8x, "
1022                         "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1023         } else {
1024                 /* shutdown IO window */
1025                 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1026                     + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1027
1028                 /* setup registers */
1029
1030                 w = (void *)&pcmcia->pcmc_pbr0;
1031                 w += winnr;
1032
1033                 out_be32(&w->or, 0);    /* turn off window */
1034                 out_be32(&w->br, 0);    /* turn off base address */
1035
1036                 dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
1037                         "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1038         }
1039
1040         /* copy the struct and modify the copy */
1041         s->io_win[io->map] = *io;
1042         s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1043         dprintk("SetIOMap exit\n");
1044
1045         return 0;
1046 }
1047
1048 static int m8xx_set_mem_map(struct pcmcia_socket *sock,
1049                             struct pccard_mem_map *mem)
1050 {
1051         int lsock = container_of(sock, struct socket_info, socket)->slot;
1052         struct socket_info *s = &socket[lsock];
1053         struct pcmcia_win *w;
1054         struct pccard_mem_map *old;
1055         unsigned int reg, winnr;
1056         pcmconf8xx_t *pcmcia = s->pcmcia;
1057
1058         dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1059                 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1060                 mem->speed, (unsigned long long)mem->static_start,
1061                 mem->card_start);
1062
1063         if ((mem->map >= PCMCIA_MEM_WIN_NO)
1064 //          || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1065             || (mem->card_start >= 0x04000000)
1066             || (mem->static_start & 0xfff)      /* 4KByte resolution */
1067             ||(mem->card_start & 0xfff))
1068                 return -EINVAL;
1069
1070         if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1071                 printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1072                 return -EINVAL;
1073         }
1074         reg <<= 27;
1075
1076         winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1077
1078         /* Setup the window in the pcmcia controller */
1079
1080         w = (void *)&pcmcia->pcmc_pbr0;
1081         w += winnr;
1082
1083         reg |= lsock << 2;
1084
1085         reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1086
1087         if (mem->flags & MAP_ATTRIB)
1088                 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1089
1090         if (mem->flags & MAP_WRPROT)
1091                 reg |= M8XX_PCMCIA_POR_WRPROT;
1092
1093         if (mem->flags & MAP_16BIT)
1094                 reg |= M8XX_PCMCIA_POR_16BIT;
1095
1096         if (mem->flags & MAP_ACTIVE)
1097                 reg |= M8XX_PCMCIA_POR_VALID;
1098
1099         out_be32(&w->or, reg);
1100
1101         dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
1102                 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1103
1104         if (mem->flags & MAP_ACTIVE) {
1105                 /* get the new base address */
1106                 mem->static_start = PCMCIA_MEM_WIN_BASE +
1107                     (PCMCIA_MEM_WIN_SIZE * winnr)
1108                     + mem->card_start;
1109         }
1110
1111         dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1112                 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1113                 mem->speed, (unsigned long long)mem->static_start,
1114                 mem->card_start);
1115
1116         /* copy the struct and modify the copy */
1117
1118         old = &s->mem_win[mem->map];
1119
1120         *old = *mem;
1121         old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1122
1123         return 0;
1124 }
1125
1126 static int m8xx_sock_init(struct pcmcia_socket *sock)
1127 {
1128         int i;
1129         pccard_io_map io = { 0, 0, 0, 0, 1 };
1130         pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1131
1132         dprintk("sock_init(%d)\n", s);
1133
1134         m8xx_set_socket(sock, &dead_socket);
1135         for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1136                 io.map = i;
1137                 m8xx_set_io_map(sock, &io);
1138         }
1139         for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1140                 mem.map = i;
1141                 m8xx_set_mem_map(sock, &mem);
1142         }
1143
1144         return 0;
1145
1146 }
1147
1148 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1149 {
1150         return m8xx_set_socket(sock, &dead_socket);
1151 }
1152
1153 static struct pccard_operations m8xx_services = {
1154         .init = m8xx_sock_init,
1155         .suspend = m8xx_sock_suspend,
1156         .get_status = m8xx_get_status,
1157         .set_socket = m8xx_set_socket,
1158         .set_io_map = m8xx_set_io_map,
1159         .set_mem_map = m8xx_set_mem_map,
1160 };
1161
1162 static int __init m8xx_probe(struct of_device *ofdev,
1163                              const struct of_device_id *match)
1164 {
1165         struct pcmcia_win *w;
1166         unsigned int i, m, hwirq;
1167         pcmconf8xx_t *pcmcia;
1168         int status;
1169         struct device_node *np = ofdev->node;
1170
1171         pcmcia_info("%s\n", version);
1172
1173         pcmcia = of_iomap(np, 0);
1174         if (pcmcia == NULL)
1175                 return -EINVAL;
1176
1177         pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1178         hwirq = irq_map[pcmcia_schlvl].hwirq;
1179         if (pcmcia_schlvl < 0) {
1180                 iounmap(pcmcia);
1181                 return -EINVAL;
1182         }
1183
1184         m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1185         m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1186
1187         pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1188                     " with IRQ %u  (%d). \n", pcmcia_schlvl, hwirq);
1189
1190         /* Configure Status change interrupt */
1191
1192         if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1193                         driver_name, socket)) {
1194                 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1195                              pcmcia_schlvl);
1196                 iounmap(pcmcia);
1197                 return -1;
1198         }
1199
1200         w = (void *)&pcmcia->pcmc_pbr0;
1201
1202         out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1203         clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1204
1205         /* connect interrupt and disable CxOE */
1206
1207         out_be32(M8XX_PGCRX(0),
1208                  M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1209         out_be32(M8XX_PGCRX(1),
1210                  M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1211
1212         /* intialize the fixed memory windows */
1213
1214         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1215                 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1216                         out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1217                                  (PCMCIA_MEM_WIN_SIZE
1218                                   * (m + i * PCMCIA_MEM_WIN_NO)));
1219
1220                         out_be32(&w->or, 0);    /* set to not valid */
1221
1222                         w++;
1223                 }
1224         }
1225
1226         /* turn off voltage */
1227         voltage_set(0, 0, 0);
1228         voltage_set(1, 0, 0);
1229
1230         /* Enable external hardware */
1231         hardware_enable(0);
1232         hardware_enable(1);
1233
1234         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1235                 socket[i].slot = i;
1236                 socket[i].socket.owner = THIS_MODULE;
1237                 socket[i].socket.features =
1238                     SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1239                 socket[i].socket.irq_mask = 0x000;
1240                 socket[i].socket.map_size = 0x1000;
1241                 socket[i].socket.io_offset = 0;
1242                 socket[i].socket.pci_irq = pcmcia_schlvl;
1243                 socket[i].socket.ops = &m8xx_services;
1244                 socket[i].socket.resource_ops = &pccard_nonstatic_ops;
1245                 socket[i].socket.cb_dev = NULL;
1246                 socket[i].socket.dev.parent = &ofdev->dev;
1247                 socket[i].pcmcia = pcmcia;
1248                 socket[i].bus_freq = ppc_proc_freq;
1249                 socket[i].hwirq = hwirq;
1250
1251         }
1252
1253         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1254                 status = pcmcia_register_socket(&socket[i].socket);
1255                 if (status < 0)
1256                         pcmcia_error("Socket register failed\n");
1257         }
1258
1259         return 0;
1260 }
1261
1262 static int m8xx_remove(struct of_device *ofdev)
1263 {
1264         u32 m, i;
1265         struct pcmcia_win *w;
1266         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1267
1268         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1269                 w = (void *)&pcmcia->pcmc_pbr0;
1270
1271                 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1272                 out_be32(&pcmcia->pcmc_per,
1273                          in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1274
1275                 /* turn off interrupt and disable CxOE */
1276                 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1277
1278                 /* turn off memory windows */
1279                 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1280                         out_be32(&w->or, 0);    /* set to not valid */
1281                         w++;
1282                 }
1283
1284                 /* turn off voltage */
1285                 voltage_set(i, 0, 0);
1286
1287                 /* disable external hardware */
1288                 hardware_disable(i);
1289         }
1290         for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1291                 pcmcia_unregister_socket(&socket[i].socket);
1292         iounmap(pcmcia);
1293
1294         free_irq(pcmcia_schlvl, NULL);
1295
1296         return 0;
1297 }
1298
1299 #ifdef CONFIG_PM
1300 static int m8xx_suspend(struct platform_device *pdev, pm_message_t state)
1301 {
1302         return pcmcia_socket_dev_suspend(&pdev->dev);
1303 }
1304
1305 static int m8xx_resume(struct platform_device *pdev)
1306 {
1307         return pcmcia_socket_dev_resume(&pdev->dev);
1308 }
1309 #else
1310 #define m8xx_suspend NULL
1311 #define m8xx_resume NULL
1312 #endif
1313
1314 static struct of_device_id m8xx_pcmcia_match[] = {
1315         {
1316          .type = "pcmcia",
1317          .compatible = "fsl,pq-pcmcia",
1318          },
1319         {},
1320 };
1321
1322 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1323
1324 static struct of_platform_driver m8xx_pcmcia_driver = {
1325         .name = driver_name,
1326         .match_table = m8xx_pcmcia_match,
1327         .probe = m8xx_probe,
1328         .remove = m8xx_remove,
1329         .suspend = m8xx_suspend,
1330         .resume = m8xx_resume,
1331 };
1332
1333 static int __init m8xx_init(void)
1334 {
1335         return of_register_platform_driver(&m8xx_pcmcia_driver);
1336 }
1337
1338 static void __exit m8xx_exit(void)
1339 {
1340         of_unregister_platform_driver(&m8xx_pcmcia_driver);
1341 }
1342
1343 module_init(m8xx_init);
1344 module_exit(m8xx_exit);