arch/s390/include/asm/system.h

   1 /*
   2  * Copyright IBM Corp. 1999, 2009
   3  *
   4  * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
   5  */
   6
   7 #ifndef __ASM_SYSTEM_H
   8 #define __ASM_SYSTEM_H
   9
  10 #include <linux/kernel.h>
  11 #include <linux/errno.h>
  12 #include <asm/types.h>
  13 #include <asm/ptrace.h>
  14 #include <asm/setup.h>
  15 #include <asm/processor.h>
  16 #include <asm/lowcore.h>
  17
  18 #ifdef __KERNEL__
  19
  20 struct task_struct;
  21
  22 extern struct task_struct *__switch_to(void *, void *);
  23
  24 static inline void save_fp_regs(s390_fp_regs *fpregs)
  25 {
  26         asm volatile(
  27                 "       std     0,8(%1)\n"
  28                 "       std     2,24(%1)\n"
  29                 "       std     4,40(%1)\n"
  30                 "       std     6,56(%1)"
  31                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
  32         if (!MACHINE_HAS_IEEE)
  33                 return;
  34         asm volatile(
  35                 "       stfpc   0(%1)\n"
  36                 "       std     1,16(%1)\n"
  37                 "       std     3,32(%1)\n"
  38                 "       std     5,48(%1)\n"
  39                 "       std     7,64(%1)\n"
  40                 "       std     8,72(%1)\n"
  41                 "       std     9,80(%1)\n"
  42                 "       std     10,88(%1)\n"
  43                 "       std     11,96(%1)\n"
  44                 "       std     12,104(%1)\n"
  45                 "       std     13,112(%1)\n"
  46                 "       std     14,120(%1)\n"
  47                 "       std     15,128(%1)\n"
  48                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
  49 }
  50
  51 static inline void restore_fp_regs(s390_fp_regs *fpregs)
  52 {
  53         asm volatile(
  54                 "       ld      0,8(%0)\n"
  55                 "       ld      2,24(%0)\n"
  56                 "       ld      4,40(%0)\n"
  57                 "       ld      6,56(%0)"
  58                 : : "a" (fpregs), "m" (*fpregs));
  59         if (!MACHINE_HAS_IEEE)
  60                 return;
  61         asm volatile(
  62                 "       lfpc    0(%0)\n"
  63                 "       ld      1,16(%0)\n"
  64                 "       ld      3,32(%0)\n"
  65                 "       ld      5,48(%0)\n"
  66                 "       ld      7,64(%0)\n"
  67                 "       ld      8,72(%0)\n"
  68                 "       ld      9,80(%0)\n"
  69                 "       ld      10,88(%0)\n"
  70                 "       ld      11,96(%0)\n"
  71                 "       ld      12,104(%0)\n"
  72                 "       ld      13,112(%0)\n"
  73                 "       ld      14,120(%0)\n"
  74                 "       ld      15,128(%0)\n"
  75                 : : "a" (fpregs), "m" (*fpregs));
  76 }
  77
  78 static inline void save_access_regs(unsigned int *acrs)
  79 {
  80         asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
  81 }
  82
  83 static inline void restore_access_regs(unsigned int *acrs)
  84 {
  85         asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
  86 }
  87
  88 #define switch_to(prev,next,last) do {                                       \
  89         if (prev == next)                                                    \
  90                 break;                                                       \
  91         save_fp_regs(&prev->thread.fp_regs);                                 \
  92         restore_fp_regs(&next->thread.fp_regs);                              \
  93         save_access_regs(&prev->thread.acrs[0]);                             \
  94         restore_access_regs(&next->thread.acrs[0]);                          \
  95         prev = __switch_to(prev,next);                                       \
  96 } while (0)
  97
  98 extern void account_vtime(struct task_struct *, struct task_struct *);
  99 extern void account_tick_vtime(struct task_struct *);
 100
 101 #ifdef CONFIG_PFAULT
 102 extern void pfault_irq_init(void);
 103 extern int pfault_init(void);
 104 extern void pfault_fini(void);
 105 #else /* CONFIG_PFAULT */
 106 #define pfault_irq_init()       do { } while (0)
 107 #define pfault_init()           ({-1;})
 108 #define pfault_fini()           do { } while (0)
 109 #endif /* CONFIG_PFAULT */
 110
 111 extern void cmma_init(void);
 112
 113 #define finish_arch_switch(prev) do {                                        \
 114         set_fs(current->thread.mm_segment);                                  \
 115         account_vtime(prev, current);                                        \
 116 } while (0)
 117
 118 #define nop() asm volatile("nop")
 119
 120 #define xchg(ptr,x)                                                       \
 121 ({                                                                        \
 122         __typeof__(*(ptr)) __ret;                                         \
 123         __ret = (__typeof__(*(ptr)))                                      \
 124                 __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
 125         __ret;                                                            \
 126 })
 127
 128 extern void __xchg_called_with_bad_pointer(void);
 129
 130 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
 131 {
 132         unsigned long addr, old;
 133         int shift;
 134
 135         switch (size) {
 136         case 1:
 137                 addr = (unsigned long) ptr;
 138                 shift = (3 ^ (addr & 3)) << 3;
 139                 addr ^= addr & 3;
 140                 asm volatile(
 141                         "       l       %0,0(%4)\n"
 142                         "0:     lr      0,%0\n"
 143                         "       nr      0,%3\n"
 144                         "       or      0,%2\n"
 145                         "       cs      %0,0,0(%4)\n"
 146                         "       jl      0b\n"
 147                         : "=&d" (old), "=m" (*(int *) addr)
 148                         : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
 149                           "m" (*(int *) addr) : "memory", "cc", "0");
 150                 return old >> shift;
 151         case 2:
 152                 addr = (unsigned long) ptr;
 153                 shift = (2 ^ (addr & 2)) << 3;
 154                 addr ^= addr & 2;
 155                 asm volatile(
 156                         "       l       %0,0(%4)\n"
 157                         "0:     lr      0,%0\n"
 158                         "       nr      0,%3\n"
 159                         "       or      0,%2\n"
 160                         "       cs      %0,0,0(%4)\n"
 161                         "       jl      0b\n"
 162                         : "=&d" (old), "=m" (*(int *) addr)
 163                         : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
 164                           "m" (*(int *) addr) : "memory", "cc", "0");
 165                 return old >> shift;
 166         case 4:
 167                 asm volatile(
 168                         "       l       %0,0(%3)\n"
 169                         "0:     cs      %0,%2,0(%3)\n"
 170                         "       jl      0b\n"
 171                         : "=&d" (old), "=m" (*(int *) ptr)
 172                         : "d" (x), "a" (ptr), "m" (*(int *) ptr)
 173                         : "memory", "cc");
 174                 return old;
 175 #ifdef __s390x__
 176         case 8:
 177                 asm volatile(
 178                         "       lg      %0,0(%3)\n"
 179                         "0:     csg     %0,%2,0(%3)\n"
 180                         "       jl      0b\n"
 181                         : "=&d" (old), "=m" (*(long *) ptr)
 182                         : "d" (x), "a" (ptr), "m" (*(long *) ptr)
 183                         : "memory", "cc");
 184                 return old;
 185 #endif /* __s390x__ */
 186         }
 187         __xchg_called_with_bad_pointer();
 188         return x;
 189 }
 190
 191 /*
 192  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 193  * store NEW in MEM.  Return the initial value in MEM.  Success is
 194  * indicated by comparing RETURN with OLD.
 195  */
 196
 197 #define __HAVE_ARCH_CMPXCHG 1
 198
 199 #define cmpxchg(ptr, o, n)                                              \
 200         ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),       \
 201                                         (unsigned long)(n), sizeof(*(ptr))))
 202
 203 extern void __cmpxchg_called_with_bad_pointer(void);
 204
 205 static inline unsigned long
 206 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 207 {
 208         unsigned long addr, prev, tmp;
 209         int shift;
 210
 211         switch (size) {
 212         case 1:
 213                 addr = (unsigned long) ptr;
 214                 shift = (3 ^ (addr & 3)) << 3;
 215                 addr ^= addr & 3;
 216                 asm volatile(
 217                         "       l       %0,0(%4)\n"
 218                         "0:     nr      %0,%5\n"
 219                         "       lr      %1,%0\n"
 220                         "       or      %0,%2\n"
 221                         "       or      %1,%3\n"
 222                         "       cs      %0,%1,0(%4)\n"
 223                         "       jnl     1f\n"
 224                         "       xr      %1,%0\n"
 225                         "       nr      %1,%5\n"
 226                         "       jnz     0b\n"
 227                         "1:"
 228                         : "=&d" (prev), "=&d" (tmp)
 229                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 230                           "d" (~(255 << shift))
 231                         : "memory", "cc");
 232                 return prev >> shift;
 233         case 2:
 234                 addr = (unsigned long) ptr;
 235                 shift = (2 ^ (addr & 2)) << 3;
 236                 addr ^= addr & 2;
 237                 asm volatile(
 238                         "       l       %0,0(%4)\n"
 239                         "0:     nr      %0,%5\n"
 240                         "       lr      %1,%0\n"
 241                         "       or      %0,%2\n"
 242                         "       or      %1,%3\n"
 243                         "       cs      %0,%1,0(%4)\n"
 244                         "       jnl     1f\n"
 245                         "       xr      %1,%0\n"
 246                         "       nr      %1,%5\n"
 247                         "       jnz     0b\n"
 248                         "1:"
 249                         : "=&d" (prev), "=&d" (tmp)
 250                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 251                           "d" (~(65535 << shift))
 252                         : "memory", "cc");
 253                 return prev >> shift;
 254         case 4:
 255                 asm volatile(
 256                         "       cs      %0,%2,0(%3)\n"
 257                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 258                         : "memory", "cc");
 259                 return prev;
 260 #ifdef __s390x__
 261         case 8:
 262                 asm volatile(
 263                         "       csg     %0,%2,0(%3)\n"
 264                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 265                         : "memory", "cc");
 266                 return prev;
 267 #endif /* __s390x__ */
 268         }
 269         __cmpxchg_called_with_bad_pointer();
 270         return old;
 271 }
 272
 273 /*
 274  * Force strict CPU ordering.
 275  * And yes, this is required on UP too when we're talking
 276  * to devices.
 277  *
 278  * This is very similar to the ppc eieio/sync instruction in that is
 279  * does a checkpoint syncronisation & makes sure that
 280  * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 281  */
 282
 283 #define eieio() asm volatile("bcr 15,0" : : : "memory")
 284 #define SYNC_OTHER_CORES(x)   eieio()
 285 #define mb()    eieio()
 286 #define rmb()   eieio()
 287 #define wmb()   eieio()
 288 #define read_barrier_depends() do { } while(0)
 289 #define smp_mb()       mb()
 290 #define smp_rmb()      rmb()
 291 #define smp_wmb()      wmb()
 292 #define smp_read_barrier_depends()    read_barrier_depends()
 293 #define smp_mb__before_clear_bit()     smp_mb()
 294 #define smp_mb__after_clear_bit()      smp_mb()
 295
 296
 297 #define set_mb(var, value)      do { var = value; mb(); } while (0)
 298
 299 #ifdef __s390x__
 300
 301 #define __ctl_load(array, low, high) ({                         \
 302         typedef struct { char _[sizeof(array)]; } addrtype;     \
 303         asm volatile(                                           \
 304                 "       lctlg   %1,%2,0(%0)\n"                  \
 305                 : : "a" (&array), "i" (low), "i" (high),        \
 306                     "m" (*(addrtype *)(&array)));               \
 307         })
 308
 309 #define __ctl_store(array, low, high) ({                        \
 310         typedef struct { char _[sizeof(array)]; } addrtype;     \
 311         asm volatile(                                           \
 312                 "       stctg   %2,%3,0(%1)\n"                  \
 313                 : "=m" (*(addrtype *)(&array))                  \
 314                 : "a" (&array), "i" (low), "i" (high));         \
 315         })
 316
 317 #else /* __s390x__ */
 318
 319 #define __ctl_load(array, low, high) ({                         \
 320         typedef struct { char _[sizeof(array)]; } addrtype;     \
 321         asm volatile(                                           \
 322                 "       lctl    %1,%2,0(%0)\n"                  \
 323                 : : "a" (&array), "i" (low), "i" (high),        \
 324                     "m" (*(addrtype *)(&array)));               \
 325 })
 326
 327 #define __ctl_store(array, low, high) ({                        \
 328         typedef struct { char _[sizeof(array)]; } addrtype;     \
 329         asm volatile(                                           \
 330                 "       stctl   %2,%3,0(%1)\n"                  \
 331                 : "=m" (*(addrtype *)(&array))                  \
 332                 : "a" (&array), "i" (low), "i" (high));         \
 333         })
 334
 335 #endif /* __s390x__ */
 336
 337 #define __ctl_set_bit(cr, bit) ({       \
 338         unsigned long __dummy;          \
 339         __ctl_store(__dummy, cr, cr);   \
 340         __dummy |= 1UL << (bit);        \
 341         __ctl_load(__dummy, cr, cr);    \
 342 })
 343
 344 #define __ctl_clear_bit(cr, bit) ({     \
 345         unsigned long __dummy;          \
 346         __ctl_store(__dummy, cr, cr);   \
 347         __dummy &= ~(1UL << (bit));     \
 348         __ctl_load(__dummy, cr, cr);    \
 349 })
 350
 351 #include <linux/irqflags.h>
 352
 353 #include <asm-generic/cmpxchg-local.h>
 354
 355 static inline unsigned long __cmpxchg_local(volatile void *ptr,
 356                                       unsigned long old,
 357                                       unsigned long new, int size)
 358 {
 359         switch (size) {
 360         case 1:
 361         case 2:
 362         case 4:
 363 #ifdef __s390x__
 364         case 8:
 365 #endif
 366                 return __cmpxchg(ptr, old, new, size);
 367         default:
 368                 return __cmpxchg_local_generic(ptr, old, new, size);
 369         }
 370
 371         return old;
 372 }
 373
 374 /*
 375  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 376  * them available.
 377  */
 378 #define cmpxchg_local(ptr, o, n)                                        \
 379         ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
 380                         (unsigned long)(n), sizeof(*(ptr))))
 381 #ifdef __s390x__
 382 #define cmpxchg64_local(ptr, o, n)                                      \
 383   ({                                                                    \
 384         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 385         cmpxchg_local((ptr), (o), (n));                                 \
 386   })
 387 #else
 388 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 389 #endif
 390
 391 /*
 392  * Use to set psw mask except for the first byte which
 393  * won't be changed by this function.
 394  */
 395 static inline void
 396 __set_psw_mask(unsigned long mask)
 397 {
 398         __load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
 399 }
 400
 401 #define local_mcck_enable()  __set_psw_mask(psw_kernel_bits)
 402 #define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
 403
 404 #ifdef CONFIG_SMP
 405
 406 extern void smp_ctl_set_bit(int cr, int bit);
 407 extern void smp_ctl_clear_bit(int cr, int bit);
 408 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
 409 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
 410
 411 #else
 412
 413 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
 414 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
 415
 416 #endif /* CONFIG_SMP */
 417
 418 static inline unsigned int stfl(void)
 419 {
 420         asm volatile(
 421                 "       .insn   s,0xb2b10000,0(0)\n" /* stfl */
 422                 "0:\n"
 423                 EX_TABLE(0b,0b));
 424         return S390_lowcore.stfl_fac_list;
 425 }
 426
 427 static inline int __stfle(unsigned long long *list, int doublewords)
 428 {
 429         typedef struct { unsigned long long _[doublewords]; } addrtype;
 430         register unsigned long __nr asm("0") = doublewords - 1;
 431
 432         asm volatile(".insn s,0xb2b00000,%0" /* stfle */
 433                      : "=m" (*(addrtype *) list), "+d" (__nr) : : "cc");
 434         return __nr + 1;
 435 }
 436
 437 static inline int stfle(unsigned long long *list, int doublewords)
 438 {
 439         if (!(stfl() & (1UL << 24)))
 440                 return -EOPNOTSUPP;
 441         return __stfle(list, doublewords);
 442 }
 443
 444 static inline unsigned short stap(void)
 445 {
 446         unsigned short cpu_address;
 447
 448         asm volatile("stap %0" : "=m" (cpu_address));
 449         return cpu_address;
 450 }
 451
 452 extern void (*_machine_restart)(char *command);
 453 extern void (*_machine_halt)(void);
 454 extern void (*_machine_power_off)(void);
 455
 456 #define arch_align_stack(x) (x)
 457
 458 #ifdef CONFIG_TRACE_IRQFLAGS
 459 extern psw_t sysc_restore_trace_psw;
 460 extern psw_t io_restore_trace_psw;
 461 #endif
 462
 463 static inline int tprot(unsigned long addr)
 464 {
 465         int rc = -EFAULT;
 466
 467         asm volatile(
 468                 "       tprot   0(%1),0\n"
 469                 "0:     ipm     %0\n"
 470                 "       srl     %0,28\n"
 471                 "1:\n"
 472                 EX_TABLE(0b,1b)
 473                 : "+d" (rc) : "a" (addr) : "cc");
 474         return rc;
 475 }
 476
 477 #endif /* __KERNEL__ */
 478
 479 #endif