arch/arm/include/asm/ptrace.h

   1 /*
   2  *  arch/arm/include/asm/ptrace.h
   3  *
   4  *  Copyright (C) 1996-2003 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef __ASM_ARM_PTRACE_H
  11 #define __ASM_ARM_PTRACE_H
  12
  13 #include <asm/hwcap.h>
  14
  15 #define PTRACE_GETREGS          12
  16 #define PTRACE_SETREGS          13
  17 #define PTRACE_GETFPREGS        14
  18 #define PTRACE_SETFPREGS        15
  19 /* PTRACE_ATTACH is 16 */
  20 /* PTRACE_DETACH is 17 */
  21 #define PTRACE_GETWMMXREGS      18
  22 #define PTRACE_SETWMMXREGS      19
  23 /* 20 is unused */
  24 #define PTRACE_OLDSETOPTIONS    21
  25 #define PTRACE_GET_THREAD_AREA  22
  26 #define PTRACE_SET_SYSCALL      23
  27 /* PTRACE_SYSCALL is 24 */
  28 #define PTRACE_GETCRUNCHREGS    25
  29 #define PTRACE_SETCRUNCHREGS    26
  30 #define PTRACE_GETVFPREGS       27
  31 #define PTRACE_SETVFPREGS       28
  32 #define PTRACE_GETHBPREGS       29
  33 #define PTRACE_SETHBPREGS       30
  34
  35 /*
  36  * PSR bits
  37  */
  38 #define USR26_MODE      0x00000000
  39 #define FIQ26_MODE      0x00000001
  40 #define IRQ26_MODE      0x00000002
  41 #define SVC26_MODE      0x00000003
  42 #define USR_MODE        0x00000010
  43 #define FIQ_MODE        0x00000011
  44 #define IRQ_MODE        0x00000012
  45 #define SVC_MODE        0x00000013
  46 #define ABT_MODE        0x00000017
  47 #define UND_MODE        0x0000001b
  48 #define SYSTEM_MODE     0x0000001f
  49 #define MODE32_BIT      0x00000010
  50 #define MODE_MASK       0x0000001f
  51 #define PSR_T_BIT       0x00000020
  52 #define PSR_F_BIT       0x00000040
  53 #define PSR_I_BIT       0x00000080
  54 #define PSR_A_BIT       0x00000100
  55 #define PSR_E_BIT       0x00000200
  56 #define PSR_J_BIT       0x01000000
  57 #define PSR_Q_BIT       0x08000000
  58 #define PSR_V_BIT       0x10000000
  59 #define PSR_C_BIT       0x20000000
  60 #define PSR_Z_BIT       0x40000000
  61 #define PSR_N_BIT       0x80000000
  62
  63 /*
  64  * Groups of PSR bits
  65  */
  66 #define PSR_f           0xff000000      /* Flags                */
  67 #define PSR_s           0x00ff0000      /* Status               */
  68 #define PSR_x           0x0000ff00      /* Extension            */
  69 #define PSR_c           0x000000ff      /* Control              */
  70
  71 /*
  72  * ARMv7 groups of APSR bits
  73  */
  74 #define PSR_ISET_MASK   0x01000010      /* ISA state (J, T) mask */
  75 #define PSR_IT_MASK     0x0600fc00      /* If-Then execution state mask */
  76 #define PSR_ENDIAN_MASK 0x00000200      /* Endianness state mask */
  77
  78 /*
  79  * Default endianness state
  80  */
  81 #ifdef CONFIG_CPU_ENDIAN_BE8
  82 #define PSR_ENDSTATE    PSR_E_BIT
  83 #else
  84 #define PSR_ENDSTATE    0
  85 #endif
  86
  87 /*
  88  * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
  89  * process is located in memory.
  90  */
  91 #define PT_TEXT_ADDR            0x10000
  92 #define PT_DATA_ADDR            0x10004
  93 #define PT_TEXT_END_ADDR        0x10008
  94
  95 #ifndef __ASSEMBLY__
  96
  97 /*
  98  * This struct defines the way the registers are stored on the
  99  * stack during a system call.  Note that sizeof(struct pt_regs)
 100  * has to be a multiple of 8.
 101  */
 102 #ifndef __KERNEL__
 103 struct pt_regs {
 104         long uregs[18];
 105 };
 106 #else /* __KERNEL__ */
 107 struct pt_regs {
 108         unsigned long uregs[18];
 109 };
 110 #endif /* __KERNEL__ */
 111
 112 #define ARM_cpsr        uregs[16]
 113 #define ARM_pc          uregs[15]
 114 #define ARM_lr          uregs[14]
 115 #define ARM_sp          uregs[13]
 116 #define ARM_ip          uregs[12]
 117 #define ARM_fp          uregs[11]
 118 #define ARM_r10         uregs[10]
 119 #define ARM_r9          uregs[9]
 120 #define ARM_r8          uregs[8]
 121 #define ARM_r7          uregs[7]
 122 #define ARM_r6          uregs[6]
 123 #define ARM_r5          uregs[5]
 124 #define ARM_r4          uregs[4]
 125 #define ARM_r3          uregs[3]
 126 #define ARM_r2          uregs[2]
 127 #define ARM_r1          uregs[1]
 128 #define ARM_r0          uregs[0]
 129 #define ARM_ORIG_r0     uregs[17]
 130
 131 #ifdef __KERNEL__
 132
 133 #define arch_has_single_step()  (1)
 134
 135 #define user_mode(regs) \
 136         (((regs)->ARM_cpsr & 0xf) == 0)
 137
 138 #ifdef CONFIG_ARM_THUMB
 139 #define thumb_mode(regs) \
 140         (((regs)->ARM_cpsr & PSR_T_BIT))
 141 #else
 142 #define thumb_mode(regs) (0)
 143 #endif
 144
 145 #define isa_mode(regs) \
 146         ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
 147          (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
 148
 149 #define processor_mode(regs) \
 150         ((regs)->ARM_cpsr & MODE_MASK)
 151
 152 #define interrupts_enabled(regs) \
 153         (!((regs)->ARM_cpsr & PSR_I_BIT))
 154
 155 #define fast_interrupts_enabled(regs) \
 156         (!((regs)->ARM_cpsr & PSR_F_BIT))
 157
 158 /* Are the current registers suitable for user mode?
 159  * (used to maintain security in signal handlers)
 160  */
 161 static inline int valid_user_regs(struct pt_regs *regs)
 162 {
 163         unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 164
 165         /*
 166          * Always clear the F (FIQ) and A (delayed abort) bits
 167          */
 168         regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
 169
 170         if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
 171                 if (mode == USR_MODE)
 172                         return 1;
 173                 if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
 174                         return 1;
 175         }
 176
 177         /*
 178          * Force CPSR to something logical...
 179          */
 180         regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
 181         if (!(elf_hwcap & HWCAP_26BIT))
 182                 regs->ARM_cpsr |= USR_MODE;
 183
 184         return 0;
 185 }
 186
 187 #define instruction_pointer(regs)       (regs)->ARM_pc
 188
 189 #ifdef CONFIG_SMP
 190 extern unsigned long profile_pc(struct pt_regs *regs);
 191 #else
 192 #define profile_pc(regs) instruction_pointer(regs)
 193 #endif
 194
 195 #define predicate(x)            ((x) & 0xf0000000)
 196 #define PREDICATE_ALWAYS        0xe0000000
 197
 198 /*
 199  * kprobe-based event tracer support
 200  */
 201 #include <linux/stddef.h>
 202 #include <linux/types.h>
 203 #define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
 204
 205 extern int regs_query_register_offset(const char *name);
 206 extern const char *regs_query_register_name(unsigned int offset);
 207 extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
 208 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
 209                                                unsigned int n);
 210
 211 /**
 212  * regs_get_register() - get register value from its offset
 213  * @regs:          pt_regs from which register value is gotten
 214  * @offset:    offset number of the register.
 215  *
 216  * regs_get_register returns the value of a register whose offset from @regs.
 217  * The @offset is the offset of the register in struct pt_regs.
 218  * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
 219  */
 220 static inline unsigned long regs_get_register(struct pt_regs *regs,
 221                                               unsigned int offset)
 222 {
 223         if (unlikely(offset > MAX_REG_OFFSET))
 224                 return 0;
 225         return *(unsigned long *)((unsigned long)regs + offset);
 226 }
 227
 228 /* Valid only for Kernel mode traps. */
 229 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
 230 {
 231         return regs->ARM_sp;
 232 }
 233
 234 #endif /* __KERNEL__ */
 235
 236 #endif /* __ASSEMBLY__ */
 237
 238 #endif
 239