drivers/net/wireless/ath/ath9k/hw.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef HW_H
  18 #define HW_H
  19
  20 #include <linux/if_ether.h>
  21 #include <linux/delay.h>
  22 #include <linux/io.h>
  23
  24 #include "mac.h"
  25 #include "ani.h"
  26 #include "eeprom.h"
  27 #include "calib.h"
  28 #include "reg.h"
  29 #include "phy.h"
  30 #include "btcoex.h"
  31
  32 #include "../regd.h"
  33
  34 #define ATHEROS_VENDOR_ID       0x168c
  35
  36 #define AR5416_DEVID_PCI        0x0023
  37 #define AR5416_DEVID_PCIE       0x0024
  38 #define AR9160_DEVID_PCI        0x0027
  39 #define AR9280_DEVID_PCI        0x0029
  40 #define AR9280_DEVID_PCIE       0x002a
  41 #define AR9285_DEVID_PCIE       0x002b
  42 #define AR2427_DEVID_PCIE       0x002c
  43 #define AR9287_DEVID_PCI        0x002d
  44 #define AR9287_DEVID_PCIE       0x002e
  45 #define AR9300_DEVID_PCIE       0x0030
  46 #define AR9300_DEVID_AR9340     0x0031
  47 #define AR9300_DEVID_AR9485_PCIE 0x0032
  48 #define AR9300_DEVID_AR9330     0x0035
  49
  50 #define AR5416_AR9100_DEVID     0x000b
  51
  52 #define AR_SUBVENDOR_ID_NOG     0x0e11
  53 #define AR_SUBVENDOR_ID_NEW_A   0x7065
  54 #define AR5416_MAGIC            0x19641014
  55
  56 #define AR9280_COEX2WIRE_SUBSYSID       0x309b
  57 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
  58 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
  59
  60 #define AR9300_NUM_BT_WEIGHTS   4
  61 #define AR9300_NUM_WLAN_WEIGHTS 4
  62
  63 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
  64
  65 #define ATH_DEFAULT_NOISE_FLOOR -95
  66
  67 #define ATH9K_RSSI_BAD                  -128
  68
  69 #define ATH9K_NUM_CHANNELS      38
  70
  71 /* Register read/write primitives */
  72 #define REG_WRITE(_ah, _reg, _val) \
  73         (_ah)->reg_ops.write((_ah), (_val), (_reg))
  74
  75 #define REG_READ(_ah, _reg) \
  76         (_ah)->reg_ops.read((_ah), (_reg))
  77
  78 #define REG_READ_MULTI(_ah, _addr, _val, _cnt)          \
  79         (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
  80
  81 #define REG_RMW(_ah, _reg, _set, _clr) \
  82         (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
  83
  84 #define ENABLE_REGWRITE_BUFFER(_ah)                                     \
  85         do {                                                            \
  86                 if ((_ah)->reg_ops.enable_write_buffer) \
  87                         (_ah)->reg_ops.enable_write_buffer((_ah)); \
  88         } while (0)
  89
  90 #define REGWRITE_BUFFER_FLUSH(_ah)                                      \
  91         do {                                                            \
  92                 if ((_ah)->reg_ops.write_flush)         \
  93                         (_ah)->reg_ops.write_flush((_ah));      \
  94         } while (0)
  95
  96 #define PR_EEP(_s, _val)                                                \
  97         do {                                                            \
  98                 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
  99                                 _s, (_val));                            \
 100         } while (0)
 101
 102 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 103 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
 104 #define REG_RMW_FIELD(_a, _r, _f, _v) \
 105         REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
 106 #define REG_READ_FIELD(_a, _r, _f) \
 107         (((REG_READ(_a, _r) & _f) >> _f##_S))
 108 #define REG_SET_BIT(_a, _r, _f) \
 109         REG_RMW(_a, _r, (_f), 0)
 110 #define REG_CLR_BIT(_a, _r, _f) \
 111         REG_RMW(_a, _r, 0, (_f))
 112
 113 #define DO_DELAY(x) do {                                        \
 114                 if (((++(x) % 64) == 0) &&                      \
 115                     (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
 116                         != ATH_USB))                            \
 117                         udelay(1);                              \
 118         } while (0)
 119
 120 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
 121         ath9k_hw_write_array(ah, iniarray, column, &(regWr))
 122
 123 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
 124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
 125 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
 126 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
 127 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
 128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
 129 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
 130
 131 #define AR_GPIOD_MASK               0x00001FFF
 132 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
 133
 134 #define BASE_ACTIVATE_DELAY         100
 135 #define RTC_PLL_SETTLE_DELAY        (AR_SREV_9340(ah) ? 1000 : 100)
 136 #define COEF_SCALE_S                24
 137 #define HT40_CHANNEL_CENTER_SHIFT   10
 138
 139 #define ATH9K_ANTENNA0_CHAINMASK    0x1
 140 #define ATH9K_ANTENNA1_CHAINMASK    0x2
 141
 142 #define ATH9K_NUM_DMA_DEBUG_REGS    8
 143 #define ATH9K_NUM_QUEUES            10
 144
 145 #define MAX_RATE_POWER              63
 146 #define AH_WAIT_TIMEOUT             100000 /* (us) */
 147 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
 148 #define AH_TIME_QUANTUM             10
 149 #define AR_KEYTABLE_SIZE            128
 150 #define POWER_UP_TIME               10000
 151 #define SPUR_RSSI_THRESH            40
 152 #define UPPER_5G_SUB_BAND_START         5700
 153 #define MID_5G_SUB_BAND_START           5400
 154
 155 #define CAB_TIMEOUT_VAL             10
 156 #define BEACON_TIMEOUT_VAL          10
 157 #define MIN_BEACON_TIMEOUT_VAL      1
 158 #define SLEEP_SLOP                  3
 159
 160 #define INIT_CONFIG_STATUS          0x00000000
 161 #define INIT_RSSI_THR               0x00000700
 162 #define INIT_BCON_CNTRL_REG         0x00000000
 163
 164 #define TU_TO_USEC(_tu)             ((_tu) << 10)
 165
 166 #define ATH9K_HW_RX_HP_QDEPTH   16
 167 #define ATH9K_HW_RX_LP_QDEPTH   128
 168
 169 #define PAPRD_GAIN_TABLE_ENTRIES        32
 170 #define PAPRD_TABLE_SZ                  24
 171 #define PAPRD_IDEAL_AGC2_PWR_RANGE      0xe0
 172
 173 enum ath_hw_txq_subtype {
 174         ATH_TXQ_AC_BE = 0,
 175         ATH_TXQ_AC_BK = 1,
 176         ATH_TXQ_AC_VI = 2,
 177         ATH_TXQ_AC_VO = 3,
 178 };
 179
 180 enum ath_ini_subsys {
 181         ATH_INI_PRE = 0,
 182         ATH_INI_CORE,
 183         ATH_INI_POST,
 184         ATH_INI_NUM_SPLIT,
 185 };
 186
 187 enum ath9k_hw_caps {
 188         ATH9K_HW_CAP_HT                         = BIT(0),
 189         ATH9K_HW_CAP_RFSILENT                   = BIT(1),
 190         ATH9K_HW_CAP_CST                        = BIT(2),
 191         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),
 192         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),
 193         ATH9K_HW_CAP_EDMA                       = BIT(6),
 194         ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(7),
 195         ATH9K_HW_CAP_LDPC                       = BIT(8),
 196         ATH9K_HW_CAP_FASTCLOCK                  = BIT(9),
 197         ATH9K_HW_CAP_SGI_20                     = BIT(10),
 198         ATH9K_HW_CAP_PAPRD                      = BIT(11),
 199         ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(12),
 200         ATH9K_HW_CAP_2GHZ                       = BIT(13),
 201         ATH9K_HW_CAP_5GHZ                       = BIT(14),
 202         ATH9K_HW_CAP_APM                        = BIT(15),
 203 };
 204
 205 struct ath9k_hw_capabilities {
 206         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 207         u16 rts_aggr_limit;
 208         u8 tx_chainmask;
 209         u8 rx_chainmask;
 210         u8 max_txchains;
 211         u8 max_rxchains;
 212         u8 num_gpio_pins;
 213         u8 rx_hp_qdepth;
 214         u8 rx_lp_qdepth;
 215         u8 rx_status_len;
 216         u8 tx_desc_len;
 217         u8 txs_len;
 218         u16 pcie_lcr_offset;
 219         bool pcie_lcr_extsync_en;
 220 };
 221
 222 struct ath9k_ops_config {
 223         int dma_beacon_response_time;
 224         int sw_beacon_response_time;
 225         int additional_swba_backoff;
 226         int ack_6mb;
 227         u32 cwm_ignore_extcca;
 228         bool pcieSerDesWrite;
 229         u8 pcie_clock_req;
 230         u32 pcie_waen;
 231         u8 analog_shiftreg;
 232         u8 paprd_disable;
 233         u32 ofdm_trig_low;
 234         u32 ofdm_trig_high;
 235         u32 cck_trig_high;
 236         u32 cck_trig_low;
 237         u32 enable_ani;
 238         int serialize_regmode;
 239         bool rx_intr_mitigation;
 240         bool tx_intr_mitigation;
 241 #define SPUR_DISABLE            0
 242 #define SPUR_ENABLE_IOCTL       1
 243 #define SPUR_ENABLE_EEPROM      2
 244 #define AR_SPUR_5413_1          1640
 245 #define AR_SPUR_5413_2          1200
 246 #define AR_NO_SPUR              0x8000
 247 #define AR_BASE_FREQ_2GHZ       2300
 248 #define AR_BASE_FREQ_5GHZ       4900
 249 #define AR_SPUR_FEEQ_BOUND_HT40 19
 250 #define AR_SPUR_FEEQ_BOUND_HT20 10
 251         int spurmode;
 252         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
 253         u8 max_txtrig_level;
 254         u16 ani_poll_interval; /* ANI poll interval in ms */
 255 };
 256
 257 enum ath9k_int {
 258         ATH9K_INT_RX = 0x00000001,
 259         ATH9K_INT_RXDESC = 0x00000002,
 260         ATH9K_INT_RXHP = 0x00000001,
 261         ATH9K_INT_RXLP = 0x00000002,
 262         ATH9K_INT_RXNOFRM = 0x00000008,
 263         ATH9K_INT_RXEOL = 0x00000010,
 264         ATH9K_INT_RXORN = 0x00000020,
 265         ATH9K_INT_TX = 0x00000040,
 266         ATH9K_INT_TXDESC = 0x00000080,
 267         ATH9K_INT_TIM_TIMER = 0x00000100,
 268         ATH9K_INT_BB_WATCHDOG = 0x00000400,
 269         ATH9K_INT_TXURN = 0x00000800,
 270         ATH9K_INT_MIB = 0x00001000,
 271         ATH9K_INT_RXPHY = 0x00004000,
 272         ATH9K_INT_RXKCM = 0x00008000,
 273         ATH9K_INT_SWBA = 0x00010000,
 274         ATH9K_INT_BMISS = 0x00040000,
 275         ATH9K_INT_BNR = 0x00100000,
 276         ATH9K_INT_TIM = 0x00200000,
 277         ATH9K_INT_DTIM = 0x00400000,
 278         ATH9K_INT_DTIMSYNC = 0x00800000,
 279         ATH9K_INT_GPIO = 0x01000000,
 280         ATH9K_INT_CABEND = 0x02000000,
 281         ATH9K_INT_TSFOOR = 0x04000000,
 282         ATH9K_INT_GENTIMER = 0x08000000,
 283         ATH9K_INT_CST = 0x10000000,
 284         ATH9K_INT_GTT = 0x20000000,
 285         ATH9K_INT_FATAL = 0x40000000,
 286         ATH9K_INT_GLOBAL = 0x80000000,
 287         ATH9K_INT_BMISC = ATH9K_INT_TIM |
 288                 ATH9K_INT_DTIM |
 289                 ATH9K_INT_DTIMSYNC |
 290                 ATH9K_INT_TSFOOR |
 291                 ATH9K_INT_CABEND,
 292         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
 293                 ATH9K_INT_RXDESC |
 294                 ATH9K_INT_RXEOL |
 295                 ATH9K_INT_RXORN |
 296                 ATH9K_INT_TXURN |
 297                 ATH9K_INT_TXDESC |
 298                 ATH9K_INT_MIB |
 299                 ATH9K_INT_RXPHY |
 300                 ATH9K_INT_RXKCM |
 301                 ATH9K_INT_SWBA |
 302                 ATH9K_INT_BMISS |
 303                 ATH9K_INT_GPIO,
 304         ATH9K_INT_NOCARD = 0xffffffff
 305 };
 306
 307 #define CHANNEL_CW_INT    0x00002
 308 #define CHANNEL_CCK       0x00020
 309 #define CHANNEL_OFDM      0x00040
 310 #define CHANNEL_2GHZ      0x00080
 311 #define CHANNEL_5GHZ      0x00100
 312 #define CHANNEL_PASSIVE   0x00200
 313 #define CHANNEL_DYN       0x00400
 314 #define CHANNEL_HALF      0x04000
 315 #define CHANNEL_QUARTER   0x08000
 316 #define CHANNEL_HT20      0x10000
 317 #define CHANNEL_HT40PLUS  0x20000
 318 #define CHANNEL_HT40MINUS 0x40000
 319
 320 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 321 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
 322 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 323 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 324 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
 325 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 326 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 327 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 328 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 329 #define CHANNEL_ALL                             \
 330         (CHANNEL_OFDM|                          \
 331          CHANNEL_CCK|                           \
 332          CHANNEL_2GHZ |                         \
 333          CHANNEL_5GHZ |                         \
 334          CHANNEL_HT20 |                         \
 335          CHANNEL_HT40PLUS |                     \
 336          CHANNEL_HT40MINUS)
 337
 338 struct ath9k_hw_cal_data {
 339         u16 channel;
 340         u32 channelFlags;
 341         int32_t CalValid;
 342         int8_t iCoff;
 343         int8_t qCoff;
 344         bool paprd_done;
 345         bool nfcal_pending;
 346         bool nfcal_interference;
 347         u16 small_signal_gain[AR9300_MAX_CHAINS];
 348         u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
 349         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 350 };
 351
 352 struct ath9k_channel {
 353         struct ieee80211_channel *chan;
 354         struct ar5416AniState ani;
 355         u16 channel;
 356         u32 channelFlags;
 357         u32 chanmode;
 358         s16 noisefloor;
 359 };
 360
 361 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
 362        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
 363        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
 364        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
 365 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 366 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 367 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 368 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 369 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 370 #define IS_CHAN_A_FAST_CLOCK(_ah, _c)                   \
 371         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
 372          ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
 373
 374 /* These macros check chanmode and not channelFlags */
 375 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
 376 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
 377                           ((_c)->chanmode == CHANNEL_G_HT20))
 378 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
 379                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
 380                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
 381                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 382 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 383
 384 enum ath9k_power_mode {
 385         ATH9K_PM_AWAKE = 0,
 386         ATH9K_PM_FULL_SLEEP,
 387         ATH9K_PM_NETWORK_SLEEP,
 388         ATH9K_PM_UNDEFINED
 389 };
 390
 391 enum ath9k_tp_scale {
 392         ATH9K_TP_SCALE_MAX = 0,
 393         ATH9K_TP_SCALE_50,
 394         ATH9K_TP_SCALE_25,
 395         ATH9K_TP_SCALE_12,
 396         ATH9K_TP_SCALE_MIN
 397 };
 398
 399 enum ser_reg_mode {
 400         SER_REG_MODE_OFF = 0,
 401         SER_REG_MODE_ON = 1,
 402         SER_REG_MODE_AUTO = 2,
 403 };
 404
 405 enum ath9k_rx_qtype {
 406         ATH9K_RX_QUEUE_HP,
 407         ATH9K_RX_QUEUE_LP,
 408         ATH9K_RX_QUEUE_MAX,
 409 };
 410
 411 struct ath9k_beacon_state {
 412         u32 bs_nexttbtt;
 413         u32 bs_nextdtim;
 414         u32 bs_intval;
 415 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
 416         u32 bs_dtimperiod;
 417         u16 bs_cfpperiod;
 418         u16 bs_cfpmaxduration;
 419         u32 bs_cfpnext;
 420         u16 bs_timoffset;
 421         u16 bs_bmissthreshold;
 422         u32 bs_sleepduration;
 423         u32 bs_tsfoor_threshold;
 424 };
 425
 426 struct chan_centers {
 427         u16 synth_center;
 428         u16 ctl_center;
 429         u16 ext_center;
 430 };
 431
 432 enum {
 433         ATH9K_RESET_POWER_ON,
 434         ATH9K_RESET_WARM,
 435         ATH9K_RESET_COLD,
 436 };
 437
 438 struct ath9k_hw_version {
 439         u32 magic;
 440         u16 devid;
 441         u16 subvendorid;
 442         u32 macVersion;
 443         u16 macRev;
 444         u16 phyRev;
 445         u16 analog5GhzRev;
 446         u16 analog2GhzRev;
 447         enum ath_usb_dev usbdev;
 448 };
 449
 450 /* Generic TSF timer definitions */
 451
 452 #define ATH_MAX_GEN_TIMER       16
 453
 454 #define AR_GENTMR_BIT(_index)   (1 << (_index))
 455
 456 /*
 457  * Using de Bruijin sequence to look up 1's index in a 32 bit number
 458  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
 459  */
 460 #define debruijn32 0x077CB531U
 461
 462 struct ath_gen_timer_configuration {
 463         u32 next_addr;
 464         u32 period_addr;
 465         u32 mode_addr;
 466         u32 mode_mask;
 467 };
 468
 469 struct ath_gen_timer {
 470         void (*trigger)(void *arg);
 471         void (*overflow)(void *arg);
 472         void *arg;
 473         u8 index;
 474 };
 475
 476 struct ath_gen_timer_table {
 477         u32 gen_timer_index[32];
 478         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
 479         union {
 480                 unsigned long timer_bits;
 481                 u16 val;
 482         } timer_mask;
 483 };
 484
 485 struct ath_hw_antcomb_conf {
 486         u8 main_lna_conf;
 487         u8 alt_lna_conf;
 488         u8 fast_div_bias;
 489         u8 main_gaintb;
 490         u8 alt_gaintb;
 491         int lna1_lna2_delta;
 492         u8 div_group;
 493 };
 494
 495 /**
 496  * struct ath_hw_radar_conf - radar detection initialization parameters
 497  *
 498  * @pulse_inband: threshold for checking the ratio of in-band power
 499  *      to total power for short radar pulses (half dB steps)
 500  * @pulse_inband_step: threshold for checking an in-band power to total
 501  *      power ratio increase for short radar pulses (half dB steps)
 502  * @pulse_height: threshold for detecting the beginning of a short
 503  *      radar pulse (dB step)
 504  * @pulse_rssi: threshold for detecting if a short radar pulse is
 505  *      gone (dB step)
 506  * @pulse_maxlen: maximum pulse length (0.8 us steps)
 507  *
 508  * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
 509  * @radar_inband: threshold for checking the ratio of in-band power
 510  *      to total power for long radar pulses (half dB steps)
 511  * @fir_power: threshold for detecting the end of a long radar pulse (dB)
 512  *
 513  * @ext_channel: enable extension channel radar detection
 514  */
 515 struct ath_hw_radar_conf {
 516         unsigned int pulse_inband;
 517         unsigned int pulse_inband_step;
 518         unsigned int pulse_height;
 519         unsigned int pulse_rssi;
 520         unsigned int pulse_maxlen;
 521
 522         unsigned int radar_rssi;
 523         unsigned int radar_inband;
 524         int fir_power;
 525
 526         bool ext_channel;
 527 };
 528
 529 /**
 530  * struct ath_hw_private_ops - callbacks used internally by hardware code
 531  *
 532  * This structure contains private callbacks designed to only be used internally
 533  * by the hardware core.
 534  *
 535  * @init_cal_settings: setup types of calibrations supported
 536  * @init_cal: starts actual calibration
 537  *
 538  * @init_mode_regs: Initializes mode registers
 539  * @init_mode_gain_regs: Initialize TX/RX gain registers
 540  *
 541  * @rf_set_freq: change frequency
 542  * @spur_mitigate_freq: spur mitigation
 543  * @rf_alloc_ext_banks:
 544  * @rf_free_ext_banks:
 545  * @set_rf_regs:
 546  * @compute_pll_control: compute the PLL control value to use for
 547  *      AR_RTC_PLL_CONTROL for a given channel
 548  * @setup_calibration: set up calibration
 549  * @iscal_supported: used to query if a type of calibration is supported
 550  *
 551  * @ani_cache_ini_regs: cache the values for ANI from the initial
 552  *      register settings through the register initialization.
 553  */
 554 struct ath_hw_private_ops {
 555         /* Calibration ops */
 556         void (*init_cal_settings)(struct ath_hw *ah);
 557         bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
 558
 559         void (*init_mode_regs)(struct ath_hw *ah);
 560         void (*init_mode_gain_regs)(struct ath_hw *ah);
 561         void (*setup_calibration)(struct ath_hw *ah,
 562                                   struct ath9k_cal_list *currCal);
 563
 564         /* PHY ops */
 565         int (*rf_set_freq)(struct ath_hw *ah,
 566                            struct ath9k_channel *chan);
 567         void (*spur_mitigate_freq)(struct ath_hw *ah,
 568                                    struct ath9k_channel *chan);
 569         int (*rf_alloc_ext_banks)(struct ath_hw *ah);
 570         void (*rf_free_ext_banks)(struct ath_hw *ah);
 571         bool (*set_rf_regs)(struct ath_hw *ah,
 572                             struct ath9k_channel *chan,
 573                             u16 modesIndex);
 574         void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
 575         void (*init_bb)(struct ath_hw *ah,
 576                         struct ath9k_channel *chan);
 577         int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
 578         void (*olc_init)(struct ath_hw *ah);
 579         void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
 580         void (*mark_phy_inactive)(struct ath_hw *ah);
 581         void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
 582         bool (*rfbus_req)(struct ath_hw *ah);
 583         void (*rfbus_done)(struct ath_hw *ah);
 584         void (*restore_chainmask)(struct ath_hw *ah);
 585         void (*set_diversity)(struct ath_hw *ah, bool value);
 586         u32 (*compute_pll_control)(struct ath_hw *ah,
 587                                    struct ath9k_channel *chan);
 588         bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
 589                             int param);
 590         void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
 591         void (*set_radar_params)(struct ath_hw *ah,
 592                                  struct ath_hw_radar_conf *conf);
 593
 594         /* ANI */
 595         void (*ani_cache_ini_regs)(struct ath_hw *ah);
 596 };
 597
 598 /**
 599  * struct ath_hw_ops - callbacks used by hardware code and driver code
 600  *
 601  * This structure contains callbacks designed to to be used internally by
 602  * hardware code and also by the lower level driver.
 603  *
 604  * @config_pci_powersave:
 605  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
 606  */
 607 struct ath_hw_ops {
 608         void (*config_pci_powersave)(struct ath_hw *ah,
 609                                      bool power_off);
 610         void (*rx_enable)(struct ath_hw *ah);
 611         void (*set_desc_link)(void *ds, u32 link);
 612         bool (*calibrate)(struct ath_hw *ah,
 613                           struct ath9k_channel *chan,
 614                           u8 rxchainmask,
 615                           bool longcal);
 616         bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
 617         void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
 618                             bool is_firstseg, bool is_is_lastseg,
 619                             const void *ds0, dma_addr_t buf_addr,
 620                             unsigned int qcu);
 621         int (*proc_txdesc)(struct ath_hw *ah, void *ds,
 622                            struct ath_tx_status *ts);
 623         void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
 624                               u32 pktLen, enum ath9k_pkt_type type,
 625                               u32 txPower, u32 keyIx,
 626                               enum ath9k_key_type keyType,
 627                               u32 flags);
 628         void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
 629                                 void *lastds,
 630                                 u32 durUpdateEn, u32 rtsctsRate,
 631                                 u32 rtsctsDuration,
 632                                 struct ath9k_11n_rate_series series[],
 633                                 u32 nseries, u32 flags);
 634         void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
 635                                   u32 aggrLen);
 636         void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
 637                                    u32 numDelims);
 638         void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
 639         void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
 640         void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
 641         void (*antdiv_comb_conf_get)(struct ath_hw *ah,
 642                         struct ath_hw_antcomb_conf *antconf);
 643         void (*antdiv_comb_conf_set)(struct ath_hw *ah,
 644                         struct ath_hw_antcomb_conf *antconf);
 645
 646 };
 647
 648 struct ath_nf_limits {
 649         s16 max;
 650         s16 min;
 651         s16 nominal;
 652 };
 653
 654 /* ah_flags */
 655 #define AH_USE_EEPROM   0x1
 656 #define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
 657
 658 struct ath_hw {
 659         struct ath_ops reg_ops;
 660
 661         struct ieee80211_hw *hw;
 662         struct ath_common common;
 663         struct ath9k_hw_version hw_version;
 664         struct ath9k_ops_config config;
 665         struct ath9k_hw_capabilities caps;
 666         struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
 667         struct ath9k_channel *curchan;
 668
 669         union {
 670                 struct ar5416_eeprom_def def;
 671                 struct ar5416_eeprom_4k map4k;
 672                 struct ar9287_eeprom map9287;
 673                 struct ar9300_eeprom ar9300_eep;
 674         } eeprom;
 675         const struct eeprom_ops *eep_ops;
 676
 677         bool sw_mgmt_crypto;
 678         bool is_pciexpress;
 679         bool aspm_enabled;
 680         bool is_monitoring;
 681         bool need_an_top2_fixup;
 682         u16 tx_trig_level;
 683
 684         u32 nf_regs[6];
 685         struct ath_nf_limits nf_2g;
 686         struct ath_nf_limits nf_5g;
 687         u16 rfsilent;
 688         u32 rfkill_gpio;
 689         u32 rfkill_polarity;
 690         u32 ah_flags;
 691
 692         bool htc_reset_init;
 693
 694         enum nl80211_iftype opmode;
 695         enum ath9k_power_mode power_mode;
 696
 697         s8 noise;
 698         struct ath9k_hw_cal_data *caldata;
 699         struct ath9k_pacal_info pacal_info;
 700         struct ar5416Stats stats;
 701         struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
 702
 703         int16_t curchan_rad_index;
 704         enum ath9k_int imask;
 705         u32 imrs2_reg;
 706         u32 txok_interrupt_mask;
 707         u32 txerr_interrupt_mask;
 708         u32 txdesc_interrupt_mask;
 709         u32 txeol_interrupt_mask;
 710         u32 txurn_interrupt_mask;
 711         atomic_t intr_ref_cnt;
 712         bool chip_fullsleep;
 713         u32 atim_window;
 714
 715         /* Calibration */
 716         u32 supp_cals;
 717         struct ath9k_cal_list iq_caldata;
 718         struct ath9k_cal_list adcgain_caldata;
 719         struct ath9k_cal_list adcdc_caldata;
 720         struct ath9k_cal_list tempCompCalData;
 721         struct ath9k_cal_list *cal_list;
 722         struct ath9k_cal_list *cal_list_last;
 723         struct ath9k_cal_list *cal_list_curr;
 724 #define totalPowerMeasI meas0.unsign
 725 #define totalPowerMeasQ meas1.unsign
 726 #define totalIqCorrMeas meas2.sign
 727 #define totalAdcIOddPhase  meas0.unsign
 728 #define totalAdcIEvenPhase meas1.unsign
 729 #define totalAdcQOddPhase  meas2.unsign
 730 #define totalAdcQEvenPhase meas3.unsign
 731 #define totalAdcDcOffsetIOddPhase  meas0.sign
 732 #define totalAdcDcOffsetIEvenPhase meas1.sign
 733 #define totalAdcDcOffsetQOddPhase  meas2.sign
 734 #define totalAdcDcOffsetQEvenPhase meas3.sign
 735         union {
 736                 u32 unsign[AR5416_MAX_CHAINS];
 737                 int32_t sign[AR5416_MAX_CHAINS];
 738         } meas0;
 739         union {
 740                 u32 unsign[AR5416_MAX_CHAINS];
 741                 int32_t sign[AR5416_MAX_CHAINS];
 742         } meas1;
 743         union {
 744                 u32 unsign[AR5416_MAX_CHAINS];
 745                 int32_t sign[AR5416_MAX_CHAINS];
 746         } meas2;
 747         union {
 748                 u32 unsign[AR5416_MAX_CHAINS];
 749                 int32_t sign[AR5416_MAX_CHAINS];
 750         } meas3;
 751         u16 cal_samples;
 752
 753         u32 sta_id1_defaults;
 754         u32 misc_mode;
 755         enum {
 756                 AUTO_32KHZ,
 757                 USE_32KHZ,
 758                 DONT_USE_32KHZ,
 759         } enable_32kHz_clock;
 760
 761         /* Private to hardware code */
 762         struct ath_hw_private_ops private_ops;
 763         /* Accessed by the lower level driver */
 764         struct ath_hw_ops ops;
 765
 766         /* Used to program the radio on non single-chip devices */
 767         u32 *analogBank0Data;
 768         u32 *analogBank1Data;
 769         u32 *analogBank2Data;
 770         u32 *analogBank3Data;
 771         u32 *analogBank6Data;
 772         u32 *analogBank6TPCData;
 773         u32 *analogBank7Data;
 774         u32 *addac5416_21;
 775         u32 *bank6Temp;
 776
 777         u8 txpower_limit;
 778         int coverage_class;
 779         u32 slottime;
 780         u32 globaltxtimeout;
 781
 782         /* ANI */
 783         u32 proc_phyerr;
 784         u32 aniperiod;
 785         int totalSizeDesired[5];
 786         int coarse_high[5];
 787         int coarse_low[5];
 788         int firpwr[5];
 789         enum ath9k_ani_cmd ani_function;
 790
 791         /* Bluetooth coexistance */
 792         struct ath_btcoex_hw btcoex_hw;
 793         u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
 794         u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
 795
 796         u32 intr_txqs;
 797         u8 txchainmask;
 798         u8 rxchainmask;
 799
 800         struct ath_hw_radar_conf radar_conf;
 801
 802         u32 originalGain[22];
 803         int initPDADC;
 804         int PDADCdelta;
 805         int led_pin;
 806         u32 gpio_mask;
 807         u32 gpio_val;
 808
 809         struct ar5416IniArray iniModes;
 810         struct ar5416IniArray iniCommon;
 811         struct ar5416IniArray iniBank0;
 812         struct ar5416IniArray iniBB_RfGain;
 813         struct ar5416IniArray iniBank1;
 814         struct ar5416IniArray iniBank2;
 815         struct ar5416IniArray iniBank3;
 816         struct ar5416IniArray iniBank6;
 817         struct ar5416IniArray iniBank6TPC;
 818         struct ar5416IniArray iniBank7;
 819         struct ar5416IniArray iniAddac;
 820         struct ar5416IniArray iniPcieSerdes;
 821         struct ar5416IniArray iniPcieSerdesLowPower;
 822         struct ar5416IniArray iniModesAdditional;
 823         struct ar5416IniArray iniModesAdditional_40M;
 824         struct ar5416IniArray iniModesRxGain;
 825         struct ar5416IniArray iniModesTxGain;
 826         struct ar5416IniArray iniModes_9271_1_0_only;
 827         struct ar5416IniArray iniCckfirNormal;
 828         struct ar5416IniArray iniCckfirJapan2484;
 829         struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
 830         struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
 831         struct ar5416IniArray iniModes_9271_ANI_reg;
 832         struct ar5416IniArray iniModes_high_power_tx_gain_9271;
 833         struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
 834
 835         struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
 836         struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
 837         struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
 838         struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
 839
 840         u32 intr_gen_timer_trigger;
 841         u32 intr_gen_timer_thresh;
 842         struct ath_gen_timer_table hw_gen_timers;
 843
 844         struct ar9003_txs *ts_ring;
 845         void *ts_start;
 846         u32 ts_paddr_start;
 847         u32 ts_paddr_end;
 848         u16 ts_tail;
 849         u8 ts_size;
 850
 851         u32 bb_watchdog_last_status;
 852         u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
 853         u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
 854
 855         unsigned int paprd_target_power;
 856         unsigned int paprd_training_power;
 857         unsigned int paprd_ratemask;
 858         unsigned int paprd_ratemask_ht40;
 859         bool paprd_table_write_done;
 860         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
 861         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
 862         /*
 863          * Store the permanent value of Reg 0x4004in WARegVal
 864          * so we dont have to R/M/W. We should not be reading
 865          * this register when in sleep states.
 866          */
 867         u32 WARegVal;
 868
 869         /* Enterprise mode cap */
 870         u32 ent_mode;
 871
 872         bool is_clk_25mhz;
 873         int (*get_mac_revision)(void);
 874         int (*external_reset)(void);
 875 };
 876
 877 struct ath_bus_ops {
 878         enum ath_bus_type ath_bus_type;
 879         void (*read_cachesize)(struct ath_common *common, int *csz);
 880         bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
 881         void (*bt_coex_prep)(struct ath_common *common);
 882         void (*extn_synch_en)(struct ath_common *common);
 883         void (*aspm_init)(struct ath_common *common);
 884 };
 885
 886 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
 887 {
 888         return &ah->common;
 889 }
 890
 891 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
 892 {
 893         return &(ath9k_hw_common(ah)->regulatory);
 894 }
 895
 896 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
 897 {
 898         return &ah->private_ops;
 899 }
 900
 901 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
 902 {
 903         return &ah->ops;
 904 }
 905
 906 static inline u8 get_streams(int mask)
 907 {
 908         return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
 909 }
 910
 911 /* Initialization, Detach, Reset */
 912 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 913 void ath9k_hw_deinit(struct ath_hw *ah);
 914 int ath9k_hw_init(struct ath_hw *ah);
 915 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 916                    struct ath9k_hw_cal_data *caldata, bool bChannelChange);
 917 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
 918 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
 919
 920 /* GPIO / RFKILL / Antennae */
 921 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 922 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
 923 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
 924                          u32 ah_signal_type);
 925 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
 926 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
 927 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 928
 929 /* General Operation */
 930 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
 931 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
 932                           int column, unsigned int *writecnt);
 933 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
 934 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 935                            u8 phy, int kbps,
 936                            u32 frameLen, u16 rateix, bool shortPreamble);
 937 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 938                                   struct ath9k_channel *chan,
 939                                   struct chan_centers *centers);
 940 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 941 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 942 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 943 bool ath9k_hw_disable(struct ath_hw *ah);
 944 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
 945 void ath9k_hw_setopmode(struct ath_hw *ah);
 946 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 947 void ath9k_hw_setbssidmask(struct ath_hw *ah);
 948 void ath9k_hw_write_associd(struct ath_hw *ah);
 949 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 950 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 951 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 952 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 953 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 954 void ath9k_hw_init_global_settings(struct ath_hw *ah);
 955 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
 956 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 957 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 958 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
 959                                     const struct ath9k_beacon_state *bs);
 960 bool ath9k_hw_check_alive(struct ath_hw *ah);
 961
 962 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
 963
 964 /* Generic hw timer primitives */
 965 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
 966                                           void (*trigger)(void *),
 967                                           void (*overflow)(void *),
 968                                           void *arg,
 969                                           u8 timer_index);
 970 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 971                               struct ath_gen_timer *timer,
 972                               u32 timer_next,
 973                               u32 timer_period);
 974 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 975
 976 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 977 void ath_gen_timer_isr(struct ath_hw *hw);
 978
 979 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 980
 981 /* HTC */
 982 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
 983
 984 /* PHY */
 985 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 986                                    u32 *coef_mantissa, u32 *coef_exponent);
 987
 988 /*
 989  * Code Specific to AR5008, AR9001 or AR9002,
 990  * we stuff these here to avoid callbacks for AR9003.
 991  */
 992 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
 993 int ar9002_hw_rf_claim(struct ath_hw *ah);
 994 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
 995
 996 /*
 997  * Code specific to AR9003, we stuff these here to avoid callbacks
 998  * for older families
 999  */
1000 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1001 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1002 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1003 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1004 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1005 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1006                                         struct ath9k_hw_cal_data *caldata,
1007                                         int chain);
1008 int ar9003_paprd_create_curve(struct ath_hw *ah,
1009                               struct ath9k_hw_cal_data *caldata, int chain);
1010 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1011 int ar9003_paprd_init_table(struct ath_hw *ah);
1012 bool ar9003_paprd_is_done(struct ath_hw *ah);
1013 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1014
1015 /* Hardware family op attach helpers */
1016 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1017 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1018 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1019
1020 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1021 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1022
1023 void ar9002_hw_attach_ops(struct ath_hw *ah);
1024 void ar9003_hw_attach_ops(struct ath_hw *ah);
1025
1026 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1027 /*
1028  * ANI work can be shared between all families but a next
1029  * generation implementation of ANI will be used only for AR9003 only
1030  * for now as the other families still need to be tested with the same
1031  * next generation ANI. Feel free to start testing it though for the
1032  * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1033  */
1034 extern int modparam_force_new_ani;
1035 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1036 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1037 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1038
1039 #define ATH_PCIE_CAP_LINK_CTRL  0x70
1040 #define ATH_PCIE_CAP_LINK_L0S   1
1041 #define ATH_PCIE_CAP_LINK_L1    2
1042
1043 #define ATH9K_CLOCK_RATE_CCK            22
1044 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
1045 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
1046 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1047
1048 #endif